3.1. Sensor Signal-to-Spike Converter (SSC)
The sensor output span seldom equals the input span of the SA-SDC, as shown in
Figure 3, and if the sensor span is smaller than the input span of the SA-SDC, as shown in
Figure 3a, the dynamic range of the SA-SDC is not fully utilized; it will not make use of all ACDs. Furthermore, the spans of the sensor and SA-SDC may be equal, but they are offset, as shown in
Figure 3b. On the other side of the sensor, if the span is greater than the input range of the SA-SDC, as shown in
Figure 3c, then sensor data is lost. In another case, there is a difference in both duration (200 ns and 300 ns) and offset (100 ns) of the spans, as illustrated in
Figure 3d. Often the spans are offset and unequal. Therefore, amplification and level shifting in the time domain are needed to match the spans. The mismatched spans require an expensive increase in the SA-SDC dynamic range or loss of sensor data; therefore, the spans of the sensor and SA-SDC must be matched to obtain optimum performance. The SSC is a conditioning circuit that matches the sensor and SA-SDC, making the spans equal without a level shift. The SSC is so versatile that it amplifies and level shifts in the time domain of the sensor signal simultaneously. In the next step of the design, we will develop an SSC unit, which is required for the proposed project.
3.2. Self-Adaptive Spike-to-Digital Converter (SA-SDC)
The SA-SDC that is being proposed consists of two components, the first being the self-adaptive spike-to-rank coding (SA-SRC) and the second being the winner-take-all (WTA) mechanism that incorporates memory, as illustrated in
Figure 1. The SA-SRC has a tendency to produce spike orders that correspond to the time difference between two spikes received at its inputs. Spike order codes are a type of coding method that relies on the arrangement of spikes across a group of neurons, which is determined by the firing sequence of those neurons [
25,
26]. The rank order code is converted into digital numbers through the second component, WTA. By adding more ACDs in a cascade, the ability to measure time intervals between in1 and in2 can be enhanced, resulting in an increased resolution of the SA-SDC. The number of ACDs needed to achieve a specific number of bits (NOB) can be determined using Equation (
1), which was developed in [
18].
where
x is the number of ACDs. Sixteen adaptive coincidence detection (ACD) units are employed to implement the proposed SA-SRC for the current stage of the development, as shown in
Figure 4. The NOB can be calculated by using Equation (
1), which yields a result of 4 bits. The SA-SRC consists of two symmetrical sections, specifically the upper and lower parts, which generate the SA-SRC outputs from Out1 to Out8 and Out9 to Out16, respectively. Therefore, the presented concept can work for both single-ended and differential or difference sensorial input, the current implementation uses (spike time) difference input. This system is equipped with two inputs, referred to as in1 and in2. In the upper section, input in1 is linked straight to the first input of the ACDs. On the other hand, the input in2 is transmitted through the ACDs sequentially, representing the delay chains of the upper section. In contrast, in the lower section, input in2 is directly connected to the first input of the ACDs, while input in1 is transmitted through the ACDs one by one, representing the delay chains of the lower section. The duration of the delay chain unit depends on when the neuron fires, which is influenced by the amount of input current it receives. However, the input current to the neuron is adjusted by the synapse weight. As a result, the weights of the synapses adjust to the delay of each unit in the chain, even when there are variations.
Each ACD unit consists of one neuron (N) and two adaptive synapses (AS). In [
18], we suggested an adaptive synapse that utilizes the CMOS memristor to imitate the short-term plasticity (STP) and long-term plasticity (LTP) of a biological synapse.
Figure 5 displays the schematic of the adaptive synapse we proposed.
Indiveri’s neuron model, known as the leaky integrate and fire (LIF) neuron model, includes various components that allow for setting an arbitrary refractory period, spike frequency adaptation, positive feedback, modulating the neuron’s threshold voltage, membrane capacitor, a transistor for controlling the current leakage, and a digital inverter for pulse generation [
27]. The essential characteristics necessary for the ACD involve the ability of neurons to implement time delays in a neural network, along with an inverse correlation between the magnitude of incoming charges and the timing of the first spike. These properties are inherent in any neural spiking model. We modified the Indiveri neuron model in [
16] to fulfill the needs of ACD and enhance power efficiency, area utilization, and processing speed. A schematic of the modified neuron model can be observed in
Figure 6.
There are two modes of operation for the ASRC. The first is the normal mode, in which both synapses of the ACD are connected to the neuron. The second mode is the adaptation mode, which was created in [
18] by implementing a two-layer adaptation hierarchy. The first layer operates at the ACD level, while the second layer operates at the SA-SRC level. The first layer is entirely self-adaptive and local, operating in an unsupervised manner. In the first layer, the weight of a synapse is determined by the timing of neuron firing, which is based on the input current it receives. This approach depends on the fact that the timing of neuron firing is affected by the input current, and the weight of the synapse regulates this current. Consequently, the weight of the synapse is directly proportional to the timing of the neuron’s firing. We created a self-adaptive method for the first layer of the ACD by designing an autonomous control circuit, as illustrated in
Figure 7 in [
18]. This adaptivity is facilitated through the reset, adapt_pulse, and adapt I/O pins of the SA-SRC. Upon receiving the reset signal, the SA-SRC enters the adaptation mode and sets the adapt output to one upon completion of the unsupervised adaptation of the first level. The SA-SRC utilizes the pulse of the adapt_pulse input to adapt itself. Once the adaptation process is complete, the SA-SRC returns to normal mode, during which it can receive input pulses on its two inputs (in1 and in2), and adjust the output code based on the time difference between them.
The adaptation process in the first level occurs simultaneously for all ACDs through the control of switches T1, T2, T3, T4, and T5, as shown in
Figure 4. As a result, the time required for adaptation will not increase with the number of synapses since all synapses are adjusted simultaneously. The weight of the first synapse in all ACDs is adapted simultaneously by the autonomous circuit, achieved by connecting the first synapse while disconnecting the second synapse. Likewise, the weight of the second synapse is also adapted. The maximum adaptation time is determined by multiplying the maximum number of steps by the duration of adapt_pulse. According to [
18] (p. 246), our adaptation scheme allows for a maximum of 512 steps. The actual adaptation time will be influenced by process, voltage, and temperature (PVT) conditions. Upon powering-up the MPC USIX chip, all weights are initially set to zero, and the weight corresponds to the delay. The process of adaptation starts from scratch and progresses until the desired synapse weight is achieved, resulting in uniform delays across all connections.
The second level of adaptation operates above the first level and is responsible for adjusting the variables vg1, vg2, , and . This level operates above the first level and waits for the first level to complete its solution after every modification to these variables. If the solution successfully corrects the synapse weight, the adaptation process ends. If not, the second level updates the variables (vg1, vg2, , and ) and initiates adaptation for the next round. At present, these four variables are being manually adjusted in the current stage of development of our design.