- freely available
Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA
AbstractA novel design of force to rebalance control for a hemispherical resonator gyro (HRG) based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.
Share & Cite This Article
Wang, X.; Wu, W.; Luo, B.; Fang, Z.; Li, Y.; Jiang, Q. Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA. Sensors 2011, 11, 11761-11773.View more citation formats
Wang X, Wu W, Luo B, Fang Z, Li Y, Jiang Q. Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA. Sensors. 2011; 11(12):11761-11773.Chicago/Turabian Style
Wang, Xu; Wu, Wenqi; Luo, Bing; Fang, Zhen; Li, Yun; Jiang, Qingan. 2011. "Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA." Sensors 11, no. 12: 11761-11773.
Notes: Multiple requests from the same IP address are counted as one view.