Isolated DC-DC Converter for Bidirectional Power Flow Controlling with Soft-Switching Feature and High Step-Up/Down Voltage Conversion

Abstract

In this paper, a novel isolated bidirectional DC-DC converter is proposed, which is able to accomplish high step-up/down voltage conversion. Therefore, it is suitable for hybrid electric vehicle, fuel cell vehicle, energy backup system, and grid-system applications. The proposed converter incorporates a coupled inductor to behave forward-and-flyback energy conversion for high voltage ratio and provide galvanic isolation. The energy stored in the leakage inductor of the coupled inductor can be recycled without the use of additional snubber mechanism or clamped circuit. No matter in step-up or step-down mode, all power switches can operate with soft switching. Moreover, there is a inherit feature that metal–oxide–semiconductor field-effect transistors (MOSFETs) with smaller on-state resistance can be adopted because of lower voltage endurance at primary side. Operation principle, voltage ratio derivation, and inductor design are thoroughly described in this paper. In addition, a 1-kW prototype is implemented to validate the feasibility and correctness of the converter. Experimental results indicate that the peak efficiencies in step-up and step-down modes can be up to 95.4% and 93.6%, respectively.

1. Introduction

In order to reduce carbon emission and mitigate global warming, green energies, such as photovoltaic (PV) panel, fuel cells, and wind turbine, attract a great deal of interest and have a high rate of growth in installed capacity. A complete configuration of distributed generation system (DGS), as shown in Figure 1, not only includes green-energy sources but also combines an energy storage system for power conditioning to use electricity optimally. For grid connection, a DC-bus voltage up to around 400 V is required, which is much higher than a battery voltage. Therefore, a bidirectional DC-DC converter (BDC) with high voltage ratio to charge/discharge battery is mandatory in the DGS.

Conventional high step-up converters used in PV panel and fuel cells can boost a low voltage to a higher level to serve as an interface between the distributed generator and the DC bus [1,2,3]. Nevertheless, they only control power flow in unique direction. Bidirectional power flow control is necessary for battery system. A solution is to adopt two high-voltage-ratio converters. One is high-step-up converter for battery discharging and the other is high-step-down converter for charging, but this approach increases cost significantly. Therefore, BDC is the current design trend, which is capable of governing energy in either power flow direction by a single converter. BDCs can be simply classified as non-isolated type [4,5,6] and isolated type [7,8].

Increasing switching frequency of a power converter can reduce the size of magnetic and capacitive elements and thus has the benefit of achieving high power density. However, the higher switch frequency is, the lower conversion efficiency will be. In order to eliminate switching loss, employing resonant unit with auxiliary switches for soft-switching achievement is a common approach [9,10,11]. In literature [12], the authors develop a dual-bridge converter to fulfill bidirectional power flow controlling along with zero voltage switching (ZVS) at main switch, in which even resonant tank is utilized but the use of additional auxiliary switch can be avoided. Nevertheless, a great many switches are needed and its voltage ratio is incapable of high step-up/down applications.

The open H-bridge converter can function as a non-isolated BDC [13]. Even though this converter can achieve ZVS feature and possesses simple structure, its voltage gain is less than 2 at the duty ratio of 0.5. For higher voltage ratio, heavy switch duty cycle is the only solution to this problem, but this approach will degrade converter efficiency. To avoid excessive duty cycle operation, switched capacitor technology will be an alternative for high voltage-gain conversion [14]. However, current spike that occurs at the switching transients confines its applications and accompanies electromagnetic interference (EMI) problem, especially in high power rating. Incorporating switched capacitor along with coupled inductor into a power converter is a key to suppressing inrush current and obtaining enough voltage conversion ratio [15,16,17,18]. Since the coupled inductor can also feature electrical isolation, a BDC including coupled inductor is the major development. However, the energy dissipation caused from leakage inductor will degrade converter efficiency [19,20]. That is, clamped circuit or snubber mechanism for leakage energy harvesting is imperative. Isolated BDCs based on H-bridge topology have been proposed in the literature [21,22], which can achieve ZVS feature inherently, avoiding additional device usage. Nevertheless, low voltage ratio and more power switches required become their disadvantages. In [23], another isolated BDC which accomplishes leakage-energy recycling and can obtain high voltage-ratio conversion is presented. Nevertheless, some limitations still exist, such as ZVS only occurs at high-voltage side and duty ratio has to be greater than 0.5.

In this paper, a novel BDC is proposed, which has the advantages of galvanic isolation, high voltage conversion ratio, soft-switching feature at all power switches, high efficiency, being suitable for high power applications, and low component count. Figure 2 shows its configuration of the power stage. The symbols in the circuit are summarized in the followings. V_L and V_H denote the terminal voltages at low-voltage side and high-voltage side, respectively; L₁ is a choke inductor; S₁, S₂, S₃, S₄, S₅, and S₆ are active switches, while D_S1–D_S6 and C_S1–C_S6 express their related anti-parallel body diodes and parasitic capacitors; the magnetically-coupled device has winding N₁, magnetizing inductor L_m1, and leakage inductor L_k1 at low-voltage side, meanwhile N₂, L_m2, and L_k2, respectively, at high-voltage side; C_b1 and C_b2 are low-voltage capacitors; and C_o1 and C_o2 are high-voltage capacitors. The conversion efficiency of proposed BDC can be improved because of the following reasons:

(1)

No matter in buck or boost mode, the energy stored in leakage inductors, L_k1 and L_k2, can be recycled without any snubber mechanism or clamped circuit.

(2)

All active semiconductor components can be switched with ZVS or zero current switching (ZCS) to eliminate switching losses.

(3)

Switches S₁–S₄ endure a low voltage stress so that semiconductor device with a smaller R_ds(on) can be chosen to reduce conduction losses.

Following the introduction described in Section 1, this paper is organized as follows. The operation principle of the proposed converter is explained in Section 2. Section 3 presents the steady-state analysis. Experimental results measured from a 1-kW prototype are illustrated and discussed in Section 4, while conclusion is summarized in Section 5.

2. Operation Principle of the Proposed Converter

As shown in Figure 2, the direction of energy flow can be handled by controlling the active switches so that the converter can operate in either step-up mode or step-down mode. In step-up mode, main switches S₁, S₂, S₃, and S₄ are in switching pattern while S₅ and S₆ are in charge of rectifying. At this mode, S₁ and S₂ operate complementarily and so do both switches S₃ and S₄. The voltage gain of V_L to V_H is determined by the duty ratio of S₁. With respect to step-down mode, main switches S₂, S₄, S₅, and S₆ will be in switching pattern and the rest of main switches serve as rectifier. In addition, S₂, S₄, and S₅ are turned on and off simultaneously and complementary to S₆. The duty ratio of S₆ dominates the voltage gain of V_H to V_L in step-down mode. To describe the operation of the converter, some assumptions are made as follows:

(1)

In Figure 2, capacitances of C_b1, C_b2, C_o1, and C_o2 are large enough so that all the voltages across them can be regarded as constant in a switching cycle.

(2)

Parasitic capacitor and body diode of each switch are considered, but the internal resistance is neglected.

(3)

The leakage inductance of the coupled inductor is much less than magnetizing inductance.

(4)

All the magnetic components are designed in continuous conduction mode (CCM).

(5)

The turns ratio of secondary to primary of the coupled inductor, N₂/N₁, is defined as n.

2.1. Step-Up Mode

The converter operation in step-up mode is divided into nine main stages over one switching cycle, which are discussed stage by stage below. The equivalents of the nine stages are depicted in Figure 3, while Figure 4 illustrates the corresponding conceptual waveforms.

Stage 1 [t₀, t₁]: In this stage, referring to Figure 3a, all the switches are in off state. The energy stored in the parasitic capacitor C_S3 is drawn out but capacitor C_b1 is charged, as referred to the red dashed line in Figure 3a. Meanwhile, energy of L′_m1 is forwarded to capacitor C_o2 and the output V_H, where L′_m1 stands for the total amount of magnetizing inductance seen looking into the primary (at low-voltage side) of the coupled inductor. After the voltage across C_S3 drops to zero, the body diode D_S3 conducts to continue the currents flowing through L₁ and L_k1 thus to create ZVS turn-on condition for S₃.

Stage 2 [t₁, t₂]: This stage begins at the moment the switches S₁ and S₃ are turned on. The S₃ is turned on with ZVS. During this time interval, S₂, S₄, S₅, and S₆ are still in off-state. The voltage of the parasitic capacitor C_S1 drops. After the voltage v_ds1 is less than input voltage V_L, inductor L₁ will absorb energy from V_L and the current i_L1 increases, as referred to the blue dashed line in Figure 3b. In stage 2, the energy of L_k1 is continuously releasing to C_b1. The equivalent circuit of this stage is illustrated in Figure 3b. When the current i_Lk1 falls to zero, this mode ends.

Stage 3 [t₂, t₃]: Figure 3c depicts the equivalent circuit of this stage, in which all the switch have the same statuses as in Stage 2. Inductor L₁ continuously absorbs the energy from V_L. Capacitor C_b1 transmits energy to L_k1, L′_m1 and the secondary (at high-voltage side) of the coupled inductor, of which current path is indicated by the red dashed line in Figure 3c. The currents i_Lk1 and i_Lm1 increase. In the high-voltage side, C_o1 is charged via the loop of N₂-D_S6-C_o1-L_k2 but C_o2 discharges via the loop of L_k2-N₂-D_S6-V_H-C_o2. This mode ends when S₃ is turned off.

Stage 4 [t₃, t₄]: This stage begins at time t = t₃, and the equivalent circuit is illustrated in Figure 3d. During this time interval, all the switches are in off state except S₁. Input V_L and capacitor C_b1 charge inductor L₁ and capacitor C_b2, respectively. In addition, C_b1 forwards energy to high-voltage side via the coupled inductor to charge C_o1. The C_S4 releases energy. That is, v_ds4 decreases. The body diode of S₄ will be forward biased after v_ds4 drops to zero, which provides ZVS condition for S₄. The associated current path is referred to the red dashed line in Figure 3d. The leakage energy in L_k2 is recycling to C_o1 over the interval of Stage 4.

Stage 5 [t₄, t₅]: When S₄ is turned on, the operation of the converter enters into Stage 5. As shown in Figure 3e, in this stage switches S₁ and S₄ are closed, whereas S₂, S₃, S₅, and S₆ are open. The voltage polarity of L_k1 is reversed and the current i_Lk1 begins decreasing. Capacitor C_b2 is charged by L_k1 and C_b1 and the current flowing through S₄ is decreased, as referred to the red dashed line in Figure 3e. The energy in L_k2 is kept on recycling to C_o1, which is the same as in Stage 4. At the moment that i_Lk2 equals zero, this stage ends and D_S6 is reversely biased.

Stage 6 [t₅, t₆]: During the time interval of Stage 6, the switches S₁ and S₄ are still in on state and S₂, S₃, S₅, and S₆ in off state. Figure 3f is the corresponding equivalent, in which C_b1 charges L_k1, L′_m1, and C_b2, as referred to the red dashed line. The currents flowing through L_k1 and L′_m1 are identical and increase simultaneously. With respect to current i_L1, since the voltage across L₁ is V_L, the current i_L1 continues linearly increasing. This stage continues until S₁ is turned off.

Stage 7 [t₆, t₇]: Figure 3g depicts the equivalent circuit of Stage 7, in which all switches are open except S₄. There are two loops, V_L-L₁-C_b1-C_S2 and L_k1-L′_m1-S₄-C_b2-C_S2, to draw the energy stored in the parasitic capacitor of S₂. When the voltage across C_S2 falls to zero, the body diode of S₂ conducts and S₂ can achieve ZVS, as referred to the both dashed lines in red and blue in Figure 3g. In the high-voltage side of the converter, the both in-series capacitors C_o1 and C_o2 supply power to output.

Stage 8 [t₇, t₈]: After the time t = t₇, switches S₂ and S₄ are in on state but S₁, S₃, S₅, and S₆ are in off state. The equivalent circuit is illustrated in Figure 3h. As referred to the both red and purple dashed line in Figure 3h, capacitor C_b1 is charged by V_L and L₁, while the C_b2 absorbs energy from L′_m1 and L_k1. All the currents i_L1, i_Lk1 and i_Lm1 decrease. In addition, the energy stored in magnetizing inductor is forwarded to the secondary of the coupled inductor to charge C_o2. This stage ends as the current i_Lk1 falls to zero.

Stage 9 [t₈, t₉]: During the time interval of Stage 9, the switches S₂ and S₄ are still in on state and S₁, S₃, S₅, and S₆ in off state. The equivalent circuit is illustrated in Figure 3i. Capacitor C_b1 is still charged by V_L and L₁. Additionally, capacitor C_b2 pumps energy to inductor L_k1 via switches S₄, as referred to the red dashed line in Figure 3i. The energy stored in the magnetizing inductor is transferred to the secondary to charge C_o2 and power the output. In this stage, inductor currents i_L1 and i_Lm1 decrease but i_Lk1 and i_Lk2 increase. When switches S₂ and S₄ are turned off at t = t₉, this stage ends. The operation in step-up mode over one switching cycle is completed.

2.2. Step-Down Mode

In step-down mode, S₂, S₄, and S₅ are controlled at high switching pattern and complementary to SW₆, while SW₁ and SW₃ serve as rectifiers. The converter operation over one switching cycle in step-down mode can be divided into 12 stages, which are described stage by stage in the following. The related equivalents and corresponding waveforms are depicted in Figure 5 and Figure 6, respectively.

Stage 1 [t₀, t₁]: Referring to Figure 5a, all the switches are in off state. Since S₅ has been turned off, the voltage of C_S5 increases. Accordingly, the voltage across L′_m2 (the inductance seen looking into the high-voltage side of the coupled inductor) and L_k2, which is equal to v_Co2 − v_ds5, decreases; meanwhile the energy stored in the parasitic capacitor of S₆ releases via the loop of C_S6-C_o1-L_k2-L′_m2. In low voltage side, the body diodes of S₂ and S₄ are forward biased because of the continuity of i_Lk1. The voltage across L₁ equals v_Cb1 − V_L. Since v_Cb1 is larger than V_L, the current i_L1 increases negatively, as referred to the red dashed line in Figure 5a. During this stage, C_o2 will energize C_b2 via the coupled inductor and the loop L_k1-N₁-D_S4-C_b2-D_S2. This mode ends at the moment v_ds5 reaches the magnitude of V_H. That is, S₅ is completely turned off and its blocking voltage is clamped to V_H.

Stage 2 [t₁, t₂]: During this time interval, all the switches still stay in off state. The equivalent circuit of this stage is illustrated in Figure 5b. The voltage polarity across L′_m2 and L_k2 reverses and the value of v_Lm2 + v_Lk2 is equal to v_Co1. That is, magnetizing inductor L′_m2 and leakage inductor L_k2 release energy to C_o1 and V_H via body diode D_S6, as indicated by the purple dashed line in Figure 5b. Since voltage polarity of the coupled inductor has been changed, the body diode D_S2 will be reversely biased and the parasitic capacitor C_S1 releases energy to V_L. In stage 2, the current flowing L_k1 almost equals that in L₁. Therefore, switch S₂ is turned off at ZCS. When S₆ is turned on with ZVS, the operation of the converter enters into next stage.

Stage 3 [t₂, t₃]: In this stage, switch S₆ is closed. L′_m2 and L_k2 proceed with energy releasing toward C_o1 and V_H, and leakage energy in L_k1 is dumped to C_b2 at the same time. Accordingly, all the currents in them decrease. As referred to the blue dashed line in Figure 5c, the current of L₁ draws out the stored energy in C_S1 and then force the parasitic diode D_S1 in forward bias. The L₁ delivers energy to V_L and its current decreases linearly. In stage 3, the current flowing through L_k2 is greater than that in L′_m2 but its magnitude drops much steeper. This stage continues until i_Lk1 drops to zero. Figure 5c shows the equivalent circuit of this stage.

Stage 4 [t₃, t₄]: This stage begins at time t = t₃, and the equivalent circuit is illustrated in Figure 5d. During this time interval, all switches are still in turn-off condition except S₆. Magnetizing inductor L′_m2 forwards energy to C_o1 and C_b1 via switch S₆ and the ideal transformer, respectively. The current direction of L_k1 changes, which results in energy releasing of C_S3 and the charging of C_S4. Associated current path is shown as the red dashed line in Figure 5d. The leakage inductor L_k1 will confine the charge current of C_S4, resulting in ZCS turn-off at S₄. When the voltage v_ds4 rises to v_Cb2, Stage 5 begins.

Stage 5 [t₄, t₅]: The equivalent circuit of this stage is illustrated in Figure 5e, in which all the switches are turned off except S₆. Capacitor C_o1 still absorbs energy from L′_m2 and L_k2. In addition, L′_m2 forwards energy to C_b1 by the ideal transformer and via the loop of N₁-L_k1-D_S1-C_b1-D_S3. This current path is referred to the red dashed line in Figure 5e. The current flowing through L_k2 keeps on decreasing. This stage ends at the time that i_Lk2 is zero. That is, energy in L_k2 is completely recycled.

Stage 6 [t₅, t₆]: Figure 5f depicts the equivalent circuit of this mode, in which all switches have the same statuses as in Stage 5. The current direction of i_Lk2 changes at t = t₅, and L_k2 absorbs energy from C_o1, as referred to the green dashed line in Figure 5f. The circuit operation in low voltage side is identical to that in Stage 5. Therefore, the inductor L₁ keeps on energy supplying toward V_L and its current decreases linearly. Stage 6 continues until switch S₆ is turned off at t = t₆.

Stage 7 [t₆, t₇]: During the interval that S₆ is open, the voltage v_ds6 increases. Therefore, the voltage, v_Lm2 + v_Lk2, drops and the parasitic capacitor C_S5 dumps its stored energy, as referred to the green dashed line in Figure 5g. The circuit operation in low-voltage side behaves identically to Stage 6. When the energy in C_S5 is drawn out completely and v_ds6 rises to V_H, this stage stops. Figure 5g expresses the operation of the converter in Stage 7.

Stage 8 [t₇, t₈]: In Stage 8, the body diode D_S5 is in forward bias, which provides a ZVS condition for S₅. The green dashed line in Figure 5h shows this current path. Leakage energy in inductors L_k2 and L_k1 is recycled to C_o2 and C_b1. In addition, L₁ proceeds with energy releasing to V_L while L′_m2 still forwards energy to low voltage side via the ideal transformer. When switches S₂, S₄, and S₅ are turned on simultaneously, this stage ends. The corresponding equivalent circuit is depicted in Figure 5h.

Stage 9 [t₈, t₉]: At t = t₈, the operation of the converter enters into Stage 9. Figure 5i is the equivalent. The voltage polarity of the ideal transformer reverses because S₂ and S₄ are closed. Over the time interval of Stage 9, L_k2 and L_k1 continuously dump their stored energy and thus the currents i_Lk1 and i_Lk2 reduce. Additionally, the voltage level of v_Cb1 is higher than V_L, which results that the inductor L₁ absorbs energy from C_b1 and its current increases negatively and linearly, as referred to the blue dashed line in Figure 5i. This stage lasts until i_Lk2 drops to zero.

Stage 10 [t₉, t₁₀]: After the time t = t₉, the current direction of L_k2 changes and i_Lk2 increases. Switch statues in Stage 9 are identical to that in Stage 10. That is, S₂, S₄, and S₅ are in on state, whereas S₁, S₃, and S₆ stay in off state. The equivalent circuit is shown in Figure 5j, in which the L′_m2 draws energy from C_o2 and the voltage across L₁ is still kept at V_Cb1 − V_L. As the red dashed line in Figure 5j indicates, leakage inductor L_k1 continues releasing energy and i_Lk1 decreases. When i_Lk1 is zero at t = t₁₀, this stage ends.

Stage 11 [t₁₀, t₁₁]: Figure 5k shows the equivalent circuit of this stage, in which the statuses of all switches are kept as in Stage 10. During this time interval, C_b1 continuously supplies energy to V_L and L₁ by the loop of C_b1-L₁-V_L-S₂, of which current path is referred to the blue dashed line in Figure 5k. The current directions of N₁ and N₂ reverse and the current i_Lk1 rises positively. Meanwhile, capacitor C_b2 charges and C_o2 discharges.

Stage 12 [t₁₁, t₁₂]: From the equivalent circuit depicted in Figure 5l, switches S₂, S₄, and S₅ remain closed, while S₁, S₃, and S₆ are open. In Stage 12, inductors L_k2 and L′_m2 are magnetized by C_o2 with the same circuit behavior in Stage 11. Since the magnitude of i_Lk1 is greater than i_L1, the current flowing through S₂ becomes reverse, and then S₂ achieves ZCS at turn-off transition, as referred to the red dashed line in Figure 5l. The operation of the converter over one switching cycle is completed when the switches S₂, S₄, and S₅ are turned off simultaneously.

According to the aforementioned operation principle, the switching characteristics of all power switches are summarized in

Table 1. The switching characteristics of the proposed converter.

Mode	Main Circuit
	Low-Voltage Side				High-Voltage Side
	S1	S2	S3	S4	S5	S6
Step-up	ZVS	ZVS	ZVS	ZVS	none	none
Step-down	none	ZCS	none	ZCS	ZVS	ZVS

.

3. Steady-State Analysis

In this section, the steady-state analysis of the BDC includes voltage conversion ratio, voltage stress derivation, and magnetic element design. To simplify the analysis, the assumptions made in Section 2 are considered except the neglect of leakage inductors. In addition, the phenomenon that occurs at switching transient is also ignored.

3.1. Step-Up Mode

Voltage gain of the converter in step-up mode is first investigated. Because the output voltage V_H is the sum of V_Co1 and V_Co2, the relationships of V_Co1 to V_L and V_Co2 to V_L have to be found in advance. The voltage V_Co1 is n times the magnitude of V_Cb1 and V_Co2 is n times the V_Cb2 under the condition that leakage inductor is neglected. Accordingly, V_Cb1 and V_Cb2 in terms of V_L should be determined before the finding for V_Co1 and V_Co2. Since S₁ and S₂ are switched complementarily, the input voltage V_L can be boosted via inductor L₁. As a result, the voltage across C_b1 is given by

$$V_{Cb1}=\frac{V_L}{1-D_1},$$

(1)

where D₁ is the duty ratio of S₁. Refer to Figure 4 at any time there are two switches in closed state simultaneously over one switching cycle. While S₁ and S₃ are on, the voltage across L′_m1 is V_Cb1 and thus the amount of current increase can be estimated by

$$\Delta i_{Lm1,S3on}=\frac{V_{Cb1}}{{L^{\prime }}_{m1}}{D}_3{T}_s$$

(2)

In Equation (2), the D₃ denotes the duty ratio of S₃. After S₃ is turned off, switch S₄ will be turned on. That is, the both switches S₁ and S₄ are in on state. The voltage across L′_m1 becomes V_Cb1 − V_Cb2. If V_Cb1 is greater than V_Cb2, the L′_m1 will proceed with current increasing. The increment can be expressed as

$$\Delta i_{Lm1,S3off}=\frac{(V_{Cb1}-V_{Cb2})}{{L^{\prime }}_{m1}}(D_1-D_3)T_s$$

(3)

The switch S₂ will be turned on when switch S₁ is turned off. That is, S₂ and S₄ are in on state simultaneously and the voltage across L′_m1 is −V_Cb2. The current flowing through L′_m1 decreases, which is given by

$$\Delta i_{Lm1,S1off}=\frac{V_{Cb2}}{{L^{\prime }}_{m1}}(1-D_1)T_s$$

(4)

In steady state, the net current change on L′_m1 is equal to zero. From Equations (2)–(4), the following relationship can be derived

$$\frac{V_{Cb1}}{{L^{\prime }}_{m1}}{D}_3{T}_s+\frac{(V_{Cb1}-V_{Cb2})}{{L^{\prime }}_{m1}}(D_1-D_3)T_s-\frac{V_{Cb2}}{{L^{\prime }}_{m1}}(1-D_1)T_s=0$$

(5)

Substituting Equation (1) into Equation (5) becomes

$$V_{Cb2}=\frac{D_1}{(1-D_1)(1-D_3)}{V}_L$$

(6)

The output voltage V_H = V_Co1 + V_Co2, which can be also obtained from

$$V_H=n(V_{Cb1}+V_{Cb2})$$

(7)

Therefore, the conversion ratio of output voltage to input voltage in step-up mode, M_step-up, can be found by

$$M_{step-up}=\frac{V_H}{V_L}=\frac{n(1+D_1-D_3)}{(1-D_1)(1-D_3)}$$

(8)

As referring to the switching sequence in step-up mode, during the interval that S₂ and S₄ are open but S₁ and S₃ are closed, the S₂ and S₄ endure the voltages of V_Cb1 and V_Cb2, respectively. After the above switch status, S₂ and S₃ will be open but S₁ and S₄ are closed. The blocking voltages at S₂ and S₃ are V_Cb1 and V_Cb2, respectively. The switch status that S₁ and S₃ are off but S₂ and S₄ are on proceeds the converter operation. The voltages across S₁ and S₃ in this time interval are also V_Cb1 and V_Cb2 in turn. In brief, the voltage stresses with respect to S₁, S₂, S₃ and S₄ can be determined as follows:

$$v_{S1-stress}=v_{S2-stress}=\frac{V_L}{1-D_1}$$

(9)

$$v_{S3-stress}=v_{S4-stress}=\frac{D_1}{(1-D_1)(1-D_3)}{V}_L$$

(10)

At high-voltage side, the switch S₅ will withstand a voltage of at least V_H when the intrinsic diode of S₆ is forward biased. Similarly, S₆ also endures a reverse voltage up to V_H during the interval that the diode D_S6 is on. That is,

$$v_{ds5}=v_{ds6}=\frac{n(1+D_1-D_3)}{(1-D_1)(1-D_3)}{V}_L$$

(11)

With respect to inductance design, the average current carried by magnetic component has to be calculated in advance. For L′_m1, the application of amp-second balance criterion (ASBC) at C_b2 can give an assistance to the finding for the average of i_Lm1. The C_b2 charges during the time interval [t₅, t₆], in which S₁ and S₄ are in on state. On the contrary, C_b2 discharges during [t₈, t₉], while S₂ and S₄ are closed. The charging current of C_b2 is equal to i_Lm1 and discharging current will be i_Lm1 + ni_ds5. Thus, the following relationship holds:

$$i_{Lm1}(D_1-D_3)T_s+(i_{Lm1}-\frac{n}{1-D_1}{i}_H)(1-D_1)T_s=0$$

(12)

From Equation (12), the average current carried by L′_m1 can be given as

$$I_{Lm1}=\frac{n}{1-D_3}{I}_H$$

(13)

If the voltage across C_b1 is close to V_Cb2, the current i_Lm1 can be regard as constant in Stage 6. This phenomenon can be found in Figure 4. Assume that L′_m1 is in BCM. The following relationship can be found:

$$\frac{[(D_1-D_3)T_s+T_s]\frac{V_{Cb1}}{{L^{\prime }}_{m1}}{D}_3{T}_s}{2T_s}=\frac{n}{1-D_3}{I}_H$$

(14)

Solving for L′_m1 results:

$${L^{\prime }}_{m1,min}=\frac{D_3{(1-D_3)}^2{R}_H}{2n^2{f}_s}$$

(15)

where L′_m1,min is the minimum inductance of L′_m1 for CCM operation, R_H stands for load resistance at high-voltage side, and f_s is switch frequency.

To determine the minimum inductance of L₁, L_1,min, for CCM operation, average current of i_L1 has to be contacted. This average current can be found by applying ASBC to C_b1. Capacitor C_b1 charges during the time interval [t₇, t₉], in which both switches S₂ and S₄ are closed. There are two intervals to discharge the energy in C_b1. One is [t₂, t₄], in which S₁ and S₃ are closed, and the other is and [t₄, t₇], in which S₄ and S₁ are in on state. Based on ASBC, the following relationship holds:

$$(-\frac{n}{D_3}{i}_H-i_{Lm1})D_3{T}_s+i_{Lm1}(D_3-D_1)T_s+i_{L1}(1-D_1)T_s=0$$

(16)

Using Equation (13) and substituting for i_Lm1, the average current flowing through L₁ can be represented as

$$I_{L1}=\frac{n(1+D_1-D_3)}{(1-D_1)(1-D_3)}{I}_H$$

(17)

The current increment on L₁, Δi_L1, is estimated by

$$\Delta i_{L1}=\frac{V_L}{L_1}{D}_1{T}_s$$

(18)

Hence, the minimum of i_L1, I_L1,min, is given by

$$I_{L1,min}=\frac{n(1+D_1-D_3)}{(1-D_1)(1-D_3)}{I}_H-\frac{V_L}{2L_1}{D}_1{T}_s$$

(19)

At BCM, I_L1,min = 0. Solving for L₁ yields

$$L_{1,min}=\frac{D_1{(1-D_1)}^2{(1-D_3)}^2{R}_H}{2n^2{(1+D_1-D_3)}^2{f}_s}$$

(20)

in which L_1,min is the minimum inductance of L₁ for CCM. If R_H = 640 Ω, f_s = 40 kHz, n = 3, and D₁ = D₃. Figure 7a depicts the relationships between inductance L′_m1 and duty ratio D₁ while Figure 7b is for inductance L₁ versus D₁.

3.2. Step-Down Mode

All the assumptions in the above subsection are also adopted for the steady-state analysis in step-down mode. The switches S₂, S₄, and S₅ are controlled simultaneously and complementary to S₆. During the interval that S₆ is in turned-on state and S₂, S₄, and S₅ are in turned-off state, the voltage V_Co1 will directly impose on the high-voltage side of the transformer. Then, the body diodes D_s1 and D_s3 forward conduct and the voltage V_Cb1 will be equal to V_Co1/n. The inductor L₁ supplies energy to V_L. This state will last for D₆T_s. During the interval (1 − D₆)T_s, S₆ becomes off but S₂, S₄, and S₅ are on. The voltage polarity of the coupled inductor at high-voltage side reverses and its magnitude equals V_Co2. In addition, the voltage across inductor L₁ is V_Cb1 − V_L while V_Cb2 equals V_Co2/n. Applying volt-second balance criterion (VSBC) to L₁ yields

$$V_L=(1-D_6)V_{Cb1}$$

(21)

Equation (21) can also be expressed as

$$V_L=\frac{(1-D_6)V_{Co1}}{n}$$

(22)

Similarly, applying VSBC to magnetizing inductor L′_m2, the following relationships can be found:

$$V_{Co1}=(1-D_6)V_H$$

(23)

and

$$V_{Co2}=D_6{V}_H$$

(24)

Substituting Equation (23) into Equation (22) has the result:

$$M_{step-down}=\frac{V_L}{V_H}=\frac{{(1-D_6)}^2}{n}$$

(25)

in which M_step-down stands for the ratio of output to input voltage as in step-down mode. Figure 8a shows the curves of M_step-up versus duty ratio D₁, while M_step-down versus duty ratio D₆ is illustrated in Figure 8b.

The discussion relating to the voltage stresses of the semiconductor devices is followed up. Because the diode D_S1 and switch S₂ conduct complementarily, from the mesh of C_b1-S₁-S₂, it can be found that voltage stress of S₁ is identical to that of S₂ and equals V_Cb1. Similarly, D_S3 and S₄ are in complementary conduction, and the voltage stresses of S₃ and S₄ will be equal to V_Cb2. At high-voltage side, from the outermost loop, S₅-S₆-V_H, the input voltage V_H will impose on S₅ and S₆ alternately. That is, S₅ and S₆ have to stand a voltage of V_H.

The current gain of the converter is a reciprocal of the voltage ratio shown in Equation (25). Therefore, the input current I_H is given by

$$I_H=\frac{{(1-D_6)}^2}{n}{I}_L=\frac{{(1-D_6)}^2{V}_L}{n{R}_L}$$

(26)

where R_L denotes the load resistance at low-voltage side. From Figure 5f, the average current of magnetizing inductance L′_m2 is equals to $\frac{-i_{ds3}}{n}$ − i_ds6, which can be further estimated by

$$I_{Lm2}=\frac{(1-D_6)I_L}{n{D}_6}-\frac{I_H}{D_6}$$

(27)

In addition, the current decrement on L′_m2 over one switching cycle, Δi_Lm2, can be expressed as

$$\Delta i_{Lm2}=\frac{D_6{T}_s{V}_{Co1}}{{L^{\prime }}_{m2}}$$

(28)

Using Equation (23) and Equation (25) to substitute for V_Co1 yields

$$\Delta i_{Lm2}=\frac{D_6{T}_{s}n{V}_L}{(1-D_6){L^{\prime }}_{m2}}$$

(29)

The minimum value of i_Lm2 can be calculated by I_Lm2 − $\frac{\Delta i_{Lm2}}{2}$ and is computed as

$$I_{Lm2,min}=\frac{(1-D_6)V_L}{n{R}_L}-\frac{D_6{T}_{s}n{V}_L}{2(1-D_6){L^{\prime }}_{m2}}$$

(30)

At boundary, I_Lm2,min = 0. Then, solving for L′_m2 can obtain the following relation for determining the minimum inductance for CCM:

$${L^{\prime }}_{m2,min}=\frac{n^2{D}_6{R}_L}{2{(1-D_6)}^2{f}_s}$$

(31)

In order to find the minimum value of L₁ for continuous current operation, L_1,min, the average current of L₁, I_L1, has to be found. The I_L1 is equal to the output current I_L, which is given by

$$I_{L1}=\frac{V_L}{R_L}$$

(32)

The change on inductor current i_L1 can be computed from

$$\Delta i_{L1}=\frac{D_6{T}_s{V}_L}{L_1}$$

(33)

Accordingly, minimum of I_L1 is

$$I_{L1,\min }=\frac{V_L}{R_L}-\frac{D_6{T}_s{V}_L}{2L_1}$$

(34)

Let I_L1,min = 0 and solving for L₁ can obtains:

$$L_{1,min}=\frac{D_6{R}_L}{2f_s}$$

(35)

Assume that R_L is 9.216 Ω, f_s is 40 kHz, and n = 3. Figure 9a depicts the relationship between D₆ and L′_m2, while L₁ versus D₆ is illustrated in Figure 9b.

Figure 10 is the equivalent circuit of proposed converter considering non-ideal parameters, in which r_L1 represents the inductor resistance at the low voltage side and r_ds1, r_ds2, r_ds3, r_ds4, r_ds5, and r_ds6 are the on-state resistance of switches S₁, S₂, S₃, S₄, S₅, and S₆, respectively; and r_lk1 and r_lk2 are the primary winding resistances and the secondary one respectively. By using VSBC and ASBC, the non-ideal voltage conversion ratio M′_step-up and conversion efficiency η_step-up in step-up mode can be obtained as

$${M^{\prime }}_{Step-up}=\frac{-n(-2(1+D_1-D_3)f_s{L}_m+(-1+D_3\left)D_3\right(-2r_{ds4}+(-3+2D_3)r_{lk1}\left)\right)}{2(-1+D_1)(-1+D_3)f_s{L}_m(1+\frac{n^2\left(\right(-1+D_1{)}^2{D}_1{r}_{ds3}+{D_3}^3(r_{ds1}+D_1{r}_{L1})-2{D_3}^2\left(\right(1+D_1)r_{ds1}+D_1(r_{ds2}-D_1{r}_{ds2}+r_{L1}+D_1{r}_{L1}+(-1+D_1{)}^2{r}_{lk1}))+D_3((1+D_1{)}^2{r}_{ds1}+D_1(-3(-1+D_1)r_{ds2}+(1+D_1{)}^2{r}_{L1}+3(-1+D_1{)}^2{r}_{lk1}\left)\right))}{{(-1+D_1)}^2{D}_1{(-1+D_3)}^2{D}_3{R}_H}+\frac{-\frac{r_{ds5}}{-1+D_1}+\frac{r_{ds6}}{D_3}+4r_{lk2}}{R_H})}$$

(36)

$${\eta }_{Step-up}={M^{\prime }}_{Step-up}\left[\frac{(1-D_1)(1-D_3)}{n(1+D_1-D_3)}\right]$$

(37)

In addition, step-down voltage ratio M′_step-down and efficiency η_step-down are estimated by

$${M^{\prime }}_{Step-down}=\left[\frac{{(-1+D_6)}^2{D}_{6}n{R}_L}{{(-1+D_6)}^3(-r_{ds6}+D_6(r_{ds5}+r_{ds6}))+n^2(r_{ds1}+r_{ds3}+r_{lk1}+D_6(r_{ds2}-D_6{r}_{ds2}+(-2+D_6)r_{ds3}+R_L+r_{L1}+(-2+D_6)r_{lk1}))}\right]$$

(38)

$${\eta }_{Step-down}={M^{\prime }}_{Step-down}\left[\frac{n}{{(1-D_6)}^2}\right]$$

(39)

Based on Equations (36) to (39), relationships of voltage gain versus duty ratios D₁ and D₃ in step-up mode are depicted in Figure 11a,b, respectively; meanwhile, so do Figure 11c,d for step-down operation. Figure 12 shows the non-ideal voltage gain in step-up mode under different choke resistances.

Among all power switches, the main switch S₁ will endure the maximum current stress no matter in step-up or step-down mode. Thereby, the current stress determination is focused on S₁. This current stress can be estimated by the sum of the valley current of inductor L₁ and the peak current of leakage inductance L_k1. That is,

$$I_{ds1,peak}=\frac{I_L(2-D_6)}{D_6}-\frac{V_L{D}_6}{2f_s{L}_1}$$

(40)

As for the current stresses of the other active switches in step-down mode, the ASBC should be applied to capacitors C_o1, C_o2, C_b2, and C_b1, which yields

$$I_{ds2,peak}=I_L\frac{2-D_6}{D_6}-\frac{V_L{D}_6}{2f_s{L}_1}$$

(41)

$$I_{ds3,peak}=I_{ds4,peak}=2\frac{I_L(1-D_6)}{D_6}$$

(42)

$$I_{ds5,peak}=I_{ds6,peak}=\frac{I_L(1-D_6)(2+D_6)}{n{D}_6}-\frac{n{D}_6{V}_L}{2(1-D_6)f_s{L^{\prime }}_{m2}}$$

(43)

Similarly, in step-up mode, current stresses of switches can be expressed as

$$I_{ds1,peak}=\frac{n{I}_H\left[2(1-D_1+D_1{D}_3)-{D_3}^2\right]}{D_3(1-D_1)(1-D_3)}+\frac{V_L{D}_3}{2f_s{L}_1}$$

(44)

$$I_{ds2,peak}=n{I}_H\frac{2-D_3}{(1-D_1)(1-D_3)}+\frac{V_L{D}_1}{2f_s{L}_1}$$

(45)

$$I_{ds3,peak}=I_{ds4,peak}=n{I}_H\frac{2-D_3}{D_3(1-D_3)}+\frac{V_L{D}_3}{2f_s{L^{\prime }}_{m1}(1-D_1)}$$

(46)

$$I_{ds5,peak}=\frac{2I_H}{(1-D_1)}$$

(47)

$$I_{ds6,peak}=\frac{2I_H}{D_3}$$

(48)

4. Experimental Results

To validate the proposed BDC, a 1-kW prototype is built with the specifications and components summarized in

Table 2. Specifications and components used in experimentations.

Symbols	Values & Types
VL (Low voltage)	48 V
VH (High voltage)	400 V
Po (Output power)	1 kW
fs (Switching frequency)	40 kHz
L1 (Filter inductance)	46.2 μH
L′m1 (Magnetizing inductance)	130 μH
Lk1 (Leakage inductance)	2.07 μH
Lk2 (Leakage inductance)	18.82 μH
n (Transformer turns ratio)	3
Cb1 and Cb2 (Capacitances)	33 μF
Co1 and Co2 (Capacitances)	220 μF
S1 and S2 (Switches)	IXFH160N15T2
S3 and S4 (Switches)	IXTP160N075T
S5 and S6 (Switches)	IXFH52N50P2

. If a converter operates in discontinuous conduction mode (DCM), it can easily avoid switching loss. However, during the interval of high power loading, serious conduction loss will result in unacceptable efficiency. The proposed converter intrinsically has the outstanding feature of soft switching at all power switches even in CCM. Therefore, we design the converter operation from DCM into CCM at 250-W power loading for overall efficiency consideration. Accordingly, a Toroids 55195-A2 MPP core and an EE-55 core are adopted to form main inductor and coupled inductor, respectively. To make sure the CCM and DCM operate, as mentioned, the main inductance L₁ should be 46 μH and magnetizing inductance L′_m1 is 130 μH with a turns ratio of n = 3.

According to the discussion in Section 3, voltage and current stresses of all active switches can be specified, which offers us a benefit to choose appropriate semiconductor devices for prototype constructing. Since a lower R_ds(on) can achieve a higher conversion efficiency, active switches which meet the power rating and have conduction resistance as low as possible are considered. At low-voltage side, power MOSFETs IXFH160N15T2 with on-state resistance R_ds(on) of 9 mΩ is chosen as S₁ and S₂, while IXTP160N075T with 6 mΩ R_ds(on) as S₃ and S₄. With regard to the active switches S₅ and S₆ at high-voltage side, power MOSFET IXFH52N50P2 is considered, of which R_ds(on) is 0.12 Ω. Microcontroller ATMEGA328P-PU is in charge of the converter controlling. Additionally, PV simulator Chroma 62050H-600S, high voltage power supply IDRC CDSP-500-010C, electronic load Chroma 63202 are adopted for terminal source or load. All waveforms are measured by oscilloscope KEYSIGHT DSOX4024A. Figure 12 shows the voltage and current waveforms measured from switches S₁–S₆, while D₁ = 0.44 and D₃ = 0.3. In Figure 13a, the first trace and second trace are the switch voltage and current of S₁, respectively, whereas the third and fourth traces depict the measurements of S₂. From Figure 13a, it can be found that S₁ endures a voltage of around 100 V. This value is consistent with the estimation in Equation (9). The measured i_ds1 matches the conceptual waveform in Figure 4. In addition, the waveforms of v_ds2 and i_ds2 release that ZCS turn-off feature is achieved at S₂. Figure 13b presents the practical measurements of v_ds3, i_ds3, v_ds4, and i_ds4, which illustrates that both switches S₃ and S₄ can be turned on with ZVS. While operated in step-up mode, S₅ and S₆ of the converter are in the role of rectifier. Figure 13c presents the zoomed-in waveforms of S₁ and S₂, and Figure 13d is for S₃ and S₄. The blocking voltages of v_ds5 and v_ds6 are both equal to 400 V, as shown in Figure 13e, which conforms to the calculation of Equation (11). Figure 13f confirms a stable output and CCM operation in L₁; moreover, the measurements of i_Lk1 and i_Lk2 are consistent with the waveforms in Figure 4.

While operating in step-down mode with D₆ = 0.37, related practical waveforms are shown in Figure 14. From Figure 14a,b, it can be seen that both switches S₁ and S₃ are just in charge of rectifying whereas S₂ and S₄ can accomplish ZCS turn-off feature. Figure 14c reveals that S₅ and S₆ are turned on with ZVS and their voltage stresses are about 400 V. The output voltage at low-voltage side and the currents of L₁, L_k1, and L_k2 are also given in Figure 14d, in which a constant 48 V output and CCM operation in L₁ are illustrated.

Figure 15 depicts measured efficiency of the prototype. The maximum values of the practical efficiency in step-up and step-down modes are up to 95.4% and 93.6%, respectively, while P_o is equal to 1 kW. The efficiency values are measured after 1hr burn-in test and the maximum temperature of all active components is around 56 °C. Figure 16 shows the photo of the prototype, where its length, width, and height are 17.2, 14.6, and 4.2 cm in turn. Therefore, its power density is 948.13 kW/m³. In addition, the converter’s weight is 0.985 kg. That is, specific power is 1.015 kW/kg.

Table 3. Performance comparisons of proposed BDC with other bidirectional DC-DC converters proposed in [25,26,27].

References	[24]	[25]	[26]	[27]	Proposed
Topology	Non-Isolated	Isolated	Isolated	Isolated	Isolated
Voltage conversion ratio in step-up mode (VH/VL)	[(1 + n)/(1 − D)] + n	n	n/(1 − D)	2n/(1 − D)	[n(1 + D1 − D3)]/[(1 − D1)(1 − D3)]
Voltage conversion ratio in step-down mode (VL/VH)	D/(1 + n + nD)	1/n	(1 − D)/n	(1 − D)/2n	(1 − D6)2/n
Output power	200 W	500 W	1 kW	1.5 kW	1 kW
Number of MOSFETs	5	8	4	8	6
Number of diodes	0	0	2	0	0
Number of inductors	0	1	1	0	1
Number of coupled inductors	1	1	1	2	1
Number of capacitors	3	1	4	5	4
Full-load efficiency (Step-up/step-down)	93%/90%	92.4%/91.7%	85%/89%	96.5%/95.8%	94.1%/91%

summarizes the comparison of the proposed converter with other bidirectional converters in [24,25,26,27]. The proposed converter has the better features such as galvanic isolation, soft switching at all switches, no any diode required, and high voltage-ratio conversion. For example, in step-up mode and under the conditions that n = 3 and duty cycle is 0.5 (in addition, D₁ = D₃ in the proposed converter), the proposed one can achieve a much higher voltage gain up to 12 while those in [24,25,26,27] are 11, 3, 6, and 12, respectively. For clearer presentation, the plots to express the comparison result among the mentioned converters are shown in Figure 17. In high conversion ratio converters, current-sharing path structure along with interleaved control can suppress current ripples and then lowers current stress and conduction loss [27,28,29,30]. However, bi-directional power flow controlling or more power components needed are still their demerits.

5. Conclusions

This paper has proposed a high efficiency and high voltage-ratio isolated bidirectional DC-DC converter. A coupled inductor is employed for achieving galvanic isolation, in which the energy stored in leakage inductor can be recycled without additional components. The main contribution of this paper is that voltage stress across semiconductor devices can be lowered by adjusting duty ratio, all power switches can complete soft switching feature in step-up and step-down modes, and higher voltage conversion can inherently be achieved. Because semiconductor device endures low voltage stress, MOSFETs with low R_ds,on can be employed. Unlike conventional converters whose voltage gain is merely determined by a fixed duty ratio, the proposed converter has the ability of compromising the duty ratios of switches at primary side to meet a certain voltage gain and to find an available power component. Operation principle of the circuit and detailed derivation of voltage gain, voltage stress, and current stress are carried out. Finally, experimental results measured from a 1-kW prototype have verified the theoretical analysis and feasibility.