A Short-Current Control Method for Constant Frequency Current-Fed Wireless Power Transfer Systems

Abstract

Frequency drift is a serious problem in Current-Fed Wireless Power Transfer (WPT) systems. When the operating frequency is drifting from the inherent Zero Voltage Switching (ZVS) frequency of resonant network, large short currents will appear and damage the switches. In this paper, an inductance-dampening method is proposed to inhibit short currents and achieve constant-frequency operation. By adding a small auxiliary series inductance in the primary resonant network, short currents are greatly attenuated to a safe level. The operation principle and steady-state analysis of the system are provided. An overlapping time self-regulating circuit is designed to guarantee ZVS running. The range of auxiliary inductances is discussed and its critical value is calculated exactly. The design methodology is described and a design example is presented. Finally, a prototype is built and the experimental results verify the proposed method.

1. Introduction

Wireless Power Transfer (WPT) technology utilizes high frequency magnetic fields to realize energy transfer. This can eliminate the risk of sparks and electrical shocks and make the power transfer process safe and convenient. In recent years, this technology has seen more and more applications in EV charging, biomedical implants and consumer electronics [1,2,3,4,5,6].

Figure 1 illustrates a typical Current-Fed WPT system. A DC voltage source $E_{in}$ and inductance $L_{DC}$ compose a quasi-current source. A parallel resonant network is used on the primary side. The post-circuit contains a resonant network, rectifier, filter and load. Series, parallel or other types of resonant network can be used on the secondary side of a WPT system.

In the above system, the parallel-resonant capacitor $C_P$ has the risk of being shorted by switches. If this happens, a large short current will be generated in the inner loop between the inverter and resonant tank. Mismatch between the Zero Voltage Switching (ZVS) frequency ($f_{ZVS}$) and operation frequency ($f_S$) will lead to a short current. The existence of short currents will damage the switching components and greatly increase the risk of breakdown of the whole system. Generally, a short current is a common phenomenon in the topology shown in Figure 2.

One typical type of application circuit is a high step-up converter [7,8]. In these converters, $C_P$ represents the parasitic capacitance of a high turn-ratio transformer. Another typical application circuit is the parallel resonant converter. The Current-Fed WPT system is a parallel resonant converter.

For a Current-Fed WPT system, frequency drift is an important issue [9,10]. Mutual inductance $M$ and load resistance $R_L$ change dynamically, which means $f_{ZVS}$ cannot be a constant value. Calculation of the ZVS frequency is a complicated and time-consuming process [11,12]. Moreover, real-time load and mutual inductance identification methods also require complex calculations and detection circuits [13,14], so some real-time and simple methods need to be used.

By using a passive zero crossing point detection method such as the ZVS method, operation frequency $f_S$ can keep up with $f_{ZVS}$ in real-time [9,10,15]. However, due to the time lag on the detection route, there exists a mismatch between $f_S$ and $f_{ZVS}$. Other methods including active frequency tracking [16] and the self-oscillating switching technique [17] are also proposed to reduce short currents. A common property of these methods is that the operating frequency $f_S$ is time-variant in order to track $f_{ZVS}$. This makes filter design difficult. Another disadvantage of these methods is the frequency-bifurcation phenomenon [12], which will cause a significant decrease of transferred power.

To eliminate short currents and achieve constant frequency operation simultaneously, the classical method utilizes four blocking diodes placed in series with switches to cut off the loops of short current flows [9], which increases the energy losses and costs.

This paper proposes an inductance damping method for Current-Fed WPT systems. The inductance is connected in series with the parallel resonant network. Short currents are suppressed, while no extra switching component needs to be added. All switches of the inverter are ZVS. Most importantly, the method hardly affects the input and output characteristics of the original Current-Fed WPT system. Operation conditions of the system are discussed, including operation frequency, overlapping time and value of L₁. Based on the conditions, a design methodology is proposed to apply the method to traditional Current-Fed WPT systems.

The rest of this paper is organized as follows: Section 2 briefly introduces the mechanism of short current formation in Current-Fed WPT systems. The proposed inductance damping method is elaborated in Section 3. The circuit and its cyclical switching operation are presented. In Section 4, operating conditions governing the use of the proposed method are listed and explained. An overlapping-time self-regulating circuit is described to satisfy the second operation condition in Section 5. Section 6 discusses the range of $L_1$, and the critical value $L_{1\_cri}$ is calculated exactly. The design procedure and an example are given in Section 7. The experimental results obtained on a 60 W prototype are presented.

2. Mechanism of Short Current

As shown in Figure 1, the voltage source $E_{in}$ and large DC inductor $L_{DC}$ comprise a quasi-current source. Two switching pairs (S1/S4 and S2/S3) operate complementarily to inject a square wave current into the parallel resonant tank (composed of $L_P$ and $C_P$). When the operating frequency $f_S$ equals $f_{ZVS}$, the switching instants are accurate on the zero crossing point of the resonant voltage $u_{C_P}$. The corresponding waveform and circuit are illustrated in Figure 3.

For the resonant network, ZVS frequency $f_{ZVS}$ is close to the zero phase angle resonant frequency $f_r$ [9,11]. Because $f_r$ is easier to calculate than $f_{ZVS}$, $f_{ZVS}$ can be replaced by $f_r$ in the following analysis. $f_r$ is calculated by:

$$Angle\left[Z_{in}(f_r)\right]=0$$

(1)

As illustrated in Figure 1, $Z_{in}$ is the input impedance of the resonant network under the operation frequency $f_S$. Therefore, when $f_S$ equals $f_r$, the resonant network is purely resistant and the short current is eliminated. If $f_S$ drifts away from $f_r$, a frequency drift will happen, and a short current will be generated. According to the different loops of short current, short currents can be divided into two types:

A. Capacitive case, $Angle\left[Z_{in}(f_s)\right]<0$

In this case, the resonant network is resistive-capacitive ($Angle\left[Z_{in}(f_s)\right]<0$) when $f_S$ drifts away from $f_r$. The AC input voltage $u_{C_P}$ is lagging the fundamental harmonic of the AC input current $i_{inv\_out}$. When $i_{inv\_out}$ reverses its direction, $u_{C_P}$ has not reached its zero point. The change of switches’ state generates a path to short $C_P$. As a result, the generated short current is extremely high. The instantaneous short current may damage the switch devices. This is shown in Figure 4a.

Generally, the resonant network is resistant-capacitive when $f_S$ is higher than $f_r$, since a parallel network is used on the primary side. This case is called “higher case”.

B. Inductive case, $Angle\left[Z_{in}(f_s)\right]>0$

Meanwhile, in the inductive case, the resonant network is resistive-capacitive ($Angle\left[Z_{in}(f_s)\right]>0$) when $f_S$ deviates from $f_r$. The AC input voltage $u_{C_P}$ is led to the fundamental harmonic of the AC input current $i_{inv\_out}$. When $u_{C_P}$ reaches its zero point, $i_{inv\_out}$ has not reversed its direction. A loop is generated to clamp $u_{C_P}$ to 0 V. The short current will be clamped to track the current (flowing in $L_P$). The waveform and short circuit in this case are shown in Figure 4b.

Generally, the resonant network is resistant-inductive when $f_S$ is lower than $f_r$. This case is called “lower case” in [16]. From the above analysis, a criterion is proposed to eliminate short currents in circuits that have the same topology as Figure 2:

• When $u_{C_P}>0$, S2 and S3 must remain in an off state.
• When $u_{C_P}<0$, S1 and S4 must remain in an off state.

If the criterion is broken, a short current will appear. Comparing the two cases, the capacitive case is more dangerous to the switching devices because short current in this case is uncontrollable. The inductive case is relatively safe because the short current can be clamped to a certain value (the current flowing in $L_P$).

3. The Proposed Inductance-Damping Method

Figure 5 shows a typical current-fed WPT system topology with the proposed inductance-damping method. Inductor $L_1$ is connected in series with the resonant network. $L_1$ is placed in the loop of the short current and will dampen any high di/dt ratio generated by a short current.

On the primary side, the topology of the proposed circuit is similar to a LCL network, but it works in an absolutely different way. In an LCL network, $L_1$ is a resonant component. However, in the proposed circuit, $L_1$ is not a resonant component. It is used to smooth the short current during the commutation period During the other switching cycle periods, it undertakes the DC current $I_{in}$.

Figure 6 shows the theoretical waveform of the circuit over a steady-state cycle. S1 and S4 are switched with the same pulse, while S3 and S4 are switched with the other pulse. Turn-on signals of S1/S4 and S2/S3 have a phase difference of 180°.

Compared with the PWM pulse in Section 2, the turn-off signals of S1/S4 and S2/S3 are delayed by $T_{ov}$. That is, an overlap time $T_{ov}$ is added to the PWM sequence, which means each switch is in the on state during the period. In addition, to guarantee the generation of a short current in the capacitive case, the frequency of the PWM frequency $f_S$ must satisfy:

$$Angle\left[Z_{in}(f_S)\right]<0$$

(2)

Generally, $f_S$ need to be higher than $f_r$ to satisfy (2). Since operation and the waveform under steady state conditions are symmetrical in every half cycle, the equivalent circuit of every operation mode between $t_0$ and $t_5$ is illustrated in Figure 7.

Normally due to the frequency selection ability of the resonant network, the voltage of $C_P$ can be considered as its fundamental component. When $t_0$ is selected as the origin of a cycle, $u_{C_P}$ can be represented as:

$$u_{C_P}(t)=V_{C_P\_m}\sin (\omega t-\omega t_3)$$

(3)

where $\omega =2\pi f_S$.

A. Mode 0: Before $t_0$, Figure 7a

In the mode, S2 and S3 are in the on state, S1 and S4 are in the off state. The voltage of S1 and S4 is equal to the absolute value of $u_{C_P}$. The current flowing through $L_1$ ($i_{L_1}$) is equal to $-I_{in}$.

B. Mode 1: $t_0-t_4$, Figure 7b, Overlapping Period/Commutation Period

In this mode, $i_{L_1}$ changes its direction smoothly, and no voltage spike is generated. At $t_0$, S1 and S4 turn on, and the four switches are all on. This means the resonant network and power supply are in the short mode. $C_P$ is connected in parallel with $L_1$. So:

$$\begin{array}{l}{u}_{inv\_out}=0\\ u_{L_1}(t)=L_1\frac{d{i}_{L_1}(t)}{dt}=-u_{C_P}(t)\end{array}$$

(4)

Because $u_{C_P}$ is negative, the current of $L_1$ starts to increase from $-I_{in}$ to positive:

$$i_{L_1}(t)={\displaystyle {\int }_{t_0}^t\frac{-u_{C_P}(t)}{L_1}}\cdot dt-I_{in}=V_{C_P\_m}\frac{\cos (\omega t-\omega t_3)-\cos (-\omega t_3)}{\omega L_1}-I_{in}$$

(5)

In the mode, the current flowing in each switch is the combination of the input current $I_{in}$ and short current $i_{L_1}$. We have:

$$\begin{array}{l}{i}_{S1}=i_{S4}=\frac{I_{in}}{2}+\frac{i_{L_1}}{2}\\ i_{S2}=i_{S3}=\frac{I_{in}}{2}-\frac{i_{L_1}}{2}\end{array}$$

(6)

As can be seen in Figure 6, current flows through S1 and S4, $i_{S1}/i_{S4}$ increases from 0 to positive gradually after $t_0$. Therefore, S1 and S4 turn on with ZCS.

At $t_1$, $i_{L_1}$ crosses the zero point.

At $t_2$, $i_{L_1}$ increases to $I_{in}$, and $i_{S2}/i_{S3}$ decreases to 0. After $t_2$, $i_{L_1}$ is higher than $I_{in}$. It means $i_{S2}/i_{S3}$ is reversed to negative.

At $t_3$, $u_{C_P}$ is equal to 0, $i_{L_1}$ reaches its peak and starts to decrease:

$$i_{L_1\_m}=i_{L_1}(t_3)=V_{C_P\_m}\frac{1-\cos (-\omega t_3)}{\omega L_1}-I_{in}$$

(7)

At $t_4$, $i_{L_1}$ decreases to $I_{in}$, and S2/S3’s anti-parallel diodes turn off.

When S2 and S3 turn off between $t_2$ and $t_4$, the reversed $i_{\mathrm{S}2}/i_{\mathrm{S}3}$ current will flow through their anti-parallel diodes. As a result, S2 and S3 can turn off with ZVS, so the switches’ overlap time $T_{ov}$ should satisfy:

$$\left(t_2-t_0\right)<T_{ov}<\left(t_4-t_0\right)$$

(8)

C. Mode 2: $t_4-t_5$, Figure 7c, Energy-input Period

In this mode, $i_{L_1}$ is equal to the input current $I_{in}$ and stays constant. Considering the inductor $L_1$ is usually designed small, $u_{inv\_out}$ is nearly equal to $u_{C_P}$. Thus energy from $E_{in}$ is input to the resonant network. Operation in the remaining half switching cycle is symmetrical to the previous four operation modes. Therefore, the four switches S1–S4 can all turn on with ZCS and turn off with ZVS.

4. Steady-State Analysis and Operation Conditions

4.1. Steady-State Analysis

Because of the high order and resonant characteristics, the accurate steady state model becomes extremely complex and is not suitable for design. The paper proposes an approximate modeling method by ignoring the short overlap time in a cycle. The detailed analysis is as follows:

Since $u_{C_P}$ can be considered as a standard sinusoid, the system can be divided into two parts, the switching network and the resonant network. As illustrated in Figure 8, for the switching part, the post-circuit can be regarded as an AC load $u_{C_P}$; for the resonant part, the pre-circuit can be regarded as an AC source $u_{C_P}$.

As shown in Figure 6, during the first half cycle, $u_{inv\_out}$ can be written as:

$$u_{inv\_out}=\{\begin{array}{c}0\\ V_{C_P\_m}\sin (\omega t-\omega t_3)\end{array}\begin{array}{c}{t}_0\le t<t_4\\ t_4\le t\le t_5\end{array}$$

(9)

Output power of power supply can be derived:

$$P_{\mathrm{supple}\_in}=E_{in}\cdot I_{\mathrm{in}}$$

(10)

Output power of inverter is:

$$\begin{array}{l}{P}_{inv\_out}=\frac{2}{T}{\displaystyle {\int }_{t_0}^{t_5}{i}_{L_1}}{u}_{inv\_out}\cdot dt=\frac{2}{T}{\displaystyle {\int }_{t_4}^{t_5}{I}_{in}}{V}_{C_P\_m}\sin \left(\omega t-\omega t_3\right)\cdot d\theta \\ =\frac{1}{\pi }{I}_{in}{V}_{C_P\_m}\cdot \left[\cos \left(\omega t_4-\omega t_3\right)-\cos \left(\pi -\omega t_3\right)\right]\end{array}$$

(11)

Considering that most of the power is transferred by the fundamental harmonics, the input power of resonant network can be derived:

$$P_{res\_in}=\frac{V_{Cp\_m}^2}{2}\cdot \frac{\cos \theta }{\left|Z_{in}\right|}$$

(12)

Phase difference $\theta$ between $u_{inv\_out}$ and fundamental harmonic of $i_{L_1}$ is the same as the impedance angle of resonant network ($Z_{in}$):

$$Z_{in}=\left(j\omega L_P+\frac{{\omega }^2{M}^2}{Z_S}\right)//\frac{1}{j\omega C_P}=\frac{1}{\frac{1}{\left(j\omega L_P+\frac{{\omega }^2{M}^2}{Z_S}\right)}+j\omega C_P}$$

(13)

In (13), $Z_S$ is the impedance of circuit in secondary side, which is relative to the resonant network and load. Compared with the switching period $T$, the short overlap time between $t_0$ and $t_4$ can be ignored. Thus, $t_3\approx t_4\approx 0$, (11) and (12) can be simplified:

$$P_{inv\_out}=\frac{2}{\pi }{I}_{in}{V}_{C_P\_m}$$

(14)

Ignoring the loss of $L_{DC}$, inverter and $L_1$, we have:

$$P_{\mathrm{supple}\_in}=P_{inv\_out}=P_{res\_in}$$

(15)

Using (10), (12), (14) and (15), we have:

$$I_{in}=\frac{{\pi }^2{E}_{in}}{8}\frac{\cos \theta }{\left|Z_{in}\right|}$$

(16)

$$V_{C_P\_m}=\frac{\pi }{2}{E}_{in}$$

(17)

$$P_{res\_in}=\frac{{\pi }^2{E}_{in}^2}{8}\cdot \frac{\cos \theta }{\left|Z_{in}\right|}$$

(18)

Equations (17) and (18) can be used to consider the voltage and current stress of switches and passive components. Equation (19) can be used to approximately calculate the power that is transferred to the load.

4.2. DC Voltage Gain

In the system, input-output voltage gain ($G_v$) can be divided into two parts: voltage gain of the inverter and voltage gain of the rest circuit. Voltage gain of the inverter is derived by:

$$G_{v1}=\frac{V_{C_P\_m}}{E_{in}}=\frac{\pi }{\cos \left(\omega t_4-\omega t_3\right)-\cos \left(\pi -\omega t_3\right)}$$

(19)

When $t_3$ and $t_4$ are small enough, (19) is simplified:

$$G_{v1}=\frac{\pi }{2}$$

(20)

Voltage gain of the rest circuit is related to the circuit in secondary side. In Section 7, input-output voltage gain of the experimental system is derived.

4.3. Operation Condition

In order to achieve the expected operation in the proposed circuit, three conditions need to be guaranteed.

4.3.1. Operation Frequency $f_S$

Since the proposed method in the paper is applied to reduce the short current in the capacitive case, $Z_{in}$ must be resistive-capacitive. Thus, $f_S$ needs to satisfy (2) under all load and all mutual inductance conditions, from rated load to light load and from rated coupling to lighter coupling. Generally, when $f_S$ is higher than $f_r$, Equation (2) is satisfied.

If $Z_{in}$ is resistive-inductive (generally when $f_S<f_r$), the peak value of short current will be suppressed in this situation because of the damping of $L_1$. However, switches will sustain high voltage spikes during the switching time to change the direction of $i_{L_1}$, so this is not a normal operation mode.

4.3.2. Duty Ratio of PWM Pulses

S2 and S3 must turn off between $t_2$ and $t_4$ to guarantee ZVS running. That is, the two switches needs to turn off during the period when $i_{L_1}$ is higher than $I_{in}$. The duty ratio of PWM pulses need to satisfy:

$$\begin{array}{c}D=0.5+\frac{T_{ov}}{T}\\ 0.5+\frac{t_2-t_0}{T}<D<0.5+\frac{t_4-t_0}{T}\end{array}$$

(21)

It is complex to calculate the exact value of $t_2-t_0$ and $t_4-t_0$ because the system is under resonant state. Moreover, when load and mutual inductance vary, $t_2-t_0$ and $t_4-t_0$ are changed. It means the final D needs to satisfy (21) under all load and mutual inductance condition. A simple strategy is used to satisfy the condition in all load and inductance conditions, which is carefully described in Section 5.

4.3.3. Value of $L_1$

Peak value of $i_{L_1}$ must be higher than input current $I_{in}$ to guarantee that the two switches turn off with ZVS. If $L_1$ is too large, the peak value of $i_{L_1}$ during the commutation period is lower than $I_{in}$. In the case, $i_{L_1}$ has to hop from a value to $I_{in}$ in the turn-off transition of the two switches. Large voltage spikes are imposed on the switches. Figure 9 shows system’s waveforms in this situation. Fortunately, because of the existence of the Collector-to-Emitter capacitor $C_{CE}$ in switches and junction capacitors in their anti-parallel diodes, the peak value of the voltage will be suppressed. This is because the parasite capacitor can absorb the high voltage spike and make the voltage transient smoother. The critical value of $L_1$ is calculated in Section 6.

If the above conditions are satisfied, the short current can be dumped and switch voltage spike he will be eliminated.

5. Overlapping Time Self-Regulating Circuit

The turn-off time of the two on-state switches must happen between $t_2$ and $t_4$ to satisfy the second condition listed in Section 4. An automatic overlapping-time regulator is proposed to guarantee the turn-off time happens between $t_2$ and $t_4$. Because $\left|t_2-t_0\right|$ and $\left|t_4-t_0\right|$ is short (usually below 1 μs), the regulating circuit should be extremely fast.

In this paper, a simple but effective implement is fabricated based on the principle pointed in Section 3. When $i_{L_1}$ reach its peak at $t_3$, $u_{C_P}$ will definitely cross its zero point, and $t_3$ must be between $t_2$ and $t_4$. If the switch can turn off at the moment when $u_{C_P}$ crosses the zero point, soft commutation can be achieved. In implementation, only a high-speed zero-crossing comparator is needed to detect the moment when $u_{C_P}$ crosses the zero point. The implementation diagram that automatically regulates the overlapping-time is shown in Figure 10.

Considering time delay in the zero-crossing comparator and driver, a phase-lead compensator is used to compensate the time delay. Two phase-lead networks are generally used in practice [18], which is also shown in Figure 10. Network 1 is used in the experimental circuit to compensate the time delay.

6. Range of L₁ and the Critical Value

In the proposed system, $L_1$ is an important circuit component. The value of $L_1$ must be considered carefully. During the commutation period, if $L_1$ is too large, the peak value of $i_{L_1}$ is lower than $I_{in}$ and soft commutation fails. If $L_1$ is too small, the peak value of $i_{L_1}$ is too high to damp the short current. Therefore, the range of $L_1$ needs to be ascertained, and the boundary value of $L_1$ needs to be calculated exactly. The proper value of $L_1$ needs to be considered based on that.

A special operation situation (the critical mode) of the system is observed and used to confirm range of $L_1$.In the critical mode, peak value of $i_{L_1}$ equals to $I_{in}$. Value of $L_1$ in this situation is the boundary value of $L_1$—called $L_{1\_cri}$. Waveform of the critical mode is shown in Figure 11.

In the critical mode, $t_2=t_3=t_4$.

$i_{L_1}$ during the commutation period is derived by:

$$\begin{array}{l}{u}_{L_1}(t)=-u_{C_P}(t)=L_{1\_cri}\frac{d{i}_{L_1}(t)}{dt}\\ i_{L_1}(t)={\displaystyle {\int }_{t_0}^t\frac{-u_{C_P}(t)}{L_{1\_cri}}}\cdot dt-I_{in}=V_{C_P\_m}\frac{\cos (\omega t-\omega t_3)-\cos (-\omega t_3)}{\omega L_{1\_cri}}-I_{in}\end{array}$$

(22)

At $t_3$, $u_{C_P}$ is equal to zero and $i_{L_1}$ reaches its peak value:

$$i_{L_1\_m}=V_{C_P\_m}\frac{1-\cos (\omega t_3)}{\omega L_1}-I_{in}=I_{in}$$

(23)

During the first half cycle, $i_{L_1}$ can be written as:

$$i_{L_1}(t)=\{\begin{array}{c}{V}_{C_P\_m}\frac{\cos (\omega t-\omega t_3)-1}{\omega L_{1\_cri}}+I_{in}\\ I_{in}\end{array}\begin{array}{c}0\le t<t_3\\ t_3\le t\le t_5\end{array}$$

(24)

In the second half cycle, $i_{L_1}$ is the negative value of the first half cycle. So the fundamental component of $i_{L_1}$ ($i_{L_1,fun}$) is derived by Fourier series, we have:

$$\begin{array}{l}{i}_{L_1,fun}=A\cos \omega t+B\sin \omega t=\sqrt{A^2+B^2}\sin \left(\omega t+\phi \right)\\ A=\frac{4}{T}{\displaystyle {\int }_0^{\frac{T}{2}}{i}_{L_1}\cos }\omega t\cdot dt\\ B=\frac{4}{T}{\displaystyle {\int }_0^{\frac{T}{2}}{i}_{L_1}\sin }\omega t\cdot dt\\ \tan \phi =\frac{A}{B}\end{array}$$

(25)

$\phi$ is the phase angle of $i_{L_1,fun}$, which takes $t_0$ as a reference.

Then we have:

$$\begin{array}{c}Angle[u_{C_P}]-Angle[i_{L_1,fun}]=Angle[Z_{in}]\\ \omega t_3-\phi =\theta \end{array}$$

(26)

In the mode, (11) is simplified:

$$P_{inv\_out}=\frac{1}{\pi }{I}_{in}{V}_{C_P\_m}\cdot \left[1+\cos \left(\omega t_3\right)\right]$$

(27)

Equations (15) and (27) make up a simultaneous equation set. Thus, $L_{1\_cri}$, $t_3$ and $V_{Cp\_m}$ can be calculated by a numerical algorithm simultaneously.

$L_1$ must be lower then to satisfy the third operation condition, so we have:

$$L_1<L_{1\_cri}$$

(28)

A value of $L_1$ that is slightly lower than $L_{1\_cri}$ is suitable, since the operation conditions are satisfied while performance of the proposed method is guaranteed.

7. Design Procedure, Example and Measurements

7.1. Design Flowchart

When applying the proposed method to a traditional Current-Fed IPT system, $f_S$ and $L_1$ need to be considered. The criterion of choosing $f_S$ and $L_1$ is that the system must operate normally when resonant components and loads vary. The design procedure is shown in Figure 12.

7.2. Design Example

A 60 W experimental system was built using the proposed method. Its parameters are listed in

Table 1. Parameters of the experimental system.

Parameter	Value
Ein	60 V
LDC	2.23 mH
RLDC	0.19 Ω
LP	29.89 µH
RLP	0.058 Ω
CP	0.528 µF
M	11.53 µH (rated)
LS	60.59 µH
RLS	0.093 Ω
CS	0.37 µF
CO	220 µF
RL	10 Ω (rated)

. The new system is designed using the strategy in Figure 12.

In the experimental system, the series network used on the secondary side is taken as an example, as illustrated in Figure 13. It must be mentioned that application of the proposed method is irrelevant to the type of network used on the secondary side. Moreover, the type of network on the secondary side is irrelevant to the analysis approach and design methodology.

In the circuit:

$$Z_S=j\omega L_S+\frac{1}{j\omega C_S}+Z_o$$

(29)

$Z_o$ is the equivalent AC impedance of the rectifier and its post-circuit, which can also be regarded as the AC equivalent AC load of the system. Generally, the equivalent load is considered to be purely resistant, and $Z_o$ is calculated by:

$$Z_o=\frac{8}{{\pi }^2}{R}_L$$

(30)

The input-output voltage gain ($G_v$) of the experimental system can be divided into three parts: voltage gain of the inverter, voltage gain of the resonant network and voltage gain of rectifier. Voltage gain of inverter has been given in (20). Voltage gain of the resonant network is derived by:

$$G_{v2}=\frac{V_{rec\_1\_m}}{V_{C_P\_m}}=\frac{j\omega M}{\left(j\omega L_P+R_{L_P}\right)+\frac{\left(j\omega L_P+R_{L_P}\right)\left(j\omega L_S+R_{L_S}+\frac{1}{j\omega C_S}\right)+{\omega }^2{M}^2}{Z_O}}$$

(31)

$V_{rec\_1\_m}$ is peak value of the fundamental component of the rectifier’s input voltage $u_{rec}$.

When $Z_o$ is large enough and $R_{L_P}$ is small enough, Equation (33) is simplified:

$$G_v{}_2=\frac{M}{L_P}$$

(32)

The voltage gain of the rectifier and filter is:

$$G_{v3}=\frac{V_o}{V_{ref\_1\_m}}=\frac{\pi }{4}$$

(33)

Thus, the voltage gain of the whole system is derived:

$$G_v=G_{v1}\cdot G_{v2}\cdot G_{v3}=\frac{{\pi }^2}{8}\frac{M}{L_P}$$

(34)

Equation (34) shows that the voltage gain of the whole system is independent of the load $R_L$ and $f_S$ when $R_L$ is large enough and $R_{L_P}$ is small enough. However, the calculation result of the above model has a big error when calculating $L_{1\_cri}$ using the equation set in Section 6. Since there exists some distortion in the secondary current $i_S$, the equivalent load $Z_o$ cannot be regarded as a pure resistance and simply calculated using Equation (30). Based on the extended fundamental frequency analysis method [19], a more accurate $Z_o$ is derived:

$$Z_o=\frac{8L_S{R}_L\omega }{-j({\pi }^2-8)R_L+L_S{\pi }^2\omega }$$

(35)

Replacing (30) with (35), the exact value of $L_{1\_cri}$ can be obtained.

The relationship between $f_S$ and $Angle\left[Z_{in}\right]$ of the experimental system is drawn in Figure 14. The zero phase angle resonant frequencies $f_r$ for different loads and mutual inductance conditions are all near 40 kHz. When $f_S$ is chosen to be higher than 40 kHz, $Angle\left[Z_{in}\right]$ are all negative under different load conditions. 41 kHz is chosen to be the operation frequency since $Angle\left[Z_{in}\left(41\mathrm{kHz}\right)\right]$ remains negative when the load changes from heavy to light ($R_L$ increases continuously) and the mutual inductance changes from the rated coupling to loose coupling.

Next, the proper value of $L_1$ is considered. The first thing is calculating $L_{1\_cri}$ at the rated load and coupling ($R_L=10\mathsf{\Omega },M=11.53\mathsf{\mu }\mathrm{H}$). In this case, $L_{1\_cri}=6.86\mathsf{\mu }\mathrm{H}$.

Then calculate $L_{1\_cri}$ when $M$ and $R_L$ vary. The results are shown in Figure 15. When $R_L$ varies from rated load to light load, the correspondent $L_{1\_cri}$ increases monotonously. When the mutual inductance $M$ varies from rated coupling to weak coupling, the corresponding $L_{1\_cri}$ increases monotonously. Therefore, if $L_{1\_cri}$ is equal to or lower than 6.87 μH, the third operating condition will be naturally achieved when $R_L$ and $M$ vary.

Considering the error of measurement and modeling, $L_1$ needs to be smaller than 6.86 μH to guarantee the third operating condition. In this experimental system, the value of $L_1$ is 3.85 μH.

7.3. Experiment and Performance

A proposed 60 W Current-Fed WPT prototype is built to verify the method. The experimental system is set up as shown in Figure 13. The switching components used are IGBT FGA25N120ANTD and STPS20120D diodes. The driving signals are produced by a TMS320X2812 DSP. Photos of the prototype system are shown in Figure 16 and Figure 17.

Figure 18 shows a comparison of the measured waveforms at rated load. Short currents are greatly damped in the system with the proposed method. The peak value of the short current in a traditional system is several times higher than $I_{in}$, while the short current in the system with the proposed method is kept at a very low level.

Due to parasitic capacitance in the switches and junction capacitors in their anti-parallel diode, a current oscillation exists in $i_{L_1}$ after t4. Figure 18c illustrates the waveform of the system with the proposed approach when $L_1$ = 6.40 µH. In this situation, the peak value of the short current is nearly equal to I_in, which verifies the accuracy of the model in Section 6. As shown in Figure 18b, 3.45 µH is a proper value of $L_1$, so in the remaining experiments, $L_1$ is chosen to be 3.45 µH.

Detailed waveforms of the proposed system are shown in Figure 19. As described in Section 5, the switches turn off in the zero-crossing point of u_Cp. The overlap time Tov is regulated automatically and the operation conditions are satisfied.

Figure 20 shows waveforms of one switch. During the turn-on time, the current of switch i_S equals to 0 and slowly increases, which means ZCS is achieved. At turn-off time, the voltage of the switch u_Cp remains at zero and ZVS are achieved. Because of these excellent properties, loss of switching devices in the system can be greatly reduced, that is, the efficiency will be enhanced. When the distances of L_P and L_S increase, the system still operates normally, as shown in Figure 21.

To verify the theoretical model, a set of experimental data was measured. The experimental and theoretical voltage gains are compared in Figure 22.

The efficiency of traditional parallel WPT system and new WPT system is compared in Figure 23. During large load variation, efficiency of proposed system is always higher than traditional system due to short current is effectively controlled.

8. Conclusions

Short currents occur in WPT systems when the operation frequency drifts from the inherent frequency of the resonant network. This phenomenon is quite dangerous for switching components and other circuit components. This paper proposes a novel method, named inductance-damping method, based on utilizing an additional small inductance to inhibit short currents. Steady-state mode and operating conditions are analyzed. An overlapping time regulation circuit is given and the range of $G_v$ is discussed. The system design procedure is described and a design example is discussed. The experimental waveforms and data are given to verify the method. Furthermore, this method can be extended to Current-Fed full-resonant converters.