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Appl. Sci. 2018, 8(8), 1341; doi:10.3390/app8081341
Charge Carrier Distribution in Low-Voltage Dual-Gate Organic Thin-Film Transistors
Research Center for Organic Electronics (ROEL), Yamagata University, 4-3-16 Jonan, Yonezawa, Yamagata 992-8510, Japan
Yokohama R&D Center, Mitsubishi Chemical Corporation, 1000 Kamoshida-cho, Aoba-ku, Yokohama, Kanagawa 227-8502, Japan
Authors to whom correspondence should be addressed.
Received: 13 July 2018 / Accepted: 8 August 2018 / Published: 10 August 2018
Organic Integrated Circuits.
Dual-gate organic thin-film transistors (DGOTFTs), which exhibit better electrical properties, in terms of on-current and subthreshold slope than those of single-gate organic thin-film transistors (OTFTs) are promising devices for high-performance and robust organic electronics. Electrical behaviors of high-voltage (>10 V) DGOTFTs have been studied: however, the performance analysis in low-voltage DGOTFTs has not been reported because fabrication of low-voltage DGOTFTs is generally challenging. In this study, we successfully fabricated low-voltage (<5 V) DGOTFTs by employing thin parylene film as gate dielectrics and visualized the charge carrier distributions in low-voltage DGOTFTs by a simulation that is based on finite element method (FEM). The simulation results indicated that the dual-gate system produces a dual-channel and has excellent control of charge carrier density in the organic semiconducting layer, which leads to the better switching characteristics than the single-gate devices.
Keywords:organic transistor; dual-gate; carrier distribution; simulation
Organic thin-film transistors (OTFTs) have been attracting attention in the field of flexible and printed electronics. OTFTs have intrinsic mechanical flexibility due to the loose van der Waals force between organic molecules, and can be fabricated on flexible plastic films by a low temperature printing method. Ink-jet printing provides for drop-on-demand fabrication from digital data and can directly pattern customizable elements on a substrate. These features are ideal for large-are electronic applications, including a flexible sensor sheet  and radio frequency identification (RFID) tags .
Towards improving the OTFT device performances, in terms of on-current (ION) and subthreshold slope (SS), the transistor channel length (L) and gate dielectric thickness have been scaled down [3,4]. Dual-gate (DG) architecture which has both bottom-gate (BG) and top-gate (TG) electrode is also known as a way to get a higher current and a steeper subthreshold slope than those from single-gate architecture commonly employed [5,6]. This DG architecture also enables control of threshold voltage (VTH) of the OTFTs . These features are significant for realizing high-performance and robust organic electronics [8,9,10,11,12,13,14,15].
Operation analysis of low-voltage dual-gate organic thin-film transistors can be significant, since low-voltage OTFTs have specific issues that is less significant in high-voltage, for example, contact resistance which is associated with gate-voltage . The electrical behaviors of dual-gate organic transistors (DGOTFTs) have been studied, including its analytical model [17,18], contact resistance , charge transport and back-gate-bias effects . However, these studies are based on OTFTs that were operated at high-voltage (>10 V): the operation analysis in low-voltage (<5 V) DGOTFTs is never reported. This possible reason is that fabrication of low-voltage DGOTFTs is generally challenging because vertical multi-layer-stacking of thin gate dielectric layers would be required.
In this study, charge carrier distribution in low-voltage OTFTs with BG, TG, and DG architecture was reported. Low-voltage DGOTFTs were successfully fabricated by employing 140-nm-thick parylene film as gate dielectrics formed by chemical vapor deposition (CVD). Numerical simulation of the carrier distribution was carried out based on a finite element method (FEM). The charge carrier distributions were successfully imaged. The simulation results indicated that DG system produces a dual-channel and has excellent control of charge carrier density in the organic semiconducting layer, which leads to the better switching characteristics of the OTFTs than the single-gate devices.
2. Materials and Methods
2.1. Device Fabrication
Schematic structure and photograph of the fabricated OTFT devices are shown in Figure 1. Single- and dual-gate OTFTs were integrated on a glass substrate, as shown in Figure 1a,b. Note that for the DG devices, the bottom- and top-gate electrode was connected each other. All layers except the gate dielectrics were formed by printing processes at process temperatures below 150 °C [21,22]. 140-nm-thick parylene films that were formed by chemical vapor deposition (CVD) were used as the gate dielectric and encapsulation layer. Parylene is good for low-voltage operation due to its low trap density  and fine thin-film formation . The electrodes were fabricated by inkjet printing of a silver nanoparticle ink. Formation of the short-channels was enabled by separate printing of the source/drain electrodes as reported . In this work, the standard deviation in channel length was ±2 µm. A printed fluoropolymer layer was used as a confining bank layer, whereby the semiconducting layer was printed in the area defined by the bank layer using dispenser equipment. These device fabrication processes used drop-on-demand printing techniques such as ink-jet printing and dispenser printing for ease of the layout customization.
Cross-linked poly(4-vinyl-phenol) (PVP) was formed on 0.5-mm-thick glass substrates to modify the surface wettability. PVP (MW ≈ 25,000, Sigma-Aldrich, St. Louis, MI, USA) and poly(melamine-co-formaldehyde) (MN ≈ 432.84 wt %, Sigma-Aldrich, St. Louis, MI, USA) were dissolved in propylene glycol monomethyl ether acetate (PGMEA), and spin-coated onto the substrates, followed by annealing process at 150 °C for 30 min. in ambient air to produce thermal-crosslinking. Next, a silver nanoparticle ink in hydrocarbon-based solution (NPS-JL, Harima Chemicals, Chuo-ku, Tokyo, Japan) was printed as bottom-gate electrodes using an inkjet printer (DMP2831, Fujifilm Dimatix, Santa Clara, CA, USA) with 10 pl nozzles. During the inkjet printing process, the substrates and cartridge were kept at 50 and 40 °C, respectively. The substrates were then heated at 150 °C for 15 min. in ambient air to sinter the silver nanoparticles. A 140-nm-thick parylene (diX-SR, KISCO, Tokyo, Japan) gate dielectric layer was then formed by chemical vapor deposition. Source and drain electrodes were subsequently printed in the same manner as the gate electrodes. The conditions of S/D printing and sintering process were same as those for the gate electrodes. Fluoropolymer (DuPont, Teflon AF1600) bank layers (70 nm thick) were then printed using a dispenser system (MUSASHI Engineering, Image Master 350 PC) at a pattering speed of 20 mm∙s–1 and with a discharge pressure of 6 kPa. During the dispensing process, the plates and nozzle temperatures were kept at 60 and 30 °C, respectively. A p-type donor-acceptor polymer semiconductor ink (0.03 wt %, mesitylene solvent, Mitsubishi Chemical, MOP-01) was then printed onto the area defined by the bank layer by the dispenser system at a patterning speed of 20 mm∙s−1 and discharge pressure of 2 kPa, while keeping the stage and nozzle temperatures at 60 and 30 °C, respectively, followed by an anneal at 150 °C in nitrogen globe box for 1 h to remove the solvent. 10-nm-thick semiconducting layer was obtained. Then, a 140-nm-thick parylene (diX-SR, KISCO, Tokyo, Japan) gate dielectric layer was then formed by chemical vapor deposition. Finally, top-gate electrodes were printed and sintered in the same manner as the bottom-gate electrodes.
2.2. Device Characterization
The capacitance of the dielectric was measured using an LCR meter (ZM2376, NF Corporation, Yokohama, Japan). The electrical characteristics of the OTFTs and inverter circuits were measured using a semiconductor parameter analyzer (model 4200A-SCS, Keithley, Cleveland, OH, USA). All electrical measurements were carried out in the air. Optical microscope images of the devices were obtained using a digital microscope (LEXT OLS4000, Olympus, Shinjuku, Tokyo, Japan).
2.3. Method of the Device Simulation
Device simulation in finite element method (FEM) was carried out to investigate the carrier distribution in single- and dual-gate p-type transistors by using the mathematics module of COMSOL Multiphysics (KESCO Ltd., Tokyo, Japan) . The simulation was based on the Poisson equation and the continuity equation.
Here V is the electrostatic potential, e is the elementary charge, ε is the dielectric constant, nf is the free hole carrier density, nt is the trapped hole carrier density, n0 is the carrier density in the neutral state, μ is the mobility tensor, and EF is the Fermi energy. These equations contain two independent variables: V(x, y) and EF(x, y). Carrier densities nf and nt were approximated as
Here Dv is the effective density of states in the valence band, Ev is the top energy of the valence band, kB is the Boltzmann constant, T is the temperature, Dt is the total density of trap states, and Et is the average energy of traps with exponential density of states.
The parameters used in the simulation were summarized in Table 1. Channel width, channel length, channel thickness, dielectric constant of insulator (εi), and dielectric thickness were measured directly by experiments. The dielectric constant of semiconductor (εs) and temperature were set at typical values. The effective density of states in the valence band (Dv) was estimated from a typical effective mass of organic semiconductor, 3m0, and has little effect on the simulation results. Here m0 is the mass of a free electron. The other parameters, mobility, work function, ionization energy, density of trap states (Dt), average energy of trap states (Et), and carrier density in the neutral state (n0), were arbitrarily set to fit the experimental data. In the simulation, either work function or ionization energy does not matter as long as the difference between the two does not change. We assumed anisotropic mobility because it is a common nature of polymeric semiconductors as reported .
3. Results and Discussion
Transfer characteristics in the saturation regime and output characteristics of the OTFTs were shown in Figure 2. Transfer characteristics in the linear regime obtained from experimental and numerical simulation were shown in Figure 3. The simulated characteristics were similar to the experimental. Channel width (W) and length (L) was 740 µm and 7 µm, respectively. Capacitance per unit area was 21 nF/cm2. The electrical properties such as mobility in saturation (μsat) and linear regime (μlin), threshold voltage (VTH), on-current (ION) and subthreshold slope (SS) were summarized at Table 2. At VDS = −5 V, ION for the BG, TG, and DG devices was 0.23 ± 0.04 µA, 1.5 ± 0.2 µA, and 1.9 ± 0.2 µA, respectively. SS for the BG, TG, and DG devices was 0.5 ± 0.3 V/dec, 1.5 ± 1.0 V/dec, and 0.3 ± 0.1 V/dec, respectively. The higher ION and steeper SS were obtained: the result is consistent with that from previously reported [5,6]. Furthermore, for the DG devices, saturation (VDS = −5 V) and linear (VDS = −0.1 V) mobility was 0.05 ± 0.013 cm2/Vs and 0.047 ± 0.013 cm2/Vs, respectively. The mobility for the DG devices was also better than those of the single-gate devices. On the whole, the DG devices exhibited better electrical properties.
To elucidate the origin of better switching characteristics of the DG device, charge carrier distribution in the organic semiconducting layer was displayed in Figure 4. Spatial x-axis and y-axis were defined as Figure 4a, where the origin was set to be the crossing point of middle of the channel and the line along the bottom-dielectric/semiconductor interface. Free hole densities as a function of y-axis at VGS = 1 V (off state) and VGS = −2 V (on state) were shown in Figure 4b,c. VDS = −0.1 V in all three device simulations. For the single-gate devices, the carrier density at the side of the gate electrode could be controlled in the range of 6.2 × 1020–2.5 × 1023 m−3. Nevertheless, the carrier density at the opposite side of the gate electrode was hardly controlled (2.1 × 1021–5.5 × 1022 m−3). On the other hand, for the DG system, the carrier density over the entire region in the channel could be controlled in the wider range of 4.8 × 1018–3.8 × 1023 m−3. This excellent control of carrier density in the DG system should contribute to obtaining the steeper SS than those from the single-gate system.
We note that the difference in threshold voltage between three device structures needs to be taken into account: however, it is well known that the determination of threshold voltage from experimental transfer characteristics is not always accurate in organic field-effect transistors . On the other hand, in this simulation, the flat band gate voltages, which has a similar implication of threshold voltage, were −0.2 V for all three device structures: the comparison of carrier density at a same gate voltage is reasonable in this simulation.
Moreover, the charge carrier distributions at on/off state were visualized in Figure 4d–i. It is clear that DG device could control the carrier density well, as opposite to single-gate devices. For all the gate structure devices, the accumulation channel whose thickness was estimated to be about 2-nm-thick  was formed at on-state. In particular, for the DG device, the channel was formed at both bottom- and top-gate side, and carrier density of this dual-channel was estimated to be <3.8 × 1023 m−3, which was higher density than that of single-gate devices (<2.5 × 1023 m−3). This dual-channel obviously flow current more than the single-channel, while ION for the DG devices (IONDG) was approximately equivalent to the sum of ION for the BG devices (IONBG) and ION for the TG devices (IONTG), IONDG ≈ IONBG + IONTG, according to Table 2.
For a discussion about the reason why mobility for the DG devices was higher than that of the single-gate devices, potential in the channel were simulated, as shown in Figure 5a,b. Potential in the source and drain region was pinned at 0 V and −0.1 V, respectively. Gate voltage affected the slope of the channel potential and voltage drop at source/channel interface and channel/drain interface.
Channel-width-normalized channel resistance (RchW), contact resistance at source/channel (RsW) and channel/drain (RdW) were extracted from Figure 5a,b and plotted as a function of gate voltage in Figure 5c–e. At VGS = −2 V, RchW for the BG, TG, DG device was estimated to be 1.8 × 103 Ωm, 1.8 × 103 Ωm, 0.8 × 103 Ωm, respectively. There was negligible difference between RchW for the BG device (RchWBG) and RchW for the TG device (RchWTG), on the other hand, RchW for the DG device (RchWDG) was about 55% less than that of the single-gate devices at VGS = −2 V (RchWBG ≈ RchWTG > RchWDG), because the DG device produces the dual-channel as shown in Figure 4i.
Contact resistances at VGS = −2 V for the DG device (RsWDG: 1.5 × 103 Ωm, RdWDG: 0.6×103 Ωm) were approximately equivalent values to those for the TG device (RsWTG: 1.2 × 103 Ωm, RdWTG: 0.6 × 103 Ωm). RsW and RdW (at VGS = −2 V) for the TG/DG device were 60−70% less than those for the BG device (RsWBG: 4.1 × 103 Ωm, RdWBG: 1.5 × 103 Ωm). In brief, RsW, RdW for the TG, DG device were less than the BG device (RsW or RdW: BG > TG ≈ DG) . This is the reason why mobility for the TG, DG devices was higher than the BG devices.
Meanwhile, mobility for the DG devices was also higher than that for the TG devices. For a discussion about the reason for this, we focus on carrier density of the channels. Maximum carrier density of the dual-channel (3.8 × 1023 m−3) was 1.5 times more than that of single-channel (2.5 × 1023 m−3), as shown in Figure 4c. To achieve carrier density equivalent of the dual-channel, at least VGS < −2 V would be required in the TG devices. Since the mobility was associated with gate-voltage , we suggest that higher carrier density of the DG devices would contribute to obtaining the higher mobility than the TG devices.
In conclusion, we successfully fabricated low-voltage BG, TG, DG organic transistors by employing thin parylene dielectrics. The DG devices exhibited better switching characteristics than the single-gate devices. To elucidate this reason, charge carrier distribution and channel potential in BG, TG, DG devices were successfully simulated based on a FEM simulation. It was clear that the DG system produces a dual-channel, and that it has excellent control of charge carrier density in an organic semiconducting layer, which leads to higher ION and steeper SS than the single-gate devices. The conclusions also would apply to OTFTs that employ other organic semiconductor materials. These results can be significant information for the better understanding of a low-voltage DG device operation, as well as for the realization of the high-performance and robust organic electronics.
R.S., H.M. and S.T. designed the research and experiments. T.M. prepared and supplied the polymer semiconductor material. R.S., M.T., Y.T. and T.M. performed fabrication and characterization of the organic transistors. M.T. and H.M. carried out the device simulation. Each of the authors prepared figures and helped write the manuscript.
This work was supported by the JSPS KAKENHI Grant Number 18J10982, JSPS LEADER program, JSPS KAKENHI Grant Number 18H01855, JST COI program, and JST OPERA program.
The polymer semiconductor material was provided by Mitsubishi Chemical Corporation.
Conflicts of Interest
The authors declare no conflict of interest.
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Figure 1. (a) Schematic structures, (b) photograph and (c) layout of fabricated organic thin-film transistor (OTFT) devices.
Figure 2. Transfer characteristics of fabricated (a) bottom-gate (BG), (b) top-gate (TG), and (c) dual-gate (DG) OTFTs at VDS = −5 V. Output characteristics of fabricated (d) bottom-gate, (e) top-gate, and (f) dual-gate OTFTs. Gate-source voltages were from 0 to −5 V in −0.5 V step. The channel dimensions were W/L = 740 µm/ 7 µm.
Figure 3. Transfer characteristics of (a) bottom-gate, (b) top-gate, and (c) dual-gate OTFTs obtained from the experimental and numerical simulation at VDS = −0.1 V. The channel dimensions were W/L = 740 µm/7 µm.
Figure 4. (a) Device geometry in the simulation; free hole density as a function of y-axis at (b) VGS = 1 V and (c) VGS = −2 V. Charge carrier distribution in (d) BG, (e) TG, (f) DG device at VGS = 1 V (off-state), and (g) BG, (h) TG, (i) DG devices at VGS = −2 V (on-state). VDS = −0.1 V.
Figure 5. Simulation of the potential in source, channel, drain region as a function of x-axis at (a) VGS = 1 V and (b) VGS = −2 V. Channel-width-normalized (c) channel resistance (RchW), (d) source/channel contact resistance (RsW) and (e) channel/drain contact resistance (RdW) as a function of VGS.
Table 1. Parameters Used in the finite element method (FEM) Simulation.
|Channel width||732 µm||Temperature||300 K|
|Channel length||6.73 µm||Work function of source, drain and gate electrodes||4.6 eV|
|Channel thickness||10 nm||Ionization energy of semiconductor||5.0 eV|
|Dielectric constant of insulator, εi||3.38ε0||The effective density of states in the valence band, Dv||1.6 × 1020 cm−3|
|Dielectric constant of semiconductor, εs||4ε0|
|Dielectric thickness||140 nm||Density of trap states, Dt||3 × 1018 cm−3|
|Mobility along the channel, μx||0.24 cm2/Vs||Average energy of trap states, Et||0.15 eV|
|Mobility perpendicular to the channel, μy||0.048 cm2/Vs||Carrier density in the neutral state, n0||3 × 1023 cm−3|
Table 2. Electrical Properties of the Fabricated OTFTs.
|Device Structure||μsat (cm2/Vs)||VTH (V)||ION (µA)||SS (V/dec)||μlin (cm2/Vs)||ION (nA)||SS (V/dec)|
|VDS = −5 V, VGS > −5 V||VDS = −0.1 V, VGS > −2 V|
|BG||0.012 ± 0.002||1.5 ± 0.1||0.23 ± 0.04||0.5 ± 0.3||0.012 ± 0.002||6.4 ± 0.8||1.6 ± 0.3|
|TG||0.038 ± 0.005||0.68 ± 0.06||1.5 ± 0.2||1.4 ± 1.0||0.032 ± 0.003||19 ± 1||1.4 ± 0.2|
|DG||0.050 ± 0.013||0.42 ± 0.04||1.9 ± 0.2||0.3 ± 0.1||0.047 ± 0.011||24 ± 2||0.4 ± 0.1|
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