Next Issue
Previous Issue

Table of Contents

J. Low Power Electron. Appl., Volume 1, Issue 3 (December 2011), Pages 334-372

  • Issues are regarded as officially published after their release is announced to the table of contents alert mailing list.
  • You may sign up for e-mail alerts to receive table of contents of newly released issues.
  • PDF is the official format for papers published in both, html and pdf forms. To view the papers in pdf format, click on the "PDF Full-text" link, and use the free Adobe Readerexternal link to open them.
View options order results:
result details:
Displaying articles 1-2
Export citation of selected articles as:

Research

Open AccessArticle Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review
J. Low Power Electron. Appl. 2011, 1(3), 334-356; doi:10.3390/jlpea1030334
Received: 20 May 2011 / Revised: 29 September 2011 / Accepted: 29 September 2011 / Published: 11 October 2011
Cited by 6 | PDF Full-text (2222 KB) | HTML Full-text | XML Full-text
Abstract
While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap [...] Read more.
While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Figures

Open AccessArticle Low Power Testing—What Can Commercial Design-for-Test Tools Provide?
J. Low Power Electron. Appl. 2011, 1(3), 357-372; doi:10.3390/jlpea1030357
Received: 16 August 2011 / Revised: 2 December 2011 / Accepted: 5 December 2011 / Published: 9 December 2011
PDF Full-text (251 KB) | HTML Full-text | XML Full-text
Abstract
Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to [...] Read more.
Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to achieve comprehensive testing of low power designs and reduce test power consumption during test application. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Figures

Journal Contact

MDPI AG
JLPEA Editorial Office
St. Alban-Anlage 66, 4052 Basel, Switzerland
jlpea@mdpi.com
Tel. +41 61 683 77 34
Fax: +41 61 302 89 18
Editorial Board
Contact Details Submit to JLPEA
Back to Top