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J. Low Power Electron. Appl., Volume 4, Issue 2 (June 2014), Pages 65-167

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Research

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Open AccessArticle Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology
J. Low Power Electron. Appl. 2014, 4(2), 77-89; doi:10.3390/jlpea4020077
Received: 1 March 2014 / Revised: 22 April 2014 / Accepted: 23 April 2014 / Published: 5 May 2014
Cited by 5 | PDF Full-text (1113 KB) | HTML Full-text | XML Full-text
Abstract
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV [...] Read more.
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems
J. Low Power Electron. Appl. 2014, 4(2), 90-109; doi:10.3390/jlpea4020090
Received: 29 January 2014 / Revised: 18 March 2014 / Accepted: 10 April 2014 / Published: 7 May 2014
Cited by 3 | PDF Full-text (2988 KB) | HTML Full-text | XML Full-text
Abstract
With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. [...] Read more.
With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS) and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works. Full article
Open AccessArticle Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs
J. Low Power Electron. Appl. 2014, 4(2), 110-118; doi:10.3390/jlpea4020110
Received: 28 February 2014 / Revised: 7 May 2014 / Accepted: 16 May 2014 / Published: 23 May 2014
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Abstract
A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved [...] Read more.
A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin). Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle MOS Current Mode Logic Near Threshold Circuits
J. Low Power Electron. Appl. 2014, 4(2), 138-152; doi:10.3390/jlpea4020138
Received: 6 March 2014 / Revised: 29 April 2014 / Accepted: 15 May 2014 / Published: 11 June 2014
Cited by 1 | PDF Full-text (469 KB) | HTML Full-text | XML Full-text
Abstract
Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant [...] Read more.
Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials
J. Low Power Electron. Appl. 2014, 4(2), 153-167; doi:10.3390/jlpea4020153
Received: 28 February 2014 / Revised: 1 June 2014 / Accepted: 3 June 2014 / Published: 20 June 2014
Cited by 2 | PDF Full-text (1348 KB) | HTML Full-text | XML Full-text
Abstract
The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V [...] Read more.
The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

Review

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Open AccessReview Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V
J. Low Power Electron. Appl. 2014, 4(2), 65-76; doi:10.3390/jlpea4020065
Received: 27 February 2014 / Revised: 7 April 2014 / Accepted: 10 April 2014 / Published: 24 April 2014
Cited by 4 | PDF Full-text (441 KB) | HTML Full-text | XML Full-text
Abstract
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many [...] Read more.
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessReview An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications
J. Low Power Electron. Appl. 2014, 4(2), 119-137; doi:10.3390/jlpea4020119
Received: 1 March 2014 / Revised: 6 May 2014 / Accepted: 19 May 2014 / Published: 27 May 2014
Cited by 1 | PDF Full-text (1198 KB) | HTML Full-text | XML Full-text
Abstract
Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work [...] Read more.
Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
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