Journal of Low Power Electronics and Applications

2872 KiB

Open AccessArticle

Delay Insensitive Ternary CMOS Logic for Secure Hardware

by Ravi S. P. Nair, Scott C. Smith and Jia Di

J. Low Power Electron. Appl. 2015, 5(3), 183-215; https://doi.org/10.3390/jlpea5030183 - 11 Sep 2015

Cited by 11 | Viewed by 8071

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This [...] Read more.

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU. Full article

(This article belongs to the Special Issue Low-Power Asynchronous Circuits)

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1150 KiB

Open AccessArticle

A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories

by Alireza Shafaei, Shuang Chen, Yanzhi Wang and Massoud Pedram

J. Low Power Electron. Appl. 2015, 5(3), 165-182; https://doi.org/10.3390/jlpea5030165 - 11 Aug 2015

Cited by 1 | Viewed by 9027

Abstract

This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, [...] Read more.

This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap) is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)

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551 KiB

Open AccessArticle

Communication and Sensing Circuits on Cellulose

by Federico Alimenti, Chiara Mariotti, Valentina Palazzi, Marco Virili, Giulia Orecchini, Paolo Mezzanotte and Luca Roselli

J. Low Power Electron. Appl. 2015, 5(3), 151-164; https://doi.org/10.3390/jlpea5030151 - 25 Jun 2015

Cited by 15 | Viewed by 8245

Abstract

This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that [...] Read more.

This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper) by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable) materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT) era. Full article

(This article belongs to the Special Issue Low-Power Systems on Chip Enabling Internet of Things)

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J. Low Power Electron. Appl., Volume 5, Issue 3 (September 2015) – 3 articles , Pages 151-215

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