Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions ^†

Abstract

Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model.

1. Introduction

Going with the trend of increasing connectivity and services offered by computing devices, the amount of sensitive information processed by and stored on computing devices is growing rapidly. Recently, Physical Unclonable Function (PUF) has sprouted up as a promising primitive to enforce data privacy and access control to electronic devices. Among the PUF implementations [1,2,3,4,5], SRAM-based PUF (SPUF) has attracted tremendous attention. This is because SRAM, being an integral part of computer memory sub-system, plays a pivotal role in trusted computing platforms. The ability to use the storage cells of SRAM inseparably as PUF will replace or augment memory curtaining as a stronger fortification to the roots of trust for memory authentication. Unfortunately, existing SPUF cells cannot be doubled as regular storage elements. The exploitation of process-variation induced device mismatches in the cross-coupled inverter cell for random, unique and reliable response bit generation is detrimental to the regular memory operation, as it will result in increased parametric failures due principally to destructive read and unsuccessful write operations. Archived literatures reported wide varieties of design approaches that either improve the qualities of SPUF or harness the readability and writability of SRAM cells as data storage elements, albeit independently [5,6]. However, no design strategy has been proposed to tackle the conflicting quality requirements to unify the two different modes of operation in an SRAM cell.

In this paper, we expand the design space exploration of our preliminary proposal in [7], by taking into consideration circuit-level techniques that can be used to mitigate conflicting design criteria of both PUF response reliability and memory data stability. The proposed design procedure provides greater opportunity to meet tighter functional and performance specifications of both modes of operation at a small cost of area, delay and power overheads.

The remainder of this paper is organized as follows. Section 2 analyzes the impacts of process variations (PV) and transistor sizing on the two different working modes of SRAM. Section 3 presents the proposed design methodology to expand the design space for PUF and memory stability optimization. Section 4 discusses the comparison results for seven different design configurations. The paper is concluded in Section 5.

2. Impact of Process Variations (PV) on Different Operation Modes

The block structure of a complete SPUF is shown in Figure 1a. The core of the SPUF is a two-dimensional array of storage cells, where the horizontal rows are referred to as word-lines ($WLs$) and the two vertical lines that run through each cell are called the bit-line ($BL$) and complement bit-line ($BLB$). An individual cell can be selected by the row and column decoder circuit with an external input address, addr. One sense amplifier is attached to each bit-line pair of the column to accelerate read operation while the write driver circuit improves the access time in write operation. When the SPUF is set to PUF mode by the mode_sel input, the SPUF is reset and powered up. Due to mismatches and noise between the cross-coupled inverters formed by the transistor pairs, M1–M2 and M4–M5, a response bit is generated in each of the SRAM cells. An input challenge is applied to the $WL$ of the addressed cells to turn on the access transistors, M3 and M6. The response bits are then read from the bit-lines [2]. In the memory mode, regular read and write operations are performed on the same SRAM array after the SPUF has been fully powered up. For a read operation, the small voltage difference between the true and complement bit-lines is amplified by the sense amplifier and the data stored in the addressed cell is transferred to the output. For a write operation, the bit-lines are initialized with the data that is to be written into the cell with its word-line asserted. These two different modes of operation on a 6-transistor (6T) SRAM cell are shown in Figure 1b.

While the two modes of operation seem independent, they cannot be designed independently because the PV influences on them occur simultaneously. As shown in Figure 2, when the threshold voltage variation ${\sigma }_{V_{th}}$ increases, the failure rate of memory operations increases, whereas the reliability of response bits for PUF operation improves.

2.1. Impact of PV on Physical Unclonable Function (PUF) Quality

During the power-up process, all transistors in an SRAM cell operate in the sub-threshold region. The currents that drive the two output nodes, BIT and BITB, in Figure 1b are determined by the strength of the two inverters in the cell. The currents flowing through M1–M2 and M4–M5 will simultaneously pull up the voltage at BIT and BITB, respectively. Owing to the transistor mismatches between the two inverters, one of the two nodes may reach the “trip-point” ($V_{trip}$) of the inverter faster than the other. If the voltage at BITB increases to $V_{trip}$ first, the output node BIT of INV-1 will be pulled down to ground. As the voltage at BIT descends, M5 will be fully turned on eventually and pull the voltage at BITB to the supply voltage $V_{DD}$. This process is shown in Figure 3a. Figure 3b shows the state evolution of the SRAM in the phase plane [8]. During the initial phase of power-up, BIT and BITB are approaching the meta-stable point ($V_{trip}$) together. Due to mismatches of the two inverters, the SRAM cell will stabilize to one of the two stable states ($V_{BIT}$ = “1” or “0”).

Since each response bit is independently generated from an SRAM cell and dominated by independent intra-die variations such as random dopant fluctuation and line edge roughness, the randomness among bits generated is guaranteed. While the response bits produced from individual SRAM cells are generally uncorrelated, their reliability may be jeopardized when the noise effects overwhelm the mismatches between the two inverters in an SRAM cell. In addition, temporal post-manufacturing variations such as unexpected change of environmental conditions in which the devices operate will also impact the reliability.

2.1.1. Mismatch of INV-1 and INV-2

The reliability of a PUF is a measure of the reproducibility of its response to the same challenge at different times and conditions [1]. It is the complement of the bit error rate (BER) of its responses, which can be measured by calculating the intra-chip Hamming distance of the responses generated from a single PUF chip with the same challenge. Ideally, BER should be 0% and reliability should be 100%. The reliability of the start-up state of an SRAM cell is highly dependent on the degree of mismatch between INV-1 and INV-2. The mismatch is dominated by the intra-die variation where the variation of $V_{th}$ is the most prevalent. During power-up process, a small deviation of $V_{th}$, denoted as $\mathrm{\Delta }{V}_{th}$, between the transistors of INV-1 and INV-2 may change the drive currents and shift the intersection of their voltage transfer curves (VTC) [9], causing asymmetric output sensitivity to external stress. The magnitude of $\mathrm{\Delta }{V}_{th}$ is primarily determined by ${\sigma }_{V_{th}}$, which has been proven empirically to be related to the transistor geometry as follows [10]:

$${\sigma }_{V_{th}}=\frac{\mathrm{\Lambda }·{\sigma }_{V_{th,\text{max}}}}{\sqrt{(W·L)}},$$

(1)

where Λ is a technology-dependent parameter and ${\sigma }_{V_{th,\text{max}}}$ is the maximum value of ${\sigma }_{V_{th}}$.

Based on Equation (1), ${\sigma }_{V_{th}}$ can be reduced by sizing up the transistors in an SRAM cell (see Figure 4a). Depending on the transistor sizes, the mismatch between the inverters of a cell may be reduced to an extent that its output state becomes highly susceptible to variations of external condition or in the worst case, completely determined by the noise present in the SPUF. This can be explained in Figure 5. Based on the propensity of the output to settle at one of the two states upon power-up, SRAM cells can generally be categorized as 1-skewed, 0-skewed or neutral cells [2]. Highly 1-skewed (0-skewed) cells have larger mismatches between its two inverters and have a high tendency to power up to “1” (“0”). Neutral cells have equal probability to power up to either “1” or “0”, depending on the noise.

Figure 4b depicts the simulation results of the response bits generated by powering up the same SRAM cell 10 times in the presence of noise, whose parameters are set as $f_{min}={10}^6$ and $f_{max}={10}^{11}$, where $f_{min}$ and $f_{max}$ are, respectively, the base and maximum frequencies used for modeling frequency dependent noise sources [11]. An SRAM cell that does not generate the same start-up value, i.e., “1” or “0”, is consistently regarded as unreliable. The percentage of unreliable bits obtained from 500 cells of an SRAM array is plotted against the size of SRAM cell. The data points can be fitted by a second order polynomial, which indicates that the percentage of unreliable bits increases almost linearly with the transistor size.

2.1.2. Loop-Gain at Trip Point

The “Loop-gain” at the metastable trip point of a cross-coupled inverter pair is an important factor that affects the reliability of SPUF [12]. The node voltages of SRAM cells stabilize faster if the loop-gain is higher. According to [13], the loop-gain is formulated as

$$LG\left(V_{BIT}\right)=\frac{\partial {\text{VTC}}_2}{\partial V_{BIT}}·\frac{\partial {\text{VTC}}_1}{\partial V_{BITB}},$$

(2)

where $V_{BIT}={\text{VTC}}_1\left(V_{BITB}\right)$ or $V_{BITB}={\text{VTC}}_2\left(V_{BIT}\right)$. VTC refers to the voltage transfer characteristic function and can be formulated as follows [9]

VTC for INV-2:

$$\begin{array}{c}{V}_{BITB}=V_{DD}+V_T\text{ln}\left\{\frac{1}{2}\left[1-G+\sqrt{{(G-1)}^2+4\text{exp}\left(-\frac{V_{DD}}{V_T}\right)G}\right]\right\},\hfill \\ G=\text{exp}\left(\frac{2V_{BIT}}{n{V}_T}-\text{ln}\frac{I_{S5}}{I_{S4}}-\frac{V_{DD}}{n{V}_T}-\frac{V_{th,4}-V_{th,5}}{n{V}_T}\right),\hfill \end{array}$$

(3)

where $I_{Si}$ and $V_{th,i}$ refer to the saturation current and threshold voltages of the transistor Mi in Figure 1. VTC for INV-1 can be derived similarly.

As pointed out in [12], large loop-gain degrades the reliability of SPUF as the amplified noise in the power-up process overwhelms the transistor mismatches due to process variation. From Equations (2) and (3), the loop-gain is mainly governed by $V_{DD}$, $V_{th}$ and $V_T$.

2.2. Impact of PV on SRAM Read/Write Failures

While the strength mismatches between different transistors of an SRAM cell are good to skew its power-up value to resist SPUF response bit flipping under temporal variations in operational condition, they can increase the read failure (RF) and write failure (WF) rates in the memory-mode. RF occurs when the voltage ($V_{read}$) sensed at BIT (or BITB) rises above the inverter read trip point ($V_{tripRD}$) to cause the bit stored in the SRAM cell to flip accidentally (see Figure 6a). As shown in Figure 1b, when the bit-line $BL$ is precharged, the access transistor M6 and the pull-down transistor M4 act as a voltage divider. The PV induced voltage deviation at BITB may trigger a flip of the data bit stored in the SRAM cell [14]. To avoid RF, the relative strength of M4 and M6 (known as beta ratio (${\beta }_{npd-nax}$)) should be designed larger, where $B{R}_{npd-nax}$ is given by

$$B{R}_{npd-nax}=\frac{{\beta }_{npd}}{{\beta }_{nax}}=\frac{{\beta }_{M4}}{{\beta }_{M6}}={\displaystyle \frac{\frac{{\mu }_{eff}{C}_{ox}{W}_{M4}}{L_{M4}}}{\frac{{\mu }_{eff}{C}_{ox}{W}_{M6}}{L_{M6}}}},$$

(4)

where ${\mu }_{eff}$ is the effective mobility and $C_{ox}$ is the oxide capacitance. WF refers to the failure of SRAM cells to respond to the data bit written into it within an acceptable time (see Figure 6b) [14]. Consider the SRAM cell in Figure 1b, if “0” is to be written into the cell that stores logic “1”, the voltage at BIT will be discharged to a low value. If this value is higher than the trip point of INV-2, the write operation fails and the stored data bit remains unchanged. To reduce the probability of WF, the beta ratio of the access transistor and pull-up p-channel metal-oxide-semiconductor field-effect transistor (PMOS) ($B{R}_{nax-pup}={\beta }_{nax}/{\beta }_{pup}={\beta }_{M3}/{\beta }_{M2}$) should be designed such that the write time is less than the word-line turn-on time.

It is possible to reduce the probability $\mathbf{Pr}(\mathrm{RF},\mathrm{WF})$ of memory access failures by manipulating the transistor sizes [14]. The relationship between $\mathbf{Pr}(\mathrm{RF},\mathrm{WF})$ and the sizing of each transistor in an SRAM cell is shown in Figure 7. Curve fitting by polynomial functions shows that sizing up the transistors helps to reduce failure probability. This is expected since ${\sigma }_{V_{th}}$ decreases when the size of transistors increases according to Equation (1).

3. Proposed Design Method for Dual-Mode PUF

To design a dual-mode SPUF, the transistors in the SRAM cell need to be sized such that the quality expectations can be met for both modes. For memory mode, the memory failure probability should be kept as low as possible, whereas for PUF mode, the randomness, uniqueness and reliability of response bits should be made as high as possible. As randomness and uniqueness can be easily enhanced by fuzzy extractor at a smaller cost, this paper focuses on the reliability, which is more critical and difficult to improve for SPUF. In addition, failure probability and PUF reliability, area, leakage current and dynamic power constraints using a targeted process technology will also be considered.

3.1. Circuit-Level Techniques

In addition to transistor sizing, circuit-level techniques such as Word-Line Voltage Modulation (WLM), Dynamic Voltage Scaling (DVS), Negative Bit-Line (NBL) and Adaptive Body Bias (ABB) can also be applied to mitigate SRAM failures [15,16,17,18]. For ease of exposition, the nominal supply voltage is denoted as “SRAMVDD”. In addition, since static noise margin (SNM) is more conveniently used in practice to calibrate the SRAM cell stability against DC noise [9], it will be used as a measure to compare the efficiency of different adaptive techniques.

3.1.1. WLM

The WLM technique proposed in [15] is shown in Figure 8. This technique increases the read stability by lowing the word-line voltage to increase $B{R}_{npd-nax}$. The WL selector adapts different supply voltage to the WL ($V_{DD\_WL}$). Its control signal is determined by the requirements of speed and stability. By lowering the WL voltage and keeping the cell voltage supply at SRAMVDD, the strength of the access transistors will be lowered to improve $B{R}_{npd-nax}$. However, lowering WL voltage will also degrade the write ability due to the reduced $B{R}_{nax-pup}$. This problem can be solved by applying different $V_{WL}$ for the read and write operations. This scheme has a drawback as it can only improve read stability but not write ability, as improving $V_{WL}$ during write operation will degrade the SNM of the half-selected cells (which are equivalent to performing a read operation on these cells) even though they are not accessed.

3.1.2. DVS

A column-based DVS technique was proposed in [16] to improve both read and write margins. A differential voltage is created between the SRAM cell and the WL nodes to optimize the read and write margins separately without compromising each other. The mechanism is shown in Figure 9. Each column of memory cells has a common voltage supply, which is either $V_{DD\_hi}$ or $V_{DD\_lo}$, depending on the cell operation mode. During the read operation, the column of accessed cells switches its $V_{DD}$ to $V_{DD\_hi}$, which is higher than the word-line voltage SRAMVDD. During the write operation, the column of accessed cell switches its $V_{DD}$ to $V_{DD\_lo}$, which is lower than SRAMVDD. For the columns that are not accessed, their $V_{DD}$ will always be $V_{DD\_hi}$, as they are always experiencing “read stress” even though they are not selected to be read or written. When a cell is in standby mode, its $V_{DD}$ is switched to $V_{DD\_lo}$ to minimize leakage power. In this way, both read and write stability will be increased.

3.1.3. NBL

A write-ability enhancement technique that combines negative bit-line and $V_{DD}$ collapse scheme with high configurability was proposed in [17]. Like DVS, the $V_{DD}$ collapse technique improves $B{R}_{nax-pup}$ by weakening the pull-up PMOS. The circuit implementation of NBL is shown in Figure 10. During write operation, the bit-line is driven to a negative voltage to write “0”. This will strengthen the driving capability of pass transistors, thus improving $B{R}_{nax-pup}$ and the write ability. As this technique is only applied during the write operation, it has no influence on the read stability.

3.1.4. ABB

The SRAM cell failures are not only affected by intra-die variations, but also by inter-die variations. This can be understood by analysing the change in $V_{read}$ and $V_{tripRD}$ with an inter-die $V_{th}$ shift ($\mathrm{\Delta }{V}_{thINTER}$) of the cell transistors [18]. As shown in Figure 11, when $V_{BIT}$ = “1”,

$$\begin{array}{c}{V}_{tripRD}=V_{trip}\left(0\right)+\mathrm{\Delta }{V}_{thINTER}{\displaystyle \frac{\sqrt{{\beta }_{M1}/{\beta }_{M2}}-1}{\sqrt{{\beta }_{M1}/{\beta }_{M2}}+1}},\hfill \\ V_{read}=V_{trip}\left(0\right)-\mathrm{\Delta }{V}_{thINTER}\left(1\pm {\displaystyle \frac{\sqrt{{\beta }_{M4}/{\beta }_{M5}}}{\sqrt{1+{\beta }_{M4}/{\beta }_{M5}}}}\right).\hfill \end{array}$$

(5)

With a negative $\mathrm{\Delta }{V}_{thINTER}$, $V_{read}$ increases but $V_{tripRD}$ decreases [18]. This will reduce ($V_{tripRD}-V_{read}$), thus degrading the read stability. When $\mathrm{\Delta }{V}_{thINTER}$ is positive, write failure will increase due to the weakening of access transistors. Such stability degradation can be eliminated by employing the ABB technique proposed in [18]. Take n-channel metal-oxide-semiconductor field-effect transistor (NMOS) as an example: the body bias (BB) can be utilized to adjust $V_{th}$ as

$$V_{th}=V_{th0}+\gamma (\sqrt{2{\phi }_B+V_{SB}}-\sqrt{2{\phi }_B}),$$

(6)

where γ is the body effect parameter, ${\phi }_B$ is a physical parameter and $V_{SB}$ is the voltage between the source and body.

$V_{th}$ of M1 to M6 can be adjusted by their respective body bias voltages $V_{B1}$–$V_{B6}$. For both NMOS and PMOS in general, reverse body bias (RBB) increases $V_{th}$ whereas forward body bias (FBB) reduces $V_{th}$ [19]. According to Equation (5), the increase of $V_{th}$ with RBB leads to higher ($V_{tripRD}-V_{read}$), which, in turn, reduces the read failure probability. Conversely, the reduction of $V_{th}$ with FBB increases the driving capability of the access transistors, which leads to reduced write time and improved write ability.

Even though ABB can be applied to reduce the read and write failures, it is not without limitations. The ideal case of biasing each transistor independently is not practical due to a large amount of voltage supplies and area overhead [20]. As a practical expedient, the same body bias can be applied to all cells to mitigate the degraded cell stability against inter-die variations. In addition, unlike PMOS BB, which can be applied in a standard dual-well process, the application of BB to NMOS requires a triple-well process [18]. If cost permits, it is preferable to adjust the BBs of both PMOS and NMOS transistors to mitigate the inter-die variations. Under the constraint of manufacturing cost, BB can only be applied to PMOS transistors to reduce the read and write failures despite less efficiency [18]. Since the inter-die $V_{th}$s of PMOS and NMOS may move in different directions, it is also desirable to control the BB of the two types of transistors individually.

3.1.5. Comparison of Different Reliability Enhancement Techniques

The SRAM cells incorporated with the four aforementioned techniques were simulated to compare their effectiveness in improving the SNM. For WLM and DVS, the word-line and supply voltages were swept by $\pm 20\%$ from $0.7$ V to $1.1$ V. For NBL, the BL voltage is swept from $-0.2$ V to $0.2$ V. For ABB, the SNMs were simulated with BB applied to only NMOS, only PMOS and both NMOS and PMOS transistors, respectively. Due to the non-linear relationship between $V_{th}$ and BB voltage, the BBs were swept for a large range from $-0.5$ V to $0.5$ V. By representing the deviation of BB by $\mathrm{\Delta }V$, the BB voltages, $V_{bn}$ and $V_{bp}$, for NMOS and PMOS, respectively, are given by:

$$\begin{array}{c}{V}_{bn}=\mathrm{\Delta }V,\hfill \\ V_{bp}=\text{SRAMVDD}+\mathrm{\Delta }V.\hfill \end{array}$$

(7)

The SNM obtained by applying each circuit-level enhancement technique is shown in Figure 12. The efficiency is measured by the SNM sensitivity S as follows:

$$S=\left|\frac{\partial V_{SNM}}{\partial V_X}\right|,$$

(8)

where $V_X$ is the word-line voltage for WLM, supply voltage for DVS, bit-line voltage for NBL, or body bias voltage for ABB.

It can be seen that all these techniques have improved the cell stability by strengthening or weakening certain transistors. Even though the strengthening or weakening effect can be applied in the row (by modulating WL voltage) or column (by modulating bit-line or cell power supply voltages) direction, column-based approaches are preferred because they can blend well with column multiplexing and write masking [17]. A comparison of the functionalities of different adaptive techniques is shown in

Table 1. Comparison of different adaptive techniques.

Technique	Column-Based	S(Read)	S(Write)	Other Drawbacks
WLM	×	$0.325$	0	-
DVS	√	$0.323$	$0.006$	-
NBL	√	0	$0.908$	-
ABB (NMOS only)	×	$0.009$	$0.016$	Triple-well process, Large area overhead
ABB (PMOS only)	×	$0.026$	$0.006$
ABB (Both MOSFETs)	×	$0.114$	$0.015$

WLM, DVS, NBL and ABB refer to Word-Line Voltage Modulation, Dynamic Voltage Scaling, Negative Bit-Line and Adaptive Body Bias, respectively. S refers to the SNM sensitivity.

.

From the table, it can be seen that the four adaptive techniques improve the SNM in their own ways. WLM is not column-based, but it is the most efficient in increasing the read SNM. DVS is efficient in increasing the read SNM but is inefficient in increasing the write SNM. NBL cannot increase read SNM, but it is the most efficient in increasing the write SNM. ABB is not efficient in increasing either the read SNM or write SNM, but it can be used to mitigate inter-die variations. Although DVS and ABB may not improve write SNM efficiently, they have the potential to reduce write failures. This is because write SNM is not a strong indicator of dynamic write ability [21]. The latter is better analyzed by the relative strength of access transistors and pull-up PMOS transistors.

3.2. Problem Formulation

Based on the above analysis, the design space of an SPUF is shown in Figure 13. The objective of the design problem is to find an optimal point ($\mathbf{X},\mathbf{M}$) that combines the key parameters $\mathbf{X}$ (e.g., W of its transistors) associated with SRAM cell dimension and the aggressiveness $\mathbf{M}$ (e.g., by changing the voltage $V_X$) of WLM, DVS, NBL adaptation, to minimize

$$F(\mathbf{X},\mathbf{M})=\underset{\mathbf{X},\mathbf{M}}{\min }\mathbf{Pr}(\mathrm{RF},\mathrm{WF}),$$

(9)

subject to the following constraints:

$$\left\{\begin{array}{c}\text{reliability}\left(\text{ECC}[n,k,t]\right)\ge {\text{reliability}}_{\min },\hfill \\ \text{area}\_\text{cell}\le \text{area}\_{\text{cell}}_{\text{max}},\hfill \\ \text{leakage}\_\text{cell}\le \text{leakage}\_{\text{cell}}_{\text{max}},\hfill \\ \text{power}\_\text{cell}\le \text{power}\_{\text{cell}}_{\text{max}},\hfill \end{array}\right.$$

(10)

where ECC$[n,k,t]$ is the error correction code specified by the code word length n, number of information bits k and number of correctable errors t. The PUF reliability is measured by the complement of BER. The $\text{area}\_\text{cell}$, $\text{leakage}\_\text{cell}$ and $\text{power}\_\text{cell}$ refer to the area, standby power and dynamic power dissipated during the read and write operations of the SRAM cell.

The design problem can be solved by the design flow described in Figure 14. It should be noted that the ABB technique is not considered at design time, but it is applied in the post-silicon tuning to calibrate against inter-die variation to reduce degradation of cell reliability [18]. Its application alongside with other techniques is limited mainly by the constraint of hardware resources and target fabrication process. In applying circuit-level techniques, combinations of multiple techniques should be considered if one technique alone is inadequate to reduce $\mathbf{Pr}(\mathrm{WF},\mathrm{RF})$ to meet the target. If $\mathbf{Pr}\left(\text{RF}\right)$ dominates $\mathbf{Pr}(\mathrm{WF},\mathrm{RF})$, priority should be given to WLM. Otherwise, if $\mathbf{Pr}\left(\text{WF}\right)$ dominates, NLB should be included primarily. If $\mathbf{Pr}\left(\text{RF}\right)$ and $\mathbf{Pr}\left(\text{WF}\right)$ are comparable, then DVS should be chosen. The aggressiveness of the three techniques are increased by tuning their control knobs differently. For WLM, it means decreasing $V_{WL}$ in read operation. For DVS, it means increasing $V_{DD}$ in read operation and decreasing $V_{DD}$ in write operation. For NBL, it means decreasing the bit-line voltage.

The variables and constraints involved can be evaluated as follows.

3.2.1. Failure Probability

The overall failure probability of an SRAM cell can be estimated by [14]

$$\mathbf{Pr}(\mathrm{RF},\mathrm{WF})=\mathbf{Pr}\left(\text{RF}\right)+\mathbf{Pr}\left(\text{WF}\right)-\mathbf{Pr}(\text{RF}·\text{WF}).$$

(11)

The failure probabilities $\mathbf{Pr}\left(\text{RF}\right)$ and $\mathbf{Pr}\left(\text{WF}\right)$ can be efficiently estimated using the method proposed in [14].

3.2.2. Reliability

The raw reliability of the raw PUF response can be estimated by:

$${\text{reliability}}_{\text{raw}}=1-{\text{BER}}_{\text{raw}}=1-\frac{1}{m}\sum _{i=1}^m\frac{\text{HD}(R,R^{\prime })}{n},$$

(12)

where m is the number of responses generated by the same challenge, n is the bit-length of the response, and $\text{HD}(R,R^{\prime })$ is the Hamming distance between two responses, R and $R^{\prime }$, to the same challenge generated by the same PUF at different time or different environmental conditions. With ECC$[n,k,t]$, the reliability can be improved to

$$\begin{array}{c}{\text{reliability}}_{\text{final}}=\sum _{i=0}^t\left(\genfrac{}{}{0pt}{}{n}{t}\right){\left({\text{BER}}_{\text{raw}}\right)}^i{(1-{\text{BER}}_{\text{raw}})}^{n-i}.\end{array}$$

(13)

The final bit error rate is

$$\begin{array}{c}\text{BER}=1-{\text{reliability}}_{\text{final}}.\end{array}$$

(14)

3.2.3. Area

The area of an SRAM array is estimated by

$${\text{area}}_{\text{array}}\approx N\times {\text{area}}_{\text{cell}},$$

(15)

where N is the number of SRAM cells and ${\text{area}}_{\text{cell}}={\text{X}}_{\text{cell}}\times {\text{Y}}_{\text{cell}}$. Based on the layout of [14],

$$\begin{array}{c}{\mathrm{X}}_{\text{cell}}=5\lambda +2\text{max}(3\lambda ,W_{M3})+2L,\hfill \\ {\mathrm{Y}}_{\text{cell}}=9\lambda +\text{max}(3\lambda ,W_{M2})+\text{max}(3\lambda ,W_{M1})+L,\hfill \end{array}$$

(16)

where λ is half of the feature size. W and L are the channel width and length of the transistor, respectively. The area overhead incurred by any of the abovementioned circuit-level adaptive techniques is negligible compared to ${\text{area}}_{\text{array}}$.

3.2.4. Power Consumption

The power consumption of the SRAM array can be calculated by

$${\text{power}}_{\text{array}}=N\times {\text{power}}_{\text{cell}},$$

(17)

where ${\text{power}}_{\text{cell}}$ is the total power consumption of each SRAM cell. Its dynamic and leakage components can be obtained by the built-in function of the SPICE simulator. During the read and write operations, dynamic power dominates. Otherwise, leakage current is the major contributor of ${\text{power}}_{\text{array}}$ [14]. The power consumption of circuit-level techniques is insignificant when compared to the total power consumption of the SRAM core [17]. For computational efficiency without compromising the quality of optimization, a small fraction of the total power consumption can be set aside as a guard band in the power consumption constraint specifications to account for the power consumption overheads of circuit-level techniques.

4. Simulation Results and Discussions

To demonstrate the efficiency of our optimization strategy, seven different designs were compared. Designs 1 and 2 were optimized for single-mode PUF and single-mode SRAM with the parameters of $\mathbf{X}$ set to the minimum and maximum values, respectively. The transistors of Design 3 were sized for the lowest $\mathbf{Pr}(\mathrm{RF},\mathrm{WF})$ under the constraints of reliability ($1-\text{BER}$), area and leakage without applying any circuit-level techniques. Design 4 uses WLM to improve the cell stability, with $V_{WL}=0.8$ V in read operation and $V_{WL}=0.9$ V in write operation. Design 5 uses DVS, with $V_{DD}=1$ V in read operation and $V_{DD}=0.8$ V in write operation. Design 6 uses NBL, with bit-line voltage $-0.1$ V applied in write operation. Design 7 is a ring oscillator (RO) PUF used for dual-mode application, i.e., as a PUF and a clock. The designs were simulated by HSPICE with CMOS 45 nm bulk Predictive Technology Model. The maximum standard deviation of $V_{th}$ and Λ are assumed to be $15\%$ of its nominal value and 100 nm, respectively. The channel length is set to 45 nm for all transistors. The ECC used is BCH-[$127,15,27$] [22]. The following design constraints were set: ${\text{BER}}_{\text{max}}={10}^{-6}$, $\text{area}\_{\text{cell}}_{\text{max}}=1$ $\mu m^2$, $\text{leakage}\_{\text{cell}}_{\text{max}}=50nA$ and $\text{power}\_{\text{cell}}_{\text{max}}=200\mu W$.

The results are tabulated in

Table 2. Simulation results @$V_{DD}=0.9$ V, temperature $=25{}^{\circ }$C.

Description	Design	X	M	$\mathbf{Pr}\mathbf{\left(}\mathbf{RF}\mathbf{\right)}$	$\mathbf{Pr}\mathbf{\left(}\mathbf{WF}\mathbf{\right)}$	$\mathbf{Pr}\mathbf{\left(}\mathbf{RF},\mathbf{WF}\mathbf{\right)}$	BER	Area	Leakage	Power
Single-mode PUF	1	$(180,90,135)$	$N.A.$	$0.131$	$0.136$	$0.249$	$1.37\times {10}^{-7}$	$0.45$	$25.2$	140
Single-mode memory	2	$(500,250,375)$	$N.A.$	$0.022$	$0.047$	$0.068$	$3.29\times {10}^{-2}$	$1.28$	$73.2$	405
Dual-mode SPUF	3	$(202,101,152)$	$N.A.$	$0.118$	$0.125$	$0.229$	$9.73\times {10}^{-7}$	$0.49$	$28.5$	158
	4	$(202,101,152)$	$WLM$	$0.021$	$0.125$	$0.143$	$9.73\times {10}^{-7}$	$0.49$	$28.5$	154
	5	$(202,101,152)$	$DVS$	$0.027$	$0.036$	$\mathbf{0}.\mathbf{062}$	$9.73\times {10}^{-7}$	$0.49$	$19.8$	143
	6	$(202,101,152)$	$NBL$	$0.118$	$0.004$	$0.122$	$9.73\times {10}^{-7}$	$0.49$	$28.5$	155
Dual-mode RO PUF	7	−	−			$0.51$	$1.46\times {10}^{-10}$	−	−	−

The transistor width is searched in the range of $[45,500]$ nm, and the ratio $W_{\mathrm{M}1}:W_{\mathrm{M}2}:W_{\mathrm{M}3}$ is the same for the three designs so that no memory failure occurs with nominal parameter values; The power refers to the sum of dynamic power during read and write operations; The data of RO PUF was from [24]. The failure probability was calculated with 0.5% frequency tolerance and the BER was obtained with the same ECC as SPUF; The units for area, leakage and power are μm${}^2$, nA and μW, respectively; Reliability can be computed from BER by $1-\text{BER}$; WLM, DVS, NBL and ABB refer to Word-Line Voltage Modulation, Dynamic Voltage Scaling, Negative Bit-Line and Adaptive Body Bias, respectively. RF and WF refer to read failure and write failure, respectively. PUF refers to physical unclonable function. SPUF refers SRAM-based PUF. RO refers to ring oscillator.

. Design 1 has a low BER, which is good for PUF, but bad for memory mode due to its high $\mathbf{Pr}(\mathrm{RF},\mathrm{WF})$. Comparing to Design 1, Design 2 has a lower $\mathbf{Pr}(\mathrm{RF},\mathrm{WF})$ and a higher BER, which makes it a better choice for memory but a poor choice for PUF. Design 3 has a lower $\mathbf{Pr}(\mathrm{RF},\mathrm{WF})$ than Design 1. Design 4 to Design 6 meet the power constraint, but Design 5 has the lowest failure rate, which is due to the fact that both $\mathbf{Pr}\left(\text{RF}\right)$ and $\mathbf{Pr}\left(\text{WF}\right)$ are high, and they can only be reduced simultaneously by DVS. However, if we look at $\mathbf{Pr}\left(\text{RF}\right)$ and $\mathbf{Pr}\left(\text{WF}\right)$ separately, WLM is the most efficient for $\mathbf{Pr}\left(\text{RF}\right)$ reduction and NBL is the most efficient for $\mathbf{Pr}\left(\text{WF}\right)$ reduction, which attests to our postulation in Section 3.2. Compared with the dual-mode SPUF, RO PUF in Design 7 has a lower BER but a much higher functional failure rate. The optimal design (Design 5) reduces the failure rate in memory mode from the baseline design (Design 1) by $75\%$, while reducing the leakage by $21.4\%$ and keeping the BER at an acceptable range of $\le {10}^{-6}$ in PUF mode at the cost of a reasonably small area and power overheads of $\sim 8.9\%$ and $\sim 2.1\%$, respectively. It is worth noting that the bit error rate and code rate can both be improved by concatenating two ECCs at the expense of decoder complexity [22,23].

4.1. Uniqueness

Another important metric for PUF is uniqueness, which measures the capability of a PUF instance to distinguish itself from other PUF instances. The uniqueness can be measured by calculating the inter-die Harming Distance (HD). Ideally, the responses generated from two PUF instances by applying the same challenge should have half of the bits being different. Thus, the uniqueness should be 50%. Let $R_u$ and $R_v$ be the n-bit responses of two different chips, u and v, to the same challenge C, and the uniqueness U for m chips is expressed as [25]

$$U={\displaystyle \frac{2}{m(m-1)}}\sum _{u=1}^{m-1}\sum _{v=u+1}^m{\displaystyle \frac{\text{HD}(R_u,R_v)}{n}}\times 100\%.$$

(18)

To measure the uniqueness of the designed SPUF, two hundred 100-bit-long responses are generated and their fractional HDs are calculated. The distribution is shown in Figure 15. The uniqueness is calculated to be 0.4999, which closely approaches the ideal value of $0.5$. The fitted Gaussian curve of the histogram for fractional HDs has a mean value of $\mu =0.4999$ and a standard deviation of $\sigma =0.0503$.

4.2. Randomness

Randomness refers to the ability of a PUF to generate response bits with an equal probability of being “1” and “0” and every bit is uncorrelated with any other bits. Ideally, the probability to obtain a “1” or a “0” bit is 50%. To measure the randomness of the augmented SPUF design, one million response bits were generated and split into 100 blocks with 10,000 bits each. The National Institute of Standards and Technology (NIST) randomness test results is shown in

Table 3. National Institute of Standards and Technology (NIST) test results.

Test Description	Passed/Total	P-value	Pass?
Frequency	98/100	0.145	√
Block Frequency ($m=128$)	100/100	0.262	√
Cusum-Forward	98/100	0.249	√
Cusum-Reverse	99/100	0.817	√
Runs	97/100	0.102	√
Longest Run of Ones	98/100	0.868	√
Rank	100/100	0.015	√
Spectral DFT	100/100	0.024	√
Non-overlapping Templates ($m=9,B=000000001$)	99/100	0.367	√
Overlapping Templates ($m=9$)	99/100	0.898	√
Approximate Entropy $(m=4)$	98/100	0.475	√
Linear Complexity ($m=1000$)	96/100	0.035	√
Serial $(m=16,▽{\mathrm{\Psi }}_m^2)$	100/100	0.038	√

Cusum refers to Cumulative Sums. DFT refers to Discrete Fourier Transform.

, which shows good randomness of the PUF responses.

5. Conclusions

A novel methodology for designing SPUF for dual application modes has been proposed. Our analysis shows that the memory and PUF modes of operation are affected in a contradicting way by the device geometry of SRAM cells. Four circuit-level techniques are applied to alleviate the design constraints and expand the design space. With the proposed systematic approach to optimize the SRAM cell design for both memory and PUF requirements, the memory failure probability is reduced by $75\%$ while the BER of PUF response is maintained below ${10}^{-6}$. Meanwhile, the area, leakage current and dynamic power are kept to an acceptable level.