Submit to JLPEA Review for JLPEA Propose a Special Issue

Journal Menu

Journal Browser

► Journal Browser

Recent Advances in Emerging Low Power Circuits and Systems

Special Issue Editors
Special Issue Information
Keywords
Published Papers

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 December 2016) | Viewed by 19385

Share This Special Issue

Special Issue Editors

Prof. Dr. Ka Lok Man

E-Mail Website1 Website2
Guest Editor

School of Advanced Technology, Xi’an Jiaotong Liverpool University, Suzhou 215123, China
Interests: AI; IoT; big data analytics; IC designs; WSN
Special Issues, Collections and Topics in MDPI journals

Prof. Dr. M. L. Dennis Wong

E-Mail Website
Guest Editor

Deputy Provost, Heriot-Watt University Malaysia, Putrajaya, Malaysia
Interests: condition monitoring; VLSI signal processing; pattern classification; statistical process control
Special Issues, Collections and Topics in MDPI journals

Dr. Chao Lu

E-Mail Website
Guest Editor

Dept. of Electrical and Computer Engineering, Southern Illinois University, Carbondale, IL, USA
Interests: VLSI hardware architecture

Special Issue Information

Dear Colleagues,

This Special Issue on Emerging Low Power Circuits and Systems will focus on recent advances in design and breakthrough in CAS topics that can lead to emerging revolutionary impacts on our daily life, especially in low power consumer electronics, information and communication technologies and biomedical and health informatics technologies. With change comes opportunities, the market for these emerging electronic products and technologies is also expected to experience exponential growth in the coming decade.

This Special Issue shall highlight the potential and current developments of these low power CAS topics, along with the associated pressing challenges. We believe the proposed Special Issue is coherent and complementary to the areas of interest of semiconductor industry and electronic design automation consortiums.

Research and review papers on Emerging Low Power Circuits and System are solicited in areas including, but not limited to:

Low Power Design, Simulation and Test of Digital, Analog, Mixed Mode and RF Circuits and Systems
Low Power Processor Design and Embedded Systems
VLSI, ASIC, FPGA, SoC and MPSoC
Computer Aided Design and Electronic Design Automation for Low Power Design
Circuits and Systems for Low Power Communications
Nonlinear Circuits and Systems for Low Power Applications
Control Theory Topics in Circuits and Systems
Signal Processing
Low Power Circuits and Systems for Biomedical Applications
Energy Harvesting for Energy Constrained Applications
Circuits and Systems for Cryptography
Circuit/Device Modeling and Simulation
Battery Management Systems
Photovoltaic System Design

Dr. Ka Lok Man
Dr. M. L. Dennis Wong
Dr. Chao Lu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

Low Power Design, Simulation and Test of Digital, Analog, Mixed Mode and RF Circuits and Systems
Low Power Processor Design and Embedded Systems
VLSI, ASIC, FPGA, SoC and MPSoC
Computer Aided Design and Electronic Design Automation for Low Power Design
Circuits and Systems for Low Power Communications
Nonlinear Circuits and Systems for Low Power Applications
Control Theory Topics in Circuits and Systems
Signal Processing
Low Power Circuits and Systems for Biomedical Applications
Energy Harvesting for Energy Constrained Applications
Circuits and Systems for Cryptography
Circuit/Device Modeling and Simulation
Battery Management Systems
Photovoltaic System Design

Published Papers (2 papers)

Download All Papers

Research

Jump to: Review

3333 KiB

Open AccessArticle

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

by Yu Bai and Mingjie Lin

J. Low Power Electron. Appl. 2016, 6(3), 15; https://doi.org/10.3390/jlpea6030015 - 12 Aug 2016

Cited by 3 | Viewed by 7011

Abstract

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits. Full article

(This article belongs to the Special Issue Recent Advances in Emerging Low Power Circuits and Systems)

► Show Figures

Graphical abstract

Review

Jump to: Research

1284 KiB

Open AccessReview

Low Power Design for Future Wearable and Implantable Devices

by Katrine Lundager, Behzad Zeinali, Mohammad Tohidi, Jens K. Madsen and Farshad Moradi

J. Low Power Electron. Appl. 2016, 6(4), 20; https://doi.org/10.3390/jlpea6040020 - 20 Oct 2016

Cited by 23 | Viewed by 11805

Abstract

With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). Full article

(This article belongs to the Special Issue Recent Advances in Emerging Low Power Circuits and Systems)

► Show Figures