Special Issue "Low Power Design Methodologies and Applications"

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 June 2011)

Special Issue Editors

Guest Editor
Prof. Dr. Alexander Fish (Website)

Faculty of Engineering, Bar-Ilan University, Ramat-Gan, 52900, Israel
Interests: low power electronics; ultra low power VLSI circuits and systems; sub/near-threshold digital logic; low power memory arrays; low power CMOS image sensors; sub-threshold asynchronous design; low power applications; analog and digital on-chip image processing
Guest Editor
Prof. Dr. Kaushik Roy (Website)

School of Electrical and Computer Engineering, Purdue University, 465 Northwestern Ave., West Lafayette, IN 47907, USA
Interests: low-power electronics; scaled CMOS devices and circuits; silicon and non-silicon nanoelectronics; process variations and design with unreliable components; VLSI signal processing

Special Issue Information

Dear Colleagues,

The Journal of Low Power Electronics and Applications (JLPEA) is seeking original contributions for the forthcoming issue on low power design methodologies and applications. This issue is scheduled for publication in June, 2011. The aim of this issue is to present original design methodologies for low power design at various abstraction levels, starting with the device and technology levels, moving on through the circuit/logic level and finishing with the system and architecture levels. We intend to place special emphasis on the utilization of these methodologies in low power applications.

Prof. Dr. Kaushik Roy
Dr. Alexander Fish
Guest Editors

Keywords

  • low power applications
  • low power methodologies
  • energy efficient circuits and systems
  • low voltage designs
  • low power architectures
  • power efficient algorithms
  • EDA tools for low power
  • low power emerging technologies

Published Papers (5 papers)

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Research

Open AccessArticle CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors
J. Low Power Electron. Appl. 2012, 2(1), 30-68; doi:10.3390/jlpea2010030
Received: 20 October 2011 / Revised: 18 January 2012 / Accepted: 23 January 2012 / Published: 1 February 2012
PDF Full-text (861 KB) | HTML Full-text | XML Full-text
Abstract
Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs). While most chip [...] Read more.
Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs). While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9 instruction set enabling them to run a full operating system software stack, and hence a wide variety of benchmarking applications. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Open AccessArticle Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review
J. Low Power Electron. Appl. 2011, 1(3), 334-356; doi:10.3390/jlpea1030334
Received: 20 May 2011 / Revised: 29 September 2011 / Accepted: 29 September 2011 / Published: 11 October 2011
Cited by 6 | PDF Full-text (2222 KB) | HTML Full-text | XML Full-text
Abstract
While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap [...] Read more.
While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Figures

Open AccessArticle Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design
J. Low Power Electron. Appl. 2011, 1(2), 303-326; doi:10.3390/jlpea1020303
Received: 16 May 2011 / Revised: 22 August 2011 / Accepted: 5 September 2011 / Published: 14 September 2011
PDF Full-text (2854 KB) | HTML Full-text | XML Full-text
Abstract
The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance [...] Read more.
The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Open AccessArticle Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design
J. Low Power Electron. Appl. 2011, 1(2), 277-302; doi:10.3390/jlpea1020277
Received: 16 May 2011 / Revised: 29 June 2011 / Accepted: 30 June 2011 / Published: 8 July 2011
Cited by 6 | PDF Full-text (840 KB) | HTML Full-text | XML Full-text
Abstract
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored [...] Read more.
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Open AccessArticle Energy Efficient Supply Boosted Comparator Design
J. Low Power Electron. Appl. 2011, 1(2), 247-260; doi:10.3390/jlpea1020247
Received: 6 April 2011 / Revised: 13 June 2011 / Accepted: 20 June 2011 / Published: 24 June 2011
Cited by 3 | PDF Full-text (1694 KB) | HTML Full-text | XML Full-text
Abstract
This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow [...] Read more.
This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)

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