Chips doi: 10.3390/chips5020011

Authors: Hugo Puertas de Araújo

This paper presents the Spike Processing Unit (SPU), a digital spiking neuron model based on a discrete-time second-order Infinite Impulse Response (IIR) filter. By constraining filter coefficients to powers of two, the SPU implements all internal operations via shift-and-add arithmetic on 6-bit signed integers, eliminating general-purpose multipliers. Unlike traditional models, computation in the SPU is fundamentally temporal; spike timing emerges from the interaction between input events and internal IIR dynamics rather than signal intensity accumulation. The model’s efficacy is evaluated through a temporal pattern discrimination task. Using Particle Swarm Optimization (PSO) within a hardware-constrained parameter space, a single SPU is optimized to emit pattern-specific spikes while remaining silent under stochastic noise. Results from cycle-accurate Python simulations and synthesizable VHDL implementations indicate that the learned temporal dynamics are preserved under hardware-constrained digital execution, supporting the feasibility of the proposed approach. This work demonstrates that discrete-time IIR-based neurons enable reliable temporal spike processing under strict quantization and arithmetic constraints.

Chips doi: 10.3390/chips5020010

Authors: Stef Cuyckens Ryan Antonio Chao Fang Marian Verhelst

Hyperdimensional computing (HDC) provides a highly efficient alternative to neural networks for intracranial electroencephalography (iEEG) seizure detection on edge devices with strict resource limits. While sparse HDC can significantly reduce energy use, current hardware fails to capitalize on this for two reasons. First, existing designs do not optimize the encoding architecture specifically for sparse execution, leaving potential energy savings on the table. Second, researchers often ignore the “area” problem, the large physical space high-dimensional vectors take up on a chip, which must be solved to make these devices small enough for practical edge use. This work presents a sparse HDC accelerator that bridges these gaps through three key contributions. First, we streamline the sparse encoding architecture to improve energy and area efficiency by integrating a compressed item memory (CompIM) and simplified spatial bundling. Second, to address the area bottleneck and enable true edge deployment, we systematically explore area trade-offs via sequentialization techniques, evaluating both channel folding (CF) and vector folding (VF). Third, we push efficiency even further by proposing an item-memory-free (IM-free) architecture. By replacing the baseline segmented shift binding with a standard shift binding scheme, and gracefully utilizing raw local binary pattern (LBP) codes directly as shift amounts, we completely bypass the CompIM for simultaneous area and energy savings. However, this optimization incurs a drop in detection accuracy; hence, we ultimately present two tailored configurations. First, our energy-optimized IM-free design achieves a 5.55× area and 3.08× energy improvement over the sparse HDC baseline, alongside 8.20× and 13.37× improvements over the dense baseline. Second, to prioritize clinical performance, our balanced streamlined design utilizes a channel folding factor (CFF) of 4 to preserve higher accuracy. This balanced approach achieves a 5.97× area and a 4.66× energy improvement over the dense baseline, with a 4× latency increase.

Chips doi: 10.3390/chips5010009

Authors: Hiba El Balbali Anas Abou El Kalam

The rapid expansion of the Internet of Things (IoT) has opened resource-limited devices to novel physical threats, such as Side-Channel Attacks (SCAs) and Hardware Trojans (HTs). Traditional security mechanisms are often not capable of standing against such hardware-based attacks, specifically on low-power System-on-Chip (SoC) where static defenses can incur 2× to 3× overhead in silicon area and power. Herein, the gap between hardware security and embedded AI is compositionally formulated for discussion. We present a comprehensive survey of the current hardware threat landscape and analyze the emergence of “Secure-by-Design” paradigms, specifically focusing on the integration of Edge AI and TinyML as active, on-chip intrusion detection mechanisms. This review presents a critical analysis of trade-offs for running lightweight ML models on hardware by comparing state-of-the-art approaches. Our analysis highlights that optimized architectures, such as Mamba-Enhanced Convolutional Neural Networks (CNNs) and Gated Recurrent Unit (GRU), can achieve detection accuracies exceeding 99% against SCA and >92% against stealthy Hardware Trojans, while offering up to 75% lower power consumption compared to standard deep learning baselines. Finally, open challenges such as adversarial attacks on defense models are briefly discussed, and the focus is put on future directions toward constructing secure chips based on robust, AI-driven technology.

Chips doi: 10.3390/chips5010008

Authors: Nao Kitajima Seina Hori Ai Otani Hiroaki Ogawa Shunsuke Okura

For sensing applications, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a lateral overflow integration capacitor (LOFIC) is in high demand. The LOFIC CIS can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for a low electron-referred noise floor. However, the LOFIC CIS faces challenges regarding the power consumption and circuit area when reading both HCG and LCG signals. To address these issues, this study proposes a readout circuit composed of area-efficient MOS capacitors using a folding DC operating point technique and an in-column signal selector for an on-chip HDR merger of HCG and LCG signals. A 10-bit test chip was fabricated with a 0.18 µm CMOS process with MOS capacitors. The fabricated chip maintains high linearity, achieving an integral nonlinearity (INL) of +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal. Furthermore, the proposed design achieves a 14.92% reduction in the average power consumption of the total readout circuit and a 36.5% reduction in the readout circuit area.

Chips doi: 10.3390/chips5010007

Authors: Ramakrishna Goli Aravindhan Alagarsamy Gian Carlo Cardarilli

The fast expansion of the Internet of Things (IoT) has increased the need for strong security measures to protect the enormous network of interconnected devices. This paper proposes a unique approach that combines optimization, intuitive design principles, and Least Weighted Elliptic Curve Cryptography (LWECC) to improve IoT device security while reducing power consumption. The proposed optimization strategy focuses on lowering computational overhead, which is critical for IoT devices with limited energy and processing power. The proposed method significantly reduces the amount of energy required for cryptographic operations by carefully selecting appropriate elliptic curves and optimizing cryptographic algorithms, ensuring that IoT devices may continue to function without compromising security. Furthermore, by selecting elliptic curves with minimal attack vulnerability, the use of LWECC provides an additional layer of protection. This technique ensures that, even in the face of emerging threats, IoT devices remain highly resilient, reducing the chance of security breaches while preserving functionality without using excessive power. Experimental results show a power consumption of only 0.156 W and 0.25 W for memory and router topologies, respectively, with an error margin of 0.01. The stated error margin pertains to the simulation-based evaluation of transmission-level data handling within the LWECC-enabled memory/router pipeline, rather than the risk of physical memory-cell failure or fabrication yield. The value shows the maximum amount of packet/data-stream loss detected during encrypted data transfer, rather than hardware memory reliability.

Chips doi: 10.3390/chips5010006

Authors: Karim M. Abozeid Hassan Mostafa A. H. Khalil Mohamed Refky

This paper presents a novel design for a reconfigurable CDC as a multiplexed sensor fusion that converts three analog signals into digital output bits with different resolutions. The proposed reconfigurable CDC design uses the SAR technique that introduces a small chip area and low power consumption. The proposed novel CDC introduces reconfigurability by using a switching capacitive DAC that solves the problem of converting more than one analog signal with a single converter to a different number of output bits, giving better performance than previous designs. In this paper, three analog signals are used (as a case study) in a weather station to be converted. These signals are temperature, pressure, and humidity that are sensed using the BME-280 Bosch sensor. All CDC specifications are measured for each reconfigured number of output bits. The used supply voltage is 1.0 V, and the sampling frequency is 100 kHz. The 12-bit resolution consumes 2.54 µW, ENOB is 11.47 bits, and SNR equals 73.4 dB. The 8-bit resolution consumes 1.7 µW, ENOB is 7.39 bits, and SNR equals 46.24 dB. The 4-bit resolution consumes 0.68 µW, ENOB is 3.58 bits, and SNR equals 23.45 dB. The total chip area is 0.18 mm2.

Chips doi: 10.3390/chips5010005

Authors: Philippos Papaphilippou

Sorting networks are of prime importance as circuits, with applications in sorting small data chunks, big data analytics, permuting packets, and system interconnects. Finding optimal sorting networks is a highly complex problem, and knowledge on optimal sorting networks is limited. When optimising the network depth or the number of comparators, one of the most expensive tasks is considered to be verification, that is, to verify that the candidate compare-and-swap network actually sorts the data. This grows exponentially with the size of the sorting network. However, FPGAs allow vast amounts of internal parallelism, and our presented work exploits this flexibility using dataflow techniques to achieve unparalleled amounts of speedup for sorting network verification. This work can be used in a modular way to accelerate the search for optimal sorting networks with a high number of inputs, as well for similar verification problems.

Chips doi: 10.3390/chips5010004

Authors: Mohamed Belguith Sonia Eloued Moncef Kadi Jaleleddine Ben Hadj Slama Mahmoud Hamouda

Power converters based on gallium nitride (GaN) are progressing swiftly owing to their exceptional efficiency and tiny dimensions, boosted by high power density and fast switching capabilities. Nevertheless, these benefits are accompanied by considerable thermal management issues that impact reliability, performance, and operational lifespan. This review examines advanced thermal management approaches for high-power-density GaN power converters, including active and passive cooling technologies, sophisticated packaging designs, and the use of novel materials like graphene and diamond to improve heat dissipation. The impacts of thermal boundary resistance, self-heating phenomena, and substrate selection on thermal performance are thoroughly analyzed. Strategies for enhancing printed circuit board (PCB) layouts, thermal vias, and the use of thermal interface materials (TIMs) are also emphasized. The study highlights co-design approaches that optimize thermal resistance and layout efficiency, supporting GaN operation under high-frequency conditions. This thorough investigation offers insights into addressing the thermal challenges linked to GaN technology, promoting its adoption in forthcoming power devices.

Chips doi: 10.3390/chips5010003

Authors: Guang Chen Meng Xu Yuying Chen Fuge Yuan Lanqi Qin Jian Ren

Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration.

Chips doi: 10.3390/chips5010002

Authors: Clayton R. Farias Tiago R. Balen Paulo F. Butzen

Semiconductor technologies are susceptible to radiation effects. The particle incidence in susceptible areas of an integrated circuit (IC) can generate physical interactions capable of producing errors. This paper predicts the IC cross sections for Single Event Effects. The cross section is a metric that provides an IC’s susceptibility to radiation. It deals with particle source interaction and physical design volumes. This work evaluates the IC cross section, exploring the physical design characteristics of susceptible regions in logic gates. It explores particles with low LET, identifying the charge collection areas. Also, the heavy ions are used to evaluate the critical cross section range. Distinct benchmark circuits were simulated to characterize sensitivity trends. The influence of circuit input conditions along with cells’ susceptibility reveals significant findings. The results indicate a difference up to ten times between low- and high-energy particles. Consequently, predicting the IC cross section at an early stage of the design flow is essential, especially for electronics devices used in radiation environments.

Chips doi: 10.3390/chips5010001

Authors: Nicola Lovecchio Giulia Petrucci Fabio Cappelli Martina Baldini Vincenzo Ferrara Augusto Nascetti Giampiero de Cesare Domenico Caputo

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions.

Chips doi: 10.3390/chips4040052

Authors: Nusrat Jahan Ramisha Anan Jannatul Maua Nazia

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near VDD/4 per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows |S21| = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power Psat=8.67 dBm at VDD=4 V, with S11<−15 dB and reverse isolation ≈−16 dB. The layout occupies 1.6×1.6 mm2 and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of Psat and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs (±10% devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends.

Chips doi: 10.3390/chips4040051

Authors: Yadi Zhong

Test time per chip plays an essential role in manufacturing tests. Keeping a low number of test patterns becomes one of the prime objectives in concurrence with achieving the desired fault coverage. Unfortunately, finding an optimum set is an NP-hard problem. Today’s commercial ATPG tools have significantly reduced the number of test patterns to achieve a high fault coverage. However, there is still a huge gap for reducing the total pattern count, equivalent to minimizing test costs in the production phase. In this paper, we propose two novel methods to lower the test pattern count to detect all stuck-at faults in a circuit with the same or higher fault coverage as in the commercial ATPG tool, e.g., TetraMAX II. The first approach begins by applying a small set of random patterns to solve easy-to-detect faults. The remaining faults are detected by the SAT-based attack on logic locking with converting all the remaining faults into one locked circuit. Each stuck-at fault is modeled with its equivalent key gate. The second approach selects the first few patterns generated by the ATPG tool and applies the SAT attack of logic locking to determine the test patterns for detecting the undetected faults. By exploiting the overall linear iteration complexity and the exponential removal of incorrect key combinations per each SAT attack iteration, it is feasible to significantly reduce the total pattern count while maintaining the same or higher fault coverage as the ATPG counterpart. We demonstrate the effectiveness of both approaches and show that we are able to achieve a more compact test pattern set compared to a commercial ATPG tool.

Chips doi: 10.3390/chips4040050

Authors: Junyung Cho Jung-Hyun Lee M. Kim

This paper presents the design of a 140 GHz vector-sum phase shifter in a 28 nm CMOS process. Two variable-gain amplifiers—Gilbert cell and current-steering amplifiers—are investigated and compared. The Gilbert cell-based phase shifter controls the tail current source in a common-source amplifier. However, this configuration exhibits insufficient gain at D-band frequencies. To address this issue, we designed a current-steering variable-gain amplifier in cascode form to improve the gain performance. I/Q signals are generated by Marchand baluns and Lange couplers, and a 13-bit digital-to-analog converter enables fine bias control. Simulation results show that the current-steering phase shifter achieves up to a 4.4 dB higher gain than the Gilbert cell-based phase shifter, with an RMS gain error below 1.3 dB and an RMS phase error below 4.8° across 129–144 GHz.

Chips doi: 10.3390/chips4040049

Authors: Yota Kurokawa Masaru Fukushi

This paper proposes a novel fault-tolerant routing method without creating faulty regions for 3D mesh Network-on-Chips (NoCs). Most conventional methods create faulty regions containing faulty nodes and route packets around them to reach the destinations. However, the creation of faulty regions results in low communication performance and low node utilization. To overcome the two problems, the proposed method does not create faulty regions based on the idea of predefining paths in the absence of shortest paths while allowing the passage of faulty nodes. Simulation results show that, compared with conventional methods, the proposed method reduces average latency by about 44.5% and improves node utilization rate by about 41.2% for 3D mesh NoCs of 5×5×5 nodes.

Chips doi: 10.3390/chips4040048

Authors: Eric Hunt-Schroeder Tian Xia

Silicon-Based Physical Unclonable Functions (PUFs) exploit inherent manufacturing variations to produce a unique, random, and ideally unclonable secret key. As electronic devices are decommissioned and sent for End of Life (EOL) recycling, the encrypted critical program information remains within the device. However, conventional PUFs remain vulnerable to invasive attacks and reverse engineering that with sufficient time, resources, and effort can enable an adversary to bypass the security enclave of the system and extract this secret data. Recent research has started to explore techniques to respond to tamper attempts using electromigration (EM) and time-dependent dielectric breakdown (TDDB) to the PUF entropy source, preventing future authentication attempts with well-known semiconductor reliability failure mechanisms. This work presents a Pre-Amplifier Physical Unclonable Function (Pre-Amp PUF) with a self-corruption function designed and manufactured in a 3 nm FinFET technology. This PUF can perform a destructive read operation as an EOL anti-counterfeit measure against recycled and reused electronics. The destructive read utilizes an accelerated aging technique that exploits both Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) degradations directly at the PUF entropy source bitcell data. This work demonstrates a silicon proven ability to irreversibly corrupt the encryption key, invalidating the PUF key, and blocking future authentication attempts. By utilizing HCI and BTI aging effects rather than physical damage a PUF that can self-corrupt its own key without being detectable with imaging techniques is demonstrated for the first time. A feedback loop enables corruption of up to ~30% of the PUF entropy source, which is approximately 3× more data corruption than the prior state of the art self-corrupting PUF. Our technique reuses on-chip stable (repeatable) PUF bitcells identifying circuitry and thereby minimizes the area overhead to support this differentiated feature.

Chips doi: 10.3390/chips4040047

Authors: Mahfuzur Rahman Talukder Md. Eftekhar Alam Abu Monsur Mohammah Fahim Fakir Sharif Hossain

Cyber physical systems (CPSs) increasingly depend on complex hardware IP cores to perform critical functions. However, triggered hardware Trojans’ stealthy, malicious modifications activated under rare conditions pose significant threats to the safety and reliability of these systems. This research paper introduces a novel detection framework that integrates multi-modal side-channel analysis with trigger-aware machine learning to identify Trojans embedded within IP cores. A lightweight runtime monitoring mechanism enables real-time Trojan detection while adhering to the stringent safety constraints of CPSs. To further strengthen resilience, cryptographic integrity verification and dynamic mitigation through partial reconfiguration are incorporated. Experimental validation on two representative IP cores, AES-128 and RS232, demonstrates the framework’s effectiveness by achieving high detection accuracy (over 96%) with minimal hardware overhead (<3% LUT utilization) and latency increase of 4.95%. It can also be seen that our trigger-aware methodology more than doubles the toggling probability of rare Trojan trigger nets compared to conventional approaches. Furthermore, results from FPGA prototypes and standard Trojan benchmarks confirm the effectiveness of the proposed framework, and the proposed approach achieves high detection accuracy with minimal resource and performance penalties. This work advances the state of the art in securing CPS hardware against Trojan-based attacks.

Chips doi: 10.3390/chips4040046

Authors: Nusrat Jahan Nishat Anjumane Salsabila Susmita Barua Mohammad Mahmudul Hasan Tareq Quazi Delwar Hossain Ramisha Anan Jannatul Maua Nazia

This work presents a wideband variable gain low-noise amplifier (VGA-LNA) specifically engineered for medical systems operating in the C frequency band, which require the substantial amplification of low-intensity signals. The proposed design integrates a low-noise attenuator with a low-noise amplifier (LNA), fabricated using 90 nm CMOS technology and leveraging a combined common-source and common-gate topology. The integrated LNA achieved a notable power gain of 29 dB across a broad bandwidth of 2 GHz (6.4–8.4 GHz), maintaining an average noise figure (NF) below 3.14 dB. The design ensures superior impedance matching, demonstrated by reflection coefficients of S11 < −18.14 dB and S22 < −20.23 dB. Additionally, the amplifier exhibits a third-order input intercept point (IIP3) of 21.15 dBm while consuming only 83 mW from a 1.2 V supply voltage. A low-noise attenuator was incorporated at the input side to enable effective gain control through a digitally controlled variable gain, with step sizes ranging from 0.4 to 3.3 dB. This configuration enables a dynamic range of the transmission coefficient (|S21|) from 16 dB to 23 dB, adjustable by 0.4 dB to 3.3 dB with a trade-off in an NF maintained at 6 dB. The VGA-LNA demonstrates exceptional potential for integration into wireless body area networks (WBANs), balancing flexible gain control with stringent performance metrics.

Chips doi: 10.3390/chips4040045

Authors: Liron Cohen Emmanuel Bender

Schmitt Triggers are essential building blocks in noise-resilient systems and are useful in managing switching behavior in low-power designs. Yet, as CMOS technologies scale down, their designs become increasingly challenging. This paper presents a comprehensive investigation into the performance and reliability of multiple Schmitt Trigger topologies across two CMOS technology nodes (180 nm and 45 nm), with a particular focus on transistor sizing and layout optimization through multi-finger transistor structures. A series of pre-layout and post-layout simulations reveal that fingered implementations significantly enhance hysteresis robustness, switching speed, and delay consistency in PVT variations. Notably, post-layout results in 45 nm technology demonstrate remarkable improvements in both speed and power efficiency. This highlights the inadequacy of schematic-level models to predict the true behavior of fingered transistor configurations. Additionally, we explored the implications of finger designs on reliability concerns including electromigration and IR drop to determine the tradeoff between interconnect reliability optimization and internal routing. The findings establish practical design guidelines for optimizing number of fingers based on device width and technology node, offering new insights into layout-aware Schmitt Trigger design for high-performance and area-constrained applications.

Chips doi: 10.3390/chips4040044

Authors: Raghad H. AlShekh Shefa A. Dawwd Farah N. Qassabbashi

Every element of our contemporary lives has changed as a result of the widespread use of computing infrastructure and information technology in daily life. Less focus has been placed on the hardware components that underpin the computing revolution, despite the fact that its effects on software applications have been the most obvious. The computer chip is the most basic component of computer hardware and powers all digital devices. Every gadget, including mainframes, laptops, cellphones, tablets, desktop PCs, and supercomputers, is powered by different computer chips. Although there are many different types of these chips, the biggest producers in this field are AMD (Advanced Micro Devices), Intel, and ARM (Advanced RISC Machines). These companies make processors for both consumer and business markets. Users have compared their products based on a number of factors, including pricing, cache and memory, approaches, etc. This paper provides a comprehensive comparative analysis of Intel, AMD, and ARM processors, focusing on their architectural characteristics and performance within the context of burgeoning artificial intelligence applications. The detailed architectural features, performance evaluation for AI workloads, a comparison of power efficiency and cost, and analysis for current market trends are presented. By thoroughly examining core architectural elements and key performance factors, this work provides valuable insights for users and developers to seek optimal processor choices to maximize AI tool utilization in the contemporary era.

Chips doi: 10.3390/chips4040043

Authors: Mohammad Abdullah-Al-Shafi

Quantum-dot Cellular Automata (QCA) technology has emerged as a promising approach for constructing nanoscale digital circuits, offering notable advantages such as minimal power consumption, rapid processing speeds, and highly compact layouts. Traditional CMOS technology faces significant challenges at the nanoscale, including reduced gate control and increased current leakage. QCA, on the other hand, provides a robust platform for building next-generation digital systems. In this study, a unique single-layer QCA-based Full-Adder (QCAFA) and Carry-Save Adder (CSA) architecture is developed to enhance key performance factors such as delay, space, cost, and cell block count. The outlined designs demonstrate superior efficiency compared to state-of-the-art single-layer and multilayer QCA designs. Simulation results conducted with QCADesigner 2.0.3 and QCADesigner-E reveal that the proposed architecture achieves a substantial 34.29% diminution in total cells compared with the recent design, utilising only 46 QCA cells. Similarly, for the CSA, the proposed design attains an 18.62% reduction in cell count compared with its best counterpart, utilising only 424 QCA cell blocks. To enhance design credibility and hardware relevance, this research additionally models and validates the architecture using the Verilog hardware description language (HDL Version 12.0), thereby bridging the gap between nano-architecture and HDL-based prototyping. Simulation results obtained through QCADesigner confirm the correctness and stability of the QCA layout, while HDL simulation verifies functional equivalence at the behavioural and structural levels. The proposed designs not only enhance speed and reduce energy consumption but also offer better manufacturability. The findings of this study highlight the potential of QCA technology as a feasible substitute for CMOS for high-performance digital arithmetic circuits at the nanoscale.

Chips doi: 10.3390/chips4040042

Authors: Gabriele Manganaro

This position paper extends the author’s keynote address from the 2024 IEEE European Solid-State Electronics Research Conference, offering a perspective on effective strategies for the advancement of analog and mixed-signal (AMS) integrated circuit (IC) design. It is argued that traditional methodologies, characterized by their focus on transistor-level optimization within individual sub-blocks, are insufficient for satisfying the stringent performance and power consumption demands of contemporary information and communication technologies (ICT), especially in the context of expanding AI applications. Consequently, a paradigm shift is necessary, emphasizing “full-stack” solutions that prioritize comprehensive system-level analysis and aim to minimize physical resources and reduce complexity by innovating across the established boundaries of design abstraction levels. Building on prior work, this manuscript offers a more thorough justification for the proposed full-stack analog design methodology, supported by broader evidence and more comprehensive discussion. It also identifies key considerations regarding EDA and workforce development as topics for future work.

Chips doi: 10.3390/chips4040041

Authors: Ilya Gerasin Ilya Semerikov Wei Zhang

Microwave-driven quantum logic gates in trapped-ion systems offer a scalable and laser-free alternative to optical control, with the potential for robust integration into surface-electrode trap architectures. In this work, we present a systematic design guideline for planar ion traps optimized for fast two-qubit microwave gates using chip-integrated conductors. We investigate two electrode configurations, one employing a single microwave line for driving σ transitions, and another with two symmetric lines for π transitions. Through finite-element simulations, we analyze ion height, magnetic field gradients, heating effects, and gate durations under realistic cryogenic conditions. Our results show that both configurations can achieve two-qubit gate times in the order of 10 μs for Be+9 and Ca+40 ions.

Chips doi: 10.3390/chips4040040

Authors: Trace Langdon Jeff Dix

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems.

Chips doi: 10.3390/chips4040039

Authors: Jorge Johanny Saenz-Noval Umberto Gatti Cristiano Calligaro

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (BERsys). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and BERsys at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work.

Chips doi: 10.3390/chips4030038

Authors: Raqibul Hasan Md Shahanur Alam Tarek M. Taha

Memristor crossbar-based neural network systems offer high throughput with low energy consumption. A key advantage of on-chip training in these systems is their ability to mitigate the effects of device variability and faults. This paper presents an efficient on-chip training circuit for memristor crossbar-based multi-layer neural networks. We propose a novel method for storing the product of two analog signals directly in a memristor device, eliminating the need for ADC and DAC converters. Experimental results show that the proposed system is approximately twice as energy efficient and 1.5 times faster than existing memristor-based systems for training multi-layer neural networks.

Chips doi: 10.3390/chips4030037

Authors: Pratik Nimbalkar Pragna Bhaskar Lakshmi Narasimha Vijay Kumar Meghna Narayanan Emanuel Torres Sai Saravanan Ambi Venkataramanan Mohanalingam Kathaperumal

Artificial intelligence is redefining the computing landscape. Chiplets and heterogeneous integration have become the key strategies for current and next-generation processors. In the wake of Moore’s law slowing down, system integration through advanced packaging has emerged as the leading approach to achieve the highest performance per cost. Overall, the system is converging around substrate which is the main component of packaging. Glass stands out as the superior integration platform for chiplet-based systems. Glass substrates provide unmatched electrical and mechanical properties leading to unprecedented design and integration flexibility at a lower cost than competitive technologies. Three key advantages make glass the platform of choice: the ability to tune material properties, the ability to structure glass, and the feasibility of processing on a large panel scale. This review details the fundamentals of glass processing and manufacturing, innovative integration techniques, and cutting-edge research that collectively position glass substrate as a superior option for the next-generation systems for AI and beyond. Finally, we outline how technology must be shaped in the coming years to drive system scaling.

Chips doi: 10.3390/chips4030036

Authors: Konstantina Mylona Helen-Maria Dounavi Yiorgos Tsiatouhas

Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front end of Flash analog-to-digital converters (ADCs). BTI-induced aging leads to substantial increments in the offset voltage of the ADC comparators, which in turn affect their trip point voltage, leading to the alteration of the ADC’s performance characteristics, such as gain, full-scale error and integral nonlinearity. Thus, erroneous responses are generated. Next, we propose a low-cost BTI-induced aging mitigation technique based on a circuit reconfiguration method which periodically alters the average voltage stress on the ADC comparators’ transistors. The proposed method limits the comparators’ offset voltage development, restricting the shift in their trip point voltage. Consequently, the impact of aging on the performance characteristics of the ADC is drastically reduced, and its reliability is improved. According to our simulations, after two years of operation, the gain error is reduced by 95.43%, the full-scale error is reduced by 63.31% and the integral nonlinearity is reduced by 63.00%, with respect to operation without applying the proposed aging mitigation technique.

Chips doi: 10.3390/chips4030035

Authors: Sunil Kumar Panigrahy Fa Xing Che Yeow Chon Ong Hong Wan Ng Gokul Kumar

In recent years, many electronic device industries have shown interest in using artificial intelligence (AI) to quickly estimate package warpage. Machine learning is one of the AI techniques which will give an express prediction on package warpage with the help of several attributes of the data and different algorithms. This study uses a deep learning (DL) model which combines with a deep neural network (DNN) technique and finite element analysis (FEA) to estimate the package warpage of a mobile universal flash storage (UFS) package. Developing a DL model requires a training database from finite element simulation results and a DNN algorithm. The developed DL model accuracy for package warpage is calculated by validating FEA simulation results and experiment data. The error between the DL model prediction and FEA simulation result is less than 7%. This proposed approach can help effectively and efficiently assess package warpage for new product introduction (NPI) with less FEA simulation work and less test vehicle of a real package for warpage measurement and assessment.

Chips doi: 10.3390/chips4030034

Authors: Sujal Gupta Jolly Xavier

Drawing inspiration from biological brains’ energy-efficient information-processing mechanisms, photonic integrated circuits (PICs) have facilitated the development of ultrafast artificial neural networks. This in turn is envisaged to offer potential solutions to the growing demand for artificial intelligence employing machine learning in various domains, from nonlinear optimization and telecommunication to medical diagnosis. In the meantime, silicon photonics has emerged as a mainstream technology for integrated chip-based applications. However, challenges still need to be addressed in scaling it further for broader applications due to the requirement of co-integration of electronic circuitry for control and calibration. Leveraging physics in algorithms and nanoscale materials holds promise for achieving low-power miniaturized chips capable of real-time inference and learning. Against this backdrop, we present the State of the Art in neuromorphic photonic computing, focusing primarily on architecture, weighting mechanisms, photonic neurons, and training, while giving an overall view of recent advancements, challenges, and prospects. We also emphasize and highlight the need for revolutionary hardware innovations to scale up neuromorphic systems while enhancing energy efficiency and performance.

Chips doi: 10.3390/chips4030033

Authors: Miguel Bucio-Macías Luis Pizano-Escalante Omar Longoria-Gandara

Nowadays, Graphical Processor Units (GPUs) are a great technology to implement Artificial Intelligence (AI) processes; however, a challenge arises when the inclusion of a GPU is not feasible due to the cost, power consumption, or the size of the hardware. This issue is particularly relevant for portable devices, such as laptops or smartphones, where the inclusion of a dedicated GPU is not the best option. One possible solution to that problem is the use of a CPU with AI capabilities, i.e., parallelism and high performance. In particular, RISC-V architecture is considered a good open-source candidate to support such tasks. These capabilities are based on vector operations that, by definition, operate over many elements at the same time, allowing for the execution of SIMD instructions that can be used to implement typical AI routines and procedures. In this context, the main purpose of this proposal is to develop an ASIC Vector Engine RISC-V architecture compliant that implements a minimum set of the Vector Extension capable of the parallel processing of multiple data elements with a single instruction. These instructions operate on vectors and involve addition, multiplication, logical, comparison, and permutation operations. Especially, the multiplication was implemented using the Vedic multiplication algorithm. Contributions include the description of the design, synthesis, and validation processes to develop the ASIC, and a performance comparison between the FPGA implementation and the ASIC using different nanometric technologies, where the best performance of 110 MHz, and the best implementation in terms of silicon area, was achieved by 7 nm technology.

Chips doi: 10.3390/chips4030032

Authors: Sander Reniers Yi Wang Salim Abdi Jasper de Graaf Aleksandr Zozulia Kevin Williams Yuqing Jiao

The fast-maturing photonic integration technology is calling for a versatile platform that supports both active and passive functions as well as high scalability through component miniaturization. Indium phosphide (InP) has long been recognized for its ability to deliver a comprehensive suite of photonic components. InP membrane technology has emerged as a next-generation solution that could unite the functional completeness with high scalability. This paper describes recent advancements in the InP-membrane-on-Si (IMOS) platform, which supports high-performance passives, polarization and mode handling, native light sources, amplifiers, modulators and detectors, and novel material integration.

Chips doi: 10.3390/chips4030031

Authors: Orazio Aiello

This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital gates, enabling them to be automated and fully synthesizable. This further results in supply voltage scalability and regulator-less operation, allowing direct powering by an energy harvester without additional ancillary circuit blocks (such as current and voltage sources). In particular, the circuit similarities in implementing a rail-to-rail dynamic voltage comparator and a relaxation oscillator using only digital gates are discussed. The building blocks previously reported in the literature by the author will be described, and the common root of their design will be highlighted.

Chips doi: 10.3390/chips4030030

Authors: Enze Shi Aixia Yuan Junzheng Liu Niannan Chang Xinqi Guo

A multifunctional circuit with high-pass and low-pass negative group delays can be achieved by simply changing the values of the components in the circuit, without changing the circuit structure. While achieving negative group delay, the circuit also has flat broadband characteristics and lower losses. Theoretical calculations and equation derivation are provided. The experimental circuit was simulated, and the simulation results were essentially consistent with the theoretical results, indicating the feasibility of the experiment.

Chips doi: 10.3390/chips4030029

Authors: Paolo Lorenzi Roberto Penzo Enrico Tonazzo Edoardo Bezzati Maurizio Galvano Fausto Borghetti

A new control system implemented with a single-stage DC-DC controller to power an LED headlamp for automotive applications is presented in this work. Daytime running light (DRL), low beam (LB), high beam (HB) and adaptive driving beam (ADB) are typical functions requiring a dedicated LED driver solution to fulfill car maker requirements for front-light applications. Single-stage drivers often exhibit a significant overshoot in LED current during transitions from driving a higher number of LEDs to a lower number. To maintain LED reliability, this current overshoot must remain below the maximum current rating of the LEDs. If the overshoot overcomes this limit, it can cause permanent damage to the LEDs or reduce their lifespan. To preserve LED reliability, a comprehensive system has been proposed to minimize the peak of LED current overshoots, especially during transitions between different operating modes or LED string configurations. A key feature of the proposed system is the implementation of a parallel discharging path to be activated only when the current flowing in the LEDs is higher than a predefined threshold. A prototype incorporating an integrated test chip has been developed to validate this approach. Measurement results and comparison with state-of-the-art solutions available in the market are shown. Furthermore, a critical aspect to be considered is the proper dimensioning of the discharging path. It requires careful considerations about the gate driver capabilities, the discharging resistor values, and the thermal management of the dumping element. For this purpose, an extensive study on how to size the relative components is also presented.

Chips doi: 10.3390/chips4020028

Authors: Ahmed Hamouda Elsayed Samir Abozyd Abdelrahman Toraya Mohamed Abdelsalam Mansour Noha Gaber

On-chip optical accelerometers can be a promising alternative to capacitive, piezo-resistive, and piezo-electric accelerometers in some applications due to their immunity to electromagnetic interference and high sensitivity, which allow for robust operation in electromagnetically noisy environments. This paper focuses on the characterization of an easy-to-fabricate tri-axial fiber-free optical MEMS accelerometer, which employs a simple assembly consisting of a light emitting diode (LED), a quadrant photodetector (QPD), and a suspended proof mass, measuring acceleration through light power modulation. This configuration enables simple readout circuitry without the need for complex digital signal processing (DSP). Performance modeling was conducted to simulate the LED’s irradiance profile and its interaction with the proof mass and QPD. Additionally, experimental tests were performed to measure the device’s mechanical sensitivity and validate the mechanical model. Lateral mechanical sensitivity is obtained with acceptable discrepancy from that obtained from FEA simulations. This work consolidates the performance of the design adapted and demonstrates the accelerometer’s feasibility for practical applications.

Chips doi: 10.3390/chips4020027

Authors: Enrique M. Spinelli Valentín A. Catacora Federico N. Guerrero Marcelo A. Haberman

Fully differential amplifier circuits are well suited for instrumentation front ends and signal-conditioning applications. They offer high common-mode rejection ratios (CMRRs) regardless of the passive component tolerances but remain sensitive to imbalances in active devices. By using power supply bootstrapping (PSB), the CMRRs of these circuits can be improved, where they become independent of mismatches in both passive and active components. This technique works by forcing the power supply nodes to follow the common-mode input voltage, which significantly enhances the CMRR. However, this approach introduces stability issues that must be addressed through dedicated compensation strategies without degrading the overall performance. In this work, the theoretical background, a design methodology, and experimental validation are presented. The proposed technique was applied to a fully differential amplifier built with general purpose operational amplifiers. Prior to the PSB, the amplifier exhibited a CMRR of 90 dB at 1 kHz. A straightforward application of PSB led to instability in the common-mode behavior; however, with the proposed compensation method, the amplifier achieved stable operation and an improved CMRR of 130 dB.

Chips doi: 10.3390/chips4020026

Authors: Mehdi Otmani Ayssar Serhan Jean-Daniel Arnould Estelle Lauga-Larroze Pascal Reynier Alexandre Giry

This paper extends the quasi-load insensitive (QLI) Class-E Doherty power amplifier (PA) design methodology to address Doherty PA combiners with complex load impedance trajectories. Additionally, the QLI operation is analyzed for generalized class-E output matching networks with input series inductors and finite DC-feed inductors. We demonstrate that the QLI class-E Doherty operation can be achieved for various Doherty combiners by selecting the appropriate combination of class-E outputs matching network resonance factors and input series inductances. Moreover, a modified class-E output network is proposed to overcome the frequency limitation that might be caused by the class-E network resonance factor choice. To validate the proposed methodology, two 40 W Doherty PAs are designed and simulated using commercial GaN HEMT transistors achieving more than 70% efficiency over a 6 dB output power back-off at 3.8 GHz.

Chips doi: 10.3390/chips4020025

Authors: Qiuming Luo Yanming Lei Kunzhong Wu Xuan Wei

This paper presents an FPGA-based configurable drive waveform generation system for industrial inkjet printheads, targeting the need for real-time adaptability in printing across heterogeneous materials. The system adopts a three-array waveform description method, enabling flexible configuration and precise generation of drive waveforms with adjustable geometry, segment duration, and voltage levels. Through a modular and parameterized design, the system supports rapid waveform switching during column-wise printing without interrupting the printing process, addressing the challenges posed by varying ink absorption characteristics across different substrates. Experimental results demonstrate the system’s capability to achieve smooth waveform transitions within an interval of 830 µs between columns, with data loading times as low as 4 µs. This efficient performance ensures seamless operation and high flexibility. The proposed approach significantly reduces the hardware cost and improves printing efficiency, offering a scalable and robust solution for next-generation industrial inkjet applications involving complex and dynamic material surfaces.

Chips doi: 10.3390/chips4020024

Authors: Achraf El Bouazzaoui Omar Mouhib Abdelkader Hadjoudja

This paper presents NeuroAdaptiveNet, an FPGA-based neural network framework that dynamically self-adjusts its architectural configurations in real time to maximize performance across diverse datasets. The core innovation is a Dynamic Classifier Selection mechanism, which harnesses the k-Nearest Centroid algorithm to identify the most competent neural network model for each incoming data sample. By adaptively selecting the most suitable model configuration, NeuroAdaptiveNet achieves significantly improved classification accuracy and optimized resource usage compared to conventional, statically configured neural networks. Experimental results on four datasets demonstrate that NeuroAdaptiveNet can reduce FPGA resource utilization by as much as 52.85%, increase classification accuracy by 4.31%, and lower power consumption by up to 24.5%. These gains illustrate the clear advantage of real-time, per-input reconfiguration over static designs. These advantages are particularly crucial for edge computing and embedded applications, where computational constraints and energy efficiency are paramount. The ability of NeuroAdaptiveNet to tailor its neural network parameters and architecture on a per-input basis paves the way for more efficient and accurate AI solutions in resource-constrained environments.

Chips doi: 10.3390/chips4020023

Authors: María de Lourdes Rivas Becerra Juan José Raygoza Panduro Edwin Christian Becerra Alvarez Susana Ortega Cisneros José Luis González Vidal

This work presents the design of a system of a highly flexible pseudorandom number generator system (PRNG) incorporating both conventional and neuro-generators. The system integrates four internal generators with different conditions to produce new output sequences with adequate bits distribution and complexity. Two generators function at a frequency of 100 MHz with adjustable frequency settings, while two neuro-generators employ impulse neurons with distinct behaviours at 4 kHz, also modifiable. The proposed system meets 12 statistical randomness standards based on NIST’s (National Institute of Standards and Technology of U. S.) test suite, including the Frequency test, Binary Matrix Rank test, Linear Complexity test, and Random Excursion test, among others. Each resulted in a P-value greater than 0.01, confirming the pseudo-randomness of the generated sequences. The system is implemented on a reconfigurable device FPGA (Field Programmable Gate Array), with a low occupancy percentage, demonstrating its feasibility for various applications.

Chips doi: 10.3390/chips4020022

Authors: Yi Joe Low Yi Chen Lee Wen Xun Lian Harikrishnan Ramiah

This paper presents a novel fully integrated radio frequency (RF) rectifier tailored for a wide power dynamic range (PDR) with multiband adaptability to efficiently convert AC RF power into DC power. The proposed rectifier utilizes the strength of interstage gate biasing to achieve high power conversion efficiency (PCE) across a broad range of input power levels. Through its reconfigurable mode, the circuit seamlessly transitions between a low-power path and high-power path to ensure optimal performance across a wide PDR. Simulated using CMOS 65 nm technology, the post-layout assessment reveals a peak PCE of 48.8% at 900 MHz and 46.4% at 1800 MHz, with an extensive PDR of 20 dB for PCE exceeding 20% at both frequencies.

Chips doi: 10.3390/chips4020021

Authors: Farshad Shirani Bidabadi Mahalingam Nagarajan Thangarasu Bharatha Kumar Yeo Kiat Seng

This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other by large MIMCAPs, which results in good performance with low power consumption. The proposed circuit achieves a bandwidth of 2.5 GHz, suitable for several wireless communication standards such as GSM, WLAN, and Bluetooth. In the first stage, a current-reuse circuit with shunt feedback is used to satisfy input impedance matching and signal amplification with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve the noise figure (NF), harmonic distortion, and output impedance matching. The proposed LNA is designed in 65 nm CMOS technology and covers a frequency range of 0.17–2.68 GHz. The proposed LNA achieves a maximum gain of 17.24 dB, a minimum NF of 2.67 dB, a maximum IIP3 of −14.9 dBm, and input and output return losses of less than −10 dB. The power consumption of the proposed LNA is 3.52 mW from a 1 V power supply, and the core area is 0.3 mm2.

Chips doi: 10.3390/chips4020020

Authors: Shihai He Huan Chen

This paper presents a comprehensive review of GaAs HBT-based Doherty power amplifiers (DPAs) targeting 5G New Radio (NR) handset applications. Focusing on the critical challenges of linearity enhancement, back-off efficiency improvement, bandwidth extension under low-voltage (3.4 V) operation, and chip thermal management, the authors analyze state-of-the-art DPAs published in recent years. Key innovations including dynamic power division technique, third order intermodulation (IM3) cancellation technology, and compact output combiners are comparatively studied. Using 5G NR signals, the critical performance of the latest reported PA such as maximum linear power, back-off efficiency, bandwidth, and operating voltage are quantitatively investigated. The measurement results demonstrated that the best performance in recent DPAs achieved high linear power of 31 dBm with 34% PAE and 30 dBm with 31% PAE at the N78 and N77 bands, respectively. The corresponding adjacent channel leakage ratios (ACLRs) were lower than −36.5 dBc without digital pre-distortion (DPD). This review provides a comprehensive understanding of the latest advancements and future directions in highly efficient and linear DPA designs for 5G handset front-end modules.

Chips doi: 10.3390/chips4020019

Authors: John Taylor Maurer Ahmed Mamdouh Mohamed Ahmed Parsa Khorrami Sabrina Hassan Moon Dayane Alfenas Reis

Modern computer applications have become highly data-intensive, giving rise to an increase in data traffic between the processor and memory units. Computing-in-Memory (CiM) has shown great promise as a solution to this aptly named von Neumann bottleneck problem by enabling computation within the memory unit and thus reducing data traffic. Many simulation tools in the literature have been proposed to enable the design space exploration (DSE) of these novel computer architectures as researchers are in need of these tools to test their designs prior to fabrication. This paper presents a collection of classical nonvolatile memory (NVM) and CiM simulation tools to showcase their capabilities, as presented in their respective analyses. We provide an in-depth overview of DSE, emerging NVM device technologies, and popular CiM architectures. We organize the simulation tools by design-level scopes with respect to their focus on the devices, circuits, architectures, systems/algorithms, and applications they support. We conclude this work by identifying the gaps within the simulation space.

Chips doi: 10.3390/chips4020018

Authors: Yu Liu Pak Kwong Chan

This paper presents the design and implementation of a linear, stable, low-power and PVT insensitive floating active resistor, which is realized using TSMC 40 nm CMOS process technology. By incorporating the automatic tuning circuit, this work has achieved improved performance metrics, which include low process sensitivity, reduced temperature coefficient, and good linearity. Monte Carlo (MC) simulations are conducted to evaluate the active resistor’s performance under variations in temperature, process, and supply voltage. The proposed design has demonstrated an average resistance process sensitivity of 0.64%, a temperature coefficient (T.C.) of 57 ppm/°C across −25 °C to 85 °C, and a linearity figure of merit (FOM) of 2.4 × 10−2 V−1 with a resistance close to MΩ level. It can achieve a linear resistance tuning range of 430.5 kΩ to 1.714 MΩ. The typical power consumption of a single active resistor is 0.25 µW at 2.1 V bootstrapped supply voltage through a Dickson charge pump (DCP) circuit using a DC input of 1 V. These results have confirmed that the proposed active resistor can function as a robust and efficient resistor for low-voltage integrated circuits and systems.

Chips doi: 10.3390/chips4020017

Authors: Fotios Vartziotis

The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized solutions that minimize test costs while ensuring compliance with power and thermal constraints. The toolkit provides (a) a high-level language (HLL) for the intuitive representation of test processes, along with a smart syntax and logic checker for verification; (b) an advanced compilation and execution environment featuring two computationally efficient Time-Division Multiplexing (TDM)-specialized solvers; (c) a sophisticated Test Access Mechanism (TAM) optimization framework; (d) a customized visualization environment capable of depicting and animating power- and thermal-annotated test schedules; (e) a versatile testbed for educational and research activities.

Chips doi: 10.3390/chips4020016

Authors: Babar Ali Ghulam Murtaza Hafiz Muhammad Bilal Tariq Mahmood Muhammad Rashid Zaib Ullah

This work presents a cost-effective optical frequency comb generator (CEOFCG) solution for generating multiple, equally spaced carriers in wavelength-division-multiplexing coherent optical fiber communication systems (WDM-COFCS). It enables the replacement of multiple laser sources with a single continuous-wave laser, eliminating the need for additional amplification and filtering setups. The CEOFCG provides stable multicarrier spacing, broad phase coherence, and compatibility with advanced modulation formats, enhancing the performance of WDM-COFCS. Digital signal processing (DSP) techniques, including digital filtering, detection, and impairment compensation, contribute to high transmission and spectral efficiency (SE). The results demonstrate the potential of CEOFCG in achieving cost reduction, complexity reduction, high SE, and optimal utilization of optical fiber bandwidth, particularly in higher-order QAM-based COFCS.

Chips doi: 10.3390/chips4020015

Authors: Mattia Mirigaldi Valeria Piscopo Maurizio Martina Guido Masera

The rapid growth of the Internet of Things (IoT) has significantly expanded the deployment of resource-constrained devices, introducing new security and privacy challenges. To address these concerns, the National Institute of Standards and Technology (NIST) concluded a multi-year effort by announcing ASCON as the new lightweight cryptography standard in 2023. ASCON’s cipher suite includes both Authenticated Encryption with Associated Data (AEAD) and hashing functions, ensuring authenticity, confidentiality, and broad applicability. Since its standardization, there has been a significant research effort focused on enhancing ASCON’s performance under diverse application constraints as well as assessing its vulnerability to advanced side-channel attacks. This study offers a comprehensive overview of current ASCON hardware implementations on FPGA and ASIC platforms, examining key design trade-offs. Additionally, it examines the latest side-channel attacks on ASCON were examined. These attacks exploited weaknesses in the hardware implementations rather than in the algorithm itself. Being highly efficient, they could breach both unprotected and protected implementations. This survey also reviews the proposed countermeasures against these powerful attacks and analyzes how their associated overhead conflicts with the performance demands of real-world ASCON applications. The synthesis of these findings offers clear guidelines for designers seeking to implement ASCON. At the same time, areas requiring further investigation are identified. As ASCON sees ever more widespread deployment, this review serves as a reference for understanding the current state of research and guiding future developments toward efficient and secure implementations.

Chips doi: 10.3390/chips4020014

Authors: Yota Kurokawa Masaru Fukushi

This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, a detour direction is statically defined for each faulty region. Due to the long detour path and the use of eight virtual channels, this method has the problems of high communication latency and a large hardware overhead. To solve these problems, the first proposed method allows adaptive detours for faulty regions, and the second proposed method allows the passage of them. The simulation results show that, compared with the existing method, the second proposed method enables us to reduce the latency by about 30% and improve the throughput by about 3.1% with half of the virtual channels.

Chips doi: 10.3390/chips4020013

Authors: Qiankun Liu Sam Amiri

With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is essential for enabling real-time AI applications in areas such as autonomous systems, industrial automation, and intelligent security. Deploying BNN on FPGA using RISC-V, rather than directly deploying the model on FPGA, sacrifices detection speed but, in general, reduces power consumption and on-chip resource usage. The AI-extended RISC-V core is capable of handling tasks beyond BNN inference, providing greater flexibility. This work utilises the lightweight Zero-Riscy core to deploy a BNN on FPGA. Three custom instructions are proposed for convolution, pooling, and fully connected layers, integrating XNOR, POPCOUNT, and threshold operations. This reduces the number of instructions required per task, thereby decreasing the frequency of interactions between Zero-Riscy and the instruction memory. The proposed solution is evaluated on two case studies: MNIST dataset classification and an intrusion detection system (IDS) for in-vehicle networks. The results show that for MNIST inference, the hardware resources required are only 9% of those used by state-of-the-art solutions, though with a slight reduction in speed. For IDS-based inference, power consumption is reduced to just 13% of the original, while resource usage is only 20% of the original. Although some speed is sacrificed, the system still meets real-time monitoring requirements.

Chips doi: 10.3390/chips4010012

Authors: Vitor A. P. Aguiar Saulo G. Alberton Matheus S. Pereira

Radiation effects on electronic devices represent a major concern in applications for harsh environments, such as aerospace and nuclear facilities. This article presents a review of fundamental aspects of radiation effects on semiconductors, with a primary focus on Single-Event Effects. It discusses charge collection models, destructive effects, applications in detectors, and impacts on digital devices, drawing from recent research findings.

Chips doi: 10.3390/chips4010011

Authors: Juan Ramirez-Rios José Juan Avilés-Bravo Mario Moreno-Moreno Luis Hernández-Martínez Alfredo Morales-Sánchez

In this work, the simulation of deoxidation–oxidation of oxygen vacancies (VOs) in an oxide matrix with embedded conductive nanocrystals (c-NCs) is carried out for the development of bipolar resistive switching memories (BRSMs). We have employed the three-dimensional kinetic Monte Carlo (3D-kMC) method to simulate the RS behavior of BRSMs. The c-NC is modeled as fixed oxygen vacancy (f-VO) clusters, defined as sites with zero recombination probability. The three-dimensional oxygen vacancy configuration (3D-VOC) obtained for each voltage step of the simulation is used to calculate the resistive state and the electrical current. It was found that the c-NC reduces the voltage required to switch the memory state from a high to a low resistive state due to the increase in a nonhomogeneous electrical field between electrodes.

Chips doi: 10.3390/chips4010010

Authors: Yuanxun Cao Dayong Ma Haiming Li Guangxu Cui Jie Zhang Zhiwei Yang

This article summarizes the current development status of nanoimprint lithography (NIL) technology and its application prospects in multiple industries. Nanoimprint lithography technology has significant advantages, such as low cost, high resolution, and no development, and is not affected by standing wave effects, making it a potential technology in industries such as semiconductors, photovoltaics, and LEDs. However, nanoimprint lithography technology still faces challenges in terms of film characteristics and material selection during application. This article analyzes existing research and discusses its application advantages in the fields of patterned sapphire substrates (PSSs), Light-Emitting Diode (LED) chips, photovoltaic cells, etc., and proposes the role of technological progress in promoting industrialization. This article summarizes the opportunities and challenges of nanoimprint lithography technology in the future industrialization process and anticipates its development prospects for large-scale production.

Chips doi: 10.3390/chips4010009

Authors: Awang Ma Bin Gao Peng Yao Jianshi Tang He Qian Huaqiang Wu

The rapid advancement of artificial intelligence (AI) technologies has significantly increased the demand for high-performance computational hardware. Memristor-based compute-in-memory (CIM) technology, also known as resistive random-access memory (RRAM)-based CIM technology, shows great potential for addressing the data transfer bottleneck and supporting high-performance computing (HPC). In this paper, a multi-scale thermal model is developed to evaluate the temperature distribution in RRAM-based CIM chips and the influence of various factors on thermal behavior. The results indicate that hotspot temperatures can be mitigated by reducing the epoxy molding compound (EMC) thickness, increasing the substrate thickness, and lowering boundary thermal resistance. Moreover, optimizing the layout of analog computing circuits and digital circuits can reduce the maximum temperature by up to 4.04 °C. Furthermore, the impact of temperature on the conductance of RRAM devices and the inference accuracy of RRAM-based CIM chips is analyzed. Simulation results reveal that thermal-induced accuracy loss in CIM chips is significant, but the computation correction method effectively reduces the accuracy loss from 66.4% to 1.4% at 85 °C.

Chips doi: 10.3390/chips4010008

Authors: Jingyang Chen Nanbo Chen Zhe Wang Runjiang Dou Jian Liu Nanjian Wu Liyuan Liu Peng Feng Gang Wang

High-dynamic-range (HDR) technology enhances the capture of luminance beyond the limits of traditional images, facilitating the capture of more nuanced and lifelike visual effects. This advancement has profound implications across various sectors, such as medical imaging, augmented reality (AR), virtual reality (VR), and autonomous driving systems. The evolution of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) manufacturing techniques, particularly through backside illumination (BSI) and advancements in three-dimensional (3D) stacking architectures, is driving progress in HDR’s capabilities. This paper provides a review of the technologies developed over the past six years that augment the dynamic range (DR) of CIS. It systematically introduces and summarizes the implementation methodologies and distinguishing features of each technology.

Chips doi: 10.3390/chips4010007

Authors: Mitsutoshi Sugawara Hidekana Susa Kenji Mori Akira Matsuzawa

Leading-edge analog/mixed-signal LSI designs are still hand-crafted using graphic editors. These graphic editors do not include functionality for parameterized topologies in variable designs. Instead of graphic editors, we have developed the SWA (SoftWare Analog) language, which can describe and display placements and routing for analog/mixed-signal LSI layouts with less or similar labor time. By using SWA, we have developed an R-DAC (resistive digital–analog converter) layout with a parameterized topology and various parameters, such as ~1 Gsps, 4~12-bit (upper segment type + lower R-2R type) R-DAC, and 1~3.3 V logic with 1~3.3 Vpp analog output.

Chips doi: 10.3390/chips4010006

Authors: Jorge André Gastmaier Marques Sergiu Arpadi Maximiliam Luppe

Multiple serial interfaces have emerged to meet system requirements across devices, ranging from slower-speed buses, such as I2C, to high throughput serial interfaces, like JESD204. To address the need for a medium-speed protocol and to resolve I2C shortcomings, the MIPI Alliance developed the I3C specification, which is a royalty-free next-generation version of I2C with new features and backward compatibility. Since the MIPI Alliance’s I3C work only includes the specifications, it depends on third-party vendors to develop their own cores according to the specifications. Only a few processing systems contain I3C Controllers, each with its own partial implementation of the specification, and there are no open-source controller cores. Thus, this work presents an open-source I3C Controller HDL framework that operates at the maximum specified SDR frequency and is compatible with the Linux kernel. Both the core and Linux kernel drivers are available under permissive open-source licenses. The solution is mostly aimed at development boards with Xilinx Zynq and Intel Cyclone SoC; nevertheless, the structure of the project allows it to be ported to other vendors and carriers.

Chips doi: 10.3390/chips4010005

Authors: Haoyu Zhuang Xudong Chen Enzhe Zhang Qiang Li

This review discusses the principle of typical bandgap reference circuits and analyzes their sources of errors. In order to provide readers with a clear perspective, we categorize the error sources into four types: (a) amplifier offset; (b) high-order nonlinearity of VBE; (c) current mirror mismatch; and (d) other error sources. For these error sources, the most commonly used methods to reduce or minimize them to achieve high accuracy are summarized. Furthermore, this review explores sub-1V bandgap reference design techniques, addressing the increasing demand for low-power and low-voltage applications. Finally, we provide some suggestions for a future high-accuracy reference design.

Chips doi: 10.3390/chips4010004

Authors: Jeff Dix

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz.

Chips doi: 10.3390/chips4010003

Authors: Massimo Vatalaro Raffaele De Rose Marco Lanuzza Felice Crupi

Physically unclonable functions (PUFs) represent emerging cryptographic primitives that exploit the uncertainty of the CMOS manufacturing process as an entropy source for generating unique, random and stable keys. These devices can be potentially used in a wide variety of applications ranging from secret key generation, anti-counterfeiting, and low-cost authentications to advanced protocols such as oblivious transfer and key exchange. Unfortunately, guaranteeing adequate PUF stability is still challenging, thus often requiring post-silicon stability enhancement techniques. The latter help to contrast the raw sensitivity to on-chip noise and variations in the environmental conditions (i.e., voltage and temperature variations), but their area and energy costs are not always feasible for IoT devices that operate with constrained budgets. This pushes the demand for ever more stable, area- and energy-efficient solutions at design time. This review aims to provide an overview of several weak PUF solutions implemented in CMOS technology, discussing their performance and suitability for being employed in security applications.

Chips doi: 10.3390/chips4010002

Authors: Zirui Lin Hideharu Amano Masayuki Takigahira Naoya Terakado Katsutoshi Itoyama Haris Gulzar Kazuhiro Nakadai

This paper proposes efficient implementations of robot audition systems, specifically focusing on deployments using HARK, an open-source software (OSS) platform designed for robot audition. Although robot audition systems are versatile and suitable for various scenarios, efficiently deploying them can be challenging due to their high computational demands and extensive processing times. For scenarios involving intensive high-dimensional data processing with large-scale microphone arrays, our generalizable GPU-based implementation significantly reduced processing time, enabling real-time Sound Source Localization (SSL) and Sound Source Separation (SSS) using a 60-channel microphone array across two distinct GPU platforms. Specifically, our implementation achieved speedups of 23.3× for SSL and 3.0× for SSS on a high-performance server equipped with an NVIDIA A100 80 GB GPU. Additionally, on the Jetson AGX Orin 32 GB, which represents embedded environments, it achieved speedups of 14.8× for SSL and 1.6× for SSS. For edge computing scenarios, we developed an adaptable FPGA-based implementation of HARK using High-Level Synthesis (HLS) on M-KUBOS, a Multi-Access Edge Computing (MEC) FPGA Multiprocessor System on a Chip (MPSoC) device. Utilizing an eight-channel microphone array, this implementation achieved a 1.2× speedup for SSL and a 1.1× speedup for SSS, along with a 1.1× improvement in overall energy efficiency.

Chips doi: 10.3390/chips4010001

Authors: Rosario Mita Angelo Mazzone

This paper presents a novel procedure for designing robust high-speed asynchronous DC-DC converter controllers. The method relies on the use of Workcraft©, a plugin-based development system designed to synthesize and validate the asynchronous control logic, ensuring hazard-free implementation even in the case of non-persistent input signals. The simulation results (using a proprietary 90 nm technology) showed a typical time response from input to output of less than 1.4 ns, which fits the fast response requirements for DC-DC converters.

Chips doi: 10.3390/chips3040020

Authors: Jecel Mattos de Assumpção Oswaldo Hideo Ando Hugo Puertas de Araújo Mario Gazziro

This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key differences like a reduced instruction set that is optimized for embedded systems, the removal of floating-point instructions, reduced register count, and modified data types. These changes enable the processor to operate efficiently in resource-constrained environments while still maintaining assembly-level compatibility with the standard RISC-V architecture. The educational aspects of this project are also a key focus. By working on this project, students can gain hands-on experience with digital logic design, Verilog programming, and computer architecture. The project also includes tools and scripts to help students transform assembly code into binary format, making it easier for them to test and verify their designs. Additionally, the project’s open-source nature allows for collaboration and the sharing of knowledge among students and researchers worldwide.

Chips doi: 10.3390/chips3040019

Authors: Hidekana Susa Kenji Mori Mitsutoshi Sugawara Akira Matsuzawa

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation with DRC and LVS SWA API can be finished in about 1 min.

Chips doi: 10.3390/chips3040018

Authors: Can Hong Weizhong Chen Xianshan Wen Theodore W. Manikas Ping Gui Mitchell A. Thornton

This paper presents an advanced Controller Area Network (CAN) bus transceiver designed to enhance security using frame-level authentication with the concept of a nonphysical virtual auxiliary data channel. We describe the newly conceived transceiver security features and provide results concerning the design, implementation, fabrication and test of the transceiver to validate its functionality and robust operation in the presence of systemic error sources including Process, Voltage, and Temperature (PVT) variations. The virtual auxiliary channel integrates CAN frame authentication signatures into the primary data payload via phase modulation while also providing compatibility with existing CAN protocols, interoperability with non-enhanced systems and requiring no network or software modifications. Enhanced rail converters are designed to facilitate single-rail to dual-rail data conversion and vice versa, preserving phase information and minimizing phase errors across various nonideal effects such as frequency drift, Process, Voltage, and Temperature (PVT) variations, and cable phase mismatch. This ensures reliable data transmission and robust authentication in the presence of adversarial cyberattacks such as packet injection. The receiver recovers both the CAN frame data and the security signature, comparing the latter with an authorized signature to provide a real-time “GO/NO_GO” signal for verifying packet authenticity and without exceeding the CAN clock jitter specifications.

Chips doi: 10.3390/chips3040017

Authors: Nick Brown

FPGAs are popular in many fields but have yet to gain wide acceptance for accelerating HPC codes. A major cause is that whilst the growth of High-Level Synthesis (HLS), enabling the use of C or C++, has increased accessibility, without widespread algorithmic changes these tools only provide correct-by-construction rather than fast-by-construction programming. The fundamental issue is that HLS presents a Von Neumann-based execution model that is poorly suited to FPGAs, resulting in a significant disconnect between HLS’s language semantics and how experienced FPGA programmers structure dataflow algorithms to exploit hardware. We have developed the high-level language Lucent which builds on principles previously developed for programming general-purpose dataflow architectures. Using Lucent as a vehicle, in this paper we explore appropriate abstractions for developing application-specific dataflow machines on reconfigurable architectures. The result is an approach enabling fast-by-construction programming for FPGAs, delivering competitive performance against hand-optimised HLS codes whilst significantly enhancing programmer productivity.

Chips doi: 10.3390/chips3040016

Authors: Md Kawser Bepary Tao Zhang Farimah Farahmandi Mark Tehranipoor

Physical side-channel attacks utilize power, electromagnetic (EM), or timing signatures from cryptographic implementations during operation to retrieve sensitive information from security-critical devices. This paper provides a comprehensive review of these potent attacks against cryptographic hardware implementations, with a particular emphasis on pre-silicon leakage assessment methodologies. We explore the intricacies of cryptographic algorithms, various side-channel attacks, and the latest mitigation techniques. Although leakage assessment techniques are widely adopted in the post-silicon phase, pre-silicon leakage assessment is an emerging field that addresses the inherent limitations of its post-silicon counterpart. We scrutinize established post-silicon techniques and provide a detailed comparative analysis of pre-silicon leakage assessment across different abstraction levels in the hardware design and verification flow. Furthermore, we categorize and discuss existing pre-silicon power and electromagnetic modeling techniques for leakage detection and mitigation that can be integrated with electronic design automation (EDA) tools to automate security assessments. Lastly, we offer insights into the future trajectory of physical side-channel leakage assessment techniques in the pre-silicon stages, highlighting the need for further research and development in this critical area of cybersecurity.

Chips doi: 10.3390/chips3040015

Authors: Zhaoyang Shen Shiheng Yang Jiaxin Liu

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.

Chips doi: 10.3390/chips3040014

Authors: Jiong Pan Zeda Wang Bingchen Zhao Jiaju Yin Pengwen Guo Yi Yang Tian-Ling Ren

With the development of artificial intelligence and edge computing, the demand for high-performance non-volatile memory devices has been rapidly increasing. Two-dimensional materials have ultrathin bodies, ultra-flattened surfaces, and superior physics properties, and are promising to be used in non-volatile memory devices. Various kinds of advanced non-volatile memory devices with semiconductor, insulator, ferroelectric, magnetic, and phase-change two-dimensional materials have been investigated in recent years to promote performance enhancement and functionality extension. In this article, the recent advances in two-dimensional material-based non-volatile memory devices are reviewed. Performance criteria and strategies of high-performance two-dimensional non-volatile memory devices are analyzed. Two-dimensional non-volatile memory array structures and their applications in compute-in-memory architectures are discussed. Finally, a summary of this article and future outlooks of two-dimensional non-volatile memory device developments are given.

Chips doi: 10.3390/chips3030013

Authors: Enrico Castaldo Marco Eugenio Gibilaro

The analog–mixed signal simulation environment, used for verifying non-volatile memory macrocells, is presented. It has been adopted over the last decade, providing excellent results in verification coverage, efficiency, and flexibility. This methodology ensures a smooth and effective transition from full transistor/fully analog simulations to fully digital simulations while maintaining most of the environment’s features. This allows verification designers to exchange data, stimuli, and results, thereby enhancing debugging capabilities and reducing simulation time.

Chips doi: 10.3390/chips3030012

Authors: Biswajit Jana Ayan Roy Chaudhuri

Oxygen vacancy engineering in metal oxides is a propitious route to modulate their resistive switching properties for memory and neuromorphic applications. This review provides an account of the research works on tailoring RS behavior in oxide thin-film-based memristor devices by oxygen vacancy engineering. We discuss the recent research progress on controlling oxygen vacancy concentration in metal oxide thin films and its impact on their resistive switching properties for application in electronic memory and neuromorphic computing devices.

Chips doi: 10.3390/chips3030011

Authors: Leonardo Barboni

This study introduces a rectenna, functioning as an RF envelope detector, utilizing a 16 nm bulk MOS transistor (metal-oxide-semiconductor field-effect transistor) for nonlinear detection. A circuit architecture is presented alongside a detailed design methodology and simulations. The detector efficiently demodulates a 2.4 GHz OOK (On/Off Keying) encoded signal, comprising a 32-bit word, within 320 μs. Remarkably, the circuit operates passively, requiring no voltage supply or bias current, and functions effectively with −53 dBm input power at the antenna. This capability enables the decoding of 32-bit unsigned integer radio packets as a wakeup radio event. The effectiveness of the envelope detector is substantiated through comprehensive simulations.

Chips doi: 10.3390/chips3030010

Authors: Mario Gazziro João Paulo Carmo

This paper provides a comparative analysis of AES (Advanced Encryption Standard) and Salsa20 algorithm implementations, focusing on power consumption efficiency in passive RFID (radio-frequency identification) tags and ultra-low-power devices. The main objective of this work is to determine which of these algorithms is more suitable to operate in these types of devices. For this purpose, ASIC (application-specific integrated circuit) implementations of AES and Salsa20 based on low-power approaches were developed and their power consumption was evaluated. The results demonstrate that Salsa20 power consumption is lower than AES (about 17%), indicating that Salsa20 is a much better choice than AES for passive RFID tags.

Chips doi: 10.3390/chips3020009

Authors: Will Lillis Max Cohen Hoffing Wayne Burleson

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications.

Chips doi: 10.3390/chips3020008

Authors: Liuting Shang Sheng Lu Yichen Zhang Sungyong Jung Chenyun Pan

Datapath synthesis is a crucial step in synthesis flow and aims at globally minimizing an area by identifying shareable logic structures. This paper introduces a novel Directed Acyclic Graph (DAG)-based datapath synthesis method based on graph isomorphism and gate reconfiguration. Unlike algorithms that identify common specification logic, our approach simplifies the problem by focusing on searching for common topology. Leveraging the concept of gate reconfiguration, our algorithm extends the applicability of DAG-based datapath synthesis by transforming a topology-equivalent network into a specification-equivalent network. Experimental results demonstrate up to 23.6% improvement when optimizing the adder–subtractor circuit, a scenario not addressed by existing DAG-based datapath synthesis algorithms.

Chips doi: 10.3390/chips3020007

Authors: Victor H. Arzate-Palma David G. Rivera-Orozco Gerardo Molina Salgado Federico Sandoval-Ibarra

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed.

Chips doi: 10.3390/chips3020006

Authors: Cristiano Calligaro Umberto Gatti

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well.

Chips doi: 10.3390/chips3020005

Authors: Michele Dei Francesco Gagliardi Paolo Bruschi

This review is aimed at the integrated circuit design community and it explores slew-rate enhancement techniques for switched-capacitor amplifiers, with a primary focus on optimizing settling time within power constraints. Key challenges are addressed, including the selection between single-stage and two-stage amplifiers, along with the utilization of advanced circuit-level techniques for slew-rate enhancement. Presently, there exists a gap in comprehensive discussion, with reliance primarily on two Figures of Merit aimed at assessing power efficiency under specific capacitive loads. However, these metrics fail to adequately assess the performance of the existing slew-rate enhancer solutions at different values of capacitive loads. As a consequence, the designer lacks clear guidelines in practical situations. This review provides a state-of-the art mapping under a figure of merit dedicated to assess the whole settling delay, and also introduces a novel performance metric which highlights the role of the circuital architectures, regardless of external operating conditions. By offering a thorough examination, this review seeks to steer future research in switched-capacitor amplifier design, thereby facilitating informed decision-making and fostering innovation in the field.

Chips doi: 10.3390/chips3020004

Authors: Corina Cuntan Caius Panoiu Manuela Panoiu Ioan Baciu Sergiu Mezinescu

Because of the large number of parameters that interact in amplifier functions, determining dynamic regime parameters as well as the mode of function of amplifier stages is an extremely complex problem. This paper describes a LabVIEW application for studying the functioning of an amplifier in various connections. The user selects the generator’s parameters, the type of connection and its parameters, as well as the load circuit characteristics. The application can determine both the stage characteristics and the Bode characteristics. The amplifier’s stability zone, as well as its gain and phase, are determined based on these characteristics. An important advantage of this application is that the design of the amplifier stage can be created starting from some parameters that the amplifier can establish, from which the values of components can be determined. In order to validate the simulation results from the LabVIEW application, the specialized program Multisim was used, as well as experimental measurements using the Electronics Explorer Board. Both Multisim and Electronics Explorer Board can determine Bode characteristics. In both simulations and experimental amplifiers, the same schemes with the same transistor were used. The application can be used for educational purposes as well as to design an amplifier’s stage to achieve specific parameters.

Chips doi: 10.3390/chips3010003

Authors: Roberto La Rosa Danilo Demarchi Sandro Carrara Catherine Dehollain

This paper presents a novel CMOS RF-to-DC converter for ultra-low-power wireless sensor nodes powered by RF wireless power transfer. The proposed converter achieves 10% higher power conversion efficiency than a conventional rectifier, with only a 1% increase in power consumption. The system employs a reconfigurable Dickson topology, operates on the unlicensed 868 MHz ISM band, and includes a built-in power-efficient MPPT system architecture. Experimental measurements show a maximum power conversion efficiency of 55% in the power range from −22 dBm to 0 dBm, with a power sensitivity of −22 dBm for a DC output voltage of 2.4 V. The proposed converter offers a promising solution for efficient wireless power transfer and energy harvesting in ultra-low-power wireless sensor nodes.

Chips doi: 10.3390/chips3010002

Authors: Andrea Vittimberga Riccardo Corelli Giuseppe Scotti

Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core devoted to a real-time spike-sorting process for the classification phase based on the source neurons from which they were emitted. On-chip spike-sorting is also essential to achieve enough data reduction to allow for wireless transmission within the power constraints imposed on implantable devices. The design of such integrated circuits must meet stringent constraints related to ultra-low power density and the minimum silicon area, as well as several application requirements. The aim of this work is to present real-time hardware architecture able to perform all the spike-sorting tasks on chip while satisfying the aforementioned stringent requirements related to this type of application. The proposed solution has been coded in VHDL language and simulated in the Cadence Xcelium tool to verify the functional behavior of the digital processing chain. Then, a synthesis and place and route flow has been carried out to implement the proposed architecture in both a 130 nm and a FD-SOI 28 nm CMOS process, with a 200 MHz clock frequency target. Post-layout simulations in the Cadence Xcelium tool confirmed the proper operation up to a 200 MHz clock frequency. The area occupation and power consumption of the proposed detection and clustering module are 0.2659 mm2/ch, 7.16 μW/ch, 0.0168 mm2/ch, and 0.47 μW/ch for the 130 nm and 28 nm implementation, respectively.

Chips doi: 10.3390/chips3010001

Authors: Feifan Gao Pak Kwong Chan

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 nV/Hz @1 kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoMnpb of 1.15 × 10−6 ((µV/Hz)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications.

Chips doi: 10.3390/chips2040016

Authors: Ehsan Rahiminejad Hamed Aminzadeh

Different winner-take-all (WTA) and loser-take-all (LTA) circuits are studied, and their operations are analyzed in this review. The exclusive operation of the current conveyor, binary tree, and time-domain WTA/LTA architectures, as the most important architectures reported in the literature, are compared from the perspectives of power consumption, speed, and precision.

Chips doi: 10.3390/chips2040015

Authors: Luigi Giuffrida Guido Masera Maurizio Martina

In recent years, the development of Advanced Driver-Assistance Systems (ADASs) is driving the need for more reliable and precise on-vehicle sensing. Radar and lidar are crucial in this framework, since they allow sensing of vehicle’s surroundings. In such a scenario, it is necessary to master these sensing systems, and knowing their similarities and differences is important. Due to ADAS’s intrinsic real-time performance requirements, it is almost mandatory to be aware of the processing algorithms required by radar and lidar to understand what can be optimized and what actions can be taken to approach the real-time requirement. This review aims to present state-of-the-art radar and lidar technology, mainly focusing on modulation schemes and imaging systems, highlighting their weaknesses and strengths. Then, an overview of the sensor data processing algorithms is provided, with some considerations on what type of algorithms can be accelerated in hardware, pointing to some implementations from the literature. In conclusion, the basic concepts of sensor fusion are presented, and a comparison between radar and lidar is performed.

Chips doi: 10.3390/chips2040014

Authors: Khalid Lodhi Jayant Chhillar Sumit J. Darak Divisha Sharma

5G Cell Search (CS) is the first step for user equipment (UE) to initiate communication with the 5G node B (gNB) every time it is powered ON. In cellular networks, CS is accomplished via synchronization signals (SS) broadcasted by gNB. 5G 3rd generation partnership project (3GPP) specifications offer a detailed discussion on the SS generation at gNB, but a limited understanding of their blind search and detection is available. Unlike 4G, 5G SS may not be transmitted at the center of carrier frequency, and their frequency location is unknown to UE. In this work, we demonstrate the 5G CS by designing 3GPP compatible hardware realization of the physical layer (PHY) of the gNB transmitter and UE receiver. The proposed SS detection explores a novel down-sampling approach resulting in a 60% reduction in on-chip memory and 50% lower search time. Via detailed performance analysis, we analyze the functional correctness, computational complexity, and latency of the proposed approach for different word lengths, signal-to-noise ratio (SNR), and down-sampling factors. We demonstrate end-to-end 5G CS using GNU Radio-based RFNoC framework on the USRP-FPGA platform and achieve 66% faster SS search compared to software. The 3GPP compatibility and demonstration on hardware strengthen the commercial significance of the proposed work.

Chips doi: 10.3390/chips2030013

Authors: Filippo Di Giovanni

Silicon carbide is changing power electronics; it is enabling massive car electrification owing to its far more efficient operation with respect to mainstream silicon in a large variety of energy conversion systems like the main traction inverter of an electric vehicle (EV). Its superior performance depends upon unique properties such as lower switching and conduction losses, safer high-temperature operation and high-voltage capability. Starting briefly with a description of its physics, more detailed information is then given about some key manufacturing steps such as crystal growth and epitaxy. Afterwards, an overview of its inherent defects and how to mitigate them is presented. Finally, a typical EV’s propulsion inverter is shown, proving the technology’s effectiveness in meeting requirements for mass electrification. Foreword: In recent years, SiC has drawn the attention of a growing number of power electronics designers as the material has good prospects for reducing environmental impacts on a global basis. The goal of this paper, based on the author’s contribution to the introduction of the technology at STMicroelectronics, is to show the potential of silicon carbide in enabling massive car electrification. The company’s SiC MOSFETs, tailored to the automotive industry, are enabling visionary EV makers to pave the way for sustainable e-mobility. The intent of this paper is to describe, for a large crowd of readers, how SiC features can accelerate such a transition by quantifying the benefits they bring in terms of improved efficiency in an EV electric powertrain. The paper also has the ambition to highlight the material’s physics and to give an overview of its production processes, starting from the crystal growth for realizing substrates to the main epitaxy techniques. Some space has been devoted to the analysis of the main crystal defects not present in silicon and whose nature poses new challenges in terms of manufacturing yields and screening. Finally, some insights into the market evolution and on the transition to 200 mm wafers are given.

Chips doi: 10.3390/chips2030012

Authors: Sallar Ahmadi-Pour Mathis Logemann Vladimir Herdt Rolf Drechsler

In this paper, we propose a Virtual Prototype (VP) driven verification methodology for Hardware (HW) peripherals. In particular, we combine two approaches that complement each other and use the VP as a readily available reference model: We use (A) Coverage-Guided Fuzzing (CGF) which enables comprehensive verification at the unit-level of the Register-Transfer Level (RTL) HW peripheral with a Transaction Level Modeling (TLM) reference, and (B) an application-driven co-simulation-based approach that enables verification of the HW peripheral at the system-level. As a case-study, we utilize a RISC-V Platform Level Interrupt Controller (PLIC) as HW peripheral and use an abstract TLM PLIC implementation from the open source RISC-V VP as the reference model. In our experiments we find three behavioral mismatches and discuss the observation of these, as well as non-functional timing behavior mismatches, that were found through the proposed synergistic approach. Furthermore, we provide a discussion and considerations on the RTL/TLM Transactors, as they embody one keystone in cross-level methods. As the different approaches uncover different mismatches in our case-study (e.g., behavioral mismatches and timing mismatches), we conclude a synergy between the methods to aid in verification efforts.

Chips doi: 10.3390/chips2030011

Authors: Riccardo Della Sala Francesco Centurelli Giuseppe Scotti Gaetano Palumbo

This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.

Chips doi: 10.3390/chips2030010

Authors: Jin-Jia Shang Nicholas Phipps I-Chyn Wey Tee Hui Teo

For Convolutional Neural Networks (CNNs), Depthwise Separable CNN (DSCNN) is the preferred architecture for Application Specific Integrated Circuit (ASIC) implementation on edge devices. It benefits from a multi-mode approximate multiplier proposed in this work. The proposed approximate multiplier uses two 4-bit multiplication operations to implement a 12-bit multiplication operation by reusing the same multiplier array. With this approximate multiplier, sequential multiplication operations are pipelined in a modified DSCNN to fully utilize the Processing Element (PE) array in the convolutional layer. Two versions of Approximate-DSCNN (A-DSCNN) accelerators were implemented on TSMC 40 nm CMOS process with a supply voltage of 0.9 V. At a clock frequency of 200 MHz, the designs achieve 4.78 GOPs/mW and 4.89 GOP/mW power efficiency while occupying 1.16 mm2 and 0.398 mm2 area, respectively.

Chips doi: 10.3390/chips2020009

Authors: Hamam Abd Andreas König

In contemporary devices, the number and diversity of sensors is increasing, thus, requiring both efficient and robust interfacing to the sensors. Implementing the interfacing systems in advanced integration technologies faces numerous issues due to manufacturing deviations, signal swings, noise, etc. The interface sensor designers escape to the time domain and digital design techniques to handle these challenges. Biology gives examples of efficient machines that have vastly outperformed conventional technology. This work pursues a neuromorphic spiking sensory system design with the same efficient style as biology. Our chip, that comprises the essential elements of the adaptive neuromorphic spiking sensory system, such as the neuron, synapse, adaptive coincidence detection (ACD), and self-adaptive spike-to-rank coding (SA-SRC), was manufactured in XFAB CMOS 0.35 μm technology via EUROPRACTICE. The main emphasis of this paper is to present the measurement outcomes of the SA-SRC on-chip, evaluating the efficacy of its adaptation scheme, and assessing its capability to produce spike orders that correspond to the temporal difference between the two spikes received at its inputs. The SA-SRC plays a crucial role in performing the primary function of the adaptive neuromorphic spiking sensory system. The measurement results of the chip confirm the simulation results of our previous work.

Chips doi: 10.3390/chips2020008

Authors: Danilo Pietro Pau Prem Kumar Ambrose Fabrizio Maria Aymone

This paper presents a state-of-the-art review of different approaches for Neural Architecture Search targeting resource-constrained devices such as microcontrollers, as well as the implementations of on-device learning techniques for them. Approaches such as MCUNet have been able to drive the design of tiny neural architectures with low memory and computational requirements which can be deployed effectively on microcontrollers. Regarding on-device learning, there are various solutions that have addressed concept drift and have coped with the accuracy drop in real-time data depending on the task targeted, and these rely on a variety of learning methods. For computer vision, MCUNetV3 uses backpropagation and represents a state-of-the-art solution. The Restricted Coulomb Energy Neural Network is a promising method for learning with an extremely low memory footprint and computational complexity, which should be considered for future investigations.

Chips doi: 10.3390/chips2020007

Authors: Qummar Zaman Senan Alraho Andreas König

This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase.

Chips doi: 10.3390/chips2020006

Authors: Gian-Franco Dalla Betta Jixing Ye

Silicon radiation detectors, a special type of microelectronic sensor which plays a crucial role in many applications, are reviewed in this paper, focusing on fabrication aspects. After addressing the basic concepts and the main requirements, the evolution of detector technologies is discussed, which has been mainly driven by the ever-increasing demands for frontier scientific experiments.

Chips doi: 10.3390/chips2020005

Authors: Esteban Garzón Leonid Yavits Adam Teman Marco Lanuzza

Content-addressable memory (CAM) has been part of the memory market for more than five decades. CAM can carry out a single clock cycle lookup based on the content rather than an address. Thanks to this attractive feature, CAM is utilized in memory systems where a high-speed content lookup technique is required. However, typical CAM applications only support exact matching, as opposed to approximate matching, where a certain Hamming distance (several mismatching characters between a query pattern and the dataset stored in CAM) needs to be tolerated. Recent interest in approximate search has led to the development of new CAM-based alternatives, accelerating the processing of large data workloads in the realm of big data, genomics, and other data-intensive applications. In this review, we provide an overview of approximate CAM and describe its current and potential applications that would benefit from approximate search computing.

Chips doi: 10.3390/chips2010004

Authors: Jose M. de la Rosa

This paper reviews the state of the art on bandpass ΣΔ modulators (BP-ΣΔMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-ΣΔM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.

Chips doi: 10.3390/chips2010003

Authors: William Bontems Daniel Dzahini

This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

Chips doi: 10.3390/chips2010002

Authors: Nicola Russo Haochun Huang Eugenio Donati Thomas Madsen Konstantin Nikolic

Neuromorphic computing is promising to become a future standard in low-power AI applications. The integration between new neuromorphic hardware and traditional microcontrollers is an open challenge. In this paper, we present an interface board and a communication protocol that allows communication between different devices, using a microcontroller unit (Arduino Due) in the middle. Our compact printed circuit board (PCB) links different devices as a whole system and provides a power supply for the entire system using batteries as the power supply. Concretely, we have connected a Dynamic Vision Sensor (DVS128), SpiNNaker board and a servo motor, creating a platform for a neuromorphic robotic system controlled by a Spiking Neural Network, which is demonstrated on the task of intercepting incoming objects. The data rate of the implemented interface board is 24.64 k symbols/s and the latency for generating commands is about 11ms. The complete system is run only by batteries, making it very suitable for robotic applications.

Chips doi: 10.3390/chips2010001

Authors: Luís Henrique Rodovalho Pedro Toledo Farzad Mir Farshad Ebrahimi

Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations.

Chips doi: 10.3390/chips1030015

Authors: Junyao Li Pak Kwong Chan

This paper presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable of generating higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS transistor as the current generator, a high-threshold PMOS transistor as the active load and an active voltage doubling network to generate the reference voltage. Implemented in TSMC 40 nm CMOS technology, the proposed circuit operates at a minimum supply of 0.65 V and consumes 5.5 nA. Under one sample simulation, the obtained T.C. is 16.64 ppm/°C and the nominal Vref is 489.6 mV (75.3% of  Vddmin) for the temperature range from −20 °C to 80 °C. For Monte-Carlo simulation of 200 samples at room temperature, the average output voltage is 488 mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of 13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a power supply rejection of −45.5 dB and −76.3 dB at 100 kHz and 100 MHz. Compared to the representative prior-art works realized in the same technology and a similar supply current, the proposed circuit has offered the best 1-sampe T.C., the best average T.C. in multiple samples, the highest output voltage, the maximum output voltage per minimum supply voltage and the lowest process sensitivity in the output, Vref.