A Novel Second Harmonic Voltage Suppression Control for PSFB Converter in Dual-Stage Single-Phase Rectifier

Abstract

The inherent second harmonic power pulse in single-phase grid-connected rectifiers leads to a noticeable output voltage ripple and thus results in the degradation of the system. A novel second harmonic suppression control is introduced in this paper to address this issue. The key point of the proposed control lies in the real-time prediction of the phase-shifted full-bridge (PSFB) converter’s desired duty cycle through accurate PSFB converter modeling. By accurately predicting the ideal duty cycle, the proposed control facilitates a significant enhancement in the control loop’s gain specifically at the second harmonic frequency, thereby improving the overall system performance. To validate the theoretical analysis, a series of simulations and experiments were conducted. The results demonstrate the effectiveness of the proposed second harmonic suppression control in mitigating second harmonic output voltage ripple.

1. Introduction

As global concerns about rising fossil fuel prices and the urgent need to address climate change intensify, dual-stage single-phase rectifiers have garnered significant worldwide attention [1,2,3,4,5]. Among these rectifiers, the phase-shifted full-bridge DC-DC (PSFB) converter stands out as a crucial component in the subsequent stage due to its remarkable efficiency and unique galvanic isolation properties [6,7,8,9]. However, a significant challenge arises from the pulsating input power of the front-stage single-phase power factor corrector (PFC). This pulsating input power oscillates at twice the grid frequency (2f_ac), leading to an inherent 2f_ac ripple voltage across the DC bus. If not effectively mitigated by the rear-stage PSFB converter, this ripple voltage can have a significant negative impact on the operational lifespan of connected electrical equipment [10,11,12,13].

To effectively suppress this second harmonic voltage ripple, several approaches have been proposed. The most commonly adopted method involves the integration of large electrolytic capacitors or L-C filters directly onto the DC bus. These components serve to smooth out the ripple voltage and provide stability to the DC bus. However, this approach has its limitations, as the bulky capacitors and filters occupy significant space and reduce the overall power density of the system.

Another strategy is to introduce an active decoupling circuit onto the DC bus [14]. This circuit is specifically designed to absorb and dissipate the second harmonic power, thus reducing the ripple voltage. Although this approach is more efficient in mitigating the ripple, it also comes with the disadvantage of adding additional components and complexity to the system, further reducing power density.

In the pursuit of more efficient and compact solutions, researchers are exploring innovative approaches to suppress the second harmonic voltage ripple. One promising direction involves the optimization of the PSFB converter itself. By incorporating advanced control algorithms and optimizing the converter’s design, it is possible to improve its ability to handle the pulsating input power and reduce the ripple voltage across the DC bus. This approach has the potential to achieve higher power density while maintaining efficient ripple suppression. This approach typically involves the implementation of a Proportional Resonant (PR) controller [15,16,17]. The PR controller is designed to provide rapid tracking capabilities at the targeted frequency, in this case, 2f_ac. This enables the converter to more effectively regulate the DC bus voltage and mitigate the ripple caused by the pulsating input power from the front-stage PFC. However, while the PR controller offers a promising solution, it also has its limitations. One significant drawback is its high sensitivity to variations in the grid frequency (f_ac). As the grid frequency deviates from its nominal value, the performance of the PR controller degrades significantly. This makes it challenging to maintain optimal ripple suppression under real-world conditions where grid frequency variations are inevitable. Another limitation of the PR controller is its relatively poor dynamic performance. In scenarios where rapid changes occur in the system, such as sudden load variations or transients, the PR controller may not be able to respond quickly enough to maintain stable DC bus voltage. This can lead to increased ripple and potentially damage the connected electrical equipment.

In summary, while the existing methods of suppressing the second harmonic voltage ripple in dual-stage single-phase rectifiers, including the use of electrolytic capacitors, L-C filters, active decoupling circuits, and PR controllers, offer potential solutions, they also come with their respective drawbacks. These range from reduced power density and increased complexity to sensitivity to frequency variations and poor dynamic performance. Therefore, there is a need for further research and development to find more efficient and robust solutions to address this crucial issue [13].

To enhance the suppression of the second harmonic in PSFB converters in dual-stage single-phase rectifiers, achieve better dynamic performance, and increase resistance to the deviation of f_ac, a novel second harmonic voltage suppression (SHVS) control is introduced in this paper. The key point of the proposed SHVS control lies in the real-time prediction of the PSFB converter’s desired duty cycle through accurate PSFB converter modeling. Only the DC bus voltage (V_bus), the reference output voltage (V_ref), and the output current (I_o) is required for its operation, which significantly simplifies the implementation process. Furthermore, real-time calculation is available, and the dynamic performance of the converter is enhanced.

The remainder of this paper is structured as follows: Section 2 explains the principle of the second harmonic generation. Section 3 introduces the operation of the PSFB converter in dual-stage single-phase rectifier. Section 4 demonstrates the detailed principle of the proposed second harmonic voltage suppression control and shows the simulation results. Section 5 showcases the experimental results to validate the effectiveness of the proposed SHVS control method. Finally, Section 6 concludes the paper.

2. Mechanism of Second Harmonic Generation in Single-Phase Dual-Stage Converter

The topology of the phase-shifted full-bridge converter in the dual-stage singe-phase rectifier is shown in Figure 1. The converter consists of the primary-side full bridge Q₁–Q₄, the resonant tank, the secondary side rectifier D₁–D₄, and the output filter. The resonant tank is composed of the resonant inductor L_r and the DC blocking capacitor C_b. The transformer ratio is n. The output filter consists of the output inductor L_o and the output capacitor C_o. The AC voltage, input voltage, and output voltage are V_ac, V_bus, and V_o, respectively. The resonant inductor current, the output inductor current, and the output current are i_Lr, i_Lo, and I_o, respectively.

Assuming that the AC side voltage v_ac and the AC side current i_ac are both ideal sine waves, whose expression are

$$\left\{\begin{array}{l}{v}_{\mathrm{ac}}=V_{\mathrm{ac}}\sin ({\omega }_{\mathrm{ac}}t)\\ i_{\mathrm{ac}}=V_{\mathrm{ac}}\sin ({\omega }_{\mathrm{ac}}t)\end{array}\right.$$

(1)

where V_ac and I_ac are the amplitude of the AC side voltage and the AC side current, respectively, and ω_ac is the AC side angular frequency, the instantaneous power on the AC side can be expressed as

$$p_{\mathrm{ac}}=\frac{1}{2}{V}_{\mathrm{ac}}{I}_{\mathrm{ac}}[1+\cos (2{\omega }_{\mathrm{ac}}t)]$$

(2)

Assuming the power transmission efficiency of the inverter is 1, and ignoring the influence of energy storage components such as inductors and capacitors in the inverter, the instantaneous power on the DC side and the AC side should be completely equal. Therefore, the second input power pulse will result as the DC bus voltage ripple. Consequently, there is a second harmonic ripple on the output current I_o exhibited on the output port. If the conduction of the second harmonic current source is not restricted, this excitation will inevitably generate current excitation containing second harmonic components in various branches of the entire circuit. This not only shortens battery life and increases device current stress, but also increases losses. Without adding additional circuits and devices, the most ideal scenario is that the forward transmission path of the second harmonic current source is blocked and it only flows through the DC bus capacitor, without affecting the battery side.

3. Analysis of the PSFB Converter

Before introducing the detailed principle of the PSFB converter, it is essential to first understand the fundamental concept behind suppressing the second harmonic voltage. This fundamental knowledge will pave the way for a clearer comprehension of the subsequent discussion.

As illustrated in Figure 2, the DC bus voltage, denoted as V_bus, is overlaid with a harmonic ripple, v_bus,ripple, oscillating at twice the input frequency, 2f_ac. To maintain the output voltage, V_o, steady at the desired reference voltage, V_ref, it becomes essential to adjust the duty cycle, D, of the PSFB converter dynamically in response to the fluctuations of v_bus,ripple. This adjustment ensures the voltage gain of the converter is regulated to achieve a constant output. For instance, at operation point 1 (OP₁), where the bus voltage stands at V_bus1, the duty cycle must be set to D = D_ff + D_PI to stabilize the output voltage at V_ref, with the fluctuations of duty cycle, ∆D. However, due to the well-known duty-loss phenomenon of the phase-shifted full-bridge converter, the duty-cycle loss D_Loss should be considered.

Based on this foundational concept, the core principle of the proposed SHVS strategy revolves around real-time prediction of the ideal duty cycle D in response to the variations in v_bus,ripple. This prediction is achieved with remarkable speed and across a broad bandwidth, through the employment of a feedforward duty cycle, D_ff. This approach not only enhances the responsiveness of the system but also significantly improves its efficiency in maintaining a constant output voltage against the input voltage fluctuations.

3.1. Principle of Phase-Shifted Full-Bridge Converter

To suppress the DC bus ripple voltage, the aforementioned feedforward duty cycle, D_ff, is introduced, which is the duty cycle predicted through accurate PSFB converter modeling. Since only V_bus, I_o, and V_ref are inputs, D_ff can be calculated online and will vary with the fluctuation of V_bus, so as to help keep V_o constant at V_ref.

The key waveform of the PSFB converter is shown as in Figure 3, where T_s is the switching cycle. Switch tubes Q₃ and Q₄ are connected to the transformer as lagging bridge arms, and switch tubes Q₁ and Q₂ are used as leading bridge arms. The upper and lower switch tubes of the bridge arm are both 180 ° and complementary with the dead zone, and the leading and lagging bridge arms have a phase-shift angle of φ₁ = (1 − D)π difference in conduction. The output voltage is changed by controlling the phase-shift angle, as follows:

$$V_{\mathrm{o}}=\frac{D{V}_{\mathrm{bus}}}{n}=\frac{\pi -{\phi }_1}{n\pi }{V}_{\mathrm{bus}}$$

(3)

However, loss of duty cycle is a common issue with PSFB converters, and may lead to distortion of converter gain. To suppress the implementation of precise SHVS, it is necessary to consider the impact of duty-cycle loss on PSFB-converter voltage gain. To derive the expression of the duty-cycle loss, the operation principle of PSFB converter in a switching cycle is introduced first.

Mode 1 [t₀ ~ t₁]: This mode begins when the hysteresis bridge-arm switch transistor Q₃ is turned off, and the primary current i_Lr simultaneously charges and discharges the junction capacitors of Q₃ and Q₄. After the junction capacitor of Q₃ is charged, the body diode of Q₄ conducts, and the primary voltage v_ab rises to the input voltage. At this time, the primary current i_Lr starts to rise. Due to insufficient primary current i_Lr to support the secondary current at this time, all the body diodes of the secondary switch transistor conduct continuous current, causing the transformer to short-circuit and v_cd to be zero. At this point, the current on the resonant inductor i_Lr is

$$i_{L\mathrm{r}}(t)=\frac{V_{\mathrm{in}}}{L_{\mathrm{r}}}(t-t_0)+i_{\mathrm{p}}(t_0)$$

(4)

and the current on the output inductor i_Lo is

$$i_{L\mathrm{o}}(t)=-\frac{V_{\mathrm{o}}}{L_{\mathrm{r}}}(t-t_0)+i_{L\mathrm{o}}(t_0)$$

(5)

Mode 2 [t₁ ~ t₂]: This mode starts when the primary current i_Lr rises to the same level as the output inductor current i_Lo, at which point the body diodes of Q₆ and Q₇ naturally turn off, and the current only flows through the body diodes of Q₅ and Q₈. At the same time, the output inductance charges the junction capacitors of Q₆ and Q₇, causing a decrease in the secondary current of the transformer. The resonant inductor current i_Lr and the output inductor current i_Lo at this stage are

$$i_{L\mathrm{o}}(t)=\frac{V_{\mathrm{in}}-N{V}_{\mathrm{o}}}{L_{\mathrm{r}}+N^2{L}_{\mathrm{o}}}(t-t_1)+i_{L\mathrm{o}}(t_1)$$

(6)

$$i_{L\mathrm{r}}(t)=\frac{V_{\mathrm{in}}-N{V}_{\mathrm{o}}}{N{L}_{\mathrm{r}}+N^3{L}_{\mathrm{o}}}(t-t_1)+i_{L\mathrm{o}}(t_1)$$

(7)

Mode 3 [t₂ ~ t₃]: This mode starts when Q₁ is turned off, and the resonant inductor simultaneously charges and discharges the junction capacitors of Q₁ and Q₃. When the charging and discharging are completed, the body diode of Q₂ conducts. Meanwhile, due to the gradual decrease in v_ab during the discharge process of Q₃ junction capacitance, the corresponding voltage of v_cd also decreases. Therefore, the junction capacitors of Q₆ and Q₇ need to be discharged, and the resonant inductor current i_Lr continues to decrease. When the junction capacitance voltage of Q₆ and Q₇ resonates to zero, all the body diodes of the secondary side switch are turned on, and the transformer is short-circuited. At this time, the output inductance current i_Lo is

$$i_{L\mathrm{o}}(t)=-\frac{V_{\mathrm{o}}}{L_{\mathrm{r}}}(t-t_2)+i_{L\mathrm{o}}(t_2)$$

(8)

3.2. Derivation of the Ideal Duty Cycle

The phenomenon of duty-cycle loss represents a unique characteristic of phase-shifted full-bridge converters. It describes a situation where the duty cycle on the primary side exceeds that on the secondary side, as shown in Figure 3. Specifically, in Mode 1, when switches Q₁ and Q₄ are activated, the primary current i_Lr must reverse direction, progressively increasing from negative to zero and then to positive. During this transition, neither the primary nor secondary currents are adequate to sustain the output current. To maintain the equilibrium of the transformer’s primary and secondary currents, all secondary switches are engaged, effectively short-circuiting the transformer and reducing the secondary voltage to zero. Consequently, the primary bridge arm’s midpoint voltage v_ab equals the input voltage. During this interval, energy transfer from the input to the secondary side is halted, leading to what is termed duty-cycle loss. The effective duty cycle on the secondary side is thus impacted as

$$D=D_{\mathrm{ideal}}-D_{\mathrm{loss}}$$

(9)

Analyzing the operational principles of the phase-shifted full-bridge converter reveals that duty-cycle loss primarily occurs in Mode 1, where the resonant inductor’s voltage matches the input voltage. The primary current i_Lr at the beginning of the duty-cycle loss is

$$i_{\mathrm{p}}(t_0)=(I_{L\mathrm{o}}+\frac{\Delta I}{2}-\frac{1-D}{2}{T}_{\mathrm{s}}\frac{V_{\mathrm{o}}}{L_{\mathrm{o}}})/N$$

(10)

where ΔI is the peak-to-peak value of the output inductor current. The primary current at the end of the duty-cycle loss is

$$i_{\mathrm{p}}(t_1)=(I_{L\mathrm{o}}-\frac{\Delta I}{2})/N$$

(11)

Therefore, the loss of duty cycle can be expressed as

$$D_{\mathrm{loss}}=\frac{\Delta t_{01}}{\frac{T_{\mathrm{s}}}{2}}=\frac{i_{\mathrm{p}}(t_1)+i_{\mathrm{p}}(t_4)}{\frac{T_{\mathrm{s}}}{2}\frac{V_{\mathrm{in}}}{L_{\mathrm{r}}}}=\frac{1}{N\frac{T_{\mathrm{s}}}{2}\frac{V_{\mathrm{in}}}{L_{\mathrm{r}}}}(2I_{\mathrm{o}}-\frac{V_{\mathrm{o}}}{L_{\mathrm{o}}}(1-D)\frac{T_{\mathrm{s}}}{2})$$

(12)

The duration of duty-cycle loss is influenced by various circuit parameters and operational conditions, including the transformer ratio (N), resonant inductance (L_r), output inductance (L_o), switching period (T_s), output current (I_o), output voltage (V_o), input voltage (V_bus), and primary duty cycle (D).

Through Equations (3), (9), and (12), the output voltage of PSFB converter considering the duty-cycle loss can be derived as

$$V_{\mathrm{o}}=\frac{n{V}_{\mathrm{in}}{D}_{\mathrm{ideal}}-4I_{\mathrm{o}}{L}_{\mathrm{r}}{f}_{\mathrm{s}}}{(D_{\mathrm{ideal}}-1)k+n^2}$$

(13)

where M is the voltage gain and k is the ratio of the resonant inductor and the output inductor, which are, respectively, written as

$$M=\frac{n{V}_{\mathrm{o}}}{V_{\mathrm{in}}}$$

(14)

$$k=\frac{L_{\mathrm{r}}}{L_{\mathrm{o}}}$$

(15)

The ideal duty cycle of the PSFB converter under a certain operation point can be derived as

$$D_{\mathrm{ideal}}=1-\frac{4I_{\mathrm{o}}{L}_{\mathrm{r}}{f}_{\mathrm{s}}/V_{\mathrm{in}}-n(1-M)}{kM/n-n}$$

(16)

4. The Proposed Novel Second Harmonic Suppression Control

The ideal duty cycle of the PSFB converter, considering the duty-cycle loss in Section 3, was calculated. By feedforwarding the predicted ideal duty cycle to the PI loop, a novel SHSV control for the PSFB converter in dual-stage single-phase rectifier is proposed, where the voltage loop bandwidth of the PSFB converter will be greatly improved.

4.1. Detailed Control Scheme

The control block diagram illustrating the novel SHVS control strategy for PSFB converters is depicted in Figure 4, where MCU denotes the micro-control unit. The error between the output voltage V_o and reference voltage V_ref, v_e is compensated through the traditional PI linear controller to obtain the duty cycle D_PI. At the same time, the input voltage, output voltage, and output current are sampled, and the feedforward duty cycle D_ff = D_ideal is calculated through Equation (16) and fed forward to the PI loop. The final duty cycle signal D is obtained by adding D_PI and D_ff and D is transmitted to the pulse width modulation module of the microprocessor.

In essence, the proposed SHVS control strategy enhances the performance of the control of PSFB converters, offering a robust, reliable, and efficient solution that is poised to redefine the standards of power conversion technology. Similar control strategies, such as the well-known phenomenon of phase-shift loss due to the failure of zero-voltage switching, can also be extended to the dual active bridge converter application [18].

4.2. Simulation Results

Figure 5a,b present the critical waveforms of the single-phase rectifier-driven PSFB converter, highlighting the performance under different reference voltage conditions. Specifically, the reference voltage was set at 300 V for Figure 5a and 253 V for Figure 5b. As illustrated in Figure 5, the adoption of SHVS control significantly reduced the output ripple of the PSFB converter. Under the SHVS control, the output ripple was reduced to 1.4 V and 0.4 V, respectively, for the reference voltages of 300 V and 253 V. These values represent a substantial improvement compared with the performance under PR control and PI control.

More precisely, the output ripple under SHVS control was only 56% and 14% of that achieved under PR control, for the 300 V and 253 V reference voltages, respectively. Additionally, it was a mere 4.6% and 1.3% of the output ripple observed under PI control, respectively. This significant reduction in output ripple indicates the effectiveness of the SHVS control strategy in enhancing the performance of the single-phase rectifier-driven PSFB converter.

4.3. Bode Diagram

To validate the feasibility and effectiveness of the proposed VHSV on second harmonic suppression, simulation and experimentation were carried out. The simulation was performed with PLECS, for which the system specifications are listed in

Table 1. Prototype Specifications.

Items	Value
Transformer ratio n	6:5
Inductor Lr	5 μH
Port side capacitor Cdc	14.1 μF
Switching frequency fs	100 kHz
Dead time ddtTs	200 ns
Switches Q1–Q4	UF3C065040K4S, 52 mΩ@ ID = 40 A, TJ = 25 °C
Diode D1–D4	UF3C065040K4S (without synchronous rectification, reverse diode only), 1.5 V@ IF = 20 A, TJ = 25 °C
MCU	SPC58NN84E7

.

The PI coefficients were optimized through the PID tuner in MATLAB 2021. To validate the superiority of the proposed SHVS algorithm, the PI coefficients in the SHVS control were one-tenths that in the PI-only control.

Figure 6 shows the Bode diagram of closed-loop transfer functions of the PSFB converter voltage loop obtained under different controllers. It can be seen that the proposed SHVS control improved the bandwidth of the voltage loop to 5.4 kHz which indicates good ripple suppression effect, fast dynamic performance, and immunity from fin deviation, while the bandwidth of that under the PI control was only 200 Hz. For the PR controller, the gain was high only for the voltage loop around 100 Hz. The transfer function of the phase-shifted full-bridge converter with different controller is written as follows:

$${\mathrm{TF}}_{\mathrm{PI}}=\frac{0.002066s^4-1259s^3+1.625\times {10}^8{s}^2+3.653\times {10}^{12}s+1.11\times {10}^{16}}{s^4+3.045\times {10}^4{s}^3+9.603\times {10}^8{s}^2+1.158\times {10}^{12}s+1.088\times {10}^{16}}$$

(17)

$${\mathrm{TF}}_{\mathrm{PR}}=\frac{0.0031 s^6-157 s^5+1.87\times {10}^8{s}^4+1.41\times {10}^{12}{s}^3+1.1\times {10}^{15}{s}^2+4.33\times {10}^{17}s+2.62\times {10}^{20}}{s^6+1.63\times {10}^4{s}^5+7.66\times {10}^8{s}^4+1.9\times {10}^{12}{s}^3+1.3\times {10}^{15}{s}^2+6.22\times {10}^{17}s+2.5\times {10}^{20}}$$

(18)

$${\mathrm{TF}}_{\mathrm{SHVS}}=\frac{0.009442s^5-4003s^4+5.973\times {10}^8{s}^3+1.443\times {10}^{12}{s}^2+1.967\times {10}^{14}s+5.741\times {10}^{16}}{s^5+1.615\times {10}^4{s}^4+6.323\times {10}^8{s}^3-2.09\times {10}^9{s}^2+2.197\times {10}^{14}s+5.155\times {10}^{16}}$$

(19)

5. Experiments

The prototype and experimental setup are shown in Figure 7. The detailed specifications of the prototype are shown in Table 1.

5.1. Steady-State Performance

Figure 8 showcases the key waveforms of the PSFB converter under steady-state conditions. It shows that the output voltage experienced fluctuations of 3.5 V with the proposed SHVS control, which were 25% of the ripple observed when utilizing PI control, showcasing a significant reduction in ripple. It is crucial to note that the integral and proportional coefficients utilized in the PI controller were ten times higher than those used in the SHVS controller. Adopting identical PI coefficients for the SHVS controller could further enhance its ability to suppress ripple, highlighting the potential for improved performance.

Table 2. Comparison between the performance of different controls.

Items	Input Ripple	Output Ripple
PI control (in simulation)	27 V	30.5 V
PR control (in simulation)	27 V	2.5 V
SHVS control (in simulation)	27 V	1.4 V
PI control (in experiment)	20 V	14 V
SHVS control (in experiment)	20 V	3.5 V

summarizes the comparison of the performance of phase-shifted full-bridge converter with different controls. It was found that the proposed SHVS control could significantly suppress the second harmonic ripple in both simulation and experiment. In contrast the suppression ability of the PI control was relatively poor. In the simulation environment, PI control exhibited an input ripple of 27 V, resulting in an output ripple of 30.5 V. This suggests a relatively high output ripple compared with the input. PR control showed an input ripple of 27 V, but significantly reduced the output ripple to 2.5 V. This indicates PR control was more effective in suppressing output ripple in the simulation. SHVS control also demonstrated a 27 V input ripple but achieved an even lower output ripple of 1.4 V. Among the simulated methods, SHVS control appeared to be the most effective in minimizing the output ripple. In the experimental environment, PI control with a 20 V input ripple resulted in a higher output ripple of 14 V. SHVS control, with the same 20 V input ripple, managed to keep the output ripple lower, at 3.5 V. However, this was still higher than its simulated performance. In summary, the experimental results indicate that the performance of the control methods was generally less effective than the simulation results. Among the tested methods, SHVS control showed the best ability to suppress output ripple, though its performance was still inferior to the simulation. PR control was also effective in the simulation but is not included in the experimental data. Further optimization and analysis may be needed to improve the control methods’ performance in the experimental setting.

5.2. Dynamic Performance

As further evidence of the effectiveness of the proposed SHVS (second harmonic voltage suppression) control strategy, Figure 9 clearly demonstrates its exceptional performance during dynamic conditions. Specifically, during a reference voltage transient, the SHVS control exhibited a nearly instantaneous completion of the dynamic process, with no detectable voltage overshoot. This rapid and smooth transition from one steady-state condition to another highlights the control’s ability to quickly and precisely respond to changes in the reference voltage.

This rapid dynamic response is crucial for maintaining the stability and efficiency of the power converter system. By minimizing voltage overshoot and ensuring a smooth transition, the SHVS control not only improved the overall performance of the converter but also helps protect sensitive electronic components from potential damage caused by voltage fluctuations.

5.3. Effciency

As illustrated in Figure 10, the implementation of the proposed SHVS control technique resulted in a modest, yet noteworthy, improvement in the efficiency of the PSFB converter, with an approximate increase of 0.2%. This enhancement in efficiency can be attributed to the suppression of the second harmonic voltage, which in turn reduced the RMS current on both the primary and secondary sides of the converter. The reduction in RMS current directly contributed to a decrease in the conduction losses associated with the converter, thereby improving its overall operational efficiency.

6. Conclusions

In this paper, an innovative second harmonic voltage suppression control is introduced for phase-shifted full-bridge converters within dual-stage single-phase rectifiers, designed to mitigate the second harmonic ripple in the output voltage. This control strategy leverages an online prediction of the desired duty cycle, where only the DC bus voltage, output current, and the reference voltage are required. Furthermore, the proposed control enjoyed its rapid dynamic response and robustness against variations in grid frequency. The bandwidth of the closed-loop transfer functions within the proposed control scheme was extended to 5.4 kHz. The experimental outcomes derived from this prototype underscore the feasibility of the proposed control scheme. Notably, it demonstrated a remarkable capability for ripple suppression. An unexpected, yet welcome, discovery was the enhancement in the efficiency of the prototype by 0.5%, attributable to the exceptional ripple suppression effect engendered by the proposed control scheme. This improvement not only validates the effectiveness of proposed approach but also highlights its potential for practical applications in enhancing the performance and efficiency of dual-stage single-phase rectifiers.