An Optimized Switching Strategy Based on Gate Drivers with Variable Voltage to Improve the Switching Performance of SiC MOSFET Modules

Abstract

This paper proposes an optimized switching strategy (OSS) based on a silicon carbide (SiC) MOSFET gate driver with variable voltage, which allows simultaneous variations in several different parameters to optimize the switching performance of semiconductor devices. As a relatively new device, the SiC MOSFET shines in the field of high power density and high-frequency switching; it has become a popular solution for electric vehicles and renewable energy conversion systems. However, the increase in voltage and current slope caused by high switching speeds inevitably increases the overshoot and oscillation in a circuit and can even generate additional losses. The principle of this new control strategy is to change the voltage and current in the turn-on and turn-off stages by changing the gate driver’s voltage. That is, we reduced the drive’s voltage after a certain time delay and maintained it for a period of time, thus directly controlling the slopes of di/dt and dv/dt. This study focused on the optimization of the SiC MOSFET by changing the time delay preceding the decrease in the voltage of the gate driver, analyzing and calculating the optimal time delay before the decrease in the voltage of the gate driver, and verifying the findings using LTspice simulation software. The simulated results were compared and analyzed with hard-switching strategies. The results showed that the proposed OSS can improve the switching performance of SiC MOSFETs.

1. Introduction

Silicon carbide (SiC) MOSFETs offer a range of advantages over silicon-based switches, including faster switching, higher efficiency, higher operating voltages, and higher temperatures, enabling smaller and lighter designs [1,2]. Thus, significant progress has been made in the power semiconductor industry. These advantages allow SiC MOSFETs to be applied in a range of automotive and industrial applications. However, the excessively fast switching speed of SiC MOSFETs causes high values of di/dt and dv/dt [3]. At the same time, due to the existence of parasitic inductance and parasitic resistance in circuits, SiC MOSFETs are prone to overshoots and oscillations in current and voltage during switching, thus generating additional switching losses. These losses can even cause device damage. Therefore, reducing or even eliminating the overshoot, oscillation, and electromagnetic interference (EMI) of silicon carbide MOSFETs during switching is a priority in improving their working efficiency [4].

Current and voltage overshoots are the biggest obstacles in SiC semiconductor applications. Stray inductance and parasitic capacitance are the main contributors to current and voltage overshoots [5,6]. When a SiC MOSFET works at a high frequency, the switching speed becomes too fast and the di/dt and dv/dt slopes increase. Thus, current and voltage overshoots are amplified due to stray inductance and parasitic capacitance [7]. When the voltage and current overshoots exceed the breakdown voltage of the SiC MOSFET and the maximum recovery current of the freewheeling diode, the SiC is destroyed. However, the parasitic elements in the actual circuit cannot be eliminated [8,9,10,11]; so, the overshoot can only be eliminated by other means.

Solving the problems of overshoots and oscillations is key to improving the efficiency of SiC MOSFETs.

In the traditional approach, slowing the switching speed in the case of high gate resistance [12] can alleviate the SiC MOSFET’s overshoots and oscillations. However, this solution means the power losses become greater with longer switching times [6]. Adding an RC snubber circuit is also a common method [13,14] to eliminate overshoot and oscillation problems. Although highly efficient snubber circuits have been proposed, snubber circuits affect the overall efficiency of the system. In particular, extra devices increase the power loss of the overall circuit. Active gate driver (AGD) solutions have been developed to increase the efficiency of power devices. The main advantages of these gate drivers are reduced oscillations and overshoots. However, the extra components not only increase the volume of the SiC system but also increase the circuit’s power loss [15,16,17,18,19,20,21]. In [21], a new active gate driver was proposed that could effectively suppress overshoots and oscillation and reduce losses without compromising EMI. The main strategy of the proposed AGD was to reduce the current and voltage slope by reducing the gate driver’s voltage. However, its main disadvantages were that the process of calculating the parameters of the transformer was complicated, an additional printed circuit board was required, and the implementation of the circuit was complicated and expensive. As such, configurable digital gate drivers (DGDs) are the latest technological development in this sphere [22]. The strengths of DGDs are their programmability, support for a wide variety of power devices, and ease of use [23]. A key element of this technology is the ability to configure the turn-on and turn-off processes, which provides a series of steps to control the voltage level at specific times [24,25,26,27,28]. This allows designers to digitally configure the turn-on and turn-off curve through software without requiring changes to the hardware.

In this paper, an optimized switching strategy based on gate drivers with variable voltage (OSS) was proposed to improve the switching performance of SiC MOSFETs. This switching strategy was based on and optimized for an AGD in [21] and a DGD in [22]. There is no doubt that the AGD performed well in [21]. However, the gate driver circuits were too complex and too large. The ease of operation of the DGD in [22] is very attractive. Therefore, this article aimed to combine the advantages of the voltage gate drivers of AGDs and DGDs in waveforms to further optimize the algorithm and control and reduce overshoots and oscillations in SiC MOSFETs through an OSS. Finally, we used the LTspice simulation software to verify the feasibility of our switching strategy. Compared with AGDs and DGDs, an OSS can control more variables to achieve more precise and optimal circuit control. Due to space limitations, this article focused on the impact of delay time on switching performance and lists the formula to calculate the delay time for a given calculated decrease in voltage. At the same time, the decrease in the voltage and the time of this decrease were also considered. The development potential of the OSS is significant. Compared with other switching strategies, which can only change one or two variables, the OSS can control three variables simultaneously, namely, the delay time before a decrease in voltage, the decrease in voltage itself, and the time duration of the decrease in voltage. More variables mean better control performance. However, due to various limitations, this paper only considered the influence of the delay time before a decrease in voltage on switch performance and analyzed the relationship between voltage drop and switch performance. In our next work, we will produce more simulations and experimental results to prove the advanced nature of the OSS.

This paper is organized as follows. Section 2 and Section 3 present the control principle, circuit model, and related formulations of the proposed switching strategy. In Section 4, the simulation setup and simulation results are introduced and analyzed. Finally, in Section 5, the conclusions and a discussion of this simulation are given.

2. Operation Principle of the OSS

The working principle of the OSS is to improve the switching performance of the SiC MOSFET by controlling the voltage drop delay time, voltage drop, and voltage drop time. Compared with traditional AGDs and DGDs, the advantage of an OSS is that it has more control parameters, which means that the semiconductors can be optimally controlled. In this section, the general schematic circuit and working principle of the proposed OSS will be introduced in detail. Figure 1 shows a circuit schematic of the SiC MOSFET and Figure 2 shows a timing chart of the SiC MOSFET with an optimized switching strategy.

2.1. Operation Modes

As shown in Figure 1, the OSS circuit was mainly composed of three parts: the gate drive circuit, silicon carbide MOSFET, and DC bus power supply. The model of the SiC MOSFET, including junction capacitances (C_gd, C_gs, C_ds) and module intrinsic parasitic inductances (Ls, Lg, Ld), is also depicted in Figure 1.

In [21], the gate drive voltage used by the AGD was 20 V/−5 V; also, 15 V and 0 V were used as dropped voltages to optimize the switching performance of the SiC MOSFET. Because it used a switching bridge, it could generate four gate drive voltages (i.e., 20 V, 15 V, 0, and −5 V) from two drive power supplies (20 V and 5 V) through different combinations. In this design, the gate drive voltage waveform design of the AGD was still used. The purpose was to control variables and only explore the influence of the voltage drop delay time (t_d) on the performance of SiC MOSFETs.

2.2. Operation Principle

Figure 2 shows the timing chart of the SiC MOSFET with an optimized switching strategy. The whole process could be split into two steps: turn on and turn off. The blue interval represents the gate driver voltage in the stage of the voltage drop delay time.

2.2.1. Turn-On Stage

When the pulse width modulation (PWM) signal changed from low to high at t₀, a high value gate drive voltage V_GG of 20 V was applied to the SiC MOSFET. Then, a high gate current was generated to charge the input capacitance C_iss = C_gs + C_gd with R_g, which meant the V_GS started to increase. When the V_GS reached the threshold voltage V_TH at t₁, the I_D began to conduct. After a time delay t_d1, the lower V_GG was activated and a lower gate current was generated because the V_GG was reduced to 15 V.

In this interval, I_D continued to rise and a current peak value I_OS appeared due to the freewheeling diode effect. The V_GS reached the Miller plateau voltage and stopped rising. At the same time, the V_DS started to drop. After the voltage fall time t_vd1, the V_GS came out of the Miller plateau and continued to rise. Finally, the SiC MOSFET was fully turned on at t₄. From [21], the current slope of I_D and the voltage slope of the V_DS during the turn-on stage could be expressed as:

$$\frac{{\mathrm{dI}}_{\mathrm{D}}}{\mathrm{dt}}=\frac{{\mathrm{V}}_{\mathrm{GG}}-{\mathrm{V}}_{\mathrm{TH}}-{\mathrm{I}}_{\mathrm{D}}/{\mathrm{g}}_{\mathrm{m}}}{({\mathrm{C}}_{\mathrm{iss}}·{\mathrm{R}}_{\mathrm{on}})/{\mathrm{g}}_{\mathrm{m}}+{\mathrm{L}}_{\mathrm{s}}}$$

(1)

$$\frac{{\mathrm{dV}}_{\mathrm{DS}}}{\mathrm{dt}}=-\frac{{\mathrm{V}}_{\mathrm{GG}}-{\mathrm{V}}_{\mathrm{Miller}}}{{\mathrm{C}}_{\mathrm{GD}}·{\mathrm{R}}_{\mathrm{on}}}$$

(2)

where g_m is the transconductance of the SiC MOSFET and C_gd is the gate-drain capacitance of the SiC MOSFET.

2.2.2. Turn-Off Stage

When the signal from the voltage source changed from high to low at t₅, a negative voltage (i.e., −5 V) was generated to discharge the C_iss with R_g. The V_GS started to drop from 20 V until it reached the Miller voltage at t₆. The V_DS rose rapidly and caused a voltage overshoot V_OS due to stray inductance. After a delay time t_d2, the V_GG increased to 0 V and remained there until I_D was fully turned off at t₈. After t₈, the gate voltage stabilized at −5 V to ensure that the SiC MOSFET was always in the off state. The voltage slope could be calculated as:

$$\frac{{\mathrm{dI}}_{\mathrm{D}}}{\mathrm{dt}}={\mathrm{g}}_{\mathrm{m}}·\frac{{\mathrm{V}}_{\mathrm{TH}}+\left({\mathrm{I}}_{\mathrm{D}}/{\mathrm{g}}_{\mathrm{m}}\right)-{\mathrm{V}}_{\mathrm{GG}}}{\left({\mathrm{C}}_{\mathrm{iss}}·{\mathrm{R}}_{\mathrm{off}}\right)/{\mathrm{g}}_{\mathrm{m}}+{\mathrm{L}}_{\mathrm{s}}}$$

(3)

$$\frac{{\mathrm{dV}}_{\mathrm{DS}}}{\mathrm{dt}}=\frac{{\mathrm{V}}_{\mathrm{GG}}-{\mathrm{V}}_{\mathrm{Miller}}}{{\mathrm{C}}_{\mathrm{GD}}·{\mathrm{R}}_{\mathrm{off}}}$$

(4)

According to (1)–(4), changing the instantaneous slope of current and voltage could be achieved by changing the V_GG. In the turn-on stage, the change was reducing the gate diver voltage while in the turn-off stage, the change was increasing the gate diver voltage.

3. Calculation for Voltage Drop Delay Time

An OSS can change the switching performance through unlimited control of the voltage drop delay time, voltage drop, and voltage drop time, aiming to obtain the best data for the switching performance through countless permutations and combinations. However, this is difficult to carry out. In fact, the best data can be derived by equation. The main research direction of this paper was to explore the influence of the voltage drop delay time on the switching performance and to explore the influence of different voltage drops and different voltage drop times on the switching performance. Thus, the content of this chapter focuses on deriving the best voltage drop delay time by equation.

3.1. Equivalent Slope for Current and Voltage

The slope of the current and voltage is an important factor affecting the overshoot and oscillation during the switching process of the SiC MOSFET. It can be seen from Figure 2 that the I_OS in the turn-on stage and the V_OS in the turn-off stage were obvious and large. However, the slope of the voltage and current in the SiC MOSFET with the OSS method was not constant because of the variable gate drive voltage; so, the equivalent slope was proposed and applied in the calculation, with the aim of writing the voltage drop delay times, t_d1 and t_d2, into the equation.

In Figure 3, when the V_GG was 20 V, the slope of the current was dI_D/dt₁; when the V_GG was 15 V, the slope of the current was dI_D/dt₂. Similarly, dV_DC /dt₁ and dV_DC /dt₂ represented the value of the voltage slope under the V_GG of −5 and 0 V. In addition, ton represented the increase in the current I_D and toff represented the increase in the voltage V_DS; t_on1 and t_off1 were the rising times under dI_D/dt₁ and dV_DC/dt₁, respectively. Moreover, dI_D/dt represented the actual current slope with OSS and dV_DC/dt was the current slope with OSS, in actuality. Additionally, dI_D/dt_eq was the equivalent slope at the turn-on stage and dV_DC/dt_eq represented the equivalent slope at the turn-off stage; t_on2 and t_off2 were the actual running times for the turn-on stage and turn-off stage. In [21], the slope of the current was used in both the turn-on and turn-off stages because it was convenient for the subsequent calculations. In this paper, in order to fit reality, the voltage slope was used in the turn-off stage. According to the equivalent principle shown in Figure 3, the following equation could be obtained:

$${\mathrm{I}}_{\mathrm{L}}=\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_1\right|·{\mathrm{t}}_{\mathrm{on}}+\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_1\right|·({\mathrm{t}}_{\mathrm{d}1}-{\mathrm{t}}_{\mathrm{on}})+\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_2\right|·\left({\mathrm{t}}_{\mathrm{on}2}-{\mathrm{t}}_{\mathrm{d}1}\right)=\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_{\mathrm{eq}}\right|·{\mathrm{t}}_{\mathrm{on}2}$$

(5)

and the equivalent rising time t_on2 of the current can be expressed as:

$${\mathrm{t}}_{\mathrm{on}2}=\left({\mathrm{I}}_{\mathrm{L}}-\left(\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_1\right|-\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_2\right|\right)·{\mathrm{t}}_{\mathrm{d}1}\right)/\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_2\right|$$

(6)

Thus, according to (5) and (6), the value of the equivalent current slope at the turn-on stage can be expressed as:

$$\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_{\mathrm{eq}}\right|={\mathrm{I}}_{\mathrm{L}}·\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_2\right|/\left({\mathrm{I}}_{\mathrm{L}}-\left(\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_1\right|-\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_2\right|\right)·{\mathrm{t}}_{\mathrm{d}1}\right)$$

(7)

Similarly, at the turn-off stage, the equations of t_off2 and voltage slope are:

$${\mathrm{V}}_{\mathrm{DC}}=\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_1\right|·{\mathrm{t}}_{\mathrm{off}}+\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_1\right|·({\mathrm{t}}_{\mathrm{d}2}-{\mathrm{t}}_{\mathrm{off}})+\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_2\right|·\left({\mathrm{t}}_{\mathrm{off}2}-{\mathrm{t}}_{\mathrm{d}2}\right)=\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_{\mathrm{eq}}\right|·{\mathrm{t}}_{\mathrm{off}2}$$

(8)

$${\mathrm{t}}_{\mathrm{off}2}=\left({\mathrm{V}}_{\mathrm{DC}}-\left(\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_1\right|-\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_2\right|\right)·{\mathrm{t}}_{\mathrm{d}2}\right)/\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_2\right|$$

(9)

$$\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_{\mathrm{eq}}\right|={\mathrm{V}}_{\mathrm{DC}}·\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_2\right|/{\mathrm{V}}_{\mathrm{DC}}-\left(\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_1\right|-\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_2\right|\right)·{\mathrm{t}}_{\mathrm{d}2}$$

(10)

3.2. Power Losses in the Turn-On and Turn-Off Stages

The turn-on and turn-off losses of the power device could be calculated by (11) and (12), which were derived in []:

$${\mathrm{E}}_{\mathrm{ON}}={\mathrm{E}}_{\mathrm{on},{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}}+{\mathrm{E}}_{\mathrm{on},{\mathrm{dV}}_{\mathrm{DS}}/\mathrm{dt}}+{\mathrm{E}}_{\mathrm{Irr}}+{\mathrm{E}}_{\mathrm{Ls}}$$

(11)

$${\mathrm{E}}_{\mathrm{OFF}}={\mathrm{E}}_{\mathrm{off},{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}}+{\mathrm{E}}_{\mathrm{off},{\mathrm{dV}}_{\mathrm{DS}}/\mathrm{dt}}+{\mathrm{E}}_{\mathrm{Ls}}$$

(12)

where ${\mathrm{E}}_{\mathrm{Ls}}$ is the energy generated by the current passing through ${\mathrm{L}}_{\mathrm{S}}$ and E_Irr is the energy loss of the device generated by the reverse recovery effect, which can be calculated by (14) [29]:

$${\mathrm{E}}_{\mathrm{Ls}}=\frac{1}{2}·{\mathrm{L}}_{\mathrm{S}}·{\mathrm{I}}_{\mathrm{loop}}{}^2$$

(13)

$${\mathrm{E}}_{\mathrm{Irr}}=\left({\mathrm{I}}_{\mathrm{L}}·\sqrt{{\mathrm{Q}}_{\mathrm{rr}}/\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}+{\mathrm{Q}}_{\mathrm{rr}}\right)·{\mathrm{V}}_{\mathrm{DC}}·\left(1-\mathsf{\sigma }\right)$$

(14)

where L_loop is the stray inductance in the power loop, Q_rr is the reverse recovery charge, and $\mathsf{\sigma }$ is the overshoot ratio, which can be defined as:

$$\mathsf{\sigma }=\frac{{\mathrm{V}}_{\mathrm{OS}}}{{\mathrm{V}}_{\mathrm{DC}}}=\frac{{\mathrm{L}}_{\mathrm{loop}}·\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}{{\mathrm{V}}_{\mathrm{DC}}}$$

(15)

During the turn-on transient processes, the energy losses during the current and voltage changes can be expressed as:

$${\mathrm{E}}_{\mathrm{on},{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}}=\frac{1}{2}·{\mathrm{I}}_{\mathrm{L}}·\left({\mathrm{V}}_{\mathrm{DC}}-{\mathrm{L}}_{\mathrm{loop}}·\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|\right)·\frac{{\mathrm{I}}_{\mathrm{L}}}{\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}$$

(16)

$${\mathrm{E}}_{\mathrm{on},{\mathrm{dV}}_{\mathrm{DS}}/\mathrm{dt}}=\frac{1}{2}·{\mathrm{I}}_{\mathrm{L}}·{\mathrm{V}}_{\mathrm{DC}}·\frac{{\mathrm{V}}_{\mathrm{DC}}}{\left|{\mathrm{dV}}_{\mathrm{DS}}/\mathrm{dt}\right|}·{\left(1-\mathsf{\sigma }\right)}^2$$

(17)

Therefore, according to Formulas (11) and (13)–(17), the energy loss during the turn-on stage can be expressed as:

$${\mathrm{E}}_{\mathrm{ON}}=\frac{{\mathrm{V}}_{\mathrm{DC}}·{\mathrm{I}}_{\mathrm{L}}{}^2}{2}·\left(\frac{1+{\left(1-\mathsf{\sigma }\right)}^2}{\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}\right)+\left({\mathrm{I}}_{\mathrm{L}}·\sqrt{\frac{{\mathrm{Q}}_{\mathrm{rr}}}{\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}}+{\mathrm{Q}}_{\mathrm{rr}}\right)·{\mathrm{V}}_{\mathrm{DC}}·\left(1-\mathsf{\sigma }\right)-\frac{1}{2}·{\mathrm{L}}_{\mathrm{S}}·{\mathrm{I}}_{\mathrm{loop}}{}^2$$

(18)

Similarly, according to (12), the energy loss can be expressed as:

$${\mathrm{E}}_{\mathrm{OFF}}=\frac{{\mathrm{I}}_{\mathrm{L}}·{\mathrm{V}}_{\mathrm{DC}}{}^2}{2}·\frac{1+{\left(1+\mathsf{\sigma }\right)}^2}{\left|{\mathrm{dV}}_{\mathrm{DS}}/\mathrm{dt}\right|}+\frac{1}{2}·{\mathrm{L}}_{\mathrm{S}}·{\mathrm{I}}_{\mathrm{loop}}{}^2$$

(19)

3.3. Calculation of the Voltage Drop Delay Time

In order to simplify the calculation model, it was assumed that the change of power consumption was only related to overshoot and was positively correlated. Therefore, during the turn-on stage of the SiC MOSFET, the change in power consumption is positively correlated with the change in current overshoot [21]. Similarly, in the turn-off phase, the change of power consumption is positively correlated with the change of voltage overshoot. The formula can be expressed as:

$$\frac{\left|{\mathrm{E}}_{\mathrm{ON}}\left({\mathrm{t}}_{\mathrm{d}1}\right)-{\mathrm{E}}_{\mathrm{ON}}\left(0\right)\right|}{\left|{\mathrm{E}}_{\mathrm{ON}}\left({\mathrm{t}}_{\mathrm{on}2}\right)-{\mathrm{E}}_{\mathrm{ON}}\left(0\right)\right|}=\frac{\left|{\mathrm{I}}_{\mathrm{OS}}\left({\mathrm{t}}_{\mathrm{d}1}\right)-{\mathrm{I}}_{\mathrm{OS}}\left(0\right)\right|}{\left|{\mathrm{I}}_{\mathrm{OS}}\left({\mathrm{t}}_{\mathrm{on}2}\right)-{\mathrm{I}}_{\mathrm{OS}}\left(0\right)\right|}$$

(20)

$$\frac{\left|{\mathrm{E}}_{\mathrm{OFF}}\left({\mathrm{t}}_{\mathrm{d}2}\right)-{\mathrm{E}}_{\mathrm{OFF}}\left(0\right)\right|}{\left|{\mathrm{E}}_{\mathrm{OFF}}\left({\mathrm{t}}_{\mathrm{off}2}\right)-{\mathrm{E}}_{\mathrm{OFF}}\left(0\right)\right|}=\frac{\left|{\mathrm{V}}_{\mathrm{OS}}\left({\mathrm{t}}_{\mathrm{d}2}\right)-{\mathrm{V}}_{\mathrm{OS}}\left(0\right)\right|}{\left|{\mathrm{V}}_{\mathrm{OS}}\left({\mathrm{t}}_{\mathrm{off}2}\right)-{\mathrm{V}}_{\mathrm{OS}}\left(0\right)\right|}$$

(21)

In the turn-on phase, the most important factor affecting power consumption is the overshoot of the current; so, Equation (21) can be abbreviated as:

$${\mathrm{E}}_{\mathrm{ON}}=\frac{{\mathrm{I}}_{\mathrm{L}}{}^2·{\mathrm{V}}_{\mathrm{DC}}}{2}·\frac{1-\mathsf{\sigma }}{\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}$$

(22)

Because the main cause of current overshoot is the reverse recovery effect [21], the current overshoot can be expressed as:

$${\mathrm{I}}_{\mathrm{OS}}={\mathrm{I}}_{\mathrm{rr}}=\sqrt{{\mathrm{Q}}_{\mathrm{rr}}·\left|{\mathrm{dI}}_{\mathrm{D}}/\mathrm{dt}\right|}$$

(23)

According to (25) and (26), (11) can be expressed as:

$$\frac{\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_{\mathrm{eq}}\right|}{\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_1\right|}=\frac{\sqrt{{\mathrm{Q}}_{\mathrm{rr}}·\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_1\right|}}{\sqrt{{\mathrm{Q}}_{\mathrm{rr}}·\left|{\mathrm{dI}}_{\mathrm{D}}/{\mathrm{dt}}_{\mathrm{eq}}\right|}}$$

(24)

Similarly, in the turn-off stage, the formula can be obtained:

$${\mathrm{E}}_{\mathrm{OFF}}=\frac{{\mathrm{V}}_{\mathrm{DC}}{}^2·{\mathrm{I}}_{\mathrm{L}}}{2}·\frac{1+\mathsf{\sigma }}{\left|{\mathrm{dV}}_{\mathrm{DS}}/\mathrm{dt}\right|}$$

(25)

$$\frac{\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_{\mathrm{eq}}\right|}{\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_1\right|}=\frac{{\mathrm{L}}_{\mathrm{loop}}·\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_1\right|}{{\mathrm{L}}_{\mathrm{loop}}·\left|{\mathrm{dV}}_{\mathrm{DS}}/{\mathrm{dt}}_{\mathrm{eq}}\right|}$$

(26)

According to (1)–(4), (7), and (24), an equation expressed by t_d1 could be obtained. Similarly, according to (1)–(4), (10), and (26), an equation expressed by t_d2 could be obtained. Therefore, the optimal voltage drop delay times, t_d1 and t_d2, could be calculated.

4. Simulation Verification

In order to evaluate the performance of the proposed OSS, a double-pulse simulation test of the SiC MOSFET was performed using the software LTspice. The power device used in the test was CREE’s 1.2 KV/115 A SiC MOSFET module (C3M0016120D). In the simulation, the tested module was first modeled in LTspice to ensure that the simulation results would be closer to the experimental data and then the circuit was built and simulated. The detailed parameters of the tested modules in the experiment are shown in

Table 1. Parameters of the SiC MOSFET C3M0016120D (TCJ = 25 °C).

Symbol	Parameter	Value	Unit
VDS	Drain—Source Voltage	1200	V
VGS	Gate—Source Voltage	−8/+19
VTH	Gate Threshold Voltage	2.5
Ciss	Input Capacitance	6085	pF
Coss	Output Capacitance	230
Crss	Reverse Transfer Capacitance	13
tr	Rise Time	28	ns
tf	Fall Time	27	ns
RDS(on)	Drain-Source On-State Resistance	16	mΩ
RG(int)	Internal Gate Resistance	2.6	Ω
ID	Continuous Drain Current	115	A
Qrr	Reverse Recovery Charge	604	nC
gm	Transconductance	53	S

.

The comparison of the OSS’s performance under different time delays was simulated to verify whether the calculated time delay was the best. To further compare the performance of the OSS, it was compared with hard switching (HS) and a digital gate driver (DGD) from Agileswitch.

4.1. SiC MOSFET Device

In order to facilitate future experiments based on this simulation, this simulation used the existing silicon carbide semiconductor module in the laboratory as the test equipment. The detailed parameters of the tested modules in the experiment are shown in Table 1. Figure 4 shows the device.

4.2. Simulation Modeling

To improve the simulation, we chose LTspice as the simulation software. As shown in Figure 5, and according to Figure 1, a simulation circuit was built. The main purpose of this simulation was to verify the effect on the switching performance of the OSS and compare it with other switching strategies. It was firstly particularly important to verify whether it was necessary to study the OSS in depth. A simulation can obtain more accurate results and save time. Once the excellent switching performance of the OSS was confirmed, the next step was to build and experiment with actual circuits. According to (24), (26), and data from Table 1, we calculated an optimized delay time t_d1 of 21 ns and t_d2 of 41 ns; t_vd1 and t_vd2 used the rise time (t_r) and fall time (t_f) in the device data sheet for the simulation, respectively.

Table 2. Parameters of the SiC MOSFET and associated circuit in LTspice.

Parameters	Value
C1, C4	227 pF
C2, C5	13 pF
C3, C6	6072 pF
C7	100 µF
LD	100 nH
LG	20 nH
LS	1 nH
Lload	60 µH
RDS(on)	1 Ω
RG	2.6 Ω
VBUS	500 V
VTC	25 V

shows the parameters of some components in the analog circuit. Among them, C₁ and C₄ represent C_ds, C₂ and C₅ represent C_dg, and C₃ and C₆ represent C_gs. In order for the oscillation in the simulation results to be closer to the actual situation, L_S, L_D, and L_G were adjusted.

Because the double-pulse simulation of the SiC MOSFET was carried out using the software LTspice, it was necessary to simulate the double-pulse signal, as shown in Figure 6. Because of the convenience of the simulation software, the voltage waveform from the voltage source could be edited directly. When the SiC MOSFET was simulated with the OSS, the waveform could also be adjusted directly at the voltage source, which required corresponding devices in the actual experiments.

4.3. Simulation Results

In order to verify the feasibility of the proposed OSS, the simulation was run with the gate resistance 2.6 Ω, both at the turn-on stage and turn-off stages; the dc bus voltage was 500 V and the drain current was 30 A. The voltage drop delay times t_d1 of 21 ns and t_d2 of 41 ns were calculated by Equations (11) and (12). Meanwhile, as visible from Table 1, the t_vd1 was 28 ns and the t_vd2 was 27 ns.

It can be seen in Figure 7a that when the turn-on signal arrived, first, a high V_GG (i.e., 20 V) was applied to the gate terminal. After the delay time t_d1, which was calculated to be 21 ns, the I_DS started to rise and the V_GG dropped to 15 V. After the delay time t_vd1 (i.e., 28 ns), the high V_GG restarted to charge the SiC MOSFET. At the turn-off stage, the SiC MOSFET was first discharged by −5 V. After the delay time t_d2, which was calculated to be 41 ns, the V_DS started to rise from 0 V and the V_GG became 0 V. After the delay time t_vd2 (i.e., 27 ns), the V_DS reached the peak value and the negative V_GG was discharged again.

As mentioned in Section 2, the voltage drop delay times, t_d1 and t_d2, are very important because they can affect the switching performance of the SiC MOSFET. In order to verify the relationship between the delay time and the performance of the switch, and to further the accuracy of the calculation results in the previous chapter, more experiments were carried out. As shown in Figure 8, around the calculation result (i.e., t_d1 = 21 ns t_d2 = 41 ns) at an interval of 10 ns, a total of four other data points were taken before and after each transition and were simulated. Then, the simulation results were compared.

For the turn-on transition, because the calculation result of t_d1 was 21 ns, the five testing data points were 11 ns, 21 ns, 31 ns, 41 ns, and 51 ns, respectively. The reason t_d1 was not set to 0 was that this waveform was equal to the switching strategy of the digital gate driver. It can be seen from Figure 8a that there was no obvious difference and the V_DS and I_DS waveforms generated by the five different t_d1 were not notably different. When t_d1 was 11 ns, the overshoot of the I_DS was the smallest but the overshoot produced by the V_DS was the largest.

For the turn-off transition, since the calculation result of t_d2 was 41 ns, the five test data points were 31 ns, 41 ns, 51 ns, 61 ns, and 71 ns, respectively. It can be seen from Figure 8b that there was an obvious difference and the V_DS and I_DS waveforms produced by the five different t_d1 showed little difference. When t_d1 was 41 ns, the overshoot and oscillation of the I_DS were the smallest; the overshoot and oscillation of the V_DS were also the smallest.

As the delay time increased or decreased, the calculation results in both cases were the best. However, a trade-off between the V_DS and I_DS could be achieved when a t_d1 of about 21 ns at turn on and t_d2 of about 41 ns at turn off were, respectively, applied.

4.4. Comparison with Other Switching Strategies

After determining the optimal time delay of the OSS, it was necessary to compare the OSS with other switching strategies. First, we compared the OSS with the hard-switching (HS) strategy to confirm its advantages and improvements. Then, we compared it with a digital gate driver (DGD), which is widely used in teaching and research, to further verify the advantages of the OSS. A detailed experimental comparison of these different switching strategies follows.

4.4.1. Compared to the Hard-Switching Strategy

In order to demonstrate the excellent switching performance of the OSS in terms of overshoot and oscillation, more simulations were performed and the results were compared with the switching performance of hard switching. It can be seen from Figure 9a that during the turn-on stage, the peak value of the I_DS dropped from 70.04 A to 60.23 A, a decrease of 14%, and the oscillation was also significantly reduced. However, the overshoot of the V_DS increased, which will increase the power loss; although, this will not affect the peak value of the V_DS.

Unlike in the turn-on process, the OSS successfully reduced the oscillation and peak value during the turn-off process, not only regarding the I_DS but also the V_DS. It can be seen from Figure 9b that the overshoot of the V_DS reduced from 704.56 V to 577.52 V, a drop of 18.03%.

Combining the two processes of turn on and turn off, it can be clearly seen that the OSS effectively reduced the overshoot and oscillation of the I_DS and V_DS in the SiC MOSFET switch, thereby reducing the overshoot and power consumption of the entire circuit.

4.4.2. Compared to Digital Gate Driver

The digital gate drive system from Agileswitch is a product with a wide range of applications. It can control the voltage drop and voltage drop time of the gate voltage without limitation to affect the switching performance of semiconductors. The control strategy of the DGD is also very advanced. However, the existing DGD control strategy is still unable to design more complex gate drive waveforms, especially the voltage drop after a delay time, like an AGD. Therefore, it was necessary to compare the OSS with existing digital gate driver strategies.

Figure 10 shows the V_DS and I_DS comparison of the OSS and DGD at the same turn-on time. Compared with the hard-switching strategy, the overshoot of the DGD was reduced by 19%, which was better than the OSS’s 14%. Although the DGD was slightly better at reducing the I_DS overshoot and oscillation, the overshoot of the V_DS was larger, which seriously increased the power losses of the circuit. Although the two switching strategies were both effective in reducing overshoot, they increased power consumption and were low in cost performance. This is why the first generation of DGDs cannot adjust the pulse shape during turn on.

Figure 10 shows the comparison of the V_DS and I_DS for the OSS and DGD at the same turn-off time. Compared with the hard-switching strategy, the DGD had no advantage and even increased power consumption due to the longer switch-off process.

In order to better compare two different switching strategies, the closing time of the DGD was extended from 68 ns to 88 ns and was then simulated and compared. The new waveform comparison is in Figure 11. Compared with Figure 10b, the DGD effectively suppressed the overshoot and oscillation of the V_DS and the overshoot was reduced by 11%. Compared with the OSS, the DGD was inferior. Continuing to extend the turn-off time of the DGD will make the optimization more effective; but, this will inevitably increase power consumption and reduce the frequency of the semiconductor device.

4.5. Comparison with Different Drop Voltages

The OSS can become more complex and diverse. The previous chapter mainly considered the influence of the voltage time delay on switching performance; this section attempts to study different voltage drops.

It can be seen from Figure 12 that, whether in the on state or the off state, the larger the voltage drop, the less overshoot. Because the increase in the voltage drop reduces the slope of the current and voltage, this proves that the formula in Section 3 is valid. However, during the turn-off process, with the increase in the voltage drop, the oscillation of the voltage and current was obviously increased.

4.6. Comparison with Different Voltage Drop Times

In the previous simulation, in order to simplify the complexity of the simulation, the voltage drop time (t_vd) used the rise time (t_r) and fall time (t_f) in the device datasheet. However, in the OSS, the voltage drop time is also an important parameter, similar to the delay time and voltage drop. Therefore, in this subsection, the effect of the voltage drop time on the switching performance was studied by simulation.

For the turn-on transition, because the t_r was 28 ns, five testing data points were chosen: 18 ns, 28 ns, 38 ns, 48 ns, and 58 ns. It can be seen from Figure 13a that different voltage drop times did not have much influence on the switching performance at the turn-on stage.

For the turn-off transition, because the t_f was 27 ns, five testing data points were chosen: 17 ns, 27 ns, 37 ns, 47 ns, and 57 ns. It can be seen from Figure 13b that in the turn-off stage, different voltage drop times had an impact on the switching performance. When the voltage drop time was 27 ns, the switching achieved the best performance. As the voltage drop time increased, the suppression effect of the OSS on voltage oscillations began to weaken. On the contrary, as the voltage drop time decreased, the voltage oscillation was suppressed; but, a larger reverse current was generated.

4.7. Power Loss Comparison

To determine whether a switching strategy is good or bad, in addition to observing whether it effectively reduces overshoot and oscillation, another important criterion is whether power consumption increases. Due to the advanced nature of LTspice, the product of current and voltage can be quickly integrated directly from the simulated circuit.

Table 3. Power losses for the simulations in LTspice.

Subsection	Switching Strategy	Power Losses (μJ)
4.4	HS	494.43
	OSS	520.21
	DGD	704.52
	DGD (extended)	681.03
4.5 Different voltage drop	Voltage drop 7 V	675.11
	Voltage drop 6 V	604.05
	Voltage drop 5 V	536.85
	Voltage drop 4 V	473.72
4.6 Different voltage drop time	Voltage drop time −10 ns	491.56
	Voltage drop time 0 ns	539.26
	Voltage drop time +10 ns	582.92
	Voltage drop time +20 ns	606.19
	Voltage drop time +30 ns	686.85
4.3 Different voltage drop delay time	Voltage drop delay time −10 ns	559.25
	Voltage drop delay time 0 ns	518.93
	Voltage drop delay time +10 ns	582.87
	Voltage drop delay time +20 ns	658.26
	Voltage drop delay time +30 ns	743.88

records the power losses from simulation models in one turn-on and turn-off round.

It can be seen from Table 3 that, compared with HS and the DGD, the power consumption of the OSS was slightly higher than that of HS. However, combined with Figure 11, the optimization effect of the OSS remained obvious.

In the comparison of different voltage drops, it can be concluded that the smaller the voltage drop, the smaller the power consumption. However, combined with Figure 12, it can be seen that the smaller the voltage drop, the smaller the suppression effect of the OSS on the circuit overshoot. Similarly, in the comparison of different voltage drop times, it can be concluded that the shorter the voltage drop time, the smaller the power consumption. However, combined with Figure 13, it can be seen that the smaller the voltage drop, the smaller the effect of the OSS on circuit oscillation suppression.

Finally, in the comparison of different voltage drop delay times, it can be concluded that when the voltage drop time is the calculated value, the power consumption is close to the minimum.

5. Conclusions and Discussion

In this paper, an optimal-switching strategy was proposed for improving the switching performance of high-power SiC MOSFETs under hard-switching conditions. In addition, considering the trade-off between switching loss and switching overshoot, the voltage drop delay time was analyzed and calculated. By optimizing the voltage drop delay time of the turn-on and turn-off stages, the OSS can effectively minimize overshoot and suppress oscillation. The simulation results showed that the OSS can reduce the current overshot at the turn-on stage and minimize the voltage overshoot at the turn-off stage. In addition, compared with the hard-switching strategy, the current overshoot in the turn-on phase decreased by 14% and the voltage overshoot in the turn-off phase decreased by 18.03%. This showed that the OSS achieved a more comprehensive control strategy and better switching performance. Compared with digital gate drivers, although each has its own advantages, the OSS is more advanced and suffers less power losses.

The next step in this research is to make the actual circuit and test it. The contribution of this paper is limited due to simulation constraints. The optimization of the OSS in this paper was limited to the control voltage drop delay time; the control strategy could not be fully tested. Only the influence of a single variable of the OSS on the switching performance was tested. In future studies, multivariable control, such as delay time, voltage drop, voltage drop time, etc., could be tested in an actual circuit and jointly controlled to optimize semiconductor switching performance. However, we can confirm that the proposed OSS is promising compared to other methods.