A CMOS Rectifier with a Wide Dynamic Range Using Switchable Self-Bias Polarity for a Radio Frequency Harvester

Abstract

This paper presents a switchable self-bias polarity on the CMOS complementary cross-coupled rectifier to improve the rectifier’s power conversion efficiency (PCE) profile across a wide input power (P_IN) dynamic range. This technique achieves this by adaptively switching the polarity of the bias on the n-MOS to overdrive it during low P_IN to improve the sensitivity and underdrive it during high P_IN to suppress the shoot-through loss and the unnecessary discharge of the coupling capacitor. The popular self-biased p-MOS is also implemented further to reduce the reverse conduction loss during high P_IN. The proposed rectifier is fabricated in a 40 nm CMOS process and operates at 900 MHz with a load of 50 kΩ. The proposed rectifier achieved a peak PCE of 72.1% and maintained a 0.8xPCE_PEAK across a P_IN dynamic range of 11.5 dB.

1. Introduction

The adoption of dedicated wireless power transfer (WPT) and energy harvesting (EH) is important to realize a wireless sensor network (WSN) on a massive scale. It relieves the reliance on an onboard battery and reduces the node form factor to achieve a reasonable economy of scale in areas such as structural health monitoring and logistic tracking. The front-end of the RF energy harvesting (RFEH) system is widely implemented with the cross-coupled rectifier for having higher power conversion efficiency (PCE) and sensitivity than the Dickson rectifier [1], as summarized in Figure 1. It is the diode voltage (V_DIODE) drop in the Dickson rectifier in Figure 1a that reduces the maximum output voltage (V_OUT) of the rectifier. As a result, a larger chip area is required to accommodate a greater number of cascading Dickson rectifiers to achieve the required V_OUT. Instead of a diode, a diode-configured MOS transistor can be utilized to potentially lower the dropout voltage to the MOS threshold voltage (V_TH). Exploitation of the body effect of the MOS was demonstrated by [2,3,4] to improve further the sensitivity by reducing the V_TH at the expense of higher losses at high input power (P_IN). The cross-coupled rectifier in Figure 1b eliminates the V_DIODE by operating the transistors as switches and having a dropout voltage based on their on-resistance (r_ON). It adopts the back-to-back inverter feedback structure similar to the static random-access memory (SRAM) structure. Inevitably, the cross-coupled rectifier also inherited some of the drawbacks, such as the shoot-through current (I_SHOOT). Currently, RFEH systems that utilize RF energy as their primary source are plagued by a slew of losses, such as free-space path loss and obstruction between the line-of-sight when operating at far field. Even though these losses are of lesser concern when operating in the near field, the non-linear rectifier exhibits rapid PCE degradation when high P_IN incidence on the rectifier leads to a limited and narrow P_IN dynamic range. The PCE of the rectifier can be calculated as follows:

$$PCE=\frac{V_{OUT}^2/R_{LOAD}}{P_{IN}}$$

(1)

where R_LOAD is the resistive load at the output of the rectifier, and P_IN is the input power at the rectifier.

Figure 2a shows the block diagram of a typical RFEH system, and Figure 2b shows the details of the proposed rectifier in this work. The cascading DC–DC boost converter provides a regulated supply voltage (V_SUP) for the sensor node and, most importantly, functions as a regulated R_LOAD to the rectifier to provide optimal PCE performance. A buck-boost converter operating in the discontinuous current mode (DCM) by [5] was able to maintain the rectifier PCE above 70% across an R_LOAD from 10 Ω to 10 kΩ. It was achieved by regulating the input impedance of the converter, making it independent of the converter input voltage (V_OUT of the rectifier) while also providing decoupling of the actual R_LOAD from the rectifier. In contrast, the study in [6] proposed using a maximum power point tracking (MPPT) algorithm to maintain impedance matching at the interface between the rectifier and DC–DC converter by reconfiguring the number of rectifier stages to achieve a dynamic range from –20 dBm to 20 dBm. At the same time, in addition to modulating the input impedance like [5], the study in [7] also changes the matching network at the input of the rectifier to achieve both input and output matching for its rectifier front-end. However, in applications without the boost converter, an N-stage cascading rectifier offers V_OUT boosting at a low P_IN to meet the minimum V_SUP but incurs a higher loss at a high P_IN [8]. Furthermore, to achieve an overall higher system efficiency, the rectifier must also address the varying P_IN.

Figure 3 shows the concept of the multi-path approach demonstrated by [9,10] achieved an improved P_IN dynamic range by dynamically switching between two rectifiers optimized at two targeted P_IN. The two rectifiers need not be of the same structure as reported in [11,12,13], where the cross-coupled and Dickson rectifiers were used for low and high P_IN, respectively. It allows the effective use of the Dickson rectifier at a higher P_IN when the dropout voltage is of lesser concern. It avoids the drawback of the increased losses in the cross-coupled rectifier. However, it is challenging to predetermine the optimal transition between the two rectifiers, resulting in sub-optimal performance and power loss. A series-parallel reconfiguring of an N-stage rectifier also demonstrates an improved P_IN dynamic range [14,15]. A 6-stage to 12-stage Dickson rectifier by [14] was able to achieve a 15 dB dynamic range but suffered from downtime due to the difficulty of the control circuit to discern the appropriate configuration. An interesting reconfiguring approach was proposed in [15] by stacking different V_TH devices to achieve a dynamic range of 22.8 dB. It uses native devices for low P_IN and sequentially stacks higher V_TH devices in series to limit the losses and obtain an equivalent longer channel length device. It is important to note that [15] requires extensive and careful optimization due to the use of different devices, which severely limits its practicality against device variation during mass production. However, the rectifier input impedance (Z_REC) also requires meticulous optimization [16] or an adaptive matching network [17,18] to address the change in Z_REC based on the configuration. Lastly, self-biasing improves the P_IN dynamic range by reducing the reverse conduction loss (P_REV) from the p-MOS by limiting the reverse conduction current (I_REV) and improves the sensitivity by increasing the overdrive on the n-MOS [19,20]. However, this also results in a reduced p-MOS forward conduction current (I_FWD) [19] and introduces a conduction imbalance between the p-MOS and the n-MOS, resulting in the inefficiency of the voltage boosting introduced by the coupling capacitors. The study in [21], moreover the study in [22], proposed the underdrive of the n-MOS to mitigate the conduction imbalance at high P_IN, which requires extensive optimization to ensure reasonable sensitivity at low P_IN. Furthermore, the diode-configured transistors used to generate the self-bias voltage are also susceptible to process and temperature variation with minimally accessible tune options. The studies in [23,24] addressed this issue by tracking V_OUT and providing continuous active compensation on the n-MOS.

This paper proposes a simpler approach suitable for low-cost systems by switching the polarity of the self-bias voltage applied to the gate terminal of the n-MOS to achieve two different PCE_PEAK at two different P_IN. The advantage of this approach is that it provides two distinct PCE profile transitions with a single rectifier and offers a tuning option. Section 2 discusses the operating principle of the rectifier; Section 3 presents the measurement results of the rectifier; Section 4 provides the conclusion.

2. Proposed Rectifier Analysis and Description

2.1. The Cross-Coupled Rectifier and Its Issues

The cross-coupled rectifier is fundamentally formed by two inverter structures in feedback. When considering half of the period, the differential input V_RFP and V_RFN is rectified by transferring charges from C₁ to C_L when V_OP > V_OUT and replenishing the charges in C₂ from the ground (V_SS) when V_SS > V_ON. The sinusoidal V_OP or V_ON results in I_REV when V_OUT > V_OP or V_ON due to the p-MOS bidirectional characteristic. The single-sided self-bias by [19] reduces I_REV by introducing a clamping voltage for the p-MOS at the expense of I_FWD. The role of the n-MOS is often treated as a means for current continuity. However, due to the sinusoidal nature of V_OP and V_ON, the n-MOS also experiences a similar issue as the p-MOS. The double-sided self-bias in [19] positively bias the n-MOS to lower the overdrive to improve the sensitivity. However, this resulted in severe PCE degradation at high P_IN due to the timing mismatch between the p-MOS and n-MOS. Figure 4a shows half of the cross-coupled rectifier, along with Figure 4b illustrates the timing mismatch between M₁ and M₃. The charges are transferred by I_FWD,M1 from C₁ to C_L through M₁ when V_OP > kV_OUT. As V_OP transit, M₁ discharges C_L when kV_OUT > V_OP and until M₁ turns off when kV_OUT − V_ON < |V_THP| shown in I_REV,M1. At the same time, M₃ also turns on when V_ON − V_SS > V_THN resulting in an I_REV,M3 discharging C₁. M₃ is only able to replenish the charges in C₁ with I_FWD,M3 when V_SS > V_OP and V_ON − V_OP > V_THN. The key observations are: (1) an overlap of I_REV provides a conduction path from V_OUT to V_SS, resulting in I_SHOOT, and (2) if I_REV for M₃ is longer than M₁, it reduces of number of charges stored in C₁ and degrades the effectiveness of the voltage boosting provided by the coupling capacitor. This can be expressed as follows:

$$V_{OP}=\frac{1}{2}k{V}_{OUT}+{\eta }_{COUPLING}{V}_{RFP}$$

(2)

$${\eta }_{COUPLING}=\frac{C_1}{C_1+C_{PARASITIC}}$$

(3)

where k factors the deviation from the analytical result of ½ [25], and η_COUPLING is the coupling efficiency between C₁ and the parasitic capacitance (C_PARASITIC) on node V_OP in Equation (3). The equivalent C_PARASITIC is the sum of the gate-drain overlap capacitance, gate-source overlap capacitance and gate-body oxide capacitance contributed by the p-MOS and n-MOS [25]. Under a steady-state operation, the variation in V_OUT is minimal with a suitable C_L and can be regarded as an ac virtual ground.

2.2. Description of the Proposed Rectifier

Figure 5 shows the schematic of the proposed rectifier with a switchable self-bias polarity. The main cross-coupled rectifier is formed by M₁–M₄ and C₁–C₂ similar to Figure 1b. The low V_TH (LVT) core devices are used for M₁–M₄ to achieve better sensitivity. On the other hand, metal-insulator-metal (MIM) capacitors are used for C₁–C₂ to minimize the amount of bottom plate parasitic capacitors while maximizing the amount of capacitance per unit area. Unlike Figure 1b, the gate terminal of M₁–M₄ is not connected to V_OP and V_ON, but instead, the V_RFP and V_RFN are coupled through C₃–C₆. It allows the voltage stored in C₃–C₆ to assist or restrict the overdrive to turn on M₁–M₄. The p-MOS positive self-bias voltage is generated using the diode-configured M₅–M₆ and C₃–C₄. In this diode configuration, M₅–M₆ provide a unidirectional conducting path to charge and store the charges in C₃–C₄. It only happens when V_OUT is sufficiently large to forward bias M₅–M₆. M₅–M₆ are implemented with high V_TH (HVT) core devices to prevent degrading the I_FWD at low P_IN due to the generated p-MOS self-bias voltage. The p-MOS positive self-bias voltage is crucial during high P_IN to limit I_REV. The n-MOS positive and negative self-bias voltage is generated with LVT M₇–M₁₀, R₁–R₂ and C₅–C₆. The performance at low P_IN is improved using a positive n-MOS self-bias voltage similar to [19]. This is performed by turning off M₉–M₁₀ and allowing R₁–R₂ to provide a dc-short between the gate-source terminal of M₇–M₈. The conducting path of the diode-configured M₇–M₈ allows charges to flow from V_SS to C₅–C₆. The positive n-MOS self-bias voltage makes it easier to turn on M₃–M₄ even with a smaller V_RFP and V_RFN. However, an n-MOS positive self-bias voltage introduces conduction mismatch during high P_IN, as illustrated in Figure 4. As such, a negative n-MOS self-bias is generated by turning on M₉–M₁₀ to address the conduction mismatch. It reconfigures M₇–M₈ by providing a dc-short between the gate-drain terminal to change the conducting path from C₅–C₆ to V_SS. This operation depletes the charges stored in C₅–C₆, resulting in a negative self-bias voltage. The r_ON of M₉–M₁₀ is much smaller than R₁–R₂.

2.3. Operation of the Proposed Rectifier

The symmetry of the rectifier simplifies the analysis by considering V_RFP > V_RFN in Figure 6a,c; as such, only M₁ and M₄ are involved in the main rectifying path (red path). The p-MOS bias is generated with M₅ and stored in C₄ (blue path). Figure 6a does not indicate the blue path due to the use of high V_TH (HVT) M₅ that prevents generating a bias voltage for p-MOS M₁. Different sets of devices are involved in generating the n-MOS bias at different P_IN modes. M₇, M₉, C₆ and R₁ are involved during low P_IN, while M₈, M₁₀, C₅ and R₂ are involved during high P_IN. In Figure 6a, M₉ is disabled and allows R₁ to diode-configured M₇ to provide a conducting path (green path) to charge C₆ at a low P_IN. Figure 6c shows a different conducting path (green path) when M₁₀ is enabled. It reconfigures M₈ to provide a discharging path for C₅ at high P_IN. Similar analysis can be performed when V_RFP < V_RFN in Figure 6b,d. The body-terminal of all p-MOS and n-MOS have been connected to V_OUT and V_SS (ground), respectively. For the following analysis, the voltages are mentioned in the format of V_X,Y,P where X indicates the voltage type, Y represents the device when applicable, and P indicates the phase as ϕ1: V_RFP > V_RFN and ϕ2: V_RFP < V_RFN when applicable.

During low P_IN operation (mode = 0), the diode-configured M₅ inhibits the conduction path from V_OUT due to the high V_TH (HVT) device where V_OUT − V_PA,ϕ1 < |V_THP,M5| and as such, V_PA,ϕ1 ≈ V_RFN,ϕ1. The reverse overdrive of M₁ V_{SG-REV,M1,ϕ1} = V_OUT − V_PA,ϕ1 due to the bidirectional conduction characteristics of the device (V_OUT > V_OP,ϕ1). The reverse conduction current (I_REV) is still manageable due to a small V_{SG-REV,M1,ϕ1} at low P_IN. It favors maintaining a larger forward conduction current (I_FWD). I_FWD occurs only when V_OP,ϕ1 > V_OUT; where the forward overdrive of M₁ V_{DG-FWD,M1,ϕ1} = V_OP,ϕ1 − V_PA,ϕ1 = (½V_OUT + V_RFP,ϕ1) − V_RFN,ϕ1. As for M₄, the study in [19] demonstrated an improved sensitivity by providing a positive bias onto the gate terminal of M₄ to lower the overdrive V_GSN required to turn M₄ on. The proposed rectifier adopted a similar configuration using M₈ and R₂. The bias is generated with R₂ providing a dc-short between the gate terminal and the source terminal of M₈ and stored in C₅ as V_C5,ϕ2 = V_SS − V_THN,M8 − V_RFP,ϕ2 during ϕ2. At ϕ1, V_GSN,M4,ϕ1 = V_RFP,ϕ1 + V_C5,ϕ2 − V_SS. It can be observed in Figure 7a that V_C5 increases with P_IN. Despite the improved sensitivity at low P_IN, it is irrefutable that the assistance in the overdrive also leads to difficulty in turning off M₄. Consequentially, it results in a rapid PCE degradation due to a conduction mismatch between the p-MOS and n-MOS, resulting in the unnecessary discharge of C₁ and C₂ and reduced efficiency of the voltage doubling functionality. This effect can be observed in Figure 7b for mode = 0 with the rapid decrease in ½k = V_C1/V_OUT with increasing P_IN.

During high P_IN operation (mode = 1), M₁ is self-biased with M₅ as V_PA,ϕ1 is sufficient to forward bias and turn on M₅ to charge C₄ to generate V_C4,ϕ1 = V_OUT – |V_THP,M5| − V_RFN,ϕ1 when V_OUT − V_PA,ϕ1 > |V_THP,M5|. The bias reduces I_REV by limiting V_{SG-REV,M1,ϕ1} = V_OUT − V_PA,ϕ1 = |V_THP,M5|. The reduced I_REV comes at the expense of I_FWD when the charges in C₁ are transferred to the output. I_FWD occurs when V_OP,ϕ1 > V_OUT with V_{DG-FWD,M1,ϕ1} = V_OP,ϕ1 − V_PA,ϕ1 = (½V_OUT + V_RFP,ϕ1) − (V_C4,ϕ1 + V_RFN,ϕ1) = V_RFP,ϕ1 − ½V_OUT + |V_THP,M5|. As for M₄, to address the concern in the previous mode = 0, M₁₀ is introduced as a switch to reconfigure the conduction direction of M₈ to limit the V_GSN permissible to V_GSN,M4,ϕ1 = V_DS,M10 + V_THN,M8. It is equivalent to providing a negative bias to reduce V_GSN,M4,ϕ1 by depleting charges in C₅, thereby generating a negative bias V_C5,ϕ1 = −(V_RFP,ϕ1 − V_SS − V_THN,M8) with a negative charge pump. The r_ON of M₁₀ is designed to be much smaller than R₂. It can be observed in Figure 7a that a negative bias V_C5 is generated. Subsequently, it is clamped and reversed due to the presence of the body diode in the CMOS transistor. Unlike the low P_IN condition, ½k remains relatively stable at ½ and does not exhibit rapid reduction with increasing P_IN in Figure 7b. In this mode, a higher V_OUT is generated at a lower P_IN due to an increased PCE. As such, an excessively high P_IN must not be applied to the rectifier to prevent overvoltage beyond the rated |V_DS| across M₂ and M₃ in the off state. The transient simulation in Figure 8 further shows a reduced +I_DN,M3. It indicates the reduction in unnecessary discharge of C₁. However, there is a reduced |−I_DN,M3| from 454 µA to 78 µA, which hinders the ability to replenish C₁ with M₃. Therefore, during the design of the proposed rectifier, the net flow of charges to C₁ and C₂ ∆Q = Q_N-MOS − Q_P-MOS ≥ 0 C is considered to ensure the effectiveness of M₃ and M₄ and prevent excessive negative bias.

2.4. Description of the Common-Gate Comparator

The common-gate comparator in Figure 9 is used to switch between the low and high P_IN and has a similar implementation as [9] using HVT devices. It operates at the subthreshold region to minimize the power consumption of the comparator. A hysteresis is provided by M₁₅ and M₁₆ in positive feedback when V_MODE = 0 V. It ensures the comparator initializes with V_MODE = 0 V and requires V_OUT to be sufficiently high to overcome the hysteresis to trigger a change in V_MODE. The comparator must configure the rectifier in the low-power mode (mode = 0) during the power-up sequence. The high-power mode (mode = 1) reduces the rectifier sensitivity due to a reduced n-MOS overdrive voltage and potentially prevents sufficient V_OUT from being generated in a low P_IN condition. During system initialization, the equivalent R_LOAD at the rectifier is high, with most of the system in either the standby or sleep mode. In the low-power mode, the rate of V_OUT versus P_IN profile is gentler than in the high-power mode, which prevents a rapid V_OUT build-up at high P_IN. The functional comparison is performed by Kirchoff’s voltage loop between M₁₁ and M₁₂ as follows:

$$V_{REF}-V_{OUT}=\left(∆V_{M11}+V_{THP,M11}\right)-\left(∆V_{M12}+V_{THP,M12}\right)$$

(4)

$$∆V_{MX}=n{V}_T\ln \frac{I_{D,MX}}{I_{D0}{\frac{W}{L}}_{MX}\left(1-e^{-\frac{V_{SD,MX}}{V_T}}\right)}$$

(5)

where I_D0 is the characteristic current of the transistor, W/L is the aspect ratio of the transistor, V_T is the thermal voltage, n is the subthreshold slope factor, λ is the channel length modulation coefficient, and ∆V can be determined from Equation (5) for the overdrive voltage. ∆V_M11 contributes to the offset voltage (V_OS) as I_D,M11 ≠ 0, while ∆V_M12 is negligible due to I_D,M12 ≈ 0 when V_REF > V_OUT. Assuming that V_OS is compensated with V_REF, the effect of V_OS can be neglected for simplicity. The output of the comparator (V_MODE) tracks V_OUT when V_OUT > V_REF, as shown in Figure 10.

Figure 11a shows the total current (I_TOTAL) consumption from both V_REF and V_OUT of the comparator by varying V_REF at the typical process corner. The various process corners are simulated, and the upper and lower bound of the total current consumption having I_TOTAL < 6 nA with the worst corner at the ff corner due to a lowering of both p-MOS and n-MOS V_TH. Figure 11b shows the impact of the comparator on the PCE of the proposed rectifier by examining the current ratio between the comparator and the I_OUT. The comparator contributes less than 0.1% of I_OUT, making it suitable for the rectifier operating at low P_IN in a harvesting application.

3. Measurement Results

The proposed rectifier is implemented in a 40 nm low-power CMOS node. It occupies an area of 125 µm × 140 µm, as shown in Figure 12. The rectifier is optimized at P_IN = −16 dBm, and the device parameters are tabulated in

Table 1. Device parameters of the switchable polarity bias rectifier.

Device	Type	Width/Length
M1–M2	LVT	24 µm/40 nm
M3–M4	LVT	4 µm/40 nm
M5–M6	HVT	0.2 µm/2 µm
M7–M8	LVT	0.2 µm/2 µm
M9–M10	LVT	2 µm/100 nm
R1–R2	Poly	4 MΩ
C1–C6	MIM	630 fF
M11–M12	LVT	600 nm/2 µm
M13–M14	2.5V GP 1	500 nm/4 µm
M15–M16	2.5V GP 1	3 µm/2 µm
Inverter p-MOS	2.5V GP 1	600 nm/2 µm
Inverter n-MOS	2.5V GP 1	3 µm/2 µm

¹ GP is the general-purpose device with higher V_TH than HVT.

. The measurement setup in Figure 13a consists of a vector network analyzer (VNA) (Agilent E5061B), a digital multimeter (Agilent 34461A) and a test fixture with the rectifier in QFN40. V_OUT and S₁₁ are recorded while sweeping the VNA output port power. S₁₁ is determined by de-embedding the test fixture and setting the reference plane at the pads of the package. The rectifier’s effective P_IN is determined as follows:

$$\begin{array}{ccccccc}{P}_{IN}& =& P_{SOURCE}& -& L_{INSERT}& +& 10\log \left(1-{\left|S_{11}\right|}^2\right)\\ \left[\mathrm{d}\mathrm{B}\mathrm{m}\right]& & \left[\mathrm{d}\mathrm{B}\mathrm{m}\right]& & \left[\mathrm{d}\mathrm{B}\right]& & \left[\mathrm{d}\mathrm{B}\right]\end{array}$$

(6)

where P_SOURCE is the output power of the VNA port, and L_INSERT is the insertion loss due to the test fixture.

The rectifier is measured with different configurations to determine its performance through the MODE pin, as shown in Figure 13b. The low-power (LP) mode with V_MODE = V_SS and the high-power (HP) mode with V_MODE = 1.1 V are characterized to determine the two PCE_PEAK. The comparator-track (CT) mode switches between the two PCE_PEAK with an external V_REF for the measurement; V_REF is available from the PMU. The measured PCE versus P_IN is shown in Figure 14a, Figure 15a and Figure 16a for different R_LOAD. Figure 14b, Figure 15b and Figure 16b show V_OUT versus P_IN for different R_LOAD. The measurement is performed at 900 MHz with a R_LOAD of 50 kΩ and a C_L of 10 pF. The proposed rectifier in the LP mode has a PCE_PEAK = 69% at a P_IN = −21 dBm; while operating in the HP mode, it has a PCE_PEAK = 75% at a P_IN = −17.5 dBm. During the CT mode, it exhibited an improved P_IN dynamic range performance of 11.5 dB across a 0.8 × PCE_PEAK with an externally provided reference voltage (V_REF) of 0.6 V. The CT has a sensitivity of −20.8 dBm to achieve a V_OUT of 1 V for an R_LOAD of 1 MΩ.

Figure 17 shows the PCE_PEAK versus R_LOAD. The proposed rectifier has the optimal performance at R_LOAD = 50 kΩ. However, with an increasing R_LOAD, the internal losses in the rectifier dominate over P_OUT, resulting in PCE degradation. Furthermore, a higher V_OUT is generated at a much lower P_IN, which prematurely switches the polarity of the n-MOS bias and shifts the operating conditions between the p-MOS and n-MOS, resulting in a degraded ½k when the proposed rectifier is operating in the CT mode. On the other hand, PCE also degrades with further reducing R_LOAD as R_IN/R_LOAD reduces the V_OUT/2|V_RFP| despite an increase to I_OUT/I_INTERNAL; R_IN is the inverse of the real admittance of the rectifier and I_INTERNAL is the internal current of the rectifier [26]. This trend was also reported in the analytical studies by [25]. The PCE profile can be tuned by varying V_REF, as shown in Figure 18.

Table 2. Performance comparison of proposed rectifier with reported state-of-the-art rectifier.

	This Work	TVLSI 2023 [15]	TCAS II 2023 [12]	T-MTT 2020 [20] # *	T-MTT 2018 [19]	MWCL 2016 [27]
Technology	40 nm	0.13 µm	65 nm	65 nm	0.18 µm	0.18 µm
Frequency	900 MHz	900 MHz	900 MHz	900 MHz	900 MHz	1 GHz
Technique	Switchable bias	Reconfigurable stack	Topology amalgamation	Dual-mode nested	Double-sided bias	Self-adapting feedback bias
Matching Network	No	No	No	No	No	No
No. of Stages, N	1	3	2+1	1	1	1
Load, RLOAD	50 kΩ	100 kΩ	100 kΩ	100 kΩ	100 kΩ	100 kΩ
PCEPEAK (%) @ PIN (dBm)	72.1% @ −18 dBm	47.91% @ −14 dBm	79.8% @ −17.5 dBm	80% @ −25 dBm a	66% @ −18.8 dBm a	65% @ −20.9 dBm a
Sensitivity (dBm) @ RLOAD (kΩ) for VOUT = 1 V	−14.9 @ 50 kΩ −16.3 @100 kΩ −20.8 @ 1 MΩ	−14 @ 50 kΩ −16 @ 100 kΩ −21 @ 1 MΩ	−15.5 @ 100 kΩ	−14.9 @ 100 kΩ	−16.2 @ 50 kΩ a −18.2 @ 100 kΩ	−18 @ 100 kΩ
PIN Range (dB), PR1 @ PCE > 0.8xPCEPEAK	11.5	12 a	7 a	6.5	7 a	9.5 a
PIN Range (dB), PR2 @ PCE > 20%	17	22.8	21	Not reported	14.5 a	17 a
Area (mm2)	0.0175	0.18	0.023	0.00648	0.0088	0.105

^a Estimated from publication’s figures. # Simulation results. * Measurement was performed at 433 MHz.

compares the proposed rectifier with that of other rectifiers employing similar strategies to achieve P_IN dynamic range improvement. The proposed switchable polarity bias can provide a P_IN dynamic range of 11.5 dB and 17 dB to maintain a PCE > 0.8xPCE_PEAK (PR1) and PCE > 20% (PR2) at a R_LOAD of 50 kΩ, respectively. The sensitivity of the proposed rectifier characterized at 100 kΩ is comparable to other work, but it fares 2 dB higher than [19,27] due to an increase in the parasitic loading on the n-MOS. Under the V_OUT = 1 V condition for sensitivity characterization, the proposed rectifier is operating in high P_IN with negative polarity bias at the gate terminal of the n-MOS which degrades the sensitivity. Despite this trade-off, the proposed rectifier achieved a better PR1 and PR2 than [19,27]. Wider PR2 was achieved by improving the low P_IN performance with the use of native devices with three configuration modes for [15], while dynamic body bias was implemented on top of self-biasing for [20]. On the other hand, the study in [12] uses a Dickson rectifier in the last stage of a 3-stage rectifier to minimize I_REV at high P_IN, thereby changing the PCE degradation characteristic and achieving an additional P_IN dynamic range.

4. Conclusions

This paper presents a switchable polarity bias scheme that enhanced the P_IN dynamic range of a differential CMOS rectifier. It achieves a PCE_PEAK of 72.1% and a P_IN dynamic range of 11.5 dB for PCE > 0.8xPCE_PEAK for R_LOAD = 50 kΩ. The P_IN dynamic range enhancement is achieved by producing different polarity biasing to adapt the overdrive voltage at the n-MOS: positive during low P_IN and negative during high P_IN. The switching of the polarity changes the optimal operating condition of the rectifier, thereby resulting in two distinct PCE peaks. Having two PCE peaks from a single rectifier is desirable as multiple rectifiers are commonly used in literature to address the different P_IN domains. The switchover is performed with an auxiliary low-power comparator to monitor the V_OUT and compare it with a V_REF to trigger a V_MODE signal. The control signal V_MODE is simple compared to other similar adaptive bias which requires extensive control circuits to generate a continuous analog bias on the gate terminal of the n-MOS. The mode pin allows trimming to be performed externally or adjusted by the control of the cascading DC–DC boost converter in an IoT application. The p-MOS is also biased positively during high P_IN to reduce the reverse conduction loss. The proposed rectifier is implemented in a 40 nm process node operating at 900 MHz. The proposed rectifier has an improved dynamic range PR1 of 11.5 dB while maintaining a PCE above 80% of its PCE_PEAK despite having a simpler implementation compared with other state-of-the-art rectifiers.