1. Introduction
Recent trends in electrical power, such as the rising electrification across sectors and the expanding integration of renewable resources and energy storage applications, have ignited heightened interest in power electronics and power converters [
1,
2,
3]. The demand in the power electronics field has led to the development of new concepts as well as revisiting concepts that are already in use, which brought the PPP field into existence. One of the major examples of PPP related to renewable energy generation is the Double-Fed Induction Generator (DFIG) [
4]. The DFIG was introduced to the wind energy generation field as an advancement to overcome the disadvantages of the Adjustable-Speed Generator (ASG) [
5]. The main advantage of DFIG over ASG is that it enables the use of the partial power converter. This leads to a reduction in the total cost of the system due to reducing the size of the inverter as well as the filter’s passive components. In PPP, as the name indicates, a power converter is used to process only a part of the whole power, thus reducing the losses and permitting a reduction in components size [
6].
The majority of the applications of PPP are based on DC-DC converters due to the nature of the current flow, and the fact that several applications have varying input or output voltage, which is a common situation for PVs and battery applications, while it is not common to encounter the same in AC, where the input and output voltages are usually well defined. Nevertheless, PPC can be integrated into the DC side of DC-AC converters to obtain a PPP feature for AC applications. Furthermore, pure DC-AC topologies also exist, such as in the work of [
7], where they propose handling power conversion by higher rating IGBT master units, and a SiC MOSFET slave unit is coupled by line-frequency transformer to deal with
partial power voltage regulation and harmonic compensation. Another interesting application for AC-DC appears as an ancillary feature in the work of [
8], where PPP is implemented to provide
hold-up time compensation.
Another application of DC-AC partial power topologies was demonstrated by [
9], where the inputs of two DC-DC converters were connected in parallel to the same PV module, and hence a differential-mode sinusoidal output was achieved directly.
This paper will follow the nomenclature suggested by Anzola et al. [
4], which segregates PPP into three broad families, as demonstrated in
Figure 1. The first group in
Figure 1 is the Differential Power Processing (DPP) topology. It deals mainly with current differences in series connected elements; this is also referred to as Parallel Current Regulator (PCR) in the work of Santos, Zientarski, and Martins [
2]. The Photo-Voltaic (PV)
optimizer is one salient example of the Differential Power Converter (DPC). Active battery cell balancing topologies also belong to this category. Such devices deal with the
mis-match current between elements connected in series [
1,
4,
10]. This is a desirable feature that extends the capability of PV arrays or battery cells, where those systems are usually composed of series-connected sources, with the performance of the whole group limited by the weakest link.
The second branch of the PPP family tree is PPC (referred to as Series Voltage Regulator (SVR) by [
2]), which can further be distinguished into two groups based on isolation requirements; however, it is to be noted that whether isolation is required for the converter does not imply the fact that the overall system will not have inherited galvanic isolation between its input and its output. The main advantage of PPC operation is its ability to interface a varying voltage on one side (either
source or
load) to a fixed voltage on the other side, which is a valuable feature for Maximum Power Point Tracking (MPPT) systems and battery charging applications [
6]. The sub-group of the
isolated topologies further splits into sub-groups: Input-Series-Output-Parallel (ISOP) (also referred to as Series-Input-Parallel-Output (SIPO) in some studies), Input-Parallel-Output-Series (IPOS) (or Parallel-Input-Series-Output (PISO)), Input-Series-Output-Series (ISOS), and Input-Parallel-Output-Parallel (IPOP). Various possible arrangements are revised in the upcoming
Section 3. The sub-group of non-isolated PPP deals solely with the Fractional Power Converter (FPC), and will be revised in
Section 4.1.
The last group seen in
Figure 1 is the
mixed strategies, where topology belonging to this group mixes the two previous designs (i.e., the DPC and PPC) in order to obtain the advantages of both groups while avoiding their shortfalls [
4].
Section 2 will revise the present-day parameters used to
benchmark designs and the performance of proposed PPP topologies and comment on the grouping and categorizing of the various PPP families.
Section 3 analyzes the fundamental current and voltage relations of the
isolated PPP and uses the parameters developed in
Section 2 to derive theoretical operating limits. An assorted collection of designs is also reviewed in
Section 3.2 (for IPOS),
Section 3.4 (for ISOP), and
Section 3.6 (for ISOS).
Section 4.1 will review possible FPC architectures, and some examples from the literature will be revised in
Section 4.2. Finally,
Section 5 includes the conclusions of this work.
2. Comparison Metrics
Several aspects and merits are implemented to enable comparison between various topologies. This section will revisit and define such attributes, starting with one of the main features of any power conversion system,
efficiency . Given the fact that the PPC treats only a fraction of the whole transferred power, this will give rise to two different dimensionless parameters [
4]:
System efficiency , which is defined as the ratio of
load power to the
source power , and further in terms of Source/Load currents
, and Source/Load voltages
, as stated in (
1) [
11,
12,
13].
Another efficiency is directly related to PPC operation, which is the
Converter efficiency , defined in (
2) [
4], where
are the input and output voltages of the converter, respectively, and
is the current entering the converter, while
is the current leaving the converter. The sign convention indicates power flow through the converter; that is, current entering through the positive terminal indicates power flow
into the converter, while current flowing out of a positive terminal indicates power flowing out of the converter.
The nature of PPC converter operation requires the definition of another attribute, which is the
processed power ratio , presented in Equation (
3).
defines the ratio of the power processed by the converter
to the overall power drawn from the source
[
4,
13,
14].
In addition to the previous equations, the
static voltage gain is also a key parameter in defining PPC operation, given in Equation (
4) [
6,
15,
16,
17].
It is worth mentioning that this work considers
to be always positive, i.e.,
, since negative values in a given topology (indicating a
reversed source or load) will be equal (i.e., absolute) or refer to another topology, as will be seen in
Section 3.
The
stress factor coefficients provide a quantitative approach to evaluate and compare converter designs (
topology) [
15,
18,
19,
20], independently of their power ratings. The three main components of any power converter are
semiconductor switches,
magnetic windings, and
capacitors. The stress factor calculations can be simplified assuming a lossless converter (i.e.,
) and further assuming a large enough inductor to suppress any ripple current [
15]. Equations (
5)–(
7) relate to the Semiconductor Stress Factor (SCSF), Winding Stress Factor (WSF), and Capacitor Stress Factor (CSF), respectively [
21,
22].
where
is the weight factor of the
jth component and can be considered 1 as a starting point [
18], and
are the maximum voltages seen or
blocked by the semiconductor switch and the capacitor, respectively.
,
, and
stand for the
root-mean-square current passing through the semiconductor switch, the capacitor, and the inductor.
is the input power to the converter and
is the duty of the
ith cycle.
is the maximum voltage seen by the magnetic component (i.e., inductor).
is the absolute value of the winding voltage in the
ith operating state [
18].
After developing the stress factor for each single component, the
global stress factor for all semiconductors, capacitors, and inductors can be summed as in (
9)–(
11).
Among the reviewed literature, several papers have implemented the component stress factor to evaluate their topologies and differentiate their performance in various operations. Chao [
23] has demonstrated an inverse relation between stress factors and the turn ratio in their IPOS and ISOP PPC converters. Values well below
were reported in [
15] for all SCSFs, WSFs, and CSFs. To have perspective, ref. [
24] reported figures larger by
orders of magnitude for the component stress factors.
The work of Zeintarski et al. [
25] illustrates the component stress factors over a range of
for two proposed PPCs: the Full-Bridge Series-Connected Partial Power Processor (FBSPPC) and the Full-Bridge Push-Pull Series-Connected Partial Power Processor (FBPPSPPC). Both topologies show a reduction in component stress factors with
values approaching unity.
Load power
also has a direct impact on the component stress factors, where it is observed in [
20] that increasing
will lead to larger stress on components in the case of a full-power rated converter compared to PPC.
Lastly,
non-active power is the energy stored in the reactive element (capacitor or inductor) and not transferred from the input to the output of a DC-DC converter operating in the steady state [
2,
20], defined also in Institute of Electrical and Electronics Engineers (IEEE) standard 1459 [
26] and measured in Volt-Ampere Reactive (VAR). Inductor non-active power
and capacitor non-active power
are evaluated by (
12) and (
13), where
and
are the energy stored in inductor and capacitor in joules,
D is the dimensionless duty cycle of each switching period
.
and
are the instantaneous voltage and current.
Equation (
14) represents the
Fryze power factor
, which defines the ratio of non-active to active power [
2]. It also contributes to the converter power losses [
27] and requires over-sizing the components, although it does not contribute to the transfer of real power. Isolated topologies show a direct influence of the transformer
turn ratio to the Fryze power factor. For a given topology,
will have a direct impact.
Figure 2 indicates how the
Fryze power factor can be affected by different topologies and operation modes. Both the Symmetrical Half-Bridge Current-Fed Power Processor (SHBCFPP) and Full-Bridge Phase-Shift Current-Fed Power Processor (FBPSCFPP) appear in the work of [
2] as prototypes rated for 2200 W. The FBSPPC and FBPPSPPC are 225 W and
W, respectively, presented by Zientarski et al. in [
25].
3. Isolated PPP Architectures
The required isolation refers solely to the converter topology, since a galvanic path will exist between the system’s input and output. Non-isolated converters cannot be used in these topologies due to two main constraints: the inherited risk of short-circuit and the fact that a non-isolated converter will end up processing full power [
28]. A workaround to overcome those shortfalls will be revised in
Section 4.1.
As commented earlier, PPC deals with a new way to connect power converters. At first glance, such connections might be misleading in that they influence different topologies. Based on the work of [
28], it is proposed to use the concept of a
dummy converter as a systematic approach for segregating and evaluating all possible architectures.
Figure 3 illustrates the three main connection groups, i.e., PISO, SIPO, and ISOS. IPOP is left out as it represents a specific case study that will be commented on in
Section 3.7.
The dashed connection boxes in the same figures indicate the possibility of a variety of connections, which will be examined in the subsequent sections. In accordance with the assigned notations, the power is transferred from the
source side into the
load side; hence, the DC current flow is fixed in
Figure 3 to indicate leaving the source and entering in the load.
3.1. Input-Parallel-Output-Series Topology (IPOS)
By consulting
Figure 3a, and ensuring that
is equal to
, four generic connections can be derived.
Figure 4 presents the three possible connections while highlighting the
series connection between the two converters (in red) and the
parallel connection of
to
(in blue). The fourth connection is shaded out as it is not realizable, as will be discussed in the upcoming part.
Writing the equations of
and
as functions of
and
can further simplify the interactions between the different topologies. The equations are tabulated in
Table 1, showing that
is held to
and the three possibilities of
.
Revisiting the voltage equations in
Table 1, another feature can be deduced. The
equation in
Figure 4a indicates that the system will have overall
step-up operation, although the converter itself can be either step-up or step-down; hence, several literature sources refer to this topology as
step-up [
2,
4,
29]. Following the same analysis for the
equation in
Figure 4b, it shows that it requires a step-up converter to prevent a negative
; if the converter is
step-down, it will lead to
negative load voltage. The third case, i.e.,
Figure 4c, needs a step-down converter to maintain a positive
; otherwise, it will lead to
negative voltage on the load.
Analyzing the last case by applying Kirchoff’s Voltage Law (KVL) shows
, or in other words, a negative
. By trying to apply the same approach to circuit (d) in
Figure 3, if the designated
is kept in the direction to flow into
, it has to leave the partial converter from the negative terminal. Following the path of
, it will leave the negative terminal of the load and enter the positive terminal of the dummy converter’s output. Flowing directly through the dummy converter,
will leave from the input side’s positive terminal, which means it has to join
, and both of them enter the partial converter. This case implies positive power flow (consumption) by both ends of the partial converter, which is unrealizable.
The above features can be illustrated by deriving the relations between the different voltages in terms of
and
[
11,
15,
30]. Equations (
15)–(
17) refer to the topologies of
Figure 4a,b,c, respectively. Equation (
18), however, is developed to further provide a mathematical proof of the
unviability of the circuit in
Figure 4d, since it will develop a
negative power processing ratio.
The above equations can be further visualized in
Figure 5. Referring back to the IPOS (a)
formula in
Table 1, it can be seen that
will always be bigger than
; hence,
is always ≥1, and this achieves overall
step-up operation, and IPOS (a) cannot operate in scenarios where
is set lower than
. IPOS (b), on the other hand, can work throughout the entire range of
, which can be translated as having
negative (i.e., swapped). However,
negative values appear when operating
. This can be interpreted as having power flowing in the
reverse direction through the converter. Another feature that can be concluded about IPOS (b) is that the majority of power will be processed by the converter, and the converter will never process less than
of the total input power.
To realize IPOS (c),
will always be lower than
, as seen in
Table 1, and it can also have negative values (
reverse connected). This operation mode produces an overall
step-down operation for positive values of
.
The last case of IPOS (d) is only plotted for integrity, but it is rendered inapplicable, as seen earlier.
3.2. IPOS-Based Converters
An example of
Figure 4a is a step-down Dual Active Bridge (DAB) operation that can be seen in the work proposed by Mishra et al. [
31] as a battery emulator based on a DAB converter with step-up IPOS topology. Although the DAB was utilized, the authors commented that a common-mode circulation current will be flowing between the input and the output of the converter systems, which requires further study. Analytical work performed by the authors shows that the
is always higher than the
.
Omar et al. [
14] utilized a
current-fed dual-inductor push–pull in step-up formation, also coinciding with
Figure 4a. The authors state the main advantage is
soft switching. The proposed design of the converter also permits reverse power flow; however, this operation mode was not analyzed in their work.
Zapata et al. [
11] used a single flyback converter, which is claimed to have reduced current ripple at the input and divided the individual converters’ power ratings.
Table 2 summarizes the salient features of the reviewed systems, while
Figure 6 illustrates some designs from the literature.
Table 2.
Reviewed IPOS-based PPC.
Table 2.
Reviewed IPOS-based PPC.
Reference | Converter | Topology | | | Application | System Power [kW] | [%] |
---|
[31] | DAB | IPOS (a) | 40% | 1.73 | Battery emulator | 0.10 |
99.90
|
[14] | Dual-inductor push–pull | IPOS (a) | 25% | 13.3 | PV | 1.20 |
99.00
|
[28] | Flyback | IPOS (a) | 41% | 1.43 | PV | 0.10 |
95.50
|
[16] | Flyback | IPOS (a) | 44% | 1.99 | PV | 0.10 |
98.50
|
[32] | DAB | IPOS (a) | 44% | 3.00 | Battery charging | 0.72 |
95.60
|
[11] | Flyback | IPOS (a) | 20% | 1.17 | PV | 0.99 |
90.00
|
[33] | Buck-boost Full-bridge | IPOS (b) | <40% | <3.5 | PV | 1.80 |
98.90
|
[34]
|
Full bridge push–pull
| IPOS (a) | 20% | 0.99 | Battery charging | 22.00 | 99.0 |
[35]
|
Full bridge phase shift
| IPOS (a) | 20% | <1.0 | PV | 78.00 | 98.5 |
The DAB converter in
Figure 6a has its input connected to
, while its output is connected in series to
, and both are connected to
to give a straightforward example of the IPOS (a) case.
The outstanding feature of
Figure 6b is that the authors
reversed the
. Carrying out KVL around the circuit yields
, while if the load was wired as designated, it would yield IPOS (b).
Figure 6c demonstrates another attribute, which is the
reversed . The right-hand side of the converter was
flipped so that the negative of the converter’s output is connected to the positive side of the load, thus fulfilling the IPOS (c) topology.
As it can be seen from [
16,
20,
29,
33], for example, the PPC efficiency holds high values throughout a wide range of operating conditions, contrary to the full-power converter, which achieves high efficiency generally at a specific operating point.
3.3. Input-Series-Output-Parallel Topology (ISOP)
Applying the same systematic approach of the previous
Section 3.1 to the ISOP topology demonstrated in
Figure 3b, four connections can be derived, as demonstrated in
Figure 7.
Table 3 contains a summary of the equations describing the behavior of each topology. By utilizing the definition of
and
, Equations (
19)–(
21) are developed relevant to the topologies in
Figure 7a,b,c, respectively.
By plotting the Equations (
19)–(
22),
Figure 8 can visualize the behavior of each ISOP topology. Starting with the ISOP (a) curve, it is seen that
is bounded between 1 and 0, since
will always be bigger than
, so
is not realizable. The ISOP (b) and (c) topologies can operate throughout the whole range of
(including negative source voltage) with linear characteristics. ISOP (d) is also plotted in
Figure 8 for review integrity, but it will not be practically achievable. One of the advantages of ISOP topology is that it reduces stress on semiconductor switches in high voltage applications [
36].
3.4. ISOP-Based Converters
The work of Tao, Wang, and Zhuo [
13] demonstrated using a
converter to achieve
four-quadrant operation. Their work is based on ISOP (a), providing bi-directional power flow between a DC bus and a battery of either a higher or lower voltage.
Renaudineau et al. [
37] implemented ISOP (b) to generate
rectified sinusoidal DC from a PV string input. In their simulation, they mitigated the harmonics content by relieving the inverter from high-frequency switching and dedicating it to
unfolding only.
In [
38], Anzola, Aizpuru, and Arruti proposed ISOP (a) for EV fast charging applications. Their simulation shows a steep drop of
and
as the State of Charge (SOC) builds up. A
down-scaled prototype pf the PPP demonstrates a reduction of 65% in the size of the magnetic components, i.e., the transformer and inductor, when compared to the full power converter.
Table 4 displays a comparison between the reviewed ISOP systems, while
Figure 9 presents examples of ISOP topologies.
Figure 9a represents a DAB-based ISOP (a) topology, where
is connected in parallel to
of the converter, while the same (i.e.,
) is connected in series to
, and then the sum of both voltages is connected to
.
ISOP (b) topology is demonstrated in
Figure 9b, where the flayback converter’s output is connected in parallel to
, while its input voltage is connected in series between its output voltage and the source.
The full-bridge converter displayed in
Figure 9c displays an
inverted left-hand side, where the negative side of
is connected to the positive side of
.
3.5. Input-Series-Output-Series Topology (ISOS)
One more configuration can be deduced in the isolated topology group, which is Input-Series-Output-Series (ISOS).
Figure 10 displays all the four combinations. By examining
Figure 10a, the series connection (marked in red) can be seen on both sides of the input and the output.
By developing the power balance of the converter (for an
ideal converter) in (
23) with the aid of the current equations in
Table 5, it can be seen that topologies (b) and (c) in
Figure 10 are not achievable.
However, since
,
has a
reversed direction in comparison to the designated direction in
Figure 10b. This negative current reflected in (
24) leads to a net positive power pouring into the converter, turning the converter into one that
sinks power instead of
transferring it.
A similar case can be deduced in the topology of ISOS (c); however, this time has a reversed sign but still leads to the same conclusion of the converter ending up sinking power. These observations halt any further study of those two arrangements.
On the other hand, in
Figure 10d, the current will flow out of the positive terminals of the
Load and
Source as well, which is not a valid power transfer mode.
An attempt to
flip the
Load terminals in
Figure 10d will end up yielding an identical topology to
Figure 10a.
Deriving
in terms of
produces an extra term in Equation (
25). This term is represented by the ratio of
to
, and its effect will further be commented on in the upcoming
Section 3.6.
By plotting Equation (
25) for several values of
as in
Figure 11, the generic trends and the influence of
ratio can be seen.
The trends in
Figure 11 imply the necessity to hold
at a steady value to maintain proper and predictable operation of the system.
3.6. ISOS-Based Converters
Within the surveyed and reviewed literature, the ISOS topology was the least encountered. The work seen in [
41] contains an intermediate ISOS, utilized as a
Half DC Bus Boost Converter, but no further details about its performance characteristics were developed. Ref. [
42] described two converters connected in ISOS formation, with one of them having a 1:1 ratio, which can be thought of as the dummy converter stated earlier; however, it is introduced to achieve full galvanic isolation.
The work of Lopusina and Grbovic [
43] illustrates explicitly an ISOS-topology converter; nevertheless, it is based on a
non-isolated converter and hence will be seen in the upcoming
Section 4.2.
3.7. Input-Parallel-Output-Parallel Topology (IPOP)
This arrangement represents a special case, since two out of its four variants will lead to short-circuiting the source with the load, leaving these scenarios out of the analysis. In the other two cases,
will always be connected in parallel to
, which leads to unity
as expressed in (
26).
Furthermore,
can be seen in
Figure 12, where cases (b) and (d) are also greyed out due to short-ciruits.
Although cases (a) and (c) in
Figure 12 theoretically exist, their practical applications might not be of much interest due to the fact that
is held steady to
. Such fundamental restrictions limited the interest in further research on this type of topology, and therefore no related literature was found.
5. Conclusions
This review focuses on partial power processing technology, providing a comprehensive review from three aspects: structural classification, theoretical operation limits, and prototype examples. It discusses the principles of partial power processing technology, summarizes and clarifies the classification and naming of partial power structures in existing research, revisits the component stress factors and non-active power factor, and provides certain guidance for researching partial power DC converters.
Compared with traditional full-power solutions, partial power DC converters can achieve direct transmission of main power, with only a small portion of the system’s power being processed internally with a DC-DC converter, resulting in performance improvements in cost, volume, power density, efficiency, and thermal design. However due to the specific nature of its circuit structure, there are certain limitations in its application scenarios, and the applicability of partial power solutions needs to be considered in combination with specific scenario characteristics.
Existing research has essentially validated the energy efficiency advantages of PPC compared to traditional full-power converters. This work intends to contribute on the entry and foundation levels to the field of partial power conversion and act as a reference and base for further future development. In the future, further research can be conducted from the following two perspectives: In terms of research content, fault tolerance and fault detection techniques can be of interest as can exploring configurations based on resonant converters. Research and optimization for partial power solutions can be performed in multi-domain environments, such as vehicle-to-grid applications, green hydrogen production, kinetic energy recovery and regeneration for electric mobility, power supply for new data centers, hybrid energy storage systems, energy routers, etc.