Residual Stress and Warping Analysis of the Nano-Silver Pressureless Sintering Process in SiC Power Device Packaging

Abstract

Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin–lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal stress analysis of the nano-silver pressureless sintering process is more limited. In this study, the pressureless sintering process of nano-silver was studied using finite element software, with nano-silver as an interconnect material. Using the control variable method, we analyzed the influences of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices. In addition, orthogonal experiments were designed to optimize the parameters and determine the optimal combination of the process parameters. The results showed that the maximum residual stress of the module appeared on the connection surface between the power chip and the nano-silver solder paste layer. The module warping deformation was convex warping. The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wave change. Each parameter influenced the stress of the solder layer in this descending order: sintering temperature, cooling rate, solder paste area, and solder paste thickness. The residual stress of the nano-silver layer was 24.83 MPa under the optimal combination of the process parameters and was reduced by 29.38% compared with the original value of 35.162 MPa.

1. Introduction

Since the beginning of the 21st century, with the rapid development of semiconductors and integrated circuits, power electronic devices have been improved in terms of miniaturization, high performance, high operating temperature, and high power density [1,2,3,4]. The third generation of high-power semiconductor chips represented by silicon carbide (SiC) and gallium nitride (GaN) emerge with power devices with high bandgap width, electric field breakdown strength, and electrical and thermal conductivity [5,6]. As the mainstream device of modern power electronics technology, the insulated gate bipolar transistor (IGBT) is widely used due to its excellent electrical performance and low expenditure required for activation. In systems with low fault tolerance, such as aircrafts, high-speed trains, and hybrid electric vehicles, any sudden failure of the power devices can be fatal.

Warping and residual stress, the main causes of reliability problems, exist not only in the normal operation of devices but also in their fabrication and packaging process, which can lead to the so-called yield problem [7,8]. In the packaging process of power devices, warping and residual stress are inevitable due to the mismatch between the coefficients of thermal expansion (CTE) of the package materials [9]. The residual stress inside the module will significantly impact its reliability and operating life. Module warping not only causes direct bonded copper (DBC) substrate delamination cracking, solder layer cracks, and other fatigue failures but also reduces the contact area between the connecting layers, thus increasing the thermal resistance of the system and reducing the heat dissipation performance. The connections between the chip and the DBC substrate and between the DBC substrate and the heat dissipation substrate are two main elements that generate warping and residual stress during the packaging of power devices. Chip bonding, an essential process in power semiconductor packaging, commonly includes welding and nano-silver sintering. Traditional electronic packaging connection materials such as solder and conductive adhesive cannot be used in high-temperature applications because their operating temperature is less than 175 °C, and degradation phenomena such as creep easily occur under large temperature changes [10]. Nano-silver sintering has been widely used because of its excellent reliability and adaptability to work at high temperatures.

Xu et al. [11] studied the effect of component thickness on the residual stress and warpage of IGBT module chips in the reflow soldering process. Addagarla et al. [12] established the flip-chip model. Using the transient thermal structure coupling field analysis method, they studied the stress and deformation distribution in the chip–substrate packaging process. Kang et al. [13] analyzed the effects of solder spacing, package size, and substrate thickness on warping. The results showed that the appropriate combination of solder spacing, package size, and substrate thickness can reduce the warping of the package structure. Zhou et al. [7] studied the effect of copper layer patterns on warping and residual stress in the IGBT reflow soldering process. The results showed that the maximum equivalent stress of the patterned and unpatterned copper layer appeared in the ceramic layer of the DBC substrate after reflow soldering, and the copper layer patterns of the DBC substrate had little effect on the residual stress and warping of the IGBT module. Liu et al. [14] studied the stress distribution on the chip of a double-sided silver sintering power module under different sintering pressures. Bai et al. [15] found that a nano-silver solder paste could be sintered at a temperature as low as 190 °C without pressure, thus achieving the goals of low-temperature pressureless sintering and high-temperature service of the solder. At present, most of the research on the bonding process of power device chips focuses on the thermal stress analysis of tin–lead solder and nano-silver press-assisted sintering. There are few studies on the thermal stress analysis of the nano-silver pressureless sintering process, and the existing studies considered a single factor or no more than three factors to analyze the influence of the process parameters on the sintering joint strength.

For this reason, the pressureless sintering process of a nano-silver paste was studied by using a nano-silver paste as the bonding medium. The effects of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices were studied by using ANSYS 19.2 finite element analysis software. At the same time, an orthogonal experiment was designed to carry out an orthogonal optimization simulation [16] to analyze and classify the influence of each parameter on the stress of the solder layer. The optimal combination of the process parameters was clearly defined to provide guidance for setting the process parameters of pressureless nano-silver sintering in future practical projects.

2. Model and Parameters

In this study, ANSYS software was used for the three-dimensional finite element simulation of the power module, which consists of eight IGBT chips, chip solder layers, a DBC substrate, a gold germanium (AuGe) layer, and a cooling bottom plate. The cooling substrate is connected to the copper layer under the DBC substrate through the AuGe layer. The bottom of the power chip is connected to the upper copper layer of the DBC substrate by the under-chip solder layer [17].

The 3D model of the power module and the combination of its different layers are shown in Figure 1, and

Table 1. Geometrical size of each layer.

Layer	Materials	Length (mm)	Width (mm)	Thickness (mm)
Colling baseplate	AlSiC	60.0	45.0	6.0
Baseplate solder layer	AuGe	55.0	40.0	0.1
Down copper	Cu	55.0	40.0	0.3
Ceramic layer	Si3N4	55.0	40.0	0.32
Up copper	Cu	55.0	28.0	0.3
Chip solder layer	Nano-silver	5.0	4.6	0.13
IGBT chip	SiC	5.0	4.6	0.36

lists the geometric parameters of each part of the module. The model structure analyzed in this study was relatively simple, with no significant curvature boundary. A mapping grid was used in the meshing method. Because the ratio of the length–width to the thickness of each layer structure was too large, each layer structure was divided into at least two layers in the thickness direction.

The thermodynamic parameters of various materials in the model at room temperature are shown in

Table 2. Material parameters of each component.

Materials	Density ρ (kg/m3)	Young’s Modulus E (GPa)	Poisson’s Ratio ν	CTE α (1 × 10−6/K)	Thermal Conductivity λ (W/m·K)	Specific Heat Capacity c (J/(kg·°C))
SiC [22]	3200	410	0.14	4.5	370	800
Nano-silver [18]	10500	Table 3	0.37	19.6	240	234
Cu [11]	8950	110	0.34	16.4	385	385
Si3N4 [17]	3200	320	0.25	3	80	710
AuGe [23]	14670	68	0.32	13.4	44.4	130
AlSiC [21]	2960	Table 5	0.4	Table 5	200	750

, including density, Young’s modulus, Poisson’s ratio, coefficient of thermal expansion, thermal conductivity, and specific heat capacity. Because nano-silver particles have an enormous specific surface area and a minimal surface curvature radius, they can begin to melt at 100 °C and produce inelastic deformation. Young’s modulus will change with the temperature.

Table 3. Young’s modulus of low-temperature sintered nano-silver.

Temperature (°C)	25	60	120	150	250
Young’s modulus (GPa)	6.28	4.52	2.64	1.58	0.5

shows the specific values of Young’s modulus of nano-silver varying with the temperature [14,18]. The finite element simulation considered the nonlinear mechanical behavior, and the Anand viscoplastic constitutive model was used to describe the mechanical properties of nano-silver solder [11]. Anand first proposed the Anand constitutive model and then developed it [19]. This study refers to the Anand model of sintered silver proposed by Chen et al., and the parameters are shown in

Table 4. Anand model material parameters of nano-silver.

Parameters	Value	Definition
S0 (MPa)	2.93	Initial value of deformation resistance
Q/R (K)	5706.3	Activation energy/Boltzmann constant
A (1/s)	9.81	Pre-exponential factor
ξ	12	Stress multiplier
m	0.6572	Strain rate sensitivity of stress
h0 (MPa)	14600	Hardening coefficient
ŝ (MPa)	101.7	Coefficient for deformation resistance saturation value
n	0.00326	Strain rate sensitivity of saturation value
α	1	Strain rate sensitivity of hardening coefficient

[20]. The room temperature of 25 °C was set as the reference temperature, at which the nano-silver solder was in the state of zero stress and strain. Because the CTE and Young’s modulus of the bottom plate have a great influence on the accuracy of the finite element model, this study refers to the values of CTE and Young’s modulus of the AlSiC bottom plate at different temperatures obtained by Gao et al., and the parameters are shown in

Table 5. Structural properties of AlSiC.

Temperature (°C)	Young’s Modulus (GPa)	CTE(1E-6/K)
50	192.68	3.65
100	189.74	5.67
150	183.26	6.59
200	178.70	7.16
250	176.19	7.48
300	167.81	7.62

[21].

In the process of finite element simulation, to avoid excessive thermal expansion constraints, the three-point constraint method was adopted for the base plate to limit the six degrees of freedom of the model. As shown in Figure 2a, point A limited the displacement in the X, Y, and Z directions, point B restricted the displacement in the Y and Z directions, and point C restricted the displacement in the Y direction. The temperature load shown in Figure 2b was applied to the model.

3. Effect of the Chip Sintering Process on Warpage and Residual Stress in the Power Modules

3.1. Warpage and Residual Stress Analysis in the Power Modules after Sintering

The connection between the chip and the DBC substrate was influenced by the different thermal expansion coefficients of the SiC chip, the nano-silver solder paste, and the DBC substrate’s copper layer. The chip connection layer as subjected to a shear force along the connection surface in the cooling process. When the whole structure was warped, more complex forces and stress concentration in the corners affected the connection layer. To accurately describe the stress state of the solder layer, the literature [24,25] proposed that the classical von Mises model can explain the inelastic behavior of many materials. The main reason for the failure of the chip connection was the excessive plastic deformation of the solder layer in the sintering process; so, the stress state of the solder layer could be obtained from the equivalent stress results.

During this finite element simulation, all components of the module were initially flat, and the initial residual stresses of the DBC substrate, silver solder paste, and bottom plate were ignored. The finite element simulation results are shown in Figure 3. It can be seen from the overall stress cloud diagram of the module in Figure 3a that the maximum residual stress was 48.794 MPa and appeared in the power chip. Because the thermal mismatch between the power chip and the nano-silver layer was the most serious in the power module structure, the maximum residual stress of the module occurred on the connection surface between the power chip and the nano-silver layer. From the warping cloud diagram in Figure 3b, it can be seen that the closer to the center, the more serious the warping was. The whole module showed convex warping, and the maximum warping value was 1.3652 μm. It can be seen from the stress cloud diagram of the chip in Figure 3c that the stress distribution of the chip was large in the center and small in the corners around it. The maximum stress occurred on the contact surface between the chip and the solder, and the maximum residual stress was 48.794 MPa. Because the thermal expansion coefficient of the solder paste was greater than that of the chip, the solder paste shrank faster. It can be seen from the stress cloud diagram of the nano-silver layer in Figure 3d that the residual stress of the solder layer diffused from the center of the solder layer to its edges in a ring, and the maximum stress of the solder layer was 35.162 MPa, which occurred in the corners of the solder layer. This means that the solder was prone to stress failure in the corner areas during the working process. The trend of the residual stress distribution of solder and chip was consistent with previous numerical analysis results [21]. The stress and warping distribution results for the power devices during the press-assisted sintering process are analyzed in detail in Appendix A.

3.2. Effect of the Process Parameters on Warping and Residual Stress

The bonding of chips on power device can present welding difficulties, being prone to cavity formation and affected by excessive bonding layer thickness, warping, and other problems. Selecting better process parameters could be conducive to reducing residual stress and warping.

This study mainly focused on the four parameters of sintering temperature, cooling rate, and nano-silver coating thickness and area. Using the control variable method, only one process parameter was changed, and the effects of the different process parameters on sintering warping and residual stress were studied and analyzed through horizontal comparison. The simulation test design is shown in

Table 6. Simulation of the experimental design.

Serial Number	Sintering Temperature (°C)	Heating Rate (°C/min)	Nano-Silver Thickness (mm)	Nano-Silver Area (mm2)
1	150	10	0.13	5.0 × 4.6
2	175	10	0.13	5.0 × 4.6
3	200	10	0.13	5.0 × 4.6
4	225	10	0.13	5.0 × 4.6
5	250	10	0.13	5.0 × 4.6
6	200	10	0.13	5.0 × 4.6
7	200	10	0.13	5.0 × 4.6
8	200	10	0.13	5.0 × 4.6
9	200	10	0.13	5.0 × 4.6
10	200	10	0.13	5.0 × 4.6
11	200	3	0.13	5.0 × 4.6
12	200	5	0.13	5.0 × 4.6
13	200	7	0.13	5.0 × 4.6
14	200	10	0.13	5.0 × 4.6
15	200	15	0.13	5.0 × 4.6
16	200	10	0.11	5.0 × 4.6
17	200	10	0.12	5.0 × 4.6
18	200	10	0.13	5.0 × 4.6
19	200	10	0.14	5.0 × 4.6
20	200	10	0.15	5.0 × 4.6
21	200	10	0.13	5.0 × 4.6
22	200	10	0.13	5.1 × 4.7
23	200	10	0.13	5.2 × 4.8
24	200	10	0.13	5.3 × 4.9
25	200	10	0.13	5.4 × 5.0

.

It can be seen from Figure 4 that with the increase in sintering temperature, the maximum residual stress of the module gradually increased from 38.773 MPa to 52.089 MPa, and the maximum warping gradually increased from 1.2625 μm to 1.4258 μm. Both the maximum residual stress and warping gradually increased with the increase in sintering temperature, but the increase was gradually reduced. This is because with the increase in temperature, the stiffness of the bottom plate and the resistance to deformation decreased. This is consistent with the variation in substrate warping with the increase in sintering temperature observed by Guo et al. using the finite element model [26]. Combining Figure 4 and Figure 5, it was found that the stress distribution in the center of the solder paste layer developed towards the direction of high stress with the increase in sintering temperature, and the area of low stress in the center became progressively smaller. This change might reduce the ability of the solder paste connection layer to withstand loads such as those caused by thermal cycling or thermal shock during the working process of the module and reduce the life of the module. The maximum residual stress of the solder layer increased with the increase in sintering temperature. Li et al. [27] experimentally studied the average shear strength of a nano-silver paste at different sintering temperatures and showed that at a lower sintering temperature a higher average shear strength could be obtained under the condition of keeping other process parameters unchanged. The effect of the sintering temperature on the solder fillet shape is detailed in Appendix B.

Figure 6 shows the influence of other process parameters (cooling rate, coating thickness, and coating area) on sintering warping and residual stress. Observing the warping of the module, it can be seen that the warping of the module increased with the increase in the cooling rate, but warping caused by the sintering process of the module chip could be reduced by increasing the area and thickness of the solder paste layer.

It can be seen from Figure 6a that the residual stress of the chip and solder paste layer increased with the increase in cooling rate. Changes in the cooling rate had little effect on the stress distribution in the center of the solder layer, and large stress changes were mainly concentrated in the corners of the solder layer. These changes in cooling rate may have no obvious effect on module manufacturing but may reduce the ability of the solder layer to bear loads such as during thermal shock and reduce the life of the module while working. However, if the cooling rate is too slow in practical engineering, the grain size of the solder paste will increase, and gold intergeneric compounds will grow too much, decreasing the solder layer’s fatigue resistance. Therefore, it is necessary to adjust the cooling rate in practical engineering to reduce the solder layer’s manufacturing defects and improve its reliability.

It can be seen from Figure 6b that the residual stress of the chip and the solder paste layer decreased continuously with the increase in the thickness of the solder paste. This trend is consistent with the observed trend of residual stress of the chip and solder paste layer with the increase in solder paste thickness [7]. If the interconnection interface is too thick in chip manufacturing, the chip manufacturing cost will significantly increase, and the current requirements for the miniaturization of electronic products will not be met. On the contrary, if the interconnection interface is too thin, low connection reliability will occur. In fact, when the chip is mounted on the substrate, if the thickness of the solder paste is not sufficient due to the extrusion of the chip, the solder paste will be unevenly dispersed between the chip and the substrate, and the sintering quality will be sharply reduced.

It can be seen from Figure 6c that with the increase in the coating area, the residual stress of the chip layer first decreased and then increased, and the residual stress of the solder paste layer changed in a wavy way. The residual stress of the solder paste layer did not show a single trend with the change in the coating area. For the solder paste coating area, we could not simply conclude that the more, the better, or the less, the better, but that an appropriate coating area existed. Qi et al. [28] experimentally studied the influence of the nano-silver interconnect area on bond strength. The results showed that with the increase in the interconnect area, the bond strength of the joint showed a wavy decreasing trend. Considering that excessive area and thickness of the solder paste layer would increase the manufacturing cost and the difficulty of the welding process and easily produce voids and cracks, it is essential to choose appropriate area and thickness of the solder paste layer.

3.3. Orthogonal Analysis of the Sintering Process Parameters

According to the analysis in Section 3.2, optimal ranges for the process parameters of the nano-silver sintering process were obtained. However, these process parameters interact with each other. Therefore, a multi-factor orthogonal experiment was designed to analyze the influence of sintering temperature, cooling rate, nano-silver solder paste thickness, and nano-silver solder paste area on the sintering residual stress of the solder bonding layer. The results will provide a basis for the optimal design of the IGBT module chip bonding process.

The thickness of the nano-silver solder paste, its area, the sintering temperature, and the cooling rate were used as test factors, and three levels (levels 1, 2, 3) were selected for each test factor based on the minimum residual stress. The experiment was designed according to the orthogonal table of four factors and three levels, and the horizontal distribution of each factor is shown in

Table 7. Orthogonal experimental design, factors and levels.

Factor Level	A (mm)	B (mm2)	C (°C)	D (°C/min)
1	0.15	5.2 × 4.8	200	10
2	0.14	5.1 × 4.7	175	7
3	0.13	5.0 × 4.6	150	5

. The thickness of the nano-silver solder paste is indicated as A, the area of the nano-silver solder paste as B, the sintering temperature is expressed as C, and the cooling rate as D.

According to the simulation results, the maximum residual stress of the solder layer was obtained when the temperature was reduced to 25 °C; the range analysis method was used to analyze the residual stress. The results are shown in

Table 8. Range analysis table of orthogonal test results.

Test Number	Factor				Maximum Residual Stress (MPa)
	A	B	C	D
1	0.15	5.2 × 4.8	200	10	32.723
2	0.15	5.1 × 4.7	175	7	28.616
3	0.15	5.0 × 4.6	150	5	27.172
4	0.14	5.2 × 4.8	175	5	27.691
5	0.14	5.1 × 4.7	150	10	27.783
6	0.14	5.0 × 4.6	200	7	32.668
7	0.13	5.2 × 4.8	150	7	27.116
8	0.13	5.1 × 4.7	200	5	29.116
9	0.13	5.0 × 4.6	175	10	33.625
K1	88.511	87.530	94.507	94.131
K2	88.142	85.515	89.932	88.400
K3	89.857	93.465	82.071	83.979
k1	29.504	29.177	31.502	31.377
k2	29.381	28.505	29.977	29.467
k3	29.952	31.155	27.357	27.993
Ri	0.572	2.650	4.145	3.384
Sequence	C > D > B > A
Optimal combination	A2B2C3D3				24.83

.

Range analysis is a common method for the analysis of orthogonal test results. The magnitude of the ranges reflects the influence of the investigation factors, and an extensive range means that changes in that investigation factor have a significant influence on the test results, identifying the main factor affecting the experimental results. On the contrary, a small range identifies a secondary factor. First of all, the maximum residual stress of the solder layer in repeated tests at the corresponding level of each factor was expressed as K_i (i represents different levels of each factor). In addition, the average residual stress of the solder layer was called the index average, which was expressed as k_i. The best level of each factor could be obtained with k_i and K_i, and the relationship between them is shown in Equation (1).

$$k_i=K_i/3$$

(1)

Secondly, to compare the test indexes of the various factors at different levels, the range R_i was defined to describe the significance of each factor in the orthogonal test. The range R_i is the difference between the maximum and the minimum K_i for each factor, as shown in Equation (2).

$$R_i=k_{i\max }-k_{i\min }$$

(2)

According to the range analysis results in Table 8, it can be concluded that the optimal horizontal combination was A₂B₂C₃D₃, and the residual stress value of the sintered nano-silver solder layer under the optimal parameter combination was 24.83 MPa. Compared with the original value of 35.162 MPa, the stress was reduced by 29.38%. According to the range results, it can be seen that based on their effects on chip silver sintering, the process parameters can be classified in the following order with decreasing priority: C (sintering temperature), D (cooling rate), B (coating area), and A (coating thickness).

4. Conclusions

In this study, a 3D finite element model of the power module was successfully established, and the influence of the nano-silver pressureless sintering process parameters on the residual stress and warpage of the module was studied. The control variable method and orthogonal test analysis were used to reduce the number of tests scientifically and rationally, avoid unsignificant tests, and minimize the residual stress and warping. The main findings are as follows:

• After chip reflow welding, the power module as a whole showed convex warping. The maximum residual stress of the module appeared on the connection surface between the power chip and the solder paste layer. The stress distribution in the nano-silver solder paste layer increased from the center to the edges of the distribution circle, and the maximum residual stress appeared in the corners of the solder paste.
• The overall residual stress increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. It first decreased and then increased with the increase in coating area. Increasing the area and thickness of the solder paste layer could reduce the warping caused by the module in the chip welding process.
• The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wavy change.
• The orthogonal test analysis showed that the chip silver sintering process parameters can be classified in the following order with decreasing priority: sintering temperature, cooling rate, coating area, and coating thickness. The optimized chip welding parameters were as follows: the thickness of the solder paste was 0.14 mm, the area of the solder paste was 5.1 × 4.7 mm², the sintering temperature was 150 °C, and the cooling rate was 5 °C/min. Under this optimal combination of the process parameters, the residual stress of the solder layer obtained by sintering was 24.83 MPa and was reduced by 29.38% compared with the original value of 35.162 MPa. This study provides a reference for selecting the process parameters of power module nano-silver sintering without pressure.

This study investigated the influence of various process parameters on warping and residual stress distribution in the chip connection layer during the sintering process of power device chips. However, this research assumed that the initial state of the DBC substrate was characterized by zero stress and strain and did not take into account the porosity of nano-silver. As a result, it did not fully capture the variability of the actual processing conditions. Future studies will explore the effects of the substrate’s initial state and the porosity of nano-silver on the properties of the connected layer according to the actual process conditions.