A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

Abstract

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

1. Introduction

Digital signal processing provides opportunities to enhance and personalize the environment, improving people’s daily lives across the globe. The analog-to-digital converter (ADC) is crucial as it bridges natural signals and digital processing. Of the various types of ADCs, the successive approximation ADCs offer a good trade-off between high accuracy and conversion speed with a relatively simple structure. The recent advancements in CMOS technology allow the SAR ADC to lower power consumption and increase conversion efficiency in applications such as wireless devices, Internet of Things (IoT), in vivo sensors, photo-detector readouts, and biomedical devices [1,2,3,4].

According to the ADC evolution and the recent surveys [5], the SAR class achieves a mean resolution of 10 bits (see

Table 1. ADC SAR features in the Biomedical Applications state-of-the-art.

Specification	[7]	[8]	[9]	[10]
Architecture	NS	Single	Single	Single
	SAR	Ended	Ended	Ended
Technology (nm)	180	180	180	90
Resolution (Bits)	7	11	10	10
Bandwidth (MHz)	0.000625	–	–	–
Supply Voltage (V)	1.0	0.75	1.8	0.3
Sampling Rate (MS/s)	0.01	0.01	0.001	3
Core area (mm2)	0.12	0.128	0.15	0.08
ENoB (Bits)	10.5	9.76	7.2	9.08
Power consumption (μW)	0.09	0.25	0.76	6.6
FoM (fJ/conv-lev)	50	28.8	51.7	4.065

). For biomedical signals, the frequency range is in low bandwidth, and the Successive Approximation Register (SAR) ADC presents a good balance for these applications in terms of energy and resolution [6]. The increase in chronic diseases such as diabetes and heart disease steers the creation of devices for monitoring and processing biomedical signals for healthcare applications. These devices need resolutions larger than 10-bit which are possible with several improvements in the SAR ADC, including the SAR logic. Figure 1 shows the general block diagram of a SAR ADC in a biomedical signal conditioning circuit. The basic working principle in the SAR architecture is constructing the digital word and comparing the input signal at different weights of a reference voltage. For every bit conversion, the circuit samples and holds ($S\&H$) the input signal. Following the S&H, there is an analog summing point. It is calculated by the difference between the input signal ($S_{in}$) and a digital-to-analog converter (DAC) feedback output, obtaining the quantization error in the analog domain. Subsequently, the comparator returns a logical value (1 or 0) depending on the error. A logic register maintains this value, which, depending on the received information, sends a control signal to the DAC.

A merit of an ADC SAR is the low power consumption using a simple trial and error technique to approximate the analog signal with a converted feedback digital word. However, the SAR ADC reliability depends on a robust integrated circuit design. The recent ADC SAR publications for biomedical signal conversion aim to improve resolution, power consumption, and speed [7,8,9,10]. These proposals focus on the feedback DAC section (see Figure 1) with a traditional comparator scheme and a lineal Shift Registers array for the successive approximation. The analog comparator in the recent converters typically uses a preamplifier and latch stages, which are sensitive to process and temperature variations, reducing the converter’s ENoB performance [11]. Generally, the ADC SAR implementation comprises a DAC-capacitor array dictating the converter resolution. Resolutions beyond 12 bit complicate the DAC-capacitor array requiring larger capacitor arrays. Recent solutions focus on hybrid ADCs to improve the final performance [12,13,14]. The work in [7] proposes a noise-shaping ADC SAR. It consists of reducing power consumption and an area-efficient integrator using replica capacitors and a dynamic amplifier. The work refers to the advantages of a passive infinite impulse response switched-capacitor integrator. The mentioned ADC combines the merits of SAR and Delta-Sigma data conversion with an oversampling rate $OSR=8$, achieving an ENoB $10.5$ bits. An important note in the commented topology is the reusing voltage comparator, reducing area distribution and dynamic power with a dynamic amplifier and latch stages.

A general error source is the DAC mismatch and voltage variations. The accepted solutions are calibration schemes [8,9] where a traditional ADC SAR architecture uses calibration circuits canceling charge error associated with parasitic capacitors. The solutions in [8,9] also use a sensitive voltage comparator with a pre-amplifier and dynamic latch. The target resolution is 10 bits, achieving an ENoB of 9.76 and 12.8 bits, respectively [8,9]. Another source of error is the comparator kickback noise; the work in [10] uses a pipeline comparator in a single-ended configuration achieving $9.08$ bit of ENoB with $6.6$ $\mu$$\mathrm{W}$. The single-ended circuit provides low power but presents poor noise immunity, improved through a fully-differential solution. Table 1 synthesizes the recent ADC SAR circuits for biomedical applications where the maximum ENoB is in the order of 10 bit. Note the Successive Approximation Registers mainly use a Single-Ended configuration, requiring redundancies or calibration schemes to improve performance. The principal considerations to improve resolution in SAR ADCs are: (i) to increase the size and number of DAC capacitors and (ii) to improve the voltage comparator’s resolution (threshold sensitivity). The considerations must include the robustness of the Process, Voltage, and Temperature variations, which typically are ignored. Many publications discussing ADC SARs assume that implementing logic SAR is straightforward due to the well-known capacitor switching scheme using digital control logic as proposed by Anderson [15] (See Figure 2). In the mentioned scheme, every flip-flop linearly changes in cascade conversion steps for single-ended architectures and unipolar signals. However, the linear behavior is only present under specific conditions. For bipolar signals and fully differential structures, the digital control logic is different. Additionally, when a high-resolution ADC SAR includes a redundancy algorithm or a calibration block, the digital logic control becomes cumbersome, requiring multiple tasks to run simultaneously, with each task depending on the execution of others.

This work proposes a novel finite-state machine approach for implementing digital logic control in a fully differential 14-bit ADC SAR MCS switching configuration. The SAR logic considers the differential scheme and the initial and previous states for the conversion logic states. The physical implementation utilizes digital standard cells in UMC180nm and follows the digital synthesis flow with electronic design automation (EDA) tools. Moreover, the fully differential SAR converter uses a novel symmetrical analog comparator that exhibits robustness to the manufacturing process, voltage, and temperature variations. The paper organization is the following: Section 2 describes the traditional SAR logic, Section 3 describes the proposed logic scheme and the full description in HDL. Section 4 details the converter design and presents the overall performance with post-layout results. Finally, Section 5 concludes the work.

2. Successive Approximation Register (SAR) Control

Figure 3 illustrates the digital control logic of a 3-bit single-ended ADC SAR proposed in [15]. The circuit, depicted in Figure 2b, uses a shift register at the top, transferring the HIGH logic state from the first flip-flop to the last in cascade mode. The flip-flops Q outputs serially set “1” during one clock cycle, while the corresponding $Q_n$ triggers the lower circuit named the “code register”. This code register updates the corresponding flip-flop according to the resulting comparator bit and control signal for the analog switches. At the end of each conversion cycle, the value in the code register represents the digitally converted word ($B_2$, $B_1$ and $B_0$). Figure 2a shows the signal switch control, including switching signals for the corresponding voltage to the bottom plate capacitors (e.g., $S2[S{2}_2,S{2}_1,S{2}_0]$), including the sample and hold stages. The circuit in Figure 2 is a typical choice for its simplicity and ease of understanding in SAR ADCs with 5–10 bits of resolution. Some analog designers prefer the full custom design of the digital blocks to implement the SAR logic control. Increasing the ADC resolution spec (more than 10-bit) constrains the SAR logic digital components and increases interconnections. Moreover, if the designer projects a fully differential structure with a bipolar input signal, the implementation and time for designing the logic SAR can significantly increase due to the non-linear workflow.

To render a clear description for the SAR logic in Figure 2, let us identify the $Bout$ and control switching $S{2}_n$ to the bottom plate in $4C_u$ trough expressions (1)–(4).

$$Bou{t}_n\left(k\right)=\left\{\begin{array}{ccc}Bou{t}_n\left(5\right)\hfill & \forall & k=1\\ \\ Bou{t}_n(k-1)\hfill & \forall & k\ne n+2\\ \\ \overline{Comp}\hfill & \forall & k=n+2\end{array}\right.$$

(1)

$$S{2}_0\left(k\right)=\left\{\begin{array}{ccc}0\hfill & \forall & k=1,2\\ \\ 1\hfill & \forall & k=(n-1)\\ \\ S{2}_0(k-1)•\overline{Comp}\hfill & \forall & k=n+2\\ \\ S{2}_0\left(k\right)\hfill & \forall & k\ne n+2\end{array}\right.$$

(2)

$$S{2}_1\left(k\right)=\left\{\begin{array}{ccc}1\hfill & \forall & k=1\\ \\ 0\hfill & \forall & 1<k\end{array}\right.$$

(3)

$$S{2}_2\left(k\right)=\left\{\begin{array}{ccc}1\hfill & \forall & k=1\\ \\ 0\hfill & \forall & k=2\\ \\ S{2}_2(k-1)•Comp\hfill & \forall & k=n+2\\ \\ S{2}_2\left(k\right)\hfill & \forall & k\ne n+2\end{array}\right.$$

(4)

where k represents the discrete time of the clock signal control, n is the bit position in the SAR converter digital output $Bout\left(k\right)$, and $Comp$ is the comparator logic output. At time $k=1$, the sample stage is set, and the vector $Bout$ holds the previous conversion value for each bit position. For $k\ne n$, the output vector $Bout$ remains unchanged. This process bins the hold and conversion stage while other bits are determined. Finally, when $k=n$, the position n in vector $Bout$ takes on the comparator logic output. The expressions match the logic sequence for the SAR register in Figure 2. Therefore, it is possible to describe the switching control signal behavior through the nonlinear set of functions of the comparator state and the previous control signal. Note the design of cumbersome state machines is not a direct approximation, and the Hardware Description Language provides a good solution. Finite State Machines (FSMs) describe algorithms with multiple branches and nonlinear dependencies on previous states. For the present case, the signal $S{2}_0,S{2}_1\left(k\right),S{2}_2\left(k\right)$ correspond to the $GND$, $V_{in}$ and $V_{ref}$ respectively.

Figure 3 displays a new Finite State Machine suggested in this paper for the ADC SAR circuit in Figure 2a. State machines can simplify heavy workflows involving multiple loops and branch logic when the workflow must respond to signals such as the comparator output, reset, enable, and digital redundancies or calibration schemes. These features denote an event-driven workflow. The Verilog code in Listing Section 2 represents the FSM shown in Figure 3. The description includes two blocks: asynchronous assignment and synchronous assignment. In the asynchronous assignment block, a case statement covers all seven stages of ADC conversion depicted in Figure 3, the assigned values in $S2,S1,S0,S00$ correspond to the nonlinear equations. For instance, an if-statement determines the value of $Bout$ at each stage based on the comparator output value. The synchronous block includes the signals $clk$ and $reset$ to assign the current stage and transition to the next stage on each cloack rising edge.

Listing 1. FSM Logic SAR for ADC 3 bits single-ended Unipolar.

The automatic tools for digital circuit design facilitate the physical implementation of weighty SAR logic and save time in the overall ADC SAR design. Within this context, a designer sets constraints in the digital implementation, such as optimizing the clock signal and determining the delay response and the times of rising and falling outputs of the SAR logic. Although the automatic digital design flow is used in many works to implement SAR logic, details about its implementation, the type and langueage of description are typically unexplored. This work presents an alternative to implementing digital SAR control, with the possibility of adding more states to calibrate the converter in future designs. The following Section will present an extension of this SAR logic for a fully differential architecture, considering biomedical specifications in the design.

3. The ADC SAR Circuit Design

The resolution and low power consumption provide SAR ADCs with biomedical application specifications for autonomous and networking.

Table 2. Summary of electrical and biomedical signals features.

Signal	Bandwidth (Hz)	Amplitude Range
Electroencephalogram (EEG)	0.01 to 150	<1 μV to 1 mV
Electrooculography (EOG)	0.01 to 50	<10 μV to 10 mV
Electrocardiography (ECG)	0.01 to 300	<50 μV to 10 mV
Electromyography (EMG)-Internal	0.01 to 15 k	<200 μV to 20 mV
Electromyography (EMG)-External	10 to 8 k	<10 μV to 100 mV

shows the bandwidth and amplitudes of the most important bioelectrical signals. The bandwidth resides in the $0.01$ $\mathrm{Hz}$ to 15 $\mathrm{k}$$\mathrm{Hz}$ and amplitude ranges from 1 μV to 100 $\mathrm{m}$$\mathrm{V}$. This consideration locates the ADC SAR performance appropriate to the electrical characteristic of bioelectrical signals.

Figure 4 shows a bipolar fully differential SAR ADC with a 14-bit traditional ADC SAR architecture working as a balancing. The Sample and Hold (S&H) stage stores the input, initially comparing with half the reference voltage $\frac{1}{2}{V}_{ref}$ (the reference voltage is the maximum amplitude of the input signal frame). If the input signal is larger than the first reference, the digital/analog converter (DAC) keeps the $\frac{1}{2}{V}_{ref}$ weight on the scale. Otherwise, for the following comparison, the DAC adds a new weight of $\frac{1}{4}{V}_{ref}$ and repeats the bitwise process. This approximation continues by storing the charge in the capacitor array in Figure 4. The ADC SAR of this work considers a resolution structure of 14 bits to ensure the target resolution. The sample rate considers an oversampling factor achieving an ENoB of 14 bit, with a signal-to-noise rate of ($SN{R}_N=98.02\mathrm{dB}$). Following the expression for oversampled signal-to-noise ratio ($SN{R}_{OS}$) Equation (5),

$${\mathrm{SNR}}_{\mathrm{OS}}=98.02\mathrm{dB}=6.02·\mathrm{ENoB}+1.25+10{log}_{10}\left(\mathrm{OSR}\right).$$

(5)

From this expression the oversampling factor is $\mathrm{OSR}=16$, where $\mathrm{ENoB}=14\mathrm{bit}$. According to Table 2, this work considers a fundamental frequency $f_o=13.760\mathrm{kHz}$ for biomedical signals, with $80\mathrm{kHz}$ of Bandwidth (BW) and sampling frequency $f_s=2.56\mathrm{MHz}$.

A fully differential circuit offers benefits by canceling the common mode noise, including the fully differential comparator. The differential SAR uses two matrices of split capacitances per input terminal with the corresponding differential logic Successive Approximation Register (SAR). For this implementation the voltage references are: $V_{ref+}=+1.8$ V, $V_{ref-}=0$ V, $V_{cm}=0.9$ V suggested for a CMOS UMC 180 $\mathrm{n}$$\mathrm{m}$. The following subsections detail the design considerations in this ADC SAR implementation.

3.1. DAC Split Capacitor Array

The main advantage of using charge sharing in ADCs is low power consumption. However, as the number of bits increases, the capacitive load and DAC capacitor area exponentially increase. A solution for the DAC area is the charge scaling DAC with the split array configuration. Figure 4 shows the two matrix structures (MSBs and LSBs) with capacitive coupling. The recent SAR ADC improvements focus on the DAC structure because this block performs the sampling and hold (S&H), sum, and digital to analog conversion in a single step. An initial consideration for the design is the unitary capacitance $C_U$ for the DAC Split Array block. The ideal scenario is the minimum capacitance for a MIMCAP on UMC180nm (100 $\mathrm{f}$$\mathrm{F}$).

However, according to [16], the approximation of the minimum $C_u$ capacitance ($C_{min}$) must consider the temperature, mismatch effects, the typical capacitive density of the technology, resolution, error budget to the thermal noise, and voltage reference values. The $C_{min}$ considers all of these with:

$$C_{\min }=\max \left\{C_{m_m\mathrm{in}},C_{n_m\mathrm{in}}\right\}$$

(6)

where $C_{m_m\mathrm{in}}$ is the matching-determined minimum unit capacitance, and $C_{n_m\mathrm{in}}$ is the unitary capacitance by the capacitors array’s thermal noise.

Table 3. Considerations for the minimum unitary capacitance in UMC180nm.

Parameter	Expression	Value
Bits resolution	N	14
Voltage reference	$V_{ref}$	1.8 V
Capacitance density	$C_D$	100 fF
$C_{m_{m}in}$	$C_D{\left\{\frac{3.5\left[2^{N+2}(\sqrt{2^N-1}+(\sqrt{2}-1)\sqrt{2^N}\right]}{(\sqrt{2}-1)2^N}\right\}}^2$	18 fF
$C_{n_{m}in}$	$\frac{4KT{2}^{N+4}}{V_{re{f}^2}}$	16 fF

resumes the minimum unitary capacitance parameters. For a DAC 14 bit resolution, the thermal and voltage reference is 16 $\mathrm{f}$$\mathrm{F}$, and the process minimum capacitance successfully achieves the limit with a minimum of 18 $\mathrm{f}$$\mathrm{F}$. As a rule of thumb to ensure a $\frac{1}{2}LSB$ error budget: $C_u=4C_{\min }=72 \mathrm{f}\mathrm{F}$. However, according to the design rules in the UMC180nm [16] process, the minimum allowed capacitance is 100 $\mathrm{f}$$\mathrm{F}$. The switches associated with the DAC capacitors are complementary, and the input front-end sampling switches use the bootstrap scheme. The bootstrapped switch design utilizes the configuration and compensation scheme published in [17] to reduce nonlinearities. Additionally, the transmission gate switches, connecting the DAC assembly to different voltage references ($V_{re{f}_{\pm }}$, $V_{cm}$), consider a good ohmic contact maintaining the source and bulk terminal at the same potential to minimize body-effect nonlinearities. Reference voltages remain constant when compared with the variation of the input voltage range, allowing simulations with PVT variations to evaluate changes in the transmission gate resistance $Ro{n}_{p,n}$. The transmission gate circuit design considers a safe range to reduce the nonlinearities caused by $V_{gs}$, mitigating harmonic distortion.

3.2. Nonlinear Successive Approximation Logic

The logic SAR subsystem, as shown in Figure 5, has three input ports: $Reset$, $Clk$, and the two-bit $Co{m}_{in}$ sequence produced by the fully differential comparator. The state machine has seven outputs contolling the fully differential DAC array. The output $C_{\mathrm{RDY}}$ indicates the availability of the ADC conversion, and the output signal S enables the DAC capacitor top plates to connect to the common-mode voltage $V_{cm}$ at the sampling state. The bus $C_{Vin}$ controls the bootstrapping switches, and the buses $C_{Vr1}$ and $C_{Vr2}$ control differential voltage references to the capacitor bottom plate switches. Figure 5 also shows the logic SAR sequence where the clock signal rising edge changes the states. The reset input commands the system to the initial stage. The following process is to Sample where the $C_{Vin}$ FSM output enables all the bootstrapped switches, connecting the bottom plates to $Vi{n}^{+},Vi{n}^{-}$ according to the schematic in Figure 4. In this first cycle, the S output switches the DAC LSBs section to the common-mode $V_{cm}$ through the center-located switches. The second cycle takes the FSM to the $Hold$ state with a do not care for the values of $Co{m}_{in}$. In this state, the FSM executes three processes: (i) holds the sampled input, (ii) detects the sign of the input signal ($Vi{n}^{+}>V_{cm}$ or $Vi{n}^{-}>V_{cm}$), and (iii) sets the MSB value ($B\left[13\right]$).

The sign value results from the hold process by disabling the bootstrapped switches with $C_{Vin}$, and the S output disconnects the LSB capacitor top plates. In this process, $C_{V_{cm}}$ connects all the bottom plate capacitors to $V_{cm}$, and the top plates are in floating condition, holding the sampled input voltage at nodes $V{y}_p$ and $V{y}_n$. The bottom plate connection to the common-mode voltage subtracts $\frac{1}{2}{V}_{ref}$ to the sampled input value. With this process, the node $V{y}_{p,n}$ exhibits a differential of potential equal to $V_{i{n}^{\pm }}\mp \frac{1}{2}{V}_{ref}\mp V_{cm}$, the comparator determines the input voltage sign and the path where the conversion starts by establishing $B\left[13\right]$ in ‘1’ or ‘0’, as well as voltage reference $V_{re{f}^{\pm }}$ (e.g., shaded states in Figure 5). According to the previous state, the next state will be $S{3}_n$ or $S{3}_p$. The control signal $C_{V_{cm}}\left[13\right]=0$ turns off the $64C_u$ capacitor in the MSBs DAC array section while other capacitors remain connected to $V_{cm}$. Simultaneously, $C_{Vr1,2}\left[13\right]=1$ enables the switches connecting the $64C_u$ bottom plate to $V_{re{f}^{\pm }}$. The voltage $V_{i{n}^{\pm }}\mp \frac{1}{4}{V}_{ref}\mp V_{cm}$ appears at node $V{y}_{p,n}$ to calculate the $B\left[12\right]$ bit.

When $Co{m}_{in}=“10”$ the output $B\left[n\right]$ is ‘1’ and for $Co{m}_{in}=“01”$ the output $B\left[n\right]$ is ‘0’. There are two points to notice in the successive approximation: (i) in the left side of the FSM diagram in Figure 5, the control bus $C_{V_{cm}}[13:0]$ disconnects the capacitors from $V_{cm}$ and connect to reference voltage according to Figure 4, i.e., when the bit $B\left[n\right]$ is ‘1’, the next state returns the $C_{V_{cm}}\left[n\right]$ to 1 while returning if $C_{Vr2}=0$. Both signals maintain the previous state if $B\left[n\right]=0$. And ii) On the other hand, on the right side of the FSM for $B\left[n\right]=1$, the control signal states are at $C_{V_{cm}}\left[n\right]=0$ and $C_{Vr2}\left[n\right]=1$ and for $B\left[n\right]=0$ signals will be the opposite value. This configuration fulfills the expressions (7) and (8) for $Vi{n}^{+}>Vcm$, and (9) and (10) for $Vi{n}^{-}>Vcm$, where $V_{y_p}$ and $V_{y_n}$ represent the comparator inputs.

$$V{y}_p\left(k\right)=\left\{\begin{array}{ccc}Vi{n}^{+}\hfill & \forall & k=1\\ \\ V{y}_p\left(1\right)-\frac{1}{2}{V}_{DD}\hfill & \forall & k=2\\ \\ V{y}_p(k-1)+\frac{1}{2^{(k-1)}}{V}_{DD}\hfill & \forall & 2<k\end{array}\right.$$

(7)

$$V{y}_n\left(k\right)=\left\{\begin{array}{ccc}Vi{n}^{-}\hfill & \forall & k=1\\ \\ V{y}_n\left(1\right)+\frac{1}{2}{V}_{DD}\hfill & \forall & k=2\\ \\ V{y}_n(k-1)-\frac{1}{2^{(k-1)}}{V}_{DD}\hfill & \forall & 2<k\end{array}\right.$$

(8)

$$V{y}_p\left(k\right)=\left\{\begin{array}{ccc}Vi{n}^{+}\hfill & \forall & k=1\\ \\ V{y}_p\left(1\right)+\frac{1}{2}{V}_{DD}\hfill & \forall & k=2\\ \\ V{y}_p(k-1)-\frac{1}{2^{(k-1)}}{V}_{DD}\hfill & \forall & 2<k\end{array}\right.$$

(9)

$$V{y}_n\left(k\right)=\left\{\begin{array}{ccc}Vi{n}^{-}\hfill & \forall & k=1\\ \\ V{y}_n\left(1\right)-\frac{1}{2}{V}_{DD}\hfill & \forall & k=2\\ \\ V{y}_n(k-1)+\frac{1}{2^{(k-1)}}{V}_{DD}\hfill & \forall & 2<k\end{array}\right.$$

(10)

The states following $S{3}_{p,n}$ in Figure 5 depend on two possible decisions for each stage. For instance, Figure 6 presents a transient simulation where $B\left[13\right]=0$ and $B\left[12\right]=1$ and the next state will be $S4n_1$. The values for the $C_{V_{cm}}\left[13\right]$ and $C_{Vr2}\left[13\right]$ return to ‘1’ or ‘0’ respectively (left side of FSM), while setting $C_{V_{cm}}\left[12\right]=0$ and $C_{Vr2}\left[12\right]=1$ to generate $V_{i{n}^{+}}-\frac{1}{4}{V}_{ref}-\frac{1}{8}{V}_{ref}-V_{cm}$ at node $V{y}_p$ and $V_{i{n}^{-}}+\frac{1}{4}{V}_{ref}+\frac{1}{8}{V}_{ref}+V_{cm}$ at node $V{y}_n$ and calculate the $B\left[11\right]$ bit. The process is iterative up to the $S{15}_{x_1}$ state calculating the LSB. Finally, the $S{16}_x$ state in Figure 5 discharges the capacitor $C_u^{\prime }$ for a new conversion. The FSM considers the DAC’s fully differential feature with the Verilog description and the Cadence Genus digital synthesis with the UMC180nm CMOS technology. The Data Converter in this work uses the digital synthesis system requiring 423 standard cells, 74 sequential cells, 293 logic, and 56 inverters. The digital system section consumes $27.015\mathrm{nW}$ at $30.7$ $\mathrm{M}$$\mathrm{Hz}$ of static power. The voltage comparator design must be robust for good performance with the proposed state machine.

Notwithstanding the digital logic SAR in full-custom design can achieve a high transistor density, it is a long, error-prone process with a high development risk, especially when the ADC architecture resolution is beyond 12 bits and with fully differential architectures; the number of control lines increases considerably. An ADC SAR of 14-bit resolution requires at least eight control signals per capacitor (considering the complementary signals); there are 14 capacitors, and the control lines duplicate for a fully differential architecture. Also, it is essential to consider the extra circuit to avoid the overlap phases on control signals. The finite state machine proposed in this work uses the technology’s CAD place and route of standard cells, and the time-to-develop design is reduced significantly.

Table 4. Setup time in digital design flow Logic SAR.

Design	Flow Step	Time
Logic	Design Entry (HDL)	2 h
	Logic Synthesis	2 min
	Post-synthesis simulation	40 min
Physical	Floor Planning	10 min
	Placement and routing	2 min
	Post-Layout simulation	40 min
	Interconnections	1 h

shows the time to complete the digital place and route design flow in this work. According to the [18] report, using the fully customized method for designing digital circuits takes, on average, twice as long as using standard cells. The design in this work takes approximately 2 h to interconnect the digital logic SAR with the analog part. The FSM proposed in this work speeds up the digital logic SAR and layout design.

3.3. Fully Differential Robust Comparator Design

The SAR ADCs comparator’s specifications, such as gain, slew rate, and time response, limit the converter’s resolution. However, these are possible with a preamplifier followed by a Latch. The first step in designing the voltage comparator is the SAR ADC sampling time $F_s$. For a 14 bit of resolution with 16 clock cycles per conversion and for $F_s=$ $1.92$ $\mathrm{M}$$\mathrm{Hz}$ and $f_{\mathrm{comp}}=$ $30.7$ $\mathrm{M}$$\mathrm{Hz}$. The comparator and latch stages must cover this limit frequency and consider the LSB quantization level of 109 μV.

The proposed comparator in Figure 7 uses a complementary structure of n-type and p-type differential pairs. It adopts the continuous-time and positive feedback high-gain comparator in [19]. The basic circuit function is a latch amplifier with hysteresis. The latch-amplifier phase depends on the $\alpha$ factor in the differential gain as $A_d=(g{m}_1/g{m}_3){(1-\alpha )}^{-1}$, where $\alpha ={(W/L)}_5/{(W/L)}_3$. With $\alpha \to 1$, the comparator latches the output voltages as $A_d\to \infty$. The symmetrical feature renders the proposed comparator robust to Process Voltage and Temperature disturbances. The complementary differential pairs mirror the outputs with $m_{15}$, $m_{16}$, $m_{17}$ and $m_{18}$ and the differential gain is:

$$A_d=\left(\frac{g{m}_1·g{m}_{15}}{g{m}_3·gd{s}_{15}}\right)\left(\frac{1}{1-\alpha }\right)$$

(11)

The topology maintains a close relationship between the $m_5$ and $m_3$ transistor’s sizes, increasing the differential gain with the current mirror at the output stage. The equal dimensions ensure symmetry and robustness for the amplifier and latch operation.

The comparator design in CMOS UMC180nm with post-layout results exhibit a 20 ns @109μV_pp step response, with a ${\Delta }_{Delay}=5\mathrm{ns}$. The variations in the output dynamic range are ${\Delta }_{ODR}=358 \mu \mathrm{V}$ and the voltage offset is $24.7 \mu \mathrm{V}$ with a standard deviation below $5 \mu \mathrm{V}$.

The proposed comparator consumes $143 \mu \mathrm{W}$ of static power and improves the robustness and ODR for the state-of-the-art comparators [19]. It is possible to enhance the comparator’s sensitivity with additional pre-amplifiers. Figure 8 shows the static response under process and temperature variations. The corners for this result are Slow-Slow, Slow-Fast, Typical-Typical, and Fast-Slow, and the temperature cases −40 °C, 60 °C and, 120 °C. Figure 8a depicts critical differences compared with the proposed complementary architecture shown in Figure 8b. Figure 8c illustrates a Monte Carlo analysis, where the mismatch transistor effect increases variations in latch offset within only a range of $\pm 6\mathrm{mV}$ in the presented scheme. With a preamplifier stage the comparator reaches a sensitivity of $80 \mu \mathrm{V}$ with a delay of $1\mathrm{ns}$ and ${\Delta }_{Delay}=5\mathrm{ns}$, the ${\Delta }_{ODR}=65\mathrm{ns}$ and the voltage offset is $10 \mu \mathrm{V}$, with $\Delta V_{OS}=15 \mu \mathrm{V}$. The pre-amplifier stage uses the proposed topology with $\alpha =0.7$, maintaining the robust performance with $97 \mu \mathrm{W}$ of power consumption. The proposed continuous comparator and FSM are designed to prevent metastable outputs ($Comp=“00$”, $Comp=“11$”). If this occurs, the finite state machine does not progress to the next state, preventing conversion errors.

4. Post-Layout Characterization and Results

The proposed 14 bit SAR ADC design uses the Finite State Machine as a novel logic SAR, the robust comparator, and switches configuration of this work in a UMC180nm CMOS technology. The layout fits in 0.25 mm² (500 μm × 500 μm). The layout in Figure 9 considers a symmetrical disposition with a common centroid for the capacitive DAC array. The SAR ADC layout incorporates dummy structures for the capacitive network, with the comparator at the center alongside dummy transistors.

The post-layout simulation for a 80 $\mathrm{k}$$\mathrm{Hz}$ bandwidth and Oversampling Rate (OSR = 16) exhibits the spectrum in Figure 10a. The sampling frequency for this test is 2.56MS/s with a 13.760 kHz sinusoidal input signal, which is below the bandwidth limit to observe possible harmonic content. The post layout result yields $14.52$ bit of ENoB considering the Typical-Typical statistical models from the UMC180nm process design kit at 60 °C.

A Process and Temperature variation test validates the effectiveness of the proposed control logic SAR and the robustness of the comparator. Figure 10b shows the corner resolution with a distribution between $13.31$ bit to $14.52$ bit for 24 post-layout simulation corner tests (in transient analysis). The critical corner in this statistical test is the SF process at −40 °C. The SF and FS corners for any temperature show ENoBs below $13.5$ Bits, while TT, SS, and FF at 60 °C and 120 °C improve the ENoB because the response of the continuous comparator presents a minimum offset in these corners, changing the sensitivity of the comparator for the less significant bits.

Comments on the Simulation Results

Table 5. Propouse ADC SAR for Biomedical Applications.

Specification	This Work
Architecture	Fully Differential
Technology (nm)	180
Supply Voltage (V)	1.8
Resolution (Bits)	14
Sampling Rate (MS/s)	2.56
Core area (mm2	0.25
SNDR (dB)	84.66
Power consumption (μW)	310.3
OSR	16
Bandwidth (MHz)	0.08
ENoB (Bits)	14.07
$FO{M}_w$ ( $\mathrm{f}$$\mathrm{J}$/$\mathrm{conv}-\mathrm{lev}$)	$165.76$
$FO{M}_s$ (dB)	$165.76$

$FO{M}_w=\frac{Power}{F_s{2}^{ENoB}}$. $FO{M}_s=SNDR+10log\left(\frac{BW/2}{Power}\right)$.

summarizes the performance of the ADC converter using the proposed SAR logic. The Walden (${\mathrm{FoM}}_W$) and Schreier (${\mathrm{FoM}}_S$) [5] Figures of Merit (FoM) exhibit good performance of this work. The proposed data converter achieves a balance between sampling rates and power consumption. Furthermore, the proposed design presents robustness with process and temperature variations, typically unexplored in most publications. Despite achieving a high resolution (ENOB > 14b), it is widely recognized that during the manufacturing process, about 4 or 5 bits are lost when there is no calibration scheme [20,21,22,23]. However, the suggested finite state machine (FSM) can be adjusted to work with a calibration scheme. For instance, in [20], the calibration method uses the occurrence of metastability in the comparator and the intrinsic noise to calibrate the DAC array without changing its structure. In this case, only additional states need to be included for calibration during each conversion.

5. Conclusions

This work presents the design of a traditional 14 bit ADC SAR with a novel continuous comparator robust to PT variations and a novel Successive Approximation control logic based on a non-linear logic SAR. This research highlights the problems arising from a high-resolution and fully differential version of the SAR logic construction. The proposed digital logic considers forbidden states by observing the actual and previous conversion values. Post-layout simulations exhibit a $14.52$ bit of ENoB and robustness to process and temperature variations, with a $0.63$ bits mean loss; however, with mismatch effects, is probably to lose 3 to 5 bits. The ADC uses 0.25 mm² in area and consumes $310.3$ $\mu$$\mathrm{W}$ at a $2.56$ $\mathrm{M}$$\mathrm{Hz}$ sampling frequency. The achieved SNDR is $84.66$ dB, resulting in Schreier FoM is $165.76$ dB, and Walden FoM of 7.04 fJ conv−lev. The proposed Finite State Machine is an excellent choice for implementing SAR logic control in any ADC converter.