Schottky Barrier Formation Mechanism and Thermal Stability in Au-Free Cu/Metal–Silicide Contacts to GaN-Cap/AlGaN/AlN-Spacer/GaN-on-Si Heterostructure

Abstract

In this study, metal–silicide-based contacts to GaN-cap/AlGaN/AlN-spacer/GaN-on-Si heterostructure were investigated. Planar Schottky diodes with Cu-covered anodes comprising silicide layers of various metal–silicon (M–Si) compositions were fabricated and characterized in terms of their electrical parameters and thermal stability. The investigated contacts included Ti–Si, Ta–Si, Co–Si, Ni–Si, Pd–Si, Ir–Si, and Pt–Si layers. Reference diodes with pure Cu or Au/Ni anodes were also examined. To test the thermal stability, selected devices were subjected to subsequent annealing steps in vacuum at incremental temperatures up to 900 °C. The Cu/M–Si anodes showed significantly better thermal stability than the single-layer Cu contact, and in most cases exceeded the stability of the reference Au/Ni contact. The work functions of the sputtered thin layers were determined to support the discussion of the formation mechanism of the Schottky barrier. It was concluded that the barrier heights were dependent on the M–Si composition, although they were not dependent on the work function of the layers. An extended, unified Schottky barrier formation model served as the basis for explaining the complex electrical behavior of the devices under investigation.

1. Introduction

Enhancing the efficiency of high-power electronic devices aligns with the concept of sustainable development. Next-generation devices that utilize wide-bandgap semiconductors, such as gallium nitride (GaN) or silicon carbide (SiC), can operate at higher frequencies, voltages, and temperatures [1]. Their wide adoption will reduce electric power conversion losses and mitigate the negative impact on the environment.

The progress of high-power electronics is nowadays largely influenced by the development of new electronic devices that utilize GaN epitaxial layers grown on Si substrates [2]. The important advantage of GaN-on-Si heterostructures is their relatively low cost which stems from the ability to grow GaN epitaxial layers on inexpensive, large-area Si wafers. Additional economic benefits can be realized by fabricating devices in established silicon foundries. It implies that the design of the devices must align with the standards of the Si industry. The requirement eliminates the possibility of using gold (Au) [3,4,5,6,7,8], which has proven its applicability in GaN technology, but is a serious contaminant in Si devices.

The exceptional properties of GaN are often utilized in AlGaN/GaN High Electron Mobility Transistors (HEMTs), where gold is commonly used for metallization. The solution to Au-free metallization scheme may be to replace gold with copper (Cu), which has a lower resistivity than Au, a higher thermal conductivity, and a lower cost. Several promising reports on pure Cu/(AlGaN/GaN heterostructure) Schottky contacts have been published [9,10,11]. However, thermal stability investigations demonstrated poor reliability of Cu-based Schottky junctions [12,13,14]. Cu can easily diffuse into GaN, and chemical reactions at the Cu/heterostructure interface occur at elevated temperatures [14]. Therefore, to use Cu in Schottky gate HEMTs, a specific Schottky contact is required that can block the diffusion of Cu atoms toward the substrate.

Various Au-free Schottky contacts to AlGaN/GaN heterostructures have been investigated so far. A TiN layer frequently appears in scientific reports [6,15,16,17,18,19,20,21,22,23,24], where it is used as the first layer (i.e., in contact with the heterostructure) of the stack constituting the gate or anode. There are also research reports that use Ni as the first layer, similar to typical Au/Ni/heterostructure contacts, but with various metals replacing the Au as the second (top) layer in the stack (for example, Al [25] or W [26]). Various other materials have also been tested, including Al/W [27], WC [8], and WN_x [28].

However, in regard to copper metallization and thermal stability, the particularly promising materials for creating Schottky contacts are metal silicides [7,14,29]. These compounds can form contacts that are generally more thermally stable than those with pure metal layers [30]. Pure metals are also not ideal candidates for diffusion blocking layers because they can form alloys with Cu and thus serve as a medium for Cu diffusion. Our recent studies revealed that the insertion of a Pd₂Si layer between the Cu overlayer and AlGaN/GaN heterostructure significantly improves the thermal stability of the Schottky electrode [14]. Furthermore, the Cu/Pd₂Si Schottky electrodes revealed higher resilience to elevated temperatures compared with other Au-free contacts like TiN [24] or WC [8].

Some silicides have relatively high work functions, close to 5.0 eV [31], which are promising in terms of the expected Schottky barrier height. In our recent studies, the Cu/Pd₂Si and Au/Ni contacts, exhibited similar barrier heights [14]. Yoon et al. [7] reported Cu/TiSi₂ contacts with a higher barrier than the reference Au/Ni contact (despite a theoretically lower work function 4.53 eV vs. 5.01 eV). Since the Cu/metal–silicide/(HEMT heterostructure) system has not been thoroughly investigated to date, it is necessary to investigate Schottky barrier formation mechanism and the stability of such structures.

In this study, we investigated and compared Schottky planar diodes with anodes containing Cu-covered silicide layers of various metal–silicon compositions. The results enabled the classification of the metal–silicide-based contacts in terms of Schottky barrier height and leakage currents. Subsequently, the thermal stability of the selected devices was investigated by annealing in vacuum. Additionally, the work functions of the sputtered silicide layers were determined using Internal Photoemission Spectroscopy (IPS). This enhanced the discussion on the formation mechanism of the Schottky barrier. Finally, an extended model is employed to explain the dependence of the observed barrier height on the parameters of the technological process.

2. Materials and Methods

Metal–silicon (M–Si) layers were deposited at room temperature using DC magnetron sputtering (p_Ar = 1 × 10⁻² mbar) from stoichiometric targets, including TiSi₂, TaSi₂, CoSi₂, Ni₂Si, Pd₂Si, IrSi, and Pt₂Si. The microstructural properties of sputtered Pd–Si layers were investigated in [32], which clearly confirmed the Pd₂Si composition of the layers. The compositions of the remaining layers will be generally referred to as M–Si compositions throughout the text. To eliminate the exact composition values from the discussion of the results, the work functions of the fabricated layers were determined through IPS measurements. Dedicated M–Si/SiO₂/Si structures were fabricated for this purpose, including Ti–Si, Ta–Si, Co–Si, and Ni–Si layers. The patterns of M–Si circular pads (1 mm in diameter) were fabricated on thermally oxidized Si substrates using photolithography. After deposition, the structures were subjected to Rapid Thermal Processing (RTP) for 30 min at 300 °C under N₂ atmosphere. The IPS optical system included an Xe 450 W lamp and a monochromator. The semi-transparent M–Si pads were illuminated, and the resulting photocurrents were measured for various wavelengths and applied voltages. Further details of the IPS experiment can be found in our previous report [32], which presents the results for the Pd₂Si layer. The results for the sputtered IrSi can be found in [33].

Schottky planar diodes were fabricated on a commercially available GaN-cap/AlGaN/AlN-spacer/GaN-on-Si HEMT heterostructure. The wafer was cut into 1 cm² samples. All devices studied in this work were fabricated on samples originating from the same wafer. The layout of the device and details related to the heterostructure are shown in Figure 1. The diodes were fabricated using photolithography and consisted of a circular anode surrounded by a ring-shaped ohmic contact. The fabrication procedure began with surface preparation, which included cleaning with organic solutions and subsequent treatment with NH₃: H₂O₂: H₂O (1:1:5) and HCl: H₂O (1:1). The ohmic contacts were then prepared and subjected to RTP at 750 °C. The devices differed in terms of the composition and preparation details of Schottky anodes. In addition to metal–silicide-based devices, diodes with Au/Ni or pure Cu anodes were fabricated. In the case of Pd₂Si, Ir–Si, Pt–Si, and Ni layers, in situ Ar⁺ treatment (−300 V, 30 s) was applied directly before deposition. The layers were deposited in a manner similar to the corresponding layers in the IPS structures, i.e., using single, stoichiometric targets. After the deposition of the first layer in the anode stack (M–Si or Ni), but before the deposition of the overlayer (Cu or Au), some of the devices were subjected to RTP in N₂ ambient at various temperatures ranging from 300 °C to 600 °C. Such annealing can be referred to as post-anode annealing or post-gate annealing (PGA). The influence of PGA on the electrical properties of Cu/Pd₂Si Schottky contacts has been discussed in [29].

The current–voltage (I–V) characteristics of the diodes were measured using an Agilent B1500 analyzer and a Cascade Summit 12,000 AP probe station. The thermal stability of the selected devices was evaluated by subjecting the diodes to subsequent annealing steps in vacuum at incremental temperatures ranging from 500 °C to 900 °C. High temperatures were applied to induce temperature-dependent changes within an acceptable period of time. Each annealing step took 6 h, with the exception of annealing at 900 °C, which lasted 3 h. The I–V characteristics were measured after each annealing process. A study on the thermal stability of Cu/Pd₂Si contacts, including microstructural characterization and comparison with the reference Au/Ni and Cu anodes, was reported in [14].

3. Results and Discussion

According to the Schottky–Mott rule [34], the expected height of the barrier formed at a metal–semiconductor junction is proportional to the work function of the metal. However, this rule does not apply if additional factors, such as interface states leading to Fermi level pinning, affect barrier formation. Therefore, the experimentally derived relationship between the barrier height and work function can provide initial insight into the formation mechanism of the Schottky barrier in the investigated structures. In this study, the work functions of the deposited layers ($\mathsf{\Phi }$_M-layer) were determined through IPS measurements.

The results are summarized in

Table 1. Work functions measured with IPS technique for the prepared layers ($\mathsf{\Phi }$_M-layer) compared with the values expected for bulk metal–silicides [31] ($\mathsf{\Phi }$_M-bulk).

M–Si	$\mathbf{\Phi }$M-layer (eV) (This Work, [32,33])	$\mathbf{\Phi }$M-bulk (eV) from Ref. [31]
Ta–Si	4.72	4.71 (TaSi2)
Co–Si	4.82	4.77 (CoSi2)
Ni–Si	4.93	4.96 (Ni2Si)
Pd2Si	4.94 [32]	5.0 (Pd2Si)
Ir–Si	4.97 [33]	5.08 (IrSi)
Ti–Si	5.63	4.53 (TiSi2)

. The work functions measured for the prepared layers closely matched those expected for bulk materials with stoichiometries equal to those of the sputtering targets. The exception was the Ti–Si layer, for which the measured work function was significantly higher. This difference may be related to the exact stoichiometry or microstructure of the deposited Ti–Si layers.

To examine the electrical properties of metal–silicide Schottky contacts to the AlGaN/GaN heterostructure, planar diodes were fabricated according to the diagram shown in Figure 1. All forward I–V characteristics measured on the diodes (including the reference Au/Ni and Cu diodes) had a characteristic form, showing two linear regions on a semi-logarithmic plot. A typical curve is shown in Figure 2. The linear regions are denoted as D1 and D2. The adaptation of the two-diodes model [35,36,37,38,39] can explain the observed I–V relationships, as described in [29]. According to this model, the presence of the D1 area reflects the actual Schottky contact between the substrate and silicide (alternatively, with the Cu or Au/Ni anodes in the reference diodes). This is depicted in the band diagram in the inset at the bottom-left side of Figure 2. The D2 range is related to the heterostructure details. The interface between the GaN channel and AlGaN barrier, with a thin AlN spacing layer, limits the current flow at increased voltages. The band diagram at the bottom-right side of Figure 2 shows that electrons must overcome the barrier and tunnel through the barrier associated with the thin AlN layer. This can be modeled as a reverse-biased diode connected in series with the actual Schottky contact. Finally, at high voltages the series resistance (R_S) limits the current, whereas at low voltages, the shunt current (∝ 1/R_sh) becomes dominant. The investigations on diodes with Cu/Pd₂Si anodes indicated that the shunt component is likely caused by lateral leakage, assisted by surface states between the electrodes [29]. The properties of the actual Schottky contact are exposed only in a narrow voltage range (D1). The simple fitting of a straight line can be ambiguous, depending on the selected data points. Therefore, a more extensive analysis of the data points is advisable. The equivalent circuit of the model is shown in the inset of Figure 2. The R_S can be omitted if the voltage range is limited to R_sh, D1, and D2. The parameters of the model, including the saturation current (I_S) and ideality factor (n) of D1 diode, can be obtained by fitting the model to the experimental I–V data. The Schottky barrier height can then be calculated from the I_S using the thermionic emission model. The fitting procedure is described in detail in [29].

The forward and reverse I–V characteristics of the diodes with various Cu/M–Si anodes are shown in Figure 3. For comparison, the results for the reference Au/Ni diode are also shown (dashed lines). Measurements of the pure Cu contacts can be found in [14]. The curves presented in Figure 3 were measured on diodes fabricated with PGA at 500 °C with the exception of diodes containing Co–Si or Ni–Si layers, which were fabricated without PGA. Unlike the other cases, the Co–Si and Ni–Si diodes exhibited higher Schottky barriers and lower leakage currents when no PGA was applied. It should also be noted that in the case of Pt–Si, only the diode with PGA was investigated.

To evaluate the Schottky contacts, the two-diodes model was fitted to the experimental data shown in Figure 3a. The fitted parameters, which include saturation currents and ideality factors of the D1 and D2 diodes, are listed in

Table 2. Parameters of Schottky planar diodes extracted from the I–V characteristics. Saturation currents (I_S, I_S2) and ideality factors (n, n₂) were obtained by fitting the two-diodes model to the forward I–V data. The barrier heights ($\mathsf{\Phi }$_B, $\mathsf{\Phi }$₂(0)) were calculated from I_S and I_S2 values under the assumption of the thermionic emission model. Reverse current densities (I_r) were measured at −10 V.

Anode Stack	IS (A)	$\mathbf{\Phi }$B (eV)	n	IS2 (A)	$\mathbf{\Phi }$2(0) (eV)	n2	Ir(−10 V) (A/cm2)
Cu/Ta–Si/	9.3 × 10−12	0.82	1.89	1.2 × 10−7	0.57	6.66	9.1 × 10−2
Cu/Co–Si/	5.9 × 10−18	1.18	1.23	1.1 × 10−7	0.57	3.04	6.6 × 10−3
Cu/Ni–Si/	1.0 × 10−20	1.34	1.30	3.4 × 10−7	0.54	3.60	8.0 × 10−6
Cu/Pd2Si/	1.4 × 10−13	0.92	1.59	1.6 × 10−7	0.56	4.65	2.7 × 10-3
Cu/Ir–Si/	3.6 × 10−12	0.84	1.43	8.8 × 10−7	0.52	3.91	3.0 × 10−2
Cu/Ti–Si/	2.5 × 10−17	1.14	1.67	8.9 × 10−8	0.58	2.76	4.2 × 10−5
Cu/Pt–Si/	6.3 × 10−12	0.83	1.71	9.0 × 10−7	0.52	4.54	3.9 × 10−3
Au/Ni/	3.0 × 10−13	0.90	1.56	2.5 × 10−7	0.55	5.01	4.0 × 10−4

. The barrier heights, $\mathsf{\Phi }$_B of the D1 diode in the model, relating to the M–Si/heterostructure interface, and $\mathsf{\Phi }$₂(0) relating to the AlGaN/AlN/GaN interfaces (at zero voltage), were calculated assuming the thermionic emission model. The theoretical values of the Richardson constant (32.5 A· cm⁻² · K⁻² for AlGAN and 24 A · cm⁻² · K⁻² for GaN) were used for these calculations. However, it should be noted that high ideality factors (n), which are commonly observed for AlGaN/GaN heterostructures, indicate that pure thermionic emission might not be sufficient to describe the forward conduction. The reverse current densities (I_r) measured at −10 V are also listed in Table 2.

In the literature, a broad range of leakage current values can be found for Schottky contacts to AlGaN/GaN heterostructures. Commonly, the reported reverse current density is in the range of 10⁻³ to above 10⁻² A/cm² [7,25,26,27,28,40,41]. Some results show leakage close to 10⁻⁵ A/cm² [8] or 10⁻⁶ A/cm² [42]. The value of leakage current in most of the contacts investigated in this work falls within a typical range. The exceptionally good parameters were observed for diodes with Ti–Si and Ni–Si layers. However, comparing literature data can be challenging due to differences in substrates, details of the AlGaN/GaN heterostructure, or the geometry of the gate/anode (edge-to-area ratio). In this context, comparisons made with reference to a common Au/Ni stack can be helpful. Both Ni–Si and Ti–Si contacts showed lower leakage currents than the reference Au/Ni contact. This is consistent with the results reported in [7], where a Cu/TiSi₂ Schottky contact to a similar heterostructure exhibited a better performance than an Au/Ni stack. Furthermore, the barrier extracted in this study for the Ti–Si-based contact fabricated without PGA, equal to 1.09 eV, is in very good agreement with the value 1.07 eV reported in [7]. The remaining five Cu/M–Si contacts exhibited higher leakage currents than Au/Ni with the highest values observed for Ta–Si.

Differences in the forward I–V curves can also be noticed within the D2 voltage range. Various slopes of of the curves are visible, as evidenced by significant differences in n₂ values listed in Table 2. According to the two-diodes model (Figure 2), the current flow in this range is dictated by the properties of the AlGaN/AlN-spacer/GaN interfaces. Chen et al. [38] experimentally demonstrated that D2 range depends on the thickness of the AlN spacer layer. One could speculate that variations in the microstructural properties of the AlN interlayer are responsible for the observed differences. However, in this work, significant variations in the heterostructure are not expected, since all devices were fabricated using samples from the same wafer. Another possible origin of the observed differences is proposed at the end of this section. On the other hand, the range of observed values of $\mathsf{\Phi }$₂(0) (0.52–0.58 eV) is relatively narrow, as expected. Presumably, the observed differences can be explained by the inhomogeneities of the wafer.

In Figure 4, the work functions measured by the IPS method (Table 1) are compared with the Schottky barrier heights determined by fitting the model to the experimental I–V curves. The Schottky barrier heights were determined for the diodes fabricated under various PGA conditions. As already mentioned, the impact of PGA on the electrical properties of the diodes varied depending on the silicide applied. The solid lines plotted in the figure describe the expected dependence of the barrier height on the work function according to the Schottky–Mott rule for GaN and Al_0.25Ga_0.75N, assuming electron affinity values from the literature [43]. However, no clear relationship was observed between the experimental values. It can be concluded that the barrier height is mainly affected by the details of the technological process, such as the PGA conditions, and not by the work function. Moreover, it can be noticed that the measured barrier heights are comparable to the CNL (Charge Neutrality Level) for GaN [44], which is marked by the dashed line in Figure 4. According to the DIGS (Disorder Induced Gap States) model [44], the interface states above the CNL are acceptor-like and the states below the CNL are donor-like. The CNL may cause pinning of the Fermi level, making the Schottky barrier height independent of the metal work function. Schottky barrier formation is discussed later in this article.

To test the thermal stability, selected samples with diodes were subjected to subsequent annealing processes in vacuum, at incremental temperatures ranging from 500 °C to 900 °C. Diodes with Co–Si or Ta–Si layers were excluded from the tests because of the relatively weak performance of the as-prepared devices. Namely, the barrier height in the Co–Si diodes dropped significantly owing to the application of PGA, even when a temperature as low as 400 °C was applied during preparation (Figure 4). The Ta–Si devices were characterized by high leakage currents (2.6 × 10⁻¹ A/cm² in the diode without PGA), which were the highest regardless of the PGA applied during preparation (Figure 3b). The devices selected for the tests are indicated on the horizontal axes of Figure 5 by descriptions of the materials applied in the anodes. The good resilience of the devices to high temperatures forced the use of high temperatures to observe temperature-related changes within an acceptable time. Each annealing process lasted 6 h, except for annealing at 900 °C, which lasted for 3 h. After each annealing, the I–V characteristics were measured using the same selected devices. The diodes were subjected to subsequent annealing steps either until a temperature of 900 °C was reached, or the parameters of the tested devices significantly deteriorated. The results are summarized in Figure 5a (leakage currents measured at −10 V) and Figure 5b (barrier heights). The arrangements of the data on the horizontal axes in Figure 5a,b are identical and correspond to the maximum leakage current observed at any stage of the test. The diodes with the highest (worst) leakage current values are placed on the left side.

As shown in Figure 5a, the reference diode with a Cu anode was characterized by the highest leakage, which increased significantly after annealing at 700 °C. Because of the high leakage current, the diode was not subjected to further annealing steps. The next reference diode, that is, the one with Au/Ni anode, had a relatively low leakage current before annealing. However, during the thermal tests, the current increased by approximately two orders of magnitude, placing the Au/Ni diode close to the Cu diode in Figure 5. After completing the tests, all the tested diodes with a silicide layer were characterized by lower (better) leakage currents than those of the reference Au/Ni and Cu diodes. The lowest leakage currents before annealing were observed for Cu/Ti–Si and Cu/Ni–Si (fabricated without PGA). The Ni–Si diode fabricated without PGA had the highest Schottky barrier during all stages of the test (Figure 5b). Despite the significant relative differences in the values measured on this diode after the subsequent stages, the final leakage current was the lowest compared with the other structures (Figure 5a). The smallest relative differences between the measured values were observed for the Pd₂Si diodes. The exceptional thermal stability of Pd₂Si diodes was discussed in [14]. As shown in Figure 5, the Pt–Si diode also exhibited small relative differences in the extracted parameters.

Figure 6 combines all the measurements discussed in this study to display the ideality factors and leakage currents vs. barrier heights. The ideality factors (Figure 6a) oscillate in a wide range, and no clear relationship with the barrier height can be observed. The reverse current (measured at −10 V) exhibited a declining trend with increasing barrier height when displayed on a semi-logarithmic plot (Figure 6b). However, the scatter of the values is considerably large. The leakage currents can differ by a few orders of magnitude for diodes with similar barrier heights. Various mechanisms can contribute to the reverse current in Schottky contacts to AlGaN/GaN heterostructures [45,46], but the leakage is usually linked to some type of defects. Therefore, the broad range of measured values indicates complex interfacial phenomena, leading to variable densities of defects and electronic states near the interface.

An important factor that can influence electrical conduction is related to extended defects, which are typically introduced during epitaxial growth in lattice-mismatched systems [47,48]. The presence of threading dislocations in heteroepitaxial structures causes a local lowering of the Schottky barrier and may result in the formation of preferential current conduction paths [49]. This is particularly important for the generation of leakage current or the presence of electrically active states in the band gap. In the case of the structures investigated in this study, the effects of Schottky barrier inhomogeneity on forward conduction were observed at lowered temperatures. Forward I–V measurements performed at various temperatures for Cu/Pd₂Si contacts have shown that the effect of inhomogeneities becomes significant only below room temperature [29]. Furthermore, all investigated devices were fabricated on samples cut from the same wafer, so similar densities of extended defects are expected.

The following model is proposed to describe the complex phenomena leading to the formation of a Schottky barrier in the investigated diodes. As already pointed out, the Schottky barrier heights in the investigated diodes are not dependent on the work function of the M–Si layer. This observation can be explained by pinning of the Fermi level. According to the DIGS model [44], the atomic disorder at the metal/(Al)GaN interface introduces a continuous distribution of states energetically located in the band gap. Pinning occurs at the CNL, that is, at the energy level that separates the acceptor-like and donor-like DIGS. However, this does not explain the broad range of barrier heights observed in this study (Figure 4 and Figure 5b) and additional phenomena should be considered.

A schematic of the proposed explanation is presented in Figure 7. The figure shows two band diagrams, where the effective barrier for electrons in Figure 7a is higher than that in Figure 7b. The densities of the band gap states (n_s), which are spatially located at the M–Si/GaN-cap interface, are shown in the insets of Figure 7a,b. Beside the DIGS, discrete donor states related to nitrogen vacancies and their complexes are commonly observed in GaN [50,51,52,53,54]. Unlike the deeper, donor-like DIGS, these donor states are ionized and are represented by red lines in the insets of Figure 7a,b. The model assumes that the pinning of the Fermi level (green, dashed lines) can change its position on the energy scale (vertical axis), depending on the ratio of the density of ionized donor states to the density of the DIGS. When the densities of DIGS are relatively high (Figure 7a), the Fermi level is pinned close to the original CNL because only a small shift of the Fermi level toward the acceptor-like states is sufficient to maintain charge neutrality. The acceptor-like states below the Fermi level become ionized (marked in red in the insets of Figure 7) and compensate for the charge related to the ionized donor states. When the DIGS densities are relatively low compared with the ionized donor states (Figure 7b), a larger Fermi level shift toward an acceptor-like DIGS is necessary to compensate for the positive charge. Thus, the barrier Φ_B in Figure 7b is lower than that in Figure 7a.

Assuming that Fermi level pinning is caused by the electronic states at the interface with the GaN cap, the barrier $\mathsf{\Phi }$_B in Figure 7 should be larger than the GaN/AlGaN conduction-band offset, that is, larger than (according to Anderson’s rule), the difference between the electron affinity of GaN and Al_0.25Ga_0.75N (approximately 0.73 eV [43]). However, in a few cases in this study, the observed barrier heights were lower than 0.73 eV (Figure 4). The lowest barrier height was equal to 0.67 eV and was observed for the as-prepared diode with Cu/Ta–Si anode, fabricated without PGA. Therefore, unless the actual band offset is distinctly smaller than assumed (which is also possible [55]), the forward conduction process likely involves tunneling through the AlGaN barrier. The assumption of tunneling aligns with the conclusions drawn from the discussion of forward and reverse currents in Cu/Pd₂Si diodes, as presented in [29]. This is further supported by the observed ideality factors, which are significantly higher than 1 (Figure 6a), indicating mechanisms other than the pure thermionic emission. Tunneling through AlGaN can be explained using Thermionic Field Emission (TFE) and Thin Surface Barrier (TSB) models [44,56]. In the discussed case, the AlGaN layer is covered with a thin GaN capping layer. Because the GaN-cap/AlGaN interface is epitaxial, the DIGS are not expected to occur. Therefore, the positive charges related to the donor states, spatially located in the vicinity of the Gan-cap/AlGaN interface, are not compensated. According to the TSB model [44,56], positive charges near the surface produce thin-surface-barrier regions. This is schematically shown in Figure 7a,b, where the original conduction band edge for AlGaN is depicted by the dashed black lines. The unintentional donor states are likely introduced during device processing [56]. This assumptions is supported by the results and discussion on the effects of PGA annealing on Cu/Pd₂Si diodes presented in [29]. The thinned barrier allows the TFE to contribute to the conduction mechanism. Consequently, the measured effective barrier height ($\mathsf{\Phi }$_{B eff.} in Figure 7) is lower than the actual barrier height $\mathsf{\Phi }$_B.

The model explains the complex behavior of the investigated diodes. According to the model, the barrier height is independent of the work function, which agrees with the experimental results. It is determined by the density of unintentional donor states and the relative density of the DIGS at the M–Si/GaN-cap interface. Depending on the applied M–Si layer, various atomic arrangements are formed at the interface, which affects the DIGS. This could explain why diodes fabricated with the same technological procedure, but with various metal silicides, can reveal different barrier heights. It can also be expected that the fabrication details (surface preparation, sputtering, PGA, etc.) affect both the atomic ordering at the interface (and therefore, the DIGS) and the distribution of unintentional donor defects near the surface of the heterostructure. Hence, various barrier heights were obtained for a given M–Si layer (Figure 4). Similarly, the effect of annealing can differ depending on the M–Si layer and the fabrication details of the device.

Based on the model, it is also possible to speculate on the cause of the various slopes in I–V curves observed in the D2 voltage range (Figure 3). The insets in Figure 2 illustrate electron transport in D1 and D2 voltage regimes assuming tunneling through AlN and pure thermionic emission over the AlGaN barrier. According to the model from Figure 7, the latter assumption is not valid. Instead, the electrons will tunnel through the AlGaN barrier in TSB regions for both D1 and D2 voltage ranges. Therefore, the current flow in the D2 range is also affected by the density of unintentional donors near the GaN-cap/AlGaN interface. Assuming a thermionic field emission process through a TSB, the ideality factor should increase with the density of unintentional donors [44]. Thus, it can be implied that the different slopes in the D2 range (n₂) may result from various densities of electrically active defects near the GaN-cap/AlGaN interface. As mentioned before, high densities of unintentional donors should result in a TSB and a lowering of the measured barrier ($\mathsf{\Phi }$_B in Table 2). Therefore, in general, high values of n₂ should be accompanied by relatively low Φ_B. This is supported by the values listed in Table 2. For the diodes with n₂ in the range 3.91–6.66, relatively low effective barriers (<1 eV) were observed, while for the diodes with n₂ in the range 2.76–3.6, higher barriers (>1 eV) were extracted.

The question remains: what could be the source of different defect densities near the GaN-cap/AlGaN interface in devices differing only in the applied M–Si layer? As suggested in [56], during the deposition of a layer, the bombardment of the surface by atoms may produce defects, such as nitrogen vacancies, that can be responsible for the formation of a TSB. On the other hand, the energies of sputtered atoms depend on various factors, including atom mass and surface binding energy. The simulations reported in [57] have shown that the energies of atoms sputtered from single-element materials vary depending on the position of the element in the periodic table, including the group and period. Thus, it is expected that the energies of atoms sputtered from various metal silicide targets will differ, resulting in different densities and depth distributions of defects generated in the near-surface regions of the heterostructure, including the GaN-cap/AlGaN interface. This could explain the various n₂ values observed in this study.

4. Summary and Conclusions

The Schottky barrier heights in the planar diodes with Cu/M–Si/heterostructure contacts did not depend on the M–Si layer work function. The barriers were strongly dependent on the parameters of the fabrication process and on the choice of metal silicide. The highest Schottky barriers were obtained for the diodes with Cu/Ni–Si (up to 1.34 eV) and Cu/Ti–Si (up to 1.14 eV) anodes. These diodes also exhibited lower leakage currents than the reference Au/Ni diode. The diodes with Cu/Co–Si anodes exhibited high barriers, but with considerably high leakage currents, and were susceptible to annealing. Their electrical performance deteriorated when annealing above 300 °C was applied during fabrication.

During the thermal stability tests, the barrier height of the diode containing Ni–Si gradually worsened after each annealing, but were always better than those in all other measured devices (including the as-prepared diodes) even after the final annealing at 900 °C. The diodes with Pd–Si or Pt–Si layers exhibited exceptionally small relative differences in the extracted parameters measured after subsequent annealing steps. After completion of the tests, all tested diodes with M–Si layers (Ni–Si, Pd–Si, Ir–Si, Ti–Si, or Pt–Si) had lower leakage currents than the reference Au/Ni diode.

The mechanism for Schottky barrier formation was proposed to explain the complex behavior of the investigated diodes. The mechanism is based on the unified DIGS and TSB models [44] and assumes the pinning of the Fermi level at the M–Si/GaN-cap interface. It also incorporates a pinning shift that depends on the ratio of the donor to acceptor-like band gap states densities.

It can be concluded that Au-free Schottky contacts based on specific M–Si layers exhibit the performance that is very promising for applications in GaN-on-Si HEMTs. The thermal stability of the diodes with Cu/M–Si anode stack was greatly improved compared to that of the devices with the single-layer Cu contact. The parameters of some metal–silicide-based devices exceeded those of the reference Au/Ni Schottky diode. Optimizing the stoichiometry and fabrication processes of specific M–Si layers could lead to further improvements.