Flying Capacitor Double Dual Boost DC-DC Converter

Abstract

This article presents a detailed analysis of a previously introduced boost converter based on cascaded capacitor connections. The analyzed converter maintains the same voltage gain as its conventional double-boost converter counterpart. The main advantage of the redesigned converter is that it requires smaller capacitors, rated to a lower voltage, due to the cascaded connection. This makes it suitable for various applications, including distributed generation and microgrids. This paper conducts the mathematical modeling of the converter with large signal models and the equilibrium operation in continuous conduction mode, employed to implement a control scheme. Even though the individual capacitor voltage ripple reaches high values, for voltage gains above five, the output voltage ripple is lower compared with that of other converters. The analysis also includes a comparative study with the conventional double dual boost converter. Simulations assess the proposed topology’s ability to effectively minimize the switching ripple in the output voltage, even with smaller capacitors. Finally, experimental results are also provided to confirm the functionality of the proposed converters under various operational conditions, which confirm its suitability for low-voltage generator applications.

1. Introduction

The surge in global energy demand has spurred numerous countries to champion the research and development of renewable and clean energy sources. These sources, often referred to as clean energy, include solar, wind, and hydroelectric power. The widespread adoption of these energy forms has notably accelerated the growth of solar energy, which is abundant across the planet [1,2]. The advances and progress in photovoltaic energy technology have made electricity from photovoltaic cells very profitable and, at the same time, very practical [3,4]. Recent advancements in photovoltaic technology have reduced the cost of PV systems, making them practical for real applications. Consequently, numerous nations are committed to producing and utilizing photovoltaic energy by developing solar fields. Recent advances and innovations in photovoltaic technology have led to cost reductions and efficiency improvements, fueling a global shift towards solar energy [5,6].

Normally, photovoltaic systems are integrated into the electrical grid through a coupling system, such as a DC-DC converter for the purpose of regulating and conditioning the voltage generated by the photovoltaic system [1,7].

In PV systems, a challenge is that the energy is generated at low voltage, necessitating components capable of elevating the voltage to usable levels. To address this, photovoltaic systems often use a power-electronics-based converter capable of stepping up the voltage. Power converters, such as boost converters, are essential for this purpose, as they are designed to significantly increase voltage levels.

This paper focuses on the analysis of an existing double boost power converter [8], which is based on the original idea of the converter proposed in [9,10]. Such a converter is used to equalize the capacitor voltages by employing a series-connected transistor, while simultaneously achieving boosting capability. However, in the analyzed structure, the capacitor voltages are added to the voltage source, contributing to the output voltage.

In low-voltage generation within the field of renewable energy, PECs are designed to maximize power extraction, offering a broad spectrum of output voltages at the highest possible efficiency. Desired voltage gains are often achieved using hybrid or cascaded topologies, which address the limitations of conventional boost topology, particularly in voltage amplification. Notably, quadratic-type boost converters stand out among these topologies for their ability to achieve high voltage gains while potentially minimizing or eliminating the switching ripple at the input port. Usually, the current from the renewable source is extracted with low or null ripple [11,12]. Similarly, employing specific strategies can result in minimal or no voltage ripple for a series of cascade-connected capacitors [13]. Additionally, reducing the rated voltage of capacitors can decrease their physical size, as the size of a capacitor is proportional to the energy stored in its dielectric.

Compared with recent advancements in traditional boost converter topologies, quadratic or other cascaded topologies offer a significantly broader range of voltage conversions [14,15]. In the Double Inductor Quadratic Boost (DIQB) topology [16], a coupled inductor is utilized to augment the voltage gain further. Additionally, steady-state analysis indicates that this quadratic boost topology achieves a higher voltage ratio than traditional quadratic and cascaded boost topologies, with the same voltage rating on the transistor. Consequently, an efficiency analysis suggests that the most effective converter is the double-cascaded boost converter. A double inductor quadratic topology with enhanced efficiency could be further explored. Nonetheless, the use of a single transistor, as seen in the DIQB topology, remains appealing due to its substantial voltage gain despite a potential slight reduction in efficiency. The double dual (DD) boost topology [17,18] is akin to the interleaving boost topology in that the power is distributed across two (or more) switching stages.

This paper focuses on the analysis of a power electronics converter, which is a modified version of the double dual boost converter and capacitor voltage balancer, herein referred to as the flying capacitor double dual (FCDD) boost converter. The resulting converter [8] maintains the same voltage gain and current ratios as the traditional DDB topology. Nonetheless, the mathematical modeling and modulation strategy allow for quantifying the output voltage ripple, which in turn reduces the required capacitance. Additionally, a hybrid closed-loop scheme is proposed, where the controller is implemented using operational amplifiers, followed by a microcontroller (MCU) that generates the PWM pattern. Simulation of the converter in steady-state illustrates the cancellation of voltage ripple at the output side when small capacitances are used. The output voltage regulation capability is tested under varying output currents to validate the proposed control scheme. This document outlines the converter mathematical modeling by using the standard averaging technique, including the steady-state or equilibrium operation in continuous conduction mode (CCM). Additionally, it details a design methodology that involves selecting appropriate capacitors and inductors, along with their maximum voltage and current values, using a specific application example. A comparative analysis between the proposed converter and the traditional DDB topology is also conducted. Ultimately, experimental results are included to validate the functionality of the proposed converters under various operating conditions.

2. The Proposed Converter

Figure 1 illustrates the proposed converter, consisting of two symmetrical switching cells, each configured as a boost converter. Unlike in a traditional boost topology, in each switching cell, the negative side of the capacitor is linked to the positive side of the input power source. The direction of current flow and voltage polarities adhere to the conventions used for passive components. The transistors ($S_1$ and $S_2$) are regulated by their respective switching function, $q_1\left(t\right)$ and $q_2\left(t\right)$. These signals share the same duty ratio but are phased 180 degrees apart, a configuration similar to that used in interleaved converters [19].

Different Switching States

Given the presence of two switching signals, four switching states or equivalent circuits can be derived from the combinations of the switching signal states, which represent the states of the switches. These switching states or equivalent circuits are shown in Figure 2. Depending on the sequence employed, the switching strategy can be categorized into three types: (i) independent, where the switching signals operate asynchronously with varying duty cycles; (ii) synchronous, where the switching signal for each switch is identical; and (iii) interleaved, also called counter phase, where the firing signals have equal duty ratio but are active at the start and end of the switching period. The latter strategy is utilized in the proposed design.

In the strategy outlined, the switching period starts and concludes with ST1 (active CELL 1). The switching signals are aligned around the peak of the triangular waveform used in the PWM, as illustrated in Figure 3, positioning the switching state ST2 at the midpoint of the switching period. Hence, ST2 initiates at $t=0.5d_1{T}_{\mathrm{s}}$ seconds and concludes at t = $(1-0.5d_1)T_{\mathrm{s}}$ seconds. In Figure 3a, the duty cycle value is $50<d<100\%$, whereas in Figure 3b, it is $50<d<100\%$.

The nature of the second switching state is determined by the duty cycle value: for values below 50%, the state is ST0, referred to as “dead time”, during which both inductors discharge; for values above 50%, the state becomes ST3, known as “overlapping”, where both inductors charge.

Table 1. Possible commutations states.

State/Figure	${\mathit{q}}_1\left(\mathit{t}\right)$	${\mathit{q}}_2\left(\mathit{t}\right)$	Type
ST1/Figure 2a	0	0	dead time
ST2/Figure 2b	1	0	active CELL 1
ST3/Figure 2c	0	1	active CELL 2
ST4/Figure 2d	1	1	overlapping

encapsulates these switching states.

3. Mathematical Model of the Converter

Utilizing the circuit description and the equivalent states shown in Figure 2, averaging equations are formulated to develop the converter mathematical model [20]. In the case of both inductors, when their respective transistor is closed ($0<t<d{T}_{\mathrm{s}}$), their voltage is the voltage at the input side. During the remaining portion of the switching time ($d{T}_{\mathrm{s}}<t<T_{\mathrm{s}}$), the voltage equals that of the corresponding capacitor. Likewise, for capacitors, when their respective transistor is closed, each capacitor supplies the load current, resulting in a voltage reduction. Nevertheless, during the interval [($1-d)T_{\mathrm{s}}$], each capacitor is recharged by the currents from its inductors, and the voltages across the capacitors are described as shown in (1)–(4).

$$\begin{array}{cc}\hfill L_1{\displaystyle \frac{d{i}_{\mathrm{L}1}}{dt}}& =v_{\mathrm{d}}\left(d\right)+(-v_{\mathrm{C}1})\left(1-d\right),\end{array}$$

(1)

$$\begin{array}{cc}\hfill L_2{\displaystyle \frac{d{i}_{\mathrm{L}2}}{dt}}& =-v_{\mathrm{C}2}\left(d\right)+\left(v_{\mathrm{d}}\right)\left(1-d\right),\end{array}$$

(2)

$$\begin{array}{cc}\hfill C_1{\displaystyle \frac{d{v}_{\mathrm{C}1}}{dt}}& =(i_{\mathrm{L}1}-i_{\mathrm{o}})\left(d\right)+\left(i_{\mathrm{L}1}-{\displaystyle \frac{v_{\mathrm{o}}}{R}}\right)\left(1-d\right),\end{array}$$

(3)

$$\begin{array}{cc}\hfill C_2{\displaystyle \frac{d{v}_{\mathrm{C}2}}{dt}}& =i_{\mathrm{L}2}-{\displaystyle \frac{v_{\mathrm{o}}}{R}}\left(d\right)-{\displaystyle \frac{v_{\mathrm{o}}}{R}}\left(1-d\right)\end{array}$$

(4)

The current at the output ($i_{\mathrm{o}}$) can be straightforwardly determined by taking into account the voltage at the output port and the load resistance, calculated as $i_{\mathrm{o}}=v_{\mathrm{o}}/R$. It is important to note that the voltage at the output port is determined by applying Kirchhoff’s voltage law to the circuit topology in Figure 1, as indicated by Equation (5).

$$v_{\mathrm{o}}=v_{\mathrm{d}}+v_{\mathrm{C}1}+v_{\mathrm{C}2}.$$

(5)

3.1. Steady State Analysis

The steady-state or equilibrium operation of the converter can be derived by setting the derivatives in Equations (1)–(4) to zero. Throughout the rest of the article, capital letters denote these steady-state values. And in a matrix o vector, T represents its transpose. The system of equations is more effectively described using its canonical form in state-space and output equations, as shown in (6) and (7). The state vector $x\left(t\right)$ represents inductor currents and capacitor voltages: $x={\left[i_{\mathrm{L}1}{i}_{\mathrm{L}2}{v}_{\mathrm{C}1}{v}_{\mathrm{C}2}\right]}^T$. It should be noted that the input variable u corresponds to the constant input voltage $v_{\mathrm{d}}$, and the output variable refers to the voltage at the output port $v_{\mathrm{o}}$.

$$\begin{array}{cc}\hfill \dot{x}& =\mathbf{A}x+\mathbf{B}u,\end{array}$$

(6)

$$\begin{array}{cc}\hfill y& =\mathbf{C}x+\mathbf{D}u.\end{array}$$

(7)

$$\begin{array}{c}\hfill \mathbf{A}=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{(1-D)}{L_1}}& 0\\ 0& 0& 0& -{\displaystyle \frac{(1-D)}{L_2}}\\ {\displaystyle \frac{(1-D)}{C_1}}& 0& -{\displaystyle \frac{1}{R{C}_1}}& -{\displaystyle \frac{1}{R{C}_1}}\\ 0& {\displaystyle \frac{(1-D)}{C_2}}& -{\displaystyle \frac{1}{R{C}_2}}& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right];\\ \hfill \mathbf{B}={\left[\begin{array}{cccc}{\displaystyle \frac{D}{L_1}}& {\displaystyle \frac{D}{L_2}}& -{\displaystyle \frac{1}{R{C}_1}}& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right]}^T\end{array}$$

(8)

$$\begin{array}{c}\hfill \mathbf{C}=\left[\begin{array}{cccc}0& 0& 1& 1\end{array}\right];\mathrm{and}\mathbf{D}=\left[\begin{array}{c}1\end{array}\right].\end{array}$$

(9)

From the system of equations provided in (6) and (7), the steady-state or equilibrium operation point can be determined by using the following approximation [21]. Let us consider the variables listed in (1)–(4), which are presented in lowercase, are not constant. This approximation is known as the small-ripple approximation (SRA) and assumes that changes in state variables over a single switching cycle are insignificantly small, a result of the high switching frequency. At steady state, the derivatives of the state variables are zero. Therefore, setting (6) equal to zero and applying the SRA results in the state variables being

$$\begin{array}{cc}\hfill I_{\mathrm{L}1}& ={\displaystyle \frac{1}{(1-D)}}{\displaystyle \frac{V_{\mathrm{o}}}{R}},\end{array}$$

(10)

$$\begin{array}{cc}\hfill I_{\mathrm{L}2}& ={\displaystyle \frac{1}{(1-D)}}{\displaystyle \frac{V_{\mathrm{o}}}{R}},\end{array}$$

(11)

$$\begin{array}{cc}\hfill V_{\mathrm{C}1}& ={\displaystyle \frac{D}{(1-D)}}{V}_{\mathrm{d}},\end{array}$$

(12)

$$\begin{array}{cc}\hfill V_{\mathrm{C}2}& ={\displaystyle \frac{D}{(1-D)}}{V}_{\mathrm{d}}.\end{array}$$

(13)

DC values derived using the SRA are represented by capital letters. Following this and based on Equation (5), the DC voltage at the output port is indicated as

$$V_{\mathrm{o}}=V_{\mathrm{d}}\left({\displaystyle \frac{1+D}{1-D}}\right).$$

(14)

This denotes the converter’s voltage gain.

3.2. Small-Signal Mathematical Model

From the large signal model shown in (1)–(4), the small-signal model using the conventional approach suggested by Erickson [20] can be applied, which involves representing variables as a combination of their equilibrium components (DC) and their variable components (AC). This approach is concisely outlined in (15).

$$\begin{array}{c}\hfill \left\{\begin{array}{cc}{i}_{\mathrm{L}1}=I_{\mathrm{L}1}+{\tilde{i}}_{\mathrm{L}1},& i_{\mathrm{L}2}=I_{\mathrm{L}2}+{\tilde{i}}_{\mathrm{L}2},\\ v_{\mathrm{C}1}=V_{\mathrm{C}1}+{\tilde{v}}_{\mathrm{C}1},& v_{\mathrm{C}2}=V_{\mathrm{C}2}+{\tilde{v}}_{\mathrm{C}2},\\ v_{\mathrm{d}}=V_{\mathrm{d}}+{\tilde{v}}_{\mathrm{d}},& d=D+\tilde{d}.\end{array}\right\}\end{array}$$

(15)

Replacing each variable with its corresponding equivalent from (15) in the set (1)–(4) transforms them into expressions that include derivatives of both AC and DC quantities, as well as combinations of AC and DC product terms. For example, (1) is expanded when substituted with the appropriate values from (15), yielding

$$L_1{\displaystyle \frac{d}{dt}}\left(I_{\mathrm{L}1}+{\tilde{i}}_{\mathrm{L}1}\right)=\left(D+\tilde{d}\right)\left[V_{\mathrm{d}}+{\tilde{v}}_{\mathrm{d}}\right]-\left[\left(1-D\right)-\tilde{d}\right](V_{\mathrm{C}1}+{\tilde{v}}_{\mathrm{C}1}).$$

(16)

Expanding (16) leads to (17).

$$\begin{array}{c}{L}_1{\displaystyle \frac{d}{dt}}{I}_{\mathrm{L}1}+L_1{\displaystyle \frac{d}{dt}}{\tilde{i}}_{\mathrm{L}1}=D{V}_{\mathrm{d}}+D{\tilde{v}}_{\mathrm{d}}+V_{\mathrm{d}}\tilde{d}+\tilde{d}{\tilde{v}}_{\mathrm{d}}\hfill \\ \hfill -(1-D)V_{\mathrm{C}1}-(1-D){\tilde{v}}_{\mathrm{C}1}+V_{\mathrm{C}1}\tilde{d}+\tilde{d}{\tilde{v}}_{\mathrm{C}1}.\end{array}$$

(17)

Considering the derivative of a DC value like $I_{\mathrm{L}1}$ is zero, and also considering from (10) that $V_{\mathrm{d}}D$ equals $V_{\mathrm{C}1}(1-D)$, (17) along with the subsequent expressions, after making the necessary substitutions, can be reformulated as follows:

$$\begin{array}{c}\hfill L_1{\displaystyle \frac{d{\tilde{i}}_{\mathrm{L}1}}{dt}}=-\left(1-D\right){\tilde{v}}_{\mathrm{C}1}+\left(V_{\mathrm{d}}+V_{\mathrm{C}1}\right)\tilde{d}+D{\tilde{v}}_{\mathrm{d}},\end{array}$$

(18)

$$\begin{array}{c}\hfill L_2{\displaystyle \frac{d{\tilde{i}}_{\mathrm{L}2}}{dt}}=-\left(1-D\right){\tilde{v}}_{\mathrm{C}2}+\left(V_{\mathrm{d}}+V_{\mathrm{C}2}\right)\tilde{d}+D{\tilde{v}}_{\mathrm{d}},\end{array}$$

(19)

$$\begin{array}{c}\hfill C_1{\displaystyle \frac{d{\tilde{v}}_{\mathrm{C}1}}{dt}}=\left(1-D\right){\tilde{i}}_{\mathrm{L}1}-{\displaystyle \frac{{\tilde{v}}_{\mathrm{C}1}+{\tilde{v}}_{\mathrm{C}2}+{\tilde{v}}_{\mathrm{d}}}{R}}-I_{\mathrm{L}1}\tilde{d},\end{array}$$

(20)

$$\begin{array}{c}\hfill C_2{\displaystyle \frac{d{\tilde{v}}_{\mathrm{C}2}}{dt}}=\left(1-D\right){\tilde{i}}_{\mathrm{L}2}-{\displaystyle \frac{{\tilde{v}}_{\mathrm{C}1}+{\tilde{v}}_{\mathrm{C}2}+{\tilde{v}}_{\mathrm{d}}}{R}}-I_{\mathrm{L}2}\tilde{d}.\end{array}$$

(21)

The series of equations from (18)–(21) constitutes a linear mathematical model that can be written in the canonical form akin to Equations (6) and (7). In this reformulation, the matrix $\mathbf{A}$ retains its value, but now $x={\left[{\tilde{i}}_{\mathrm{L}1}{\tilde{i}}_{\mathrm{L}2}{\tilde{v}}_{\mathrm{C}1}{\tilde{v}}_{\mathrm{C}2}\right]}^T$, $\mathbf{u}={\left[{\tilde{v}}_{\mathrm{d}}\tilde{d}\right]}^T$ and

$$\begin{array}{c}\hfill \mathbf{B}=\left[\begin{array}{cc}{\displaystyle \frac{(V_{\mathrm{d}}+V_{\mathrm{C}1})}{L_1}}& {\displaystyle \frac{D}{L_1}}\\ {\displaystyle \frac{(V_{\mathrm{d}}+V_{\mathrm{C}2})}{L_2}}& {\displaystyle \frac{D}{L_2}}\\ -{\displaystyle \frac{I_{\mathrm{L}1}}{C_1}}& -{\displaystyle \frac{1}{C_{1}R}}\\ -{\displaystyle \frac{I_{\mathrm{L}2}}{C_2}}& -{\displaystyle \frac{1}{C_{2}R}}\end{array}\right];\mathrm{and}\mathbf{D}=\left[\begin{array}{cc}0& 1\end{array}\right].\end{array}$$

(22)

4. Passive Components Selection

This section explores the choice of reactive components dictated by the permissible maximum ripple for the state variables. Inductors $L_1$ and $L_2$ exhibit the typical current waveform seen in switched-mode power supplies, consisting of a DC component with an AC triangular fluctuation. The DC value is influenced by the duty ratio (or the voltage gain) and the load, as detailed in Equations (10) and (11).

The inductance is chosen based on the desired ripple in the following manner: as depicted in Figure 2, when the switch $S_1$ is active, the inductor voltage equals $V_{\mathrm{d}}$, causing its current to increase at a rate of ($V_{\mathrm{d}}/L_1$). This condition persists for a duration of ($D{T}_{\mathrm{s}}$), allowing for the peak-to-peak ripple to be quantified. Consequently, the inductor’s value can be determined using (23).

$$\Delta i_{\mathrm{L}1}={\displaystyle \frac{V_{\mathrm{d}}}{L_1}}D{T}_{\mathrm{s}}\Rightarrow L_1={\displaystyle \frac{V_{\mathrm{d}}}{\Delta i_{L1}}}D{T}_{\mathrm{s}}.$$

(23)

It should be noted that the SRA is applied in (23) and in all equations used for sizing reactive components. Utilizing Equation (23) facilitates the selection of $L_1$ based on a specified current ripple. When both switching stages operate with identical duty cycles, Equation (23) can also be employed to compute $L_2$, effectively allowing for $L_1$ and $L_2$ to be equal.

Capacitors $C_1$ and $C_2$: The calculation of capacitors follows a method akin to that used for inductors. The capacitor voltage comprises a DC component as well as an AC fluctuation, where the DC value is influenced by the duty ratio (or voltage gain) and the voltage at the input port.

The capacitance selection is based on the desired ripple, as outlined with the help of Figure 4: when transistor $S_1$ is closed during $d_1{T}_{\mathrm{s}}$ seconds, the current flowing through capacitor $C_1$ equals the negative of the output current, as seen in Figure 4. The negative sign in (24) indicates a decrease in voltage as the capacitor discharges. As a result, the voltage decreases at a rate of ($-I_{\mathrm{o}}/C_1$). This rate of change is marked as $m_{{\mathrm{C}}_1}$ and $m_{{\mathrm{C}}_2}$, for capacitor $C_1$ and $C_2$, respectively.

In steady-state operation, this condition persists throughout the duration $D{T}_{\mathrm{s}}$, during which the voltage reduction is calculated and presented in (24).

$$-\Delta v_{\mathrm{C}1}=-{\displaystyle \frac{I_{\mathrm{o}}}{C_1}}D{T}_{\mathrm{s}}\Rightarrow C_1={\displaystyle \frac{I_{\mathrm{o}}}{\Delta v_{C1}}}D{T}_{\mathrm{s}}.$$

(24)

Negative signs are indicative of a voltage reduction. Capacitor $C_1$ should be chosen to achieve the specified voltage ripple, $\Delta v_{\mathrm{C}1}$. Utilizing (24) enables the selection of $C_1$ to meet the targeted voltage ripple. Additionally, if both stages operate at the same voltage gain, it is practical to equalize $C_1$ and $C_2$.

Since the same duty cycle is applied to each power cell, both capacitors reach the same average and ripple voltage. Besides, given the series connection of the capacitors along with the power source and the complementary operation due to the commutation strategy, their triangular waveforms are in counterphase, this can be seen graphically in Figure 4. However, the total ripple voltage cancelation is only possible when the positive and negative are equal which occurs when $d_{(1,2)}=50$%. For a different value ($d_{(1,2)}>50$%), the output voltage ripple ($\Delta v_{\mathrm{o}}$) can be computed using the signals illustrated in the figure. The positive ($\widehat{\mathsf{\Delta }{v}_{\mathrm{o}}}$) and negative ($-\widehat{\mathsf{\Delta }{v}_{\mathrm{o}}}$) peak values of $\Delta v_{\mathrm{o}}$ coincide with the peak values of $\Delta v_{\mathrm{C}1}$ and $\Delta v_{\mathrm{C}2}$, respectively, denoted by (25). By identifying the symmetry of the ripple signals centered around the average value, (26) can be also written.

$$\begin{array}{cc}\hfill \widehat{\mathsf{\Delta }{v}_{\mathrm{o}}}& =\widehat{\mathsf{\Delta }{v}_{C_1}}-h,\end{array}$$

(25)

$$\begin{array}{cc}\hfill \widehat{\mathsf{\Delta }{v}_{\mathrm{o}}}& ={\displaystyle \frac{1}{2}}\mathsf{\Delta }{v}_{C_1}-h.\end{array}$$

(26)

Now, the problem is reduced to solve for the vertical side of the triangle $T_{\mathrm{bh}}$. This is performed by using simple trigonometry and considering the similar triangle $T_{\mathrm{BH}}$, resulting in the output voltage ripple calculation (27).

$$\mathsf{\Delta }{v}_{\mathrm{o}}={\displaystyle \frac{\mathsf{\Delta }{v}_{{\mathrm{C}}_1}(2·D-1)}{D}}.$$

(27)

Evidently, (27) also holds for the entire range of duty cycle, including the particular case when $d_{(1,2)}=50$%, which yields $\mathsf{\Delta }{v}_{\mathrm{o}}=0$.

Comparison with Other Power Converters

With the development of mathematical expressions for quantifying the various parameters, a comparison with other power converters was carried out. The parameter values employed in the evaluation are listed in

Table 2. Parameters employed in the numerical validation.

Notation	Parameter	Value
$v_{\mathrm{d}}$	Input voltage	12 V
$v_{\mathrm{o}}$	Output voltage	83 V
$f_{\mathrm{s}}$	Switching frequency	50 kHz
$P_{\mathrm{o}}$	Throughput power	100 W
$L_1=L_2$	Inductors	220 µH
$C_1$	Capacitor 1	10 µF
$C_2$	Capacitor 2	10 µF

.

Figure 5 illustrates the theoretical voltage gains for various standard power converters: (i) the traditional boost topology, (ii) the traditional single switch quadratic boost topology, and (iii) the proposed topology. Notably, the traditional single-switch quadratic boost topology achieves a larger gain for duty cycles above 60%, while the proposed topology demonstrates superior performance compared with the traditional boost converter.

Additionally,

Table 3. Various converters’ component comparison.

PEC	Ls	Cs	Ss	Ds	G
[22]	2	3	2	3	${\displaystyle \frac{1-D_1+D_1^2}{{(1-D_1)}^2}}$
[23]	3	3	2	2	${\displaystyle \frac{1}{D(1-D)}}$
[24]	2	2	2	2	${\displaystyle \frac{1}{{(1-D)}^2}}$
[13]	2	2	2	2	${\displaystyle \frac{D}{{(1-D)}^2}}$
Proposed	2	2	2	2	${\displaystyle \frac{1+D}{(1-D)}}$

includes the comparative data, which evaluate various notable power electronics converters (PEC) of different topologies available in the literature. The comparison considers the number of inductors (Ls), number of capacitors (Cs), number of transistors (Ss), number of diodes (Ds), and voltage gain (G).

Using (27), it is possible to conduct a detailed analysis of the various voltage ripples involved in the power converters. Figure 6 contains the evaluation results, from top to bottom: $V_{\mathrm{Cs}}$ represents the average capacitor voltages, $\Delta v_{\mathrm{Cs}}$ represents the voltage ripple of the corresponding capacitors, and $V_{\mathrm{os}}$ represents the output voltage ripple. The subscripts “a”,“b”, and “P” correspond to the quadratic buck-boost converter presented in [13], the quadratic boost converter proposed in [24], and the proposed converter, respectively.

In the proposed converter, the average capacitor voltage may be similar to that in other converters. However, the total voltage gain, as shown in Table 3, is higher for the other converters. While the individual capacitor voltage ripple in the proposed converter is not the lowest, due to the cascaded connection, with a duty cycle higher than 65%, the proposed converter achieves the lowest value, even with small capacitances.

5. Simulation Results

A series of simulations were performed using Matlab R2018b/Simulink 9.2 to evaluate the proposed strategy. The results from these simulations are displayed in Figure 7, Figure 8 and Figure 9, corresponding to the open- and closed-loop fashion. The signals illustrated are (top) the output voltage, (middle) the voltage across capacitors $C_1$ and $C_2$, and (bottom) the control signals $q_{(1,2)}$. In Figure 7a, the duty ratio on each transistor is 75%, which, according to (14), results in a voltage gain equal to seven. In this scenario, the arrangement mirrors that depicted in Figure 2a. The equivalent circuits obtained for this duty cycle value follow the sequence ST1-ST3-ST2-ST3-ST1, according to Figure 3a. With the voltage at the input $v_{\mathrm{d}}$ set at 12 V, the voltage at the output reaches an average value of approximately 84 V. It is observed that the output ripple is relatively smaller than that on the capacitors. As the ripples on the capacitors move in opposite directions, they tend to cancel each other out, although a small amount remains. A subsequent simulation involved setting a duty cycle of 25%, as depicted in Figure 7b. In this instance, the equivalent circuits obtained for this duty cycle value follow the sequence ST1-ST0-ST2-ST0-ST1, corresponding to the pattern of Figure 3b; the voltage ripples are reduced owing to the lower output current. Additionally, the voltage ripples on the capacitors exhibit the exponential segment of the waveform. Despite this, the cancellation effect becomes more pronounced. The parameters presented in Table 2 were used to validate the strategies.

Regarding the simulation validation the model presented in Figure 8 was proposed and implemented in Matlab/Simulink. The proposed model is based on a simple P+I controller scheme, which serves to verify the behavior under load and set-point variations. The proposed strategy consists of two independent P+I controllers capable of handling individually the capacitor voltage on each power cell. Note that the P+I parameters are determined using the linearized equations from (18)–(21), obtaining the gains $k_{\mathrm{P}}$ = 0.450 and $k_{\mathrm{i}}$ = 311. The performance of the scheme is carried out as follows: Each capacitor voltage is sensed and scaled by a factor $\beta$ in order to be manipulated by the controller in an actual implementation. Also, the block $\beta$ serves as an isolator to avoid malfunction due to the voltage level interactions. The set point or desired output voltage $V_{\mathrm{o}}^{★}$ is split into two identical values, each applied to the corresponding P+I controller input, which is compared with the conditioned capacitor voltage, generating an error voltage $v_{\mathrm{e}(1,2)}=V_{\mathrm{o}}^{★}/2-\beta v_{{\mathrm{C}}_{(1,2)\mathrm{med}}}$. Such an error is processed by the proportional and integral gains as shown in the figure, producing the duty cycles $d_{(1,2)}$ that are then converted to commanding signals $q_{(1,2)}$ to, in turn, control the power transistors $S_{(1,2)}$. A saturation block has been added to protect the gate drives on each transistor. Details for the actual implementation are provided in the following section.

The main purpose of the proposed controller is to track the voltage reference $V_{\mathrm{o}}^{★}$. This is evaluated under a load variation, shown in Figure 9a, where the load resistor has been changed from 200 to 150 Ω at approximately 10 ms and restored back to 200 Ω at approximately 30 ms. Note that in spite of the capacitor’s voltage oscillations, the output voltage is essentially kept constant, showing small overshoots at the beginning and the end of the disturbance. Moreover, the duty cycle values also change during the disturbance, presenting an oscillation defined by the resonance frequency of the controlled loop scheme.

Moreover, the set point is dynamically changed with the pattern 50-40-50 V occurring at the same interval, as illustrated in Figure 9b. The P+I controller can generate the duty cycles accordingly to follow the voltage reference. Also, oscillations appeared in the duty cycles and, therefore, in the capacitor voltages. However, due to the series-type arrangement of the capacitors, the voltage ripples are canceled out of each other.

In both cases, the correctness of the P+I controller is validated despite the presence of small oscillations and overshoots. In both cases, the correctness of the P+I controller is validated despite the presence of small oscillations and overshoots. The observed overshoots are approximately 1.46% and 3.4% for the load current and set-point variations, respectively.

6. Experimental Results

To substantiate the theoretical proposal, following the proposed scheme illustrated in Figure 8, a laboratory-scale prototype was constructed. More detailed information about the construction can be seen in Figure 10. More detailed information about the construction can be seen in Figure 1, while the setup of the experiment can be observed in Figure 11. The proposed power converter, identified as PEC, is fed a constant DC power source. Nonetheless, a capacitor for smoothing the voltage variation is necessary. In this case, a polyester capacitor $C_{\mathrm{d}}$ = 30 µF is employed. The P+I controllers are implemented using the operational amplifier MCP6002, from Microchip Technology Inc. supplied from Texas, U.S.A. which can be powered with a compatible voltage level as the microcontroller (MCU). Therefore, no additional conditioning is required. The 32-bit LAUNCHXL-F28027 MCU, from Texas Instruments, supplied from Texas, U.S.A. is utilized to generate the signal pattern presented in Figure 3, based on the controlled signal fed into the internal analog-to-digital converter. However, the PWM signals must be accommodated to the required mosfet gate levels. The isolated PEM1-S12-S12 DC-DC converter, fabricated by P-DUKE, supplied from Texas, U.S.A. along with the optoisolated driver A3120, manufactured by Broadcom Inc., also supplied supplied from Texas, U.S.A. is employed to correctly commute the transistors. Regarding the sensing voltage, a simple resistor-based voltage divider is utilized to provide the attenuation factor $\beta$, followed by an isolated coupler. The output voltage setpoint $V_{\mathrm{o}}^{★}$ is used to derive the individual capacitor voltage reference, $V_{\mathrm{C}}^{★}$, which also depends on the measured input voltage, as shown in (5), as shown in Figure 8. Preliminary findings confirm the converter’s effective performance in a steady state and dynamic regulation.

Figure 12 displays the waveforms captured using the TPS2024 digital oscilloscope, from Tektronix, imported from the U.S.A. and available from Digi-Key. and post-processed with Matlab R2018b software. Similar to the steady-state simulations presented in Section 5, the scenario with a duty cycle higher than 50% was experimentally tested to verify the boosting capability of the proposed converter. Specifically, the validation was carried out for duty cycle values of 72% and 75%; in both cases, the input voltage $v_{\mathrm{d}}$ is kept constant at 12 V. During the steady-state operation, the same duty cycle is applied to both transistors resulting in identical individual capacitor voltages. In Figure 12a, the output voltage reaches six times the input voltage ($G_{\mathrm{v}}=6$), whereas in Figure 12b, with a duty cycle of about 75%, the voltage gain is $G_{\mathrm{v}}=7$, resulting in output voltages of approximately 70.75 V and 84 V, respectively. These results agree with the theoretical calculation given in (14). Also, they illustrate the superiority over the conventional boost converter. However, its voltage gain is still below that of the quadratic-gain boost converter, as shown in Figure 12b. It is observed that the output voltage includes some spikes but generally exhibits minimal ripple.

Finally, the output voltage was regulated under current load variation; this can be seen in Figure 13. To avoid saturation of the duty cycle, the setpoint was established to 50 V.

The capacitor voltages can be obtained as formulated in the scheme proposed in Figure 10, where the difference between the desired output voltage and the input voltage is equally divided across the capacitors. The target is reached after a few milliseconds, and the capacitor voltages contain a small oscillation necessary to keep the output voltage constant.

7. Conclusions

The proposed converter is an adaptation of the traditional double dual boost converter topology, involving the relocation of the output capacitor’s negative terminal. This change maintains the voltage gain equal to the double dual boost topology but allows for cascading two power cells. This cascading of capacitors enables a reduction in output voltage ripple through an appropriate switching strategy. The required PWM pattern is generated by a microcontroller; however, to facilitate implementation, an independent analog P+I controller is employed. Due to the series-connected capacitor voltages, the individual ripples can cancel each other out, resulting in a small output voltage ripple. The topology was thoroughly analyzed to derive the system’s dynamic equations and steady-state characteristics. A prototype was constructed to verify the converter’s functionality, under open- and closed-loop fashion. However, a fully digital version could be implemented to overcome hardware limitations, leading to cost and size reductions. Additionally, the same strategy can be applied to any other cascaded power converter. Importantly, the system equations incorporate the small-ripple approximation, facilitating the selection of $C_1$ to achieve a specific voltage ripple while the value of $C_2$ can be set to the same value to maintain the same ripple when the same duty ratio is applied. An important challenge is to achieve better time responses and reduced overshoots while maintaining high voltage gain.