Memory Grouping for the Built-In Self-Test of Three-Dimensional Integrated Circuits

Abstract

As the complexity of circuit design continues to grow, the development of three-dimensional (3D) integrated circuit (IC) technology has become increasingly vital. While 3D ICs offer faster signal transmission speeds and lower power consumption compared with traditional two-dimensional (2D) ICs, they also pose greater challenges in manufacturing and testing. In memory testing, traditional 2D ICs require only a single testing stage, whereas 3D ICs involve both prebond and postbond testing stages, complicating the memory grouping process. Most existing memory grouping algorithms focus on testing 2D ICs. While one study addressed the memory grouping problem for 3D IC testing, it did not consider the impact of test scheduling. In contrast, our approach incorporates test scheduling into the memory grouping process, resulting in a reduction in BIST area overhead. Experimental results demonstrate that our method reduces built-in self-test circuit area overhead by an average of 10.28% compared with those in the existing literature.

1. Introduction

As feature sizes become smaller, Moore’s Law is gradually reaching its limit. Three-dimensional (3D) integrated circuit (IC) technology has emerged as a potential solution to overcome the limitations of Moore’s Law. This technology vertically stacks and connects multiple chips, allowing chip designers to integrate more circuit components within limited space, thereby improving overall performance and component density while achieving higher computational efficiency with reduced power consumption. By adopting the 3D IC technology, different functional chips can be stacked together, such as directly stacking memory chips with processor chips, significantly reducing the signal transmission distance between chips, improving data processing speed, and reducing power consumption. Furthermore, 3D ICs help reduce the footprint of chips, making devices lighter and more compact, which is especially important in mobile and wearable technologies.

However, the emergence of 3D ICs also brings new issues worth exploring, among which memory testing for 3D ICs is a significant emerging topic. The purpose of memory testing is to ensure that memory components are free from defects during the manufacturing process and that these memories can function properly during use. For 3D ICs, due to their stacked structure, the manufacturing process becomes more complex, making testing even more crucial. Through testing, the functionality of the memory can be verified to ensure it operates as expected. Testing can also assess the performance of the memory, determining its speed and reliability to meet technical specifications. By testing and confirming the memory without errors, the reliability of the entire electronic device can be improved.

In terms of memory testing, a built-in self-test (BIST) is a technique integrated within ICs to automate the verification and validation of the circuit’s functionality. The literature, such as in [1,2,3,4,5,6,7], introduces various BIST architectures. A BIST can improve test fault coverage and increase product yield; thus, IC manufacturers use BIST for IC production testing. Additionally, to store large amounts of information, the proportion of chip area occupied by memories is increasing, necessitating a good BIST to detect and repair memory errors. Ideally, we hope to use a single BIST to handle all the memories on a chip. However, due to routing and timing constraints, the interconnection length between a BIST and the memory it serves needs to be limited. This leads to the issue of memory grouping for testing. The work in [8,9,10,11,12,13] explores the issue of memory grouping, with the main goal of minimizing the use of the number of BIST controllers.

Apart from memory grouping, memory scheduling is also an important aspect of memory testing. Memory scheduling is mainly responsible for determining the testing sequence of each memory unit to maximize test efficiency and meet specific constraints such as power limitation. By optimizing test scheduling, multiple memory units can be tested simultaneously or in the best sequence, reducing the total test time. The literature, such as in [9,14,15,16,17], discusses memory scheduling algorithms.

Due to the stacked structure of 3D ICs, memory scheduling is divided into the prebond testing stage and the postbond testing stage according to the manufacturing process. Before stacking 2D ICs into a 3D IC, this testing stage is called prebond testing, and after stacking, it is called postbond testing. The presence of two testing stages means that the type of memory BIST controller (i.e., serial or parallel-testing BIST) is no longer determined by a single test schedule. In a 2D IC, the controller type depends on only one test schedule. However, for a 3D IC with N layers, the prebond testing stage involves N test schedules, while the postbond stage has one. Thus, in a 3D IC, the type of memory BIST controller depends on N + 1 test schedules.

Zadegan et al. [18] address the difference between session-based and sessionless memory test scheduling. Session-based test scheduling divides the entire test process into one or more sessions. In session-based test scheduling, the system continues to add memory to the current session’s schedule until it reaches the power limit. Once this limit is reached, a new session begins, and scheduling continues, with the start time of the new session based on the end time of the longest test in the previous session. On the other hand, sessionless test scheduling uses a more flexible approach. In sessionless test scheduling, each memory test can start at any time without session restrictions. When updating the test schedule, sessionless scheduling selects the earliest completion time of any test as the new start time, allowing for more efficient use of resources and time, as there is no need to wait for all memory tests in a session to complete before starting the next batch of tests. Therefore, sessionless scheduling is particularly effective in reducing total test time and increasing the flexibility of the testing process.

Kahng et al. [9] propose an innovative algorithm specifically for the configuration of BIST controllers in embedded memories within system-on-a-chip (SoC). The main innovations include using weighted hypergraphs for memory classification, adopting integer linear programming to optimize test scheduling, and precisely placing BIST logic to reduce routing and buffering costs. Experimental results in [9] show that such an algorithm can significantly reduce test time.

Yeh et al. [11] integrate BIST controllers’ placement and memory grouping to reduce the test application time and design overhead of memory testing in SoC. They use an integer linear programming (ILP) approach to simultaneously consider the grouping, placement, and test scheduling of memory BIST controllers, effectively optimizing the use of memory BIST controllers. Experimental data in [11] show that their ILP method not only reduces the total test time but also shortens the routing length of BIST controllers.

Like BIST circuits, built-in self-repair (BISR) circuits are used to automatically repair correctable memory unit errors. BISR circuits typically include additional redundant hardware (e.g., spare rows or spare columns) that can be immediately substituted when the original hardware fails. BIST and BISR are often seen as complementary technologies in modern chip design, with one responsible for detecting problems and the other for fixing them, together enhancing the reliability of chips during production and use. Hou and Li [19] propose a BISR configuration algorithm for RAMs in 3D ICs. Their memory BISR configuration aims to allocate shared BISR circuits for RAMs in each layer of SOC dies, minimizing test and repair time as well as the area of BISR circuits. Simulation results show that compared with dedicated BISR solutions (where each RAM has its own BISR circuit), the shared BISR configuration technique [19] can achieve a 35% area reduction.

Ko and Huang [20] discuss algorithms for memory grouping and scheduling in 3D ICs. Their memory grouping algorithm proceeds as follows. They first regard the grouping problem as an undirected graph where vertices represent memories and the edges (between vertices) represent the permissible sharing of the BIST controller. Then, they [20] identify maximal cliques and sorts them based on the number of vertices and total distance, where the total distance represents the Manhattan distance between memories in the layout. Basically, maximal cliques with more vertices have higher priority. If the number of vertices is the same, those with shorter total distances have higher priority. If a memory has already appeared in a previously confirmed group (i.e., a previously confirmed maximal clique), it is not considered. However, from their memory grouping algorithm, it is evident that memory grouping and memory scheduling are treated as independent processes. Therefore, to overcome this problem, we develop a new algorithm to consider memory scheduling during memory grouping, allowing the area overhead of BIST controllers on the chip to be reduced.

Through analysis, we identify two main drawbacks in the previous work [20]: (1) it does not consider memory scheduling results when grouping memories, and (2) its grouping criterion does not effectively reflect the impact of the grouping results on BIST area overhead. Therefore, in this paper, we develop a new memory grouping algorithm to address these drawbacks. Compared with the memory grouping algorithm of the previous work [20], our memory grouping algorithm considers both the two scheduling results of 3D IC memory testing, including the scheduling results of prebond testing and postbond testing stages. Moreover, our approach minimizes BIST area overhead by using a grouping criterion that effectively reflects the impact of the grouping results on the BIST area. Our objective is to minimize the number of BIST controllers and prioritize the use of serial testing BIST controllers instead of parallel ones, whenever possible. Experimental results consistently show that compared with the memory grouping algorithm of work in [20], our optimization method can achieve an average area reduction of 10.28% and up to 25.00%.

The remainder of this paper is organized as follows. Section 2 covers the background materials. Section 3 discusses our motivation. Section 4 presents the proposed memory grouping approach. Section 5 provides the experimental results. Finally, in Section 6, we offer concluding remarks.

2. Backgrounds

A 3D IC is a type of chip formed by vertically stacking multiple SoCs. The advantage of 3D IC is that it can realize more complex circuits in the same space, thereby reducing manufacturing costs. However, this also means that circuit design will need to consider more factors. In recent years, considerable literature [21,22,23] has discussed 3D IC technology.

A BIST is a testing technique embedded in circuits to perform self-detection. We usually embed a BIST in circuits to meet the need for higher reliability or lower maintenance frequencies. The rapid development of BIST technology is due to the high cost of automatic test equipment (ATE) and the increasing complexity of ICs, thus requiring BIST technology to reduce the dependence on ATE. Many previous works have discussed the architectures of BIST controllers [1,2,3,4,5,6,7]. Note that BIST controllers can be divided into two categories: logic BIST [1,4,7] and memory BIST (MBIST) [3,5,6]. Logic BIST is used for testing logic circuits, and MBIST is used for testing memory circuits. This paper uses MBIST. The advantages of BIST include reduced test costs, the ability to perform independent testing, and shorter test times. The main disadvantage of BIST is the additional area required on the chip. Therefore, the goal of this paper is to reduce the area overhead of BIST controllers on the chip.

Memory scheduling is an algorithm that determines the testing order of memories under certain power constraints. In the prebond testing stage, memories in different layers will produce different scheduling results. In other words, in the prebond testing stage, the test scheduling of each layer only targets the memories in that layer. The postbond testing stage considers the memories in all layers of the 3D IC simultaneously. More specifically, prebond testing is performed before vertically stacking each layer of the 3D IC to ensure the functionality and reliability of each layer. Postbond testing is conducted after vertical stacking and interconnecting the layers to check the overall circuit functionality.

The BIST controllers used in our work follow the assumptions outlined in [20] and support parallel testing. Note that a parallel-testing BIST controller can test multiple memories simultaneously. However, the trade-off for using a parallel-testing BIST controller is a slightly higher area overhead compared with serial testing. Additionally, our memory scheduling also adheres to the assumptions from the previous work [20], employing a session-less scheduling method.

Using

Table 1. The information for 3D IC memory scheduling.

Memory	Layer	Power (mW)	Test Length (Cycles)	Coordinate
M1	1	200	2800	(3.5, 3.4)
M2	1	200	2900	(6.9, 3.2)
M3	1	55	500	(2.6, 1.6)
M4	1	120	800	(4.7, 3.6)
M5	1	120	800	(8.6, 8.6)
M6	2	200	2600	(7.2, 4.3)
M7	2	150	700	(8.4, 3.2)
M8	2	140	1000	(6.7, 5.1)
M9	2	130	1000	(0.4, 1.6)
M10	2	135	1200	(2.0, 8.6)

as an example, we illustrate the information for 3D IC memory scheduling. In Table 1, there are 10 memories, including memories M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10. The column Layer represents the layer where this memory is located. The column Power represents the power consumption required for this memory test. The column Test Length represents the number of clock cycles required for this memory test. The column Coordinate represents the coordinate position of this memory. We assume the power constraint for prebond testing is 400 mW and for postbond testing is 500 mW. Under the power constraints of prebond testing and postbond testing, Figure 1 displays a feasible prebond testing schedule obtained by the previous work [20], and Figure 2 displays a feasible postpond testing schedule obtained by the previous work [20]. In Figure 1 and Figure 2, the red solid lines labeled PC represent the power constraint. In Figure 1, the red dashed line separates the test schedules of the two layers.

In Figure 1, each block represents a memory, its height represents the power consumption of this test, and its width represents the test time. Our memory scheduling algorithm is based on sessionless test scheduling, so there is no restriction that memory tests must start at the beginning of the test session. In other words, we allow memory tests to start at any time during the test session. The test session is defined as the memory with the longest test time within the session. For example, in Figure 1, the test time of memory M2 is the total test time of the first test session, memory M4 is the total test time of the second test session, and memory M8 does not start testing from the beginning of the second test session. In Figure 1, the red line between memory M4 and memory M6 is used to separate the test scheduling of different layers; the left side of the red line belongs to Layer 1, and the right side belongs to Layer 2. Each test session may test multiple memories simultaneously, or it may not. For example, memories M1 and M2 will be tested simultaneously for some time interval, while memories M8 and M10 will be tested at different time intervals. Since Figure 2 is the postbond testing schedule, it does not distinguish the layers where the memories are located.

Memory grouping is an algorithm that determines which memory should be assigned to which BIST controller for testing. Due to routing and timing issues, boundary constraints need to be set to limit the interconnection length between the BIST controller and the memory it serves. Therefore, the number of memories that a BIST controller can serve is limited. For the memories in the same group, we need to assign a shared BIST controller. This BIST controller must be placed in a position that meets the boundary constraints of all the memories within the group.

Note that the result of test scheduling affects the type of shared BIST controller. For example, if the testing intervals of two memories do not overlap, a serial testing BIST (which requires a smaller area) can be used; if the testing intervals overlap, a parallel-testing BIST (which requires a larger area) is necessary. In a 3D IC, if we want two memories to share a serial testing BIST controller, we must ensure that the testing intervals of these two memories do not overlap in both prebond testing and postbond testing. In other words, we need to consider both the test scheduling result of the prebond testing stage and the test scheduling result of the postbond testing stage to optimize memory grouping in 3D ICs.

Memory grouping is the primary focus of this paper. We aim to test the memories of 3D IC with minimal BIST cost, thereby reducing the area overhead on the chip. For the convenience of readers,

Table 2. The literature review of memory grouping algorithms.

Approach	Number of Dimensions	Consider Test Schedules?
Ours	3D IC	Yes
[8]	2D IC	No
[9]	2D IC	No
[10]	2D IC	No
[11]	2D IC	Yes
[12]	2D IC	No
[13]	2D IC	No
[20]	3D IC	No

provides the literature review of memory grouping algorithms. Our literature review shows that only our approach and the work in [20] explore 3D IC memory testing. However, the work in [20] does not consider the result of test scheduling when performing memory grouping.

Table 2 shows that, aside from our approach, only the memory grouping algorithm in [11] considers test scheduling results. However, the work in [11] focuses solely on 2D IC memory testing. For 3D IC memory testing, our work is the first to incorporate test scheduling results into memory grouping.

3. Motivation

In this section, we use an example to illustrate the drawbacks of the algorithm proposed in [20]. In this example, we set the power constraint for prebond testing to be 400 mW, the power constraint for postbond testing to be 500 mW, and the boundary constraint L for each memory to be 3 mm. For the memory boundary range, we use the formula in [20] to calculate the Manhattan distance. In other words, the position $(x,y)$ of the BIST controller within the feasible region should satisfy the following requirement:

$$|x - x_i| + |y - y_i| \le L,$$

where $(x_i,y_i)$ is the position of memory M_i.

Regarding the circuit area calculation of BIST controller, we also use the formula presented in [20]:

$$BISTArea=S\times [1+\alpha \times (P-1\left)\right],$$

where S is the area of the BIST controller performing only serial testing, P is the number of memories undergoing parallel testing, and $\alpha$ is a constant that represents the additional BIST area overhead incurred for each additional memory involved in parallel testing. Consistent with the assumption in [20], in this paper, we assume this constant $\alpha$ to be 0.2.

We use Table 1 as an example to explain the drawbacks of previous work [20]. Figure 3 and Figure 4 give the memory grouping results obtained by the previous work [20], where Figure 3 is the result for layer 1, and Figure 4 is the result for layer 2. In Figure 3 and Figure 4, a red circle represents that these memories are in the same group.

From the memory scheduling and grouping results obtained by the previous work [20] (including Figure 1, Figure 2, Figure 3 and Figure 4), we observe two drawbacks.

• According to Figure 3, we can calculate the BIST area overhead required for memories M1, M2, M3, and M4 in layer 1. These four memories need three BIST controllers for testing, one BIST controller for memories M1 and M4, one BIST controller for memory M2, and one BIST controller for memory M3. However, if our memory grouping result is M1 and M3 in one group, and M2 and M4 in another group, then we only need two BISTs to test these four memories. The algorithm in [20] cannot achieve this result because it uses the distance between memories as the grouping criterion, which does not help optimize memory grouping.
• According to Figure 4, we can calculate the BIST area overhead required for memories M6, M7, and M8 in layer 2. M7 is allocated to one BIST controller alone, and since it is a single memory, it does not need parallel testing, so the BIST area overhead is S. Memories M6 and M8 share one BIST controller for testing, and from Figure 1 and Figure 2, we find that the test times of M6 and M8 overlap, so they need parallel testing. Using the area formula $S\ast [1+\alpha \ast (P-1\left)\right]$, where P = 2 (i.e., the number of memories undergoing parallel testing), the BIST area overhead is $S\ast (1+\alpha )$. Therefore, the total BIST area overhead required for M6, M7, and M8 is $S\ast (2+\alpha )$. However, if our memory grouping result changes to M6 and M7 being tested by the same BIST controller, from Figure 1 and Figure 2, we see that the test time intervals of M6 and M7 do not overlap, so they do not need parallel testing, and the BIST area overhead is only S. In this way, the total BIST area overhead required for memories M6, M7, and M8 would be reduced to $S\ast 2$. However, the algorithm in the previous work [20] cannot achieve this result because it does not consider the memory scheduling results when grouping memories.

Based on these two observations, in the next section, we develop a more precise memory grouping algorithm that can significantly reduce the BIST area overhead.

4. Proposed Approach

In this section, we propose a new memory grouping algorithm that considers the memory scheduling results of 3D ICs. With the proposed algorithm, the area overhead of BIST controllers on the chip can be significantly reduced.

We follow the assumptions in [20], adopting a BIST controller that allows parallel testing and session-less scheduling. Parallel testing enables a single BIST controller to test multiple memories simultaneously. Sessionless scheduling allows memory testing to start anytime within a test session.

For 3D IC memory test scheduling, we still adopt the scheduling results obtained by the previous work [20]. Therefore, here, we briefly describe the scheduling algorithm presented in [20]. Their scheduling algorithm does not restrict memory testing to starting at the beginning of the test session. Instead, it allows memory testing to start anytime within the test session. Under power constraints, the priority of memory testing is as follows: Memories with longer test times have higher priority. If two memories have the same test time, the one with higher power consumption has a higher priority.

Using Table 1 as an example, Figure 1 and Figure 2 give the scheduling results of prebond testing and postbond testing, respectively, obtained by the scheduling algorithm proposed by [20]. Note that the previous work [20] does not mention how to determine the priority if both test time and power consumption are the same. Therefore, here, we assign higher priority to the memory with the smaller memory ID. For example, for memories M4 and M5 in Table 1, we give M4 a higher priority. Based on the priority definition above, we can list the priority order of memories as M2, M1, M6, M10, M8, M9, M4, M5, M7, and M3. Using the session containing M2, M1, and M3 in Figure 2 as an example, M2 has the highest priority, so it is added to the first session. Then, M1 has a higher priority, so it is added to the first session. Next, M6 has a higher priority, but we find it cannot be added to the current session because the power consumption would exceed the power limit. Therefore, following the priority order, we find memory M10, but adding M10 would also exceed the power limit, so it cannot be added to the current session. Following this algorithm, we continue to find memories to add to this session based on the priority order. Finally, we find that memory M3 can be added to this session, so we add memory M3 to this session. Then, we look for the memory that finishes testing earliest in the current session and continue the above algorithm after it. This process continues until no more memories can be added to the current session. Then, the algorithm starts a new session. The test time for each session is equivalent to the test time of the memory added first in the session, as this memory has the longest test time.

For a 3D IC, if it has N layers, the prebond testing stage involves N test schedules, while the postbond testing stage has 1 test schedule. Therefore, in a 3D IC, memory grouping must involve N + 1 test schedules. In our memory grouping algorithm, we use these N + 1 test schedules as inputs.

In [8,20], the problem of finding memory groups is converted into finding cliques in an undirected graph. In graph theory, a clique is a subgraph of an undirected graph where any two vertices are connected. In other words, a clique is a complete subgraph of an undirected graph. In this undirected graph, each vertex represents a memory. If two memories can share the same BIST (i.e., their boundary ranges overlap), there is an undirected edge connecting the vertices representing these two memories. In this way, a clique in the undirected graph represents a feasible memory group.

Formally, we consider an undirected graph $G=(V,E)$, where V is the set of all vertices and E is the set of all edges. If C is a subset of vertices and $C\subseteq V$, and for any two vertices u and v in C there exists an undirected edge $\langle u,v\rangle \in E$, then C is a clique. For example, suppose there is an undirected graph G with vertex set V = {A, B, C, D} and edge set E = {<A, B>, <A, C>, <B, C>, <B, D>}. In this graph, the clique {A, B, C} exists because there are edges between vertex A and vertex B, vertex A and vertex C, and vertex B and vertex C. The clique {B, C, D} does not exist because there is no edge between C and D. A single vertex, such as {A} or {B}, can also be considered as a clique of size 1. In our algorithm, we also consider single vertices as cliques. In summary, the vertices in the undirected graph represent memories, and the existence of an edge depends on whether the boundary ranges of two memories overlap. In our memory grouping algorithm, we also use cliques to describe feasible memory groups.

Unlike the previous work [20], we developed a new memory grouping algorithm that minimizes the area overhead introduced by BIST controllers. Our algorithm offers two key advantages over the previous approach: (1) it takes memory scheduling results into account during the grouping process, and (2) its grouping criteria more accurately reflect the impact of the grouping on BIST area overhead.

Algorithm 1 gives the pseudocode of our proposed memory grouping algorithm. The focus of our algorithm is to determine the priority of each feasible memory group. Then, we consider each feasible memory group in its priority order to determine whether to add it to our memory grouping solution. The principles for determining the priority of feasible memory groups are, in order of importance: the number of memories in this group, the impact of this group on the overall memory grouping, and the BIST area overhead required by this group. Our memory grouping solution is the set of memory groups we have added. Note that, in our memory grouping solution, no two memory groups intersect. Moreover, in our memory grouping solution, the union of all memory groups is all the memories in the 3D IC. Each memory group will require a BIST controller. Therefore, based on our memory grouping solution, we can determine how many BIST controllers are needed and the corresponding area overhead.

Algorithm 1 Proposed memory grouping algorithm

Enumerate all possible cliques using depth-first search;

Sort all possible cliques according to the priority function;

Let our memory grouping solution be an empty set;

for each clique in the sequence of their priorities do

if this clique has no memory already in our memory grouping solution then

add this clique to our memory grouping solution;

end if

end for

To find all possible cliques, we use a depth-first search (DFS)-based iterative method to enumerate them. This DFS method effectively uses a stack to manage the state of cliques, avoiding stack overflow issues caused by deep recursion. The key to this method is to determine whether a new vertex can be added to the current clique, which involves checking whether there are edges between the new vertex and all vertices in the current clique. Only if all these edges exist can the new vertex be added to the clique. For example, suppose we have a graph with vertex set {A, B, C, D} and edge set {<A, B>, <A, C>, <B, C>, <B, D>}. Initially, we push all single vertices onto the stack, i.e., {A}, {B}, {C}, {D}. Taking out {A} from the stack, we try to add B and C to {A}, forming new cliques {A, B} and {A, C}. Next, we take out {A, B}, try to add C, check whether it forms a clique, and form {A, B, C}. This process continues until the stack is empty, at which point all possible cliques have been found.

Next, we determine the priority of all cliques. Algorithm 2 gives the rules for determining clique priorities. Our primary consideration is the number of vertices in the clique. A clique with more vertices has a higher priority. For example, in a graph containing vertices A, B, C, D, and E, if {A, B, C} forms a clique, {B, C, D} forms a clique, and {D, E} forms a clique, then the cliques {A, B, C} and {B, C, D}, which contain three vertices, have a higher priority than the clique {D, E}, which contains only two vertices. The design rationale for this priority (i.e., rule 1 in Algorithm 2) is to allow more memories to be tested by the same BIST controller (even if it may slightly increase the area due to parallel testing). We believe this approach is useful for area reduction because the area overhead of parallel testing is smaller than the additional area of one more BIST controller.

Algorithm 2 Rules for determining the priorities of cliques

Rule 1: A clique with more vertices has a higher priority level.

Rule 2: For cliques with the same number of vertices, the clique with smaller impact has a higher priority level.

Rule 3: For cliques with the same number of vertices and the same impact, the clique that forms a smaller area has a higher priority level.

Secondly, for cliques with the same number of vertices, we determine their priority based on the impact of each clique on the overall memory grouping. The impact of a clique on the overall memory grouping mainly evaluates the impact of the memories in this clique on other cliques. Note that a memory may belong to multiple cliques. Suppose a memory belongs to n cliques; we say the impact of the memory is equal to n. Moreover, the impact of a clique is defined as the sum of the impacts of the memories in this clique. A clique with a smaller impact has a higher priority. The design rationale for this priority (i.e., rule 2 in Figure 2) is to allow memories with fewer grouping opportunities to be grouped first.

Suppose we have a graph with vertices A, B, and C, and edge set {<A, B>, <A, C>, <B, C>}. We illustrate the impact of clique {A, B, C} on overall memory grouping as below. Vertex A can form clique {A, B} with vertex B, form clique {A, C} with vertex C, and form clique {A, B, C} with vertex B and vertex C, so the impact of vertex A is 3. Vertex B can form clique {A, B} with vertex A, form clique {B, C} with vertex C, and form clique {A, B, C} with vertex A and vertex C, so the impact of vertex B is 3. Vertex C can form clique {A, C} with vertex A, form clique {B, C} with vertex B, and form clique {A, B, C} with vertex A and vertex B, so the impact of vertex C is 3. Therefore, the impact of clique {A, B, C} on the overall memory grouping is 3 + 3 + 3 = 9. Note that when calculating the impact of a memory (a vertex), we do not consider single-vertex cliques.

We further explain how to calculate the impact of each clique on the overall memory grouping. Suppose we have a clique {A, B, C}. Then, memory A must belong to the cliques {A, B, C}, {A, B}, and {A, C}. In fact, we can use a mathematical formula to calculate; the impact calculation is equivalent to $C_2^2$ + $C_1^2$ = 3 (i.e., $C_1^2$ is the combination of 2 taken 1 at a time). Therefore, using the binomial theorem, we can deduce a simple formula to calculate the impact of a memory, which is $2^{n-1}-1$, where n is the number of memories in the clique. Note that if memory A also forms cliques with other memories (memories other than B and C), the formula must be used again. Then, we sum all the calculated values to obtain the impact of memory A. Furthermore, the impacts of all memories in the clique are summed to obtain the impact of the clique. Based on the above analysis, the impact of clique {A, B, C} is $(2^{3-1}-1)+(2^{3-1}-1)+(2^{3-1}-1)=9.$

Finally, for cliques with the same number of vertices and the same impact, we determine their priority based on the BIST area overhead required by each clique, according to the results of prebond and postbond test scheduling. Our algorithm determines the number of memories requiring parallel testing in each clique according to the test scheduling results. If the number of memories requiring parallel testing is greater than 1 (i.e., P > 1), the BIST area overhead is calculated using the formula $S\ast [1+\alpha \ast (P-1\left)\right]$. If no parallel testing is required (i.e., P = 1), the BIST area is only S. A clique with smaller area overhead has a higher priority. Suppose a clique {A, B, C}, where the test times of A, B, and C overlap, then A, B, and C require parallel testing. Therefore, we have P = 3. Conversely, if the test times of these three memories do not any overlap, then P = 1. The rationale for this priority (i.e., rule 3 in Figure 2) is intuitive, as it aims to select the clique with the smallest BIST area overhead under the same number of vertices and the same impact.

After filtering the cliques through the three priority rules given in Figure 2, we can sort all the cliques (including all the single-vertex cliques). Then, we evaluate each clique in the sorted order to determine whether to add it to our memory grouping solution until every memory has been included in our memory grouping solution. Note that here, we also consider single-vertex cliques. Therefore, in the end, all the memories will be included in our memory grouping solution.

As stated in Figure 1, we evaluate each clique based on its order to determine whether it is suitable to be added to our memory grouping solution. Note that we must ensure that each memory is tested by exactly one BIST controller. Therefore, for each clique, we check if any memory in this clique already exists in our memory grouping solution (i.e., if any memory in this clique is already scheduled to be tested by another BIST controller). If none of the memories in this clique appear in our memory grouping solution, we add this clique to our memory grouping solution; otherwise, we do not add this clique to our memory grouping solution.

For the convenience of the reader, Figure 5 gives a flow chart to describe the proposed approach. We sort all possible cliques according to the priority function. We then evaluate each clique in sorted order to decide whether to include it in our memory grouping solution. This process is repeated until all cliques have been examined. By the end of the iteration, every memory has been incorporated into our memory grouping solution.

We use Table 1 as an example to explain the proposed memory grouping algorithm. Here, we list only cliques with two or more vertices for discussion because the priority of single-vertex cliques is lower. In this example, the cliques with two or more vertices include {M1, M3}, {M1, M4}, {M2, M4}, {M6, M7}, and {M6, M8}. In fact, all these cliques have two vertices.

Since each clique has the same number of vertices, we must further sort them based on their impact. For clique {M1, M3}, memory M1 can be grouped with M3 and M4, while memory M3 can only be grouped with M1, so the impact of {M1, M3} on the overall memory grouping is 3. For clique {M1, M4}, memory M1 can be grouped with memories M4 and M3, and memory M4 can be grouped with memories M1 and M2, so the impact of {M1, M4} on the overall memory grouping is 4. Similarly, the impact of {M2, M4} is 3, the impact of {M6, M7} is 3, and the impact of {M6, M8} is 3. Therefore, we can see that clique {M1, M3}, clique {M2, M4}, clique {M6, M7}, and clique {M6, M8} have the same priority, while clique {M1, M4} has a lower priority.

Based on the 3D IC test scheduling results displayed in Figure 1 and Figure 2, we calculate the BIST area overhead required for each clique. In Figure 1, clique {M1, M3} belongs to serial testing; however, in Figure 2, clique {M1, M3} belongs to parallel testing. Therefore, clique {M1, M3} still requires a parallel-testing BIST controller. According to the area formula, the area overhead of clique {M1, M3} is $S\ast (1+\alpha )$. In Figure 1 and Figure 2, clique {M2, M4} belongs to serial testing, so the area overhead is S. Similarly, the area overhead of clique {M6, M7} is S, the area overhead of clique {M6, M8} is $S\ast (1+\alpha )$, and the area overhead of clique {M1, M4} is S. Therefore, the area overhead of cliques {M2, M4}, {M6, M7}, and {M1, M4} is S, while the area overhead of cliques {M1, M3} and {M6, M8} is $S\ast (1+\alpha )$.

As stated in Figure 2, for the order of cliques, we consider the three priority rules of vertices, impact, and area overhead. Based on the above discussion, we have the following conclusions: cliques {M2, M4} and {M6, M7} have the highest priority, cliques {M1, M3} and {M6, M8} have the next highest priority, and {M1, M4} has the lowest priority. Note that, after applying these three priority rules, cliques still with the same priority are randomly ordered. Therefore, in this example, we obtain the following sorted order: {M2, M4}, {M6, M7}, {M1, M3}, {M6, M8}, {M1, M4}. Moreover, including single-vertex cliques, the final sorted order is {M2, M4}, {M6, M7}, {M1, M3}, {M6, M8}, {M1, M4}, {M1}, {M2}, {M3}, {M4}, {M5}, {M6}, {M7}, {M8}, {M9}, {M10}.

We examine each clique in the sorted order to determine whether to add it to our memory grouping solution. For each clique, we check whether any memory in this clique already exists in our memory grouping solution. If none of the memories in this clique exist in our memory grouping solution, we add this clique to our memory grouping solution; otherwise, this clique is discarded. This iteration process continues until we examine all cliques. Consequently, our memory grouping solution will contain all added cliques. In this example, we first add cliques {M2, M4}, {M6, M7}, and {M1, M3} to our memory grouping solution. Then, cliques {M6, M8}, {M1, M4}, {M1}, {M2}, {M3}, and {M4} are discarded because they contain memories already in our memory grouping solution. Then, we add clique {M5} to our memory grouping solution. Then, cliques {M6} and {M7} are discarded because memories M6 and M7 already exist in our memory grouping solution. Finally, we add cliques {M8}, {M9}, and {M10} to our memory grouping solution. As a result, we obtain the following memory grouping solution: {M2, M4}, {M6, M7}, {M1, M3}, {M5}, {M8}, {M9}, {M10}.

Figure 6 shows the memory grouping results for layer 1, where memories M2 and M4 are in the same group (i.e., M2 and M4 share the same BIST controller), and memories M1 and M3 are in the same group (i.e., M1 and M3 share the same BIST controller). Figure 7 shows the memory grouping results for layer 2, where memories M6 and M7 are in the same group (i.e., memories M6 and M7 share the same BIST).

The proposed memory grouping algorithm overcomes the two drawbacks of [20], mentioned in Section 3. We explain it as follows:

• Memory grouping results in layer 1: The memory grouping result obtained by the previous work [20] is {M1, M4}, {M2}, {M3}, {M5}. Therefore, the previous work [20] requires four BIST controllers for testing. On the other hand, our memory grouping result is {M1, M3}, {M2, M4}, {M5}. Therefore, we only need three BIST controllers for testing.
• Memory grouping results in layer 2: The memory grouping result obtained by the previous work [20] is {M6, M8}, {M7}, {M9}, {M10}. Our grouping result is {M6, M7}, {M8}, {M9}, {M10}. Both the two memory grouping results require four BIST controllers for testing. However, the memory grouping result obtained by the previous work [20] needs a parallel-testing BIST controller for memories M6 and M8 due to overlapping test times, while our memory grouping result only needs a serial-testing BIST controller for memories M6 and M7 because their test times do not overlap. Thus, our memory grouping algorithm reduces the BIST area overhead.

5. Experimental Results

Regarding 3D IC test scheduling, there are currently no publicly available benchmarks or datasets for experimentation. We refer to the description of test cases from previous work [20] and generate test cases with characteristics similar to those in previous work [20]. Our approach for generating test cases is as follows: we adopt power consumption values, number of layers, and number of memories similar to those in previous the work [20], while randomly determining the location of each memory. We applied the test scheduling algorithm proposed in [20] to 11 test cases. The scheduling results of these 11 cases were then used for the memory grouping experiments.

We implemented both our memory grouping algorithm and the memory grouping algorithm proposed by the previous work [20] using C++ programming language running on an Intel i5-12500H 2.5 GHz 12-core processor. Moreover, we adopt the scheduling results obtained by the previous work [20] as the inputs to the memory grouping process. Based on the same scheduling results, we compare the BIST area overhead of our memory grouping algorithm with that of the memory grouping algorithm proposed by the previous work [20]. Notably, no matter our memory grouping algorithm and the algorithm proposed by the previous work [20], the CPU time for each test case does not exceed 1 s.

We conducted experiments for these 11 test cases. In the experiments, we adopt the same assumptions as in [20], setting the power constraint for prebond testing to be 400 mW, the power constraint for postbond testing to be 500 mW, the boundary constraint to 3 mm, the value of S to 0.0089 mm², and the value of $\alpha$ to 0.2 mm². To calculate the reduction ratio in area overhead of our approach compared to Ko’s approach [20], we use the following formula:

$$\mathrm{reduction}\mathrm{ratio}=\left({\displaystyle \frac{\mathrm{area}\mathrm{obtained}\mathrm{by}\mathrm{Ko}’\mathrm{s}\mathrm{approach}-\mathrm{area}\mathrm{obtained}\mathrm{by}\mathrm{our}\mathrm{approach}}{\mathrm{area}\mathrm{obtained}\mathrm{by}\mathrm{Ko}’\mathrm{s}\mathrm{approach}}}\right)\times 100\%$$

Table 3. Descriptions of the 11 test cases.

Test Case	#Layers	#Memories
test0	1	20
test1	2	10
test2	2	24
test3	2	40
test4	3	64
test5	4	96
test6	2	20
test7	2	30
test8	2	50
test9	3	70
test10	4	100

tabulates the characteristics of these 11 test cases. The column Test Case represents the name of the test case, the column #Layers represents the number of layers, and the column #Memories represents the total number of memories in this test case.

Table 4. Comparisons between our approach and Ko [20].

Test Name	Ko	Ours	Reduction
test0	0.14240	0.10680	25.00%
test1	0.07476	0.06586	11.90%
test2	0.16198	0.14418	10.99%
test3	0.25454	0.22250	12.59%
test4	0.38448	0.33286	13.43%
test5	0.50552	0.46280	8.45%
test6	0.12460	0.11748	5.71%
test7	0.15842	0.14774	6.74%
test8	0.19046	0.17622	7.48%
test9	0.29904	0.28302	5.36%
test10	0.39694	0.37558	5.38%
Average	-	-	10.28%

compares the area overheads of the two memory grouping algorithms. The column Ko represents the BIST area overhead obtained by the memory grouping algorithm from [20]. The column Ours represents the BIST area overhead obtained using our memory grouping algorithm. The column Reduction represents the reduction ratio calculated using the formula.

As shown in Table 4, our approach can reduce the BIST area overhead in each test case. On average, our approach reduces the BIST area overhead by 10.28%. Moreover, in test case test0, our method achieves a maximum reduction of up to 25.00%. Therefore, here, we use test case test0 as an example to demonstrate the advantages of our algorithm. Test case test0 contains only one layer. In this test case, every four memories are clustered together: memories M0, M1, M2, and M3 are near each other; memories M4, M5, M6, and M7 are near each other; memories M8, M9, M10, and M11 are near each other; memories M12, M13, M14, and M15 are near each other; and memories M16, M17, M18, and M19 are near each other.

Figure 8 and Figure 9, respectively, show the memory grouping result obtained by the previous work [20] and the memory grouping result obtained by our approach for test case test0. In Figure 8, every cluster (every four memories) requires three BIST controllers for testing. For example, {M0, M1} uses one BIST controller, {M2} uses one BIST controller, and {M3} uses one BIST controller. On the other hand, in Figure 9, every cluster (every four memories) only requires two BIST controllers for testing. For example, {M0, M2} uses one BIST controller, and {M1,M3} uses one BIST controller.

The reason is that the memory grouping algorithm proposed by the previous work [20] uses the distance between memories as the grouping criterion, and the distance between memory M0 and memory M1 is shorter than that between memory M0 and memory M2. Therefore, the previous work [20] groups memories M0 and M1 together. On the other hand, our algorithm sorts using the impact of the clique, making the priority of clique {M0, M1} the smallest, allowing other cliques with less impact to be selected first. This optimization reduces the BIST area overhead of test case test0 by 25.00%.

In these experiments, we use the test schedules generated from the previous work [20] as inputs. Note that our memory grouping algorithm does not change the test time or power consumption of memory testing. Therefore, our memory grouping algorithm can reduce the BIST area without affecting test time and power consumption.

6. Conclusions

This paper proposes a new memory grouping algorithm for the memory testing problem of 3D ICs. Compared with previous literature, the proposed approach considers the memory test scheduling results, optimizing the memory grouping results, and reducing BIST circuit area overhead. Experimental results consistently show that the proposed memory grouping algorithm can indeed optimize BIST circuit design effectively. Compared with the previous work, experimental data show that our approach can reduce the BIST circuit area overhead in all test cases. On average, compared with previous literature, the proposed approach can save 10.28% of the BIST circuit area overhead.

Our memory grouping algorithm can reduce the memory BIST area overhead, thereby lowering chip manufacturing costs. Note that our approach is applicable to a wide range of 3D IC designs. For any 3D IC memory test that requires the use of memory grouping for BIST controller sharing, our memory grouping algorithm can be applied.

Currently, our memory grouping algorithm assumes that test scheduling must be completed first. Then, based on the results of the test scheduling, we perform the task of memory grouping. A potential future research direction is to explore conducting both test scheduling and memory grouping simultaneously, which could offer greater optimization opportunities.