A Voltage Equalization Strategy for Series-Connected SiC MOSFET Applications

Abstract

A novel clamped voltage equalization strategy is presented for series-connected Silicon Carbide (SiC) Metal–Oxide semiconductor Field-Effect transistors (MOSFETs) in this paper. Differences in device parameters and circuit asymmetry result in the uneven voltage distribution of series-connected SiC MOSFETs, which threatens the safe operation of the circuit. Dynamic voltage equalization is difficult to achieve due to the fast switching speed of SiC MOSFETs. This paper analyzes the switching characteristics and dynamic voltage equalization characteristics of SiC MOSFETs. Based on the analysis, an energy recovery strategy based on the clamping auxiliary circuit is proposed. A 2.8 kW (50 KHz) prototype is fabricated and tested to verify the strategy. Measurement results show that the maximum voltage stress is suppressed from 600 V to less than 320 V in the experimental condition.

1. Introduction

Silicon Carbide (SiC) material can push the power density and efficiency of semiconductor devices and power systems to higher limits due to its wide band gap, high critical field, and high thermal conductivity [1,2,3]. With the development of SiC technology, the application of SiC MOSFETs (Metal–Oxide semiconductor Field-Effect transistors) is increasingly popular [4,5]. In high-voltage applications, there are two solutions, individual high-voltage and series-connected low-voltage MOSFETs. The series-connected low-voltage SiC MOSFET method has low on-state impedance [6], high current density, high switching speed and high radiation immunity [7], and has great application prospects in power electronics. Although the advantages of the series SiC MOSFET structure are numerous, the device characteristics and the gate drive circuit differences will result in uneven voltage distribution. Balancing the drain–source voltages between the series MOSFETs is a pressing issue for the applications.

Dynamic voltage equalization is the main problem in series SiC MOSFET voltage equalization. Dynamic voltage equalization ensures that the drain source voltage $V_{DS}$ of the series-connected MOSFETs is maintained within the rated voltage during the switching process, which is the main limitation in series-connected applications.

The relative waveforms of the series-connected SiC MOSFETs analysis are shown in Figure 1. The switching sequence of the three SiC MOSFETs is directly related to the gate drive resistance value, which is uncertain. When M3 is turned off first and M1 is turned off last, M1 has to withstand the bus voltage during the switching process, which is the worst working condition. The analysis is based on the worst condition. M3 turns off before the other devices, which results in a rapid $V_{DS}$ rise and suffers a larger $V_{DS}$ overshoot. Similarly, during the turn-on interval, M3 turns on first and causes $V_{DS3}$ drops. $V_{DS1}$ and $V_{DS2}$ rise to withstand the bus voltage. The overvoltage breakdown risks increase due to the switching delay. Overvoltage is even more dangerous for SiC MOSFETs due to their breakneck switching speeds. Therefore, dynamic voltage equalization is the most critical issue in series-connected SiC MOSFET applications.

Ref. [8] introduced an RCD (resistor–capacitor diode) snubber or RC (resistor capacitor) snubber. The principle is connecting, in parallel, a snubber capacitance with the drain and source of the MOSFET, and the capacity of the snubber capacitance is larger than the output capacitance of the MOSFET. This causes the rising rate of $V_{DS}$ to decrease when the MOSFET is switched on and off, and the voltage inequality decreases accordingly. Refs. [9,10] realized the voltage equation based on an RC snubber circuit and analyzed the influence of the snubber circuit parameters on the switching loss and voltage equalization effect. The energy in the snubber capacitance is completely consumed in the resistor, which results in large losses. Refs. [11,12,13] introduced a diode clamping and voltage source energy recovery strategy, but the complexity of the auxiliary circuit and power loss limited their applications.

Ref. [14] introduced a voltage equalization strategy based on closed-loop feedback gate delay signal compensation. Ref. [15] proposed a high-frequency transformer-coupled gate realization method to achieve a consistent gate current and ensure the consistency of the gate signal. However, this method cannot improve the uneven voltage affected by the difference in device characteristics. The presence of high-frequency transformer coupling capacitance and leakage inductance also affects the operation of this circuit. The gate reference voltage control strategy is proposed in ref. [16]. The gate signal of each device is controlled by the drain–source voltage feedback and high-speed op-amp circuit to ensure that the gate signal of each device is consistent with the gate reference signal to achieve voltage equalization. A master–slave control-based voltage equalization strategy is proposed in ref. [17]. The drain–source voltage of one device in the series connection is used as a reference, and the voltage equalization is achieved by adjusting the gate voltage during the switching process of other devices. However, these methods require high-speed, high-precision integrated circuits with low reliability. An active clamp circuit based on a gate–drain Zener diode clamping is proposed in refs. [18,19,20]. When the device is subjected to excessive voltage, the Zener diode and the auxiliary circuit reverse breakdown, thus limiting the further rise of the drain–source voltage of the device. Refs. [21,22,23] proposed a single-driver series MOSFET structure based on capacitive coupling. All of the above methods need to be based on the accurate calculation of the device parameters, which makes it difficult to be applied in massive applications. Refs. [24,25] proposed a single-driver series-parallel SiC MOSFET module, which uses an additional power supply to assist in driving the top-end MOSFETs. However, the voltage equalization of the series MOSFETs in this method relies on the clamping buffer circuit, and the accumulated energy in the clamping circuit is dissipated in the resistor, resulting in a large loss.

The load-side buffer circuit has a simple structure, but the disadvantages of its large size and high loss are difficult to overcome. The gate active control strategy relies on high-speed integrated circuits with the disadvantages of many components, large cost, and low reliability. The gate delay control method requires large-scale digital integrated circuits such as FPGAs (Field Programmable Gate Arrays) or DSPs (Digital Signal Processings), and the circuit and feedback control algorithms are complex. The active clamp circuit extends the switching time of the MOSFET, which is prone to causing relatively large switching losses.

By analyzing the current research status of series power devices, this paper proposes a new series SiC MOSFET topology. The strategy is analyzed in detail, and the effectiveness is verified by an experiment. The experimental results show that the structure can suppress the SiC MOSFET drain–source voltage from 600 V to 320 V. The strategy is easy to apply to multiple MOSFETs in series and has a simple structure. The loss is relatively small due to the energy recovery circuit. At the same time, the circuit control strategy is relatively simple and can improve reliability.

2. The Analysis of the Dynamic Characteristics

2.1. The Switching Characteristics of the SiC MOSFET

Dynamic voltage equalization is affected by the switching characteristics of SiC MOSFETs; the switching process is quantitatively analyzed based on the inductive clamp circuit [26]. The topology is shown in Figure 2. Since the turn-on and turn-off processes of SiC MOSFETs are similar, only the turn-on process is analyzed in this paper.

The relative schematic waveforms and the equivalent circuit diagram of the turn-on process are shown in Figure 3 and Figure 4, respectively. When the MOSFET is off, its gate–source voltage $v_{GS}$ and drain current $i_D$ are zero, and its drain–source voltage $v_{DS}$ is the bus voltage $V_{DD}$. The clamp diode $D_f$ turns on and flows the load current $I_O$. At $t_0$, the gate–source voltage $v_{GS}$ rises.

[$t_0$–$t_1$]: $v_{GS}$ rises from zero, the gate current $i_G$ charges the input capacitor. Since gate–source capacitance $C_{GS}$ is much larger than gate–drain capacitance $C_{GD}$, most of the gate current $i_G$ charges $C_{GS}$ and a small amount flows to $C_{GD}$. Since $v_{GS}$ is below the MOSFET threshold voltage $V_{TH}$, $i_D$ remains at zero, and $v_{DS}$ remains constant. The time required for $v_{GS}$ to rise from zero to the threshold voltage $V_{TH}$ is called the turn-on delay time $t_{d\left(on\right)}$, which is derived as follows:

$$i_G\left(t\right)={\displaystyle \frac{V_{GG}-v_{GS}\left(t\right)}{R_G}}=C_{GS}{\displaystyle \frac{d{v}_{GS}\left(t\right)}{dt}}-C_{GD}{\displaystyle \frac{d(v_{GS}\left(t\right)-v_{DS}\left(t\right))}{dt}}$$

(1)

$v_{DS}$ is constant and equal to the bus voltage $V_{DD}$ in this interval; the expression for $i_G$ is shown in (2):

$$i_G\left(t\right)=(C_{GS}+C_{GD}){\displaystyle \frac{d{v}_{GS}\left(t\right)}{dt}}$$

(2)

Based on (1) and (2), and the initial condition $v_{GS}$($t_0$) = 0, $v_{GS}$ can be expressed by (3) and (4) in this interval:

$$v_{GS}\left(t\right)=V_{GG}(1-e^{-(t-t_0)/\phantom{-(t-t_0)\tau }\tau })$$

(3)

$$\tau =R_G(C_{GS}+C_{GD})$$

(4)

where $R_G$ is the gate resistance of the MOSFE; $i_G$ can be expressed as (5)

$$i_G={\displaystyle \frac{V_{GG}}{R_G}}{e}^{-(t-t_0)/\phantom{-(t-t_0)\tau }\tau }$$

(5)

[$t_1$–$t_2$]: This interval is also known as the current rise interval. After $t_1$, $v_{GS}$ > $V_{TH}$, $i_G$ continues to charge the input capacitance $C_{iss}$, and $v_{GS}$ continues rising. $i_D$ rises as a function of $v_{GS}$ from the $t_1$ moment and the MOSFET enters the saturation operating region.

The transconductance $g_m$ and $i_D$ are given by (6) and (7), respectively:

$$g_m={\displaystyle \frac{\partial i_D}{\partial v_{gs}}}={\displaystyle \frac{2\sqrt{I_{DSS}{i}_D}}{V_{TH}}}$$

(6)

$$i_D\left(t\right)=g_m(v_{GS}-V_{TH})$$

(7)

where $I_{DSS}$ is the MOSFET drain current at zero gate bias.

Since $i_D$ < $I_O$ in this interval, $D_f$ is still conducting the load current and $v_{DS}$ = $V_{DD}$. The expression for $v_{GS}$ agrees with Expression (3). Expression (3) is associated with (7) to obtain Expression (8) for $i_G$, which can be seen to decrease exponentially in $i_G$:

$$i_G\left(t\right)=g_m(V_{GG}-V_{TH})-g_m{V}_{GG}{e}^{-(t-t_1)/\phantom{-(t-t_1)\tau }\tau }$$

(8)

At $t_2$, $i_D$ reaches the load current $I_O$ and $D_f$ turns off. The current rise phase time interval $t_{ri}$ satisfies (9):

$$t_{ri}=\tau ln{\displaystyle \frac{g_m{V}_{GG}}{g_m(V_{GG}-V_{TH})-I_O}}$$

(9)

[$t_2$–$t_3$]: This interval is also known as the Miller plateau interval. At $t_2$, $i_D$ reaches the load current and remains constant. The MOSFET operates in the saturation region and $v_{GS}$ remains constant. The Miller platform voltage $V_{GS,I_O}$ is expressed as (10)

$$V_{GS,I_O}={\displaystyle \frac{I_O}{g_m}}+V_{TH}$$

(10)

$i_G\left(t_2\right)$ can be expressed as (11):

$$i_G\left(t_2\right)={\displaystyle \frac{V_{GG}-v_{GS\left(t_2\right)}}{R_G}}={\displaystyle \frac{V_{GG}-\left(I_O/\phantom{I_O{g}_m}{g}_m\right)-V_{TH}}{R_G}}$$

(11)

In this interval, $v_{GS}$ is constant and $i_G$ begins to charge $C_{GD}$. The Formula (12) for $i_G$ can be obtained as follows:

$$i_G\left(t\right)=C_{GD}{\displaystyle \frac{d(v_G-v_D)}{dt}}$$

(12)

Since $V_{GS}$ remains constant, Expression (13) can be obtained:

$$i_G\left(t\right)=-C_{GD}{\displaystyle \frac{d{v}_{DS}}{dt}}={\displaystyle \frac{V_{GG}-V_{GG,I_O}}{R_G}}={\displaystyle \frac{V_{GG}-V_{TH}-I_O/\phantom{I_O{g}_m}{g}_m}{R_G}}$$

(13)

The initial condition is $v_{DS}$($t_2$) = $V_{DD}$ at $t_2$, and bringing in (13) yields an expression for $v_{DS}$ over time within the interval:

$$v_{DS}\left(t\right)=-{\displaystyle \frac{V_{GG}-V_{GS,I_O}}{R_G{C}_{GD}}}(t-t_2)+V_{DD}$$

(14)

As the gate drive current charges $C_{GD}$, $v_{DS}$ decreases linearly. At this point, the MOSFET gradually enters the linear operating region. The larger $V_{DD}$ is, the longer the Miller platform phase lasts. At $t_3$, $v_{DS}$ drops to the on-state drain–source voltage drop $V_{DS\left(on\right)}$, where $V_{DS\left(on\right)}$ = $I_D$$R_{ds\left(on\right)}$. The Miller platform duration $t_{fv}$ is given by (15):

$$t_{fv}=t_3-t_2=R_G{C}_{GD}{\displaystyle \frac{(V_{DD}-I_D{R}_{ds\left(on\right)})}{V_{GG}-V_{TH}-I_O/\phantom{I_O{g}_m}{g}_m}}$$

(15)

[$t_3$–$t_4$]: After $t_3$, $v_{GS}$ continues to rise under the continued charging of $i_G$. Since $v_{DS}$ remains constant at this point, the rate of rise of $v_{GS}$ can be referred to the phase [$t_0$–$t_1$].

$$v_{GS}\left(t\right)=V_{GG}(1-e^{-(t-t_3)/\phantom{-(t-t_3)\tau }\tau })$$

(16)

During this interval, $v_{GS}$ grows exponentially until the driving voltage $V_{GG}$ is reached. At $t_4$, $i_D$ becomes zero and the MOSFET turn-on process ends. The total turn-on delay $t_{ON}$ is the summation of the three part-time intervals and is given by (17):

$$t_{ON}=t_{d\left(on\right)}+t_{ri}+t_{fv}$$

(17)

2.2. The Dynamic Voltage Distribution Analysis of the Series-Connected SiC MOSFETs

Ideally, series-connected SiC MOSFETs would achieve good dynamic and static voltage equalization. However, in actual circuits, due to the impossibility of achieving perfectly uniform devices and highly symmetrical driving circuits, the voltage equalization effect often differs from the ideal situation. The device and circuit factors affecting the dynamic voltage equalization characteristics of series-connected SiC MOSFETs are theoretically investigated in what follows.

Figure 5 shows the equivalent switching model for SiC MOSFETs, where $C_{GD}$ and $C_{DS}$ are related to the drain–source voltage $V_{DS}$, while $C_{GS}$ can be considered to be constant. The input capacitance $C_{iss}$ of the MOSFET consists of capacitance $C_{GD}$ and $C_{GS}$. The output capacitance $C_{oss}$ includes capacitance $C_{DS}$ and $C_{GD}$. Furthermore, the feedback capacitance $C_{rss}$ is the capacitance $C_{GD}$. The model includes gate parasitic inductance $L_G$ and source-level parasitic inductance $L_S$. Parasitic inductance is introduced by the interconnections and affects the switching process of the devices.

The dynamic voltage inhomogeneity of series SiC MOSFETs is mainly caused by two aspects, gate drive circuit delay differences and device parameter differences. Furthermore, differences in parasitic parameters on the main circuit may cause voltage unevenness. Among them, series SiC MOSFET static voltage equalization is mainly affected by the device turn-off leakage current. The device dynamic voltage equalization is affected by more factors, including device dynamic characteristic differences, gate drive delay mismatch, and different parasitic parameters on the main circuit. Device dynamic characteristics such as threshold voltage $V_{TH}$, inter-pole parasitic capacitance, transconductance $g_m$, parasitic inductance, etc., all affect the dynamic voltage equalization of series-connected SiC MOSFETs. The causes of voltage imbalance during turn-on and turn-off will be analyzed separately in the following section.

Based on the quantitative description of the SiC MOSFET switching process, it can be assumed that the following factors may be responsible for the voltage imbalance of series-connected SiC MOSFETs during the turn-on phase:

(1)

The difference at the moment when the MOSFET enters the current rise phase ($t_{ri}$). There are two sources of this difference, one is the gate drive delay difference, which is due to the gate drive circuit difference; the other is the difference in the turn-on delay time ($t_{d\left(on\right)}$) of individual MOSFETs, which is mainly due to the threshold voltage $V_{TH}$ and input capacitance $C_{iss}$ differences. During the current rise interval, the MOSFET can be equated to a gate voltage-controlled current source. At this point, the MOSFET can be viewed as an ever-decreasing resistor from the drain–source point of view. If the MOSFET enters this stage later, its equivalent drain–source resistance is relatively large, and, thus, its drain–source voltage is large. The difference in the stage of current rise entered by each MOSFET can lead to uneven voltage.

(2)

MOSFETs have different rates of current change during the current rise interval ($t_{ri}$). According to (8), the difference in transconductance of each MOSFET will result in a different rate of current rise. This is due to unavoidable differences in device fabrication. From the drain–source point of view, the equivalent resistance of each MOSFET will be different. Uneven voltage may occur at this stage.

(3)

MOSFETs have different rates of voltage change during the voltage drop interval ($t_{fv}$). In this interval, MOSFET can be equivalent to a variable capacitor, and its capacitance rises as the drain–source voltage falls. Thus, the difference in output equivalent capacitance can lead to uneven voltage. However, since the total voltage to which the series MOSFETs are subjected at this stage has already begun to fall, voltage unevenness does not normally lead to serious problems.

In general, the main reasons for the uneven voltage of series-connected SiC MOSFETs in the turning-off process are as follows:

(1)

The difference at the moment when the MOSFET enters the voltage rise phase ($t_{rv}$). There are two sources of this difference, one is the gate drive delay difference, which is due to the gate drive circuit difference; the second is the difference in the turn-off delay time ($t_{d\left(off\right)}$) of each MOSFET, which is mainly due to the difference in the threshold voltage $V_{TH}$ and the input capacitance $C_{iss}$. In this interval, the MOSFET can be equated to a variable capacitor and its capacitance decreases as the drain–source voltage rises. The voltage rise interval can be considered as a charging process of the ever-smaller MOSFET output capacitance. MOSFETs that turn off early are necessarily subjected to higher drain–source voltages. If the difference in MOSFET turn-off delay is too large, it is easy to cause overvoltage damage to the MOSFET. According to theoretical analyses and experimental results, the turn-off delay difference [27] is considered to be the main factor affecting the turn-off voltage equalization of series-connected SiC MOSFETs. Thus, it is quite important to ensure that the series SiC MOSFET turn-off delay is synchronized.

(2)

The difference in the rate of voltage change of MOSFETs during the voltage rise phase ($t_{rv}$). Even though the drain–source voltage of each MOSFET in the series starts to rise at the same time, the difference in the rate of voltage change of the MOSFETs at this stage is difficult to avoid. The MOSFET at this stage can be equated to the charging process of a variable capacitor. The rate of voltage change during the Miller plateau period $dV/\phantom{dVdt}dt$ is mainly determined by the gate drive current and the MOSFET feedback capacitance $C_{rss}$. Due to device fabrication differences, the feedback capacitance is different, causing the MOSFET voltage imbalance at this stage.

(3)

Circuit stray capacitance. Relevant studies have shown that [28] even if the driver circuit and the MOSFET are kept the same, the difference in stray parasitic capacitance will still cause uneven turn-off voltage. There are two main sources of stray capacitance. The first is the unavoidable stray capacitance that exists between the gate driver and ground, mainly the transformer coupling capacitance. The second is the parasitic stray capacitance between each port of the MOSFET on the main circuit and ground, which is related to device placement and PCB layout.

(4)

MOSFETs have different rates of current change during the current drop phase ($t_{fi}$). At this point in this interval, the MOSFET can be regarded as an ever-increasing resistance from the drain–source point of view. The unavoidable difference in transconductance between the MOSFETs will result in a difference in the equivalent resistance of each MOSFET, which leads to an imbalance in the MOSFET drain–source voltage.

2.3. The Simulation of the Dynamic Voltage Distribution

Since the voltage imbalance in the turn-off transient is more critical than the voltage imbalance in the turn-on transient, in this section, the factors affecting the voltage equalization during turn-off was verified by PSpice simulation.

The simulation circuit is shown in Figure 6a. The bus voltage $V_{DC}$ was set to 2000 V, and the MOSFET gate resistors were all set to 20 Ω. The MOSFETs were driven by a pulse signal source $V_{pulse}$, and their turn-on and turn-off voltages were +20 V and −2 V, respectively. SCT20280KE is a typical SiC MOSFET co-packaged with SiC-SBD. The co-packaged SiC SBD can protect the MOSFET from being broken down, which is suitable for serially connected applications. The SiC MOSFET applied in the simulation was Rohm’s SCT2080KE.

Table 1. The main parameters of the simulation model.

Parameters		Parameters
Power MOSFET	SCH2080KE	Freewheeling diode	SDT12S60
Bus voltage	2800 V	PWM frequency	50 kHz
Load resistance	200 Ω	Load inductance	200 μH

lists the related parameters of the simulation model.

The $V_{DS}$ voltage unbalanced waveform during turn-off in the theoretical analysis is shown in Figure 6b. To characterize the degree of series SiC MOSFET $V_{DS}$ imbalance at turn-off, the turn-off voltage imbalance factor ${\alpha }_{off}$ is introduced in this paper. For a two-tube series SiC MOSFET, the voltage imbalance coefficient ${\alpha }_{off}$ at turn-off is defined as shown in (18):

$${\alpha }_{off}={\displaystyle \frac{\Delta V_d}{V_d/\phantom{V_{d}2}2}}\times 100\%$$

(18)

The Driver Delay Variance Affection

To verify the effect of the drive delay difference $t_{off}$ on the turn-off voltage distribution of series-connected SiC MOSFETs, the delay of the gate drive signal $V_{pulse}$ of a single MOSFET is adjusted to obtain the voltage distribution difference while keeping other parameters constant. Figure 7 shows the voltage imbalance coefficient ${\alpha }_{off}$ versus the delay difference $t_{off}$.

As shown in Figure 7, ${\alpha }_{off}$ has an approximately linear relationship with $t_{off}$. According to the previous analysis, the difference in gate signal delay will lead to the difference when the MOSFET enters the voltage rise phase ($t_{rv}$). According to the MOSFET switching characteristics, it can be assumed that the gate signal delay difference does not affect the MOSFET drain–source voltage rise rate. The voltage distribution and ${\alpha }_{off}$ can be obtained if the two MOSFET voltage rise rates are the same.

$$\Delta V_d={\displaystyle \frac{t_{off}}{2}}{\displaystyle \frac{d{V}_{DS}}{dt}}$$

(19)

$${\alpha }_{off}={\displaystyle \frac{t_{off}}{V_d}}{\displaystyle \frac{d{V}_{DS}}{dt}}$$

(20)

The MOSFET voltage rise rate was calculated to be 19.3 kV/μs. Due to the fast switching speed of SiC MOSFET, the voltage rise rate was high. Therefore, gate delay drive differences can lead to severe turn-off voltage inhomogeneity.

3. The Novel Series SiC MOSFET Topology Design

The new series SiC MOSFET topology consisted of a series SiC MOSFET, a clamp circuit and its clamp auxiliary circuit, and an energy recovery circuit, which can be used as a power switch in power electronics. The topology is shown in Figure 8. In this section, the inductive clamp circuit was used as the main power circuit to illustrate the working principle and parameter selection principle of the series SiC MOSFET topology, where $V_{DC}$ is the input bus voltage, and $C_{BUS}$ is the bus capacitance.

The topology consists of series SiC MOSFETs M1, M2, and M3. PWM is the main switching tube control signal. The circuit load is an inductor $L_{load}$ and a resistor $R_{load}$, and $D_{load}$ is a continuity diode. $D_{load}$ is the continuity diode, and $R_S$ is the static voltage equalizing resistor. A clamp circuit is connected in parallel with the drain–source of each MOSFET, consisting of clamp diode $D_C$ and clamp capacitor $C_C$. The current-limiting inductor $L_a$ and the auxiliary diode $D_a$ form the clamping auxiliary circuit. The two-tube flyback DC/DC circuit serves as an energy recovery circuit, and its input and output are clamp capacitor $C_{C1}$ and bus capacitor $C_{BUS}$, respectively. $M_{f1}$ and $M_{f2}$ are the switching tubes of the two-tube flyback circuit. Diodes $D_{f1}$ and $D_{f2}$ protect the switching tubes. The $T_F$ is a flyback transformer for voltage isolation and energy transfer.

As the designer was familiar with the clamp circuit and clamp auxiliary loop, this paper only focuses on the energy recovery circuit. The energy recovery circuit has two effects; the first one is to limit the clamp capacitance voltage, and the second one is to transfer the energy accumulated in the clamped capacitor back to the bus capacitor for reuse to reduce losses. The feedback control circuit will determine whether to turn on the energy recovery circuit switching tube based on the sampled capacitor $C_{C1}$ voltage. The energy recovery circuit only works when the capacitor $C_{C1}$’s voltage exceeds the rated value.

3.1. The Energy Recovery Circuit Design

The energy recovery circuit is based on a double-tube flyback DC/DC circuit, as shown in Figure 9. Compared with the single-tube flyback circuit, the double-tube flyback circuit reduces the MOSFET withstand voltage requirement and effectively avoids the voltage spike caused by the transformer leakage inductance during turn-off. The flyback transformer $T_F$ plays the role of electrical isolation and energy transfer, and its turns ratio is given by $N=N_P$/$N_S$. The switching of the switching tubes $M_{f1}$ and $M_{f2}$ is controlled by the output signal $V_{control}$ from the feedback control circuit. Since the energy recovery circuit operates in PFM mode with variable switching frequency, the two-tube flyback circuit designed in this paper operates in DCM mode. Compared with the CCM mode, the flyback circuit in the DCM mode is simple to calculate, easy to realize, and less prone to magnetic saturation.

The working waveform of the energy recovery circuit is shown in Figure 10, and its working process circuit diagram is shown in Figure 11. Its working process is divided into two stages, the primary coil energy storage stage and the secondary coil discharge stage:

(1) Primary coil energy storage stage: this stage of the circuit is shown in Figure 11a. $C_{C1}$ voltage is too high before $t_0$ and the feedback control circuit output $V_{control}$ becomes high at $t_0$. At this time, $V_{C1}$ = $V_0$, and the primary coil current $i_P$ = 0. The switching MOSFET $M_{f1}$ and $M_{f2}$ are turned on, and the primary coil $N_P$ stores energy, and $i_P$ continues to rise. $C_{C1}$ releases energy and $V_{C1}$ decreases from $V_0$. The pulse signal $V_{control}$ lasts for $t_{pulse}$. During the phase [$t_0$–$t_1$], the inductance $L_P$ of the primary coil of the flyback transformer resonates with the capacitance $C_{C1}$ and $i_P$ can be assumed to rise linearly during this period:

$$i_P\left(t\right)={\displaystyle \frac{V_0}{L_P}}(t-t_0)$$

(21)

At this stage, the secondary coil current $i_S$ = 0. $D_{f3}$ is off and it is subjected to a reverse voltage $V_d$:

$$V_d={\displaystyle \frac{V_{C1}}{N}}+V_{DC}$$

(22)

(2) Secondary coil discharge stage: this stage of the circuit is shown in Figure 11b. At $t_1$, $V_{control}$ becomes low and $i_P$ reaches its maximum value $I_{Pmax}$. $M_{f1}$ and $M_{f2}$ are switched off and the primary coil $N_P$ releases energy to the secondary coil $N_S$.

$$I_{Pmax}=t_{pulse}{\displaystyle \frac{V_0}{L_P}}$$

(23)

During the phase [$t_0$–$t_1$], $V_{C1}$ continues to fall, and, at the moment $t_1$, $V_{C1}$ falls to $V_1$.

$$V_1=V_0\sqrt{(1-{\displaystyle \frac{t_{pulse}^2}{2L_P{C}_{C1}}})}$$

(24)

The secondary coil $N_S$ back-excites the current at $t_1$, when $i_S$ reaches its maximum value $I_{Smax}$ = N ·$I_{Pmax}$, as shown in Figure 11b. In the [$t_1$–$t_2$] stage, $D_{f3}$ conducts, the secondary coil $N_S$ releases energy to the bus capacitance $C_{BUS}$, and the $i_S$ decreases linearly:

$$i{s}_S\left(t\right)=t_{pulse}{\displaystyle \frac{V_0·N}{L_P}}-{\displaystyle \frac{V_{DC}}{L_P}}(t-t_1)$$

(25)

where $L_S$ is the transformer secondary coil inductance. The [$t_1$–$t_2$] phase duration $t_S$ is

$$t_S={\displaystyle \frac{I_{Smax}·L_S}{V_{DC}}}=t_{pulse}{\displaystyle \frac{V_0}{V_{DC}·N}}$$

(26)

During the [$t_1$–$t_2$] stage, there is a reflected voltage $V_{NP}$ on the primary coil of the transformer, which satisfies (27). Due to the presence of transformer leakage inductance, relatively large voltage spikes will be generated when $M_{f1}$ and $M_{f2}$ are switched off at $t_1$. The leakage inductance energy of the primary coil $N_P$ can be returned to the capacitor $C_{C1}$ through $D_{f1}$ and $D_{f2}$ to avoid voltage spikes to protect the switching tube.

$$V_{NP}=N(V_{DC}+V_D)$$

(27)

$I_S$ drops to zero at $t_2$, $D_{f3}$ will turn off, and the circuit operates in DCM mode. To ensure that the flyback circuit operates in intermittent mode, (28) needs to be satisfied:

$$t_S+t_{pulse}=t_{pulse}(1+{\displaystyle \frac{V_0}{V_{DC}·N}})<{\displaystyle \frac{1}{f_{max}}}$$

(28)

Without considering losses, if the flyback circuit operates at a frequency of $f_{max}$, the power delivered is $P_S$, which is also the energy released by $C_{C1}$. The increase in $C_{C1}$ energy due to the action of the clamp circuit and the clamp auxiliary circuit will be passed back to the bus capacitor through the flyback circuit, ensuring that $V_{C1}$ does not become too high.

$$P_S={\displaystyle \frac{1}{2}}{t}_{pulse}^2·V_0^2·{\displaystyle \frac{f_{max}}{L_P}}$$

(29)

3.2. The Feedback Control Circuit Analysis

The feedback control circuit of the energy recovery circuit designed in this paper is shown in Figure 12, where $V_{sample}$ is the voltage $V_{C1}$ of the clamp capacitor $C_{C1}$ sampled by the Hall voltage sensor. To suppress the noise interference of the power circuit on the sampled output signal, $V_{sample}$ is followed by an active low-pass filter to filter out the high-frequency noise. The monostable trigger circuit will be triggered at the rising edge of the input signal and output a control signal $V_{control}$ with a certain pulse width. The $V_{control}$ is the input signal of the energy recovery circuit driver circuit, which is used to control the energy recovery circuit switching tube. The maximum voltage allowed by the clamping capacitor is $V_{C1max}$; when $V_{C1}$ exceeds $V_{C1max}$, the sampled signal $V_{sample}$ will be larger than the reference signal $V_{ref}$. At this time, COMP1’s output is high, indicating that the capacitor $C_{C1}$’s voltage is too high.

The SP signal is a high-level pulse width small period square wave that determines whether the comparator COMP1’s output is valid or not. When the short pulse signal SP goes high, there are two cases for the comparator COMP1’s output. If COMP1’s output is low, it indicates that $V_{C1}$ is lower than the allowed maximum voltage $V_{C1max}$, and the output of AND2 is low. The monostable trigger circuit output is low. If COMP1’s output is high, it indicates that $V_{C1}$ is higher than the allowed maximum voltage $V_{C1max}$. The output of AND2 changes from low to high and triggers the monostable trigger circuit. The monostable trigger circuit will output a high-level pulse to control the energy recovery circuit. As the comparator COMP1’s output is only effective when the short pulse signal SP is high, this can effectively reduce the false trigger caused by sampling error or comparator output noise. The frequency of the SP signal is the maximum operating frequency of the energy recovery circuit. The relative waveforms are shown in Figure 13.

(1)

Before $t_0$, since $V_{C1}$ is high enough, the $V_{sample}$ will be higher than $V_{ref}$, and then, COMP1’s output is high. However, SP is low and AND2’s output is still low.

(2)

At $t_0$, SP becomes high and lasts for a short time. Since the COMP1 output is high, the AND2 output changes from low to high. This rising edge will trigger a monostable trigger to generate a $V_{control}$ signal with a pulse width of $t_{pulse}$ for controlling the energy recovery circuit. The operation of the energy recovery circuit is shown in Figure 10. During phase [$t_0$–$t_2$], the switching tube of the energy recovery circuit is switched on. During this phase, the $V_{C1}$ continues to drop and energy is transferred to the primary coil of the flyback transformer.

(3)

At $t_2$, $V_{control}$ becomes low. The switching tube of the energy recovery circuit turns off, and the transformer’s secondary coil back-excites the current. Although $V_{C1}$ has dropped to the permissible value, the comparator COMP1’s output is still high. This is due to the delay of the Hall voltage sensor, which does not reduce the COMP1 output until the moment $t_3$ after the $t_{SD}$ time. During the [$t_2$–$t_4$] phase, $V_{C1}$ may rise due to the activation of the clamp capacitor and the clamp auxiliary circuit.

(4)

At $t_4$, the SP signal becomes high and the period of the SP signal is $t_{SP}$. If $V_{C1}$’s voltage rises more in the phase [$t_2$–$t_4$], causing the COMP1 output to be high at $t_4$, the monostable flip-flop will be activated next, repeating the process (1)–(3). If $V_{C1}$ is small and does not exceed the predetermined voltage in the phase [$t_2$–$t_4$], the COMP1 output is low at $t_4$, the AND2 output is low and the monostable flip-flop will not operate. The monostable circuit operation will be decided Until the next rising edge of the SP signal according to the COMP1 output.

If the switching process of the series-connected MOSFETs and the driver circuit varies greatly, it will result in a large ripple voltage of each clamp capacitor during the switching process. In this case, $V_{C1}$ will rise rapidly. To limit the rise of $V_{C1}$, the energy recovery circuit switching frequency must be larger; in contrast, if the series-connected MOSFETs and drive circuits are highly consistent, the switching process of each clamp capacitor ripple voltage is smaller. In this situation, $V_{C1}$ rises slowly, and the energy recovery circuit switching frequency is small. Ideally, if each MOSFET switching process is identical, $V_{C1}$ will not rise. At this time, the energy recovery circuit operating frequency is zero. In summary, the operating frequency of the energy recovery circuit depends on the degree of difference in the switching process of each MOSFET in the series-connected MOSFET.

Based on the above analysis, it can be seen that, if COMP1’s output signal is high every time the SP signal is high, the monostable flip-flop will continuously output pulses, which occurs when the difference in the switching process of each MOSFET is too large. Therefore, the maximum frequency of the flyback circuit operation is equal to the frequency of the SP signal $f_{max}$ = 1/$t_{SP}$. According to (29), the maximum power delivered by the flyback circuit is $P_{Smax}$.

$$P_{Smax}={\displaystyle \frac{1}{2}}{t}_{pulse}^2·V_0^2·{\displaystyle \frac{f_{max}}{L_P}}$$

(30)

The maximum power $P_{Smax}$ in the worst case needs to be taken into account when the flyback circuit operates at the maximum frequency $V_{C1}$. Consideration needs to be given to the value of the energy that will be accumulated by the clamp capacitor due to the clamping action when the difference in drive delay between the MOSFETs is at its maximum, and $P_{Smax}$ needs to be ensured to be greater than the amount of energy that will be accumulated due to the clamping action. For the three-tube tandem SiC MOSFET topology in this paper, when only the turn-off process is considered, it is assumed that the M3 drive signal is delayed $t_{D1}$ to M1, while the M2 drive signal is delayed $t_{D2}$ to M1. Then, the maximum power $P_{Smax}$ of the flyback circuit needs to satisfy (31):

$$\left(t_{D1}+t_{D2}\right)·I_{load}·{\displaystyle \frac{V_{DC}}{3}}·f_{PWM}<P_{Smax}$$

(31)

If $t_{D1}$ and $t_{D2}$ are assumed to be 100 ns and 200 ns, respectively, it is a serious case for series-connected SiC MOSFETs. When the bus voltage is 2800 V and the load current is 10 A, the maximum power of the flyback circuit needs to be higher than 140 W. With the turn-on phase considered, the maximum power of the flyback circuit should be greater than the calculated value in (31), which can be taken to be about 1.5–2 times the calculated value. For series n-MOSFETs, the maximum capacitance of $V_{C1max}$ needs to be set to be slightly larger than the equilibrium voltage $V_{DC}$/n, and, at the same time, $V_{C1max}$ needs to be smaller than the breakdown voltage of the MOSFET. In this paper, $V_{C1max}$ is larger than $V_{DC}$/n by 30–50 V. If $V_{control}$ pulse width is set to 10 μs, and the inductance of the primary coil of the flyback transformer is set to 1.5 mH, the maximum current of the primary coil is 6.5 A. The maximum power of the designed flyback transformer is 210 W, and it can meet the design requirements. Flyback circuit design needs to consider the switching device voltage stress. This paper takes the margin of switching device voltage stress as 20%. According to (22), the diode $D_{f3}$ is subjected to the maximum reverse voltage at $t_0$. Its rated reverse voltage $V_F$ needs to satisfy the relation (32):

$$0.8V_F>{\displaystyle \frac{V_0}{N}}+V_{DC}$$

(32)

According to (27), $M_{f1}$ and $M_{f2}$ are subjected to the maximum reverse voltage at $t_1$. The rated voltage $V_{MOS}$ of $M_{f1}$ and $M_{f2}$ needs to satisfy the relation (33):

$$2\times 0.8V_{MOS}>N(V_{DC}+V_D)+V_1$$

(33)

In this paper, we took N = 0.316, and set $V_0$ = 930 V and $V_1$ = 950 V. According to (22), the diode reverse voltage $V_F$ is >7200 V, which was realized by connecting six 1200 V SiC SBDs in series. According to (27), $V_{MOS}$> 1146 V, which was realised by using 1200 V SiC MOSFETs.

4. The Experimental Results

A prototype was also fabricated and tested to verify its effectiveness. The overall circuit of the test is shown in Figure 14, where M1 and M2 are two SiC MOSFETs connected in series. The prototype is shown in Figure 15. The main parameters of the converter are in

Table 2. The relative parameters of the prototype.

Circuit Parameters		Circuit Parameters
The main MOSFET	SCH2080KE	Diode $D_1$ and $D_2$	SCS240KE2
Bus voltage	600 V	Working frequency	50 kHz
Load inductance	400 μH	Output capacitance	340 μF
Clamp capacitance	2 μF	Clamp diode $D_C$	ES1J
Auxiliary diode	ES1J	Current limiting Inductance $L_a$	15 μH
SP working frequency	10 kHz	Static Resistor $R_S$	100 kΩ

, and the parameters of the SiC MOSFET are listed in

Table 3. The parameters of the SiC MOSFET.

Break voltage	1200 V	Leakage current	400 μA
Threshold voltage	4.0 V	on-state resistance@$v_{GS}$ = 18 V	80 mΩ
Input capacitance	1850 pF	Output capacitance	175 pF

.

In this paper, the input voltage of the main Buck circuit was set to 600 V, and the duty cycle of the Buck circuit was set to 50%, which was used to complete the 300–600 V Buck conversion. The average current of the main inductor $L_{load}$ was 10 A; then, the power of the main circuit design was 2.8 kW.

To verify the effectiveness of the strategy, the gate resistors of M1 and M2 were set differently; the M1 gate resistance was set to be 33 $\omega$, while the M2 was 0 $\omega$. M1 and M2 were directly connected in series without applying other circuits, and the drain–source voltages of the two MOSFETs, $V_{DS1}$ and $V_{DS2}$, are shown in Figure 16.

Figure 16b shows the voltage distribution during turn-off. Due to the small M2 gate resistance, M2 turns off first and $V_{DS2}$ rises first during the turn-off interval. The delay difference between the two MOSFETs during turn-off is 200 ns. In this case, $V_{DS2}$ rises directly to the bus voltage of 600 V. M1 is then turned off, resulting in severe voltage unevenness during turn-off. The difference between the two $V_{DS}$ in the static state is slightly reduced due to the static voltage equalizing resistor. This experiment verifies that different driving delays will cause voltage unevenness, which seriously affects the safe operation of series-connected SiC MOSFETs.

The tested results in the same case with the proposed strategy are shown in Figure 17. The voltage distribution during turn-off is slightly different from cycle to cycle because the clamp capacitor voltage changes from cycle to cycle. During both turn-on and turn-off intervals, the maximum MOSFET voltage does not exceed 320 V. Comparing with Figure 16, it can be seen that this topology can effectively limit the drain–source voltage rise, and ensure that the dynamic and static voltages of series-connected SiC MOSFETs are balanced.

The variation curves of the two MOSFET $V_{DS}$ during switching are shown in Figure 18. Figure 18b shows the turn-off detail. It can be seen that M2 turns off first, causing $V_{DS2}$ to start rising. When $V_{DS2}$ rises to the clamp capacitor voltage, the clamp circuit turns on, and $V_{DS2}$ stops rising. Then, M1 turns on, and $V_{DS1}$ starts to rise. It can be seen that this topology can limit the MOSFET drain–source voltage from being too high during the shutdown.

Figure 18b shows the curve of $V_{DS}$’s change during the turn-on process. M2 turns off first, leading $V_{DS2}$ to start falling. There is no voltage spike in the turn-on process.

The experimental results are the same as the analysis above. The voltage spike in the turn-off interval is suppressed from 600 V to 320 V.

5. Conclusions

A comparison was made between state-of-the-art approaches and the approach proposed in this work; the results are shown in

Table 4. The comparison among state-of-the-art approaches.

The Approaches	Extra Devices	Complexity	Energy Recovery
This work	10 power devices and 2 analog devices	Moderate	Yes
Ref. [29]	11 analog devices	High	No
Ref. [30]	7 analog devices	High	No
Ref. [31]	3 power devices and 6 analog devices	High	No
Ref. [32]	3 power devices and 6 analog devices	High	No

. Compared to other approaches, this work achieved energy recovery at the cost of six power devices. Due to the relative simplicity of the control method in this work, the number of analog devices used was low.

Based on the analysis above, when increasing the number of series-connected SiC MOSFETs, this method only requires adding simple auxiliary circuits to the device without changing the energy recovery circuitry, which has a small impact on the circuit complexity. The energy recovery circuit uses a transformer and is the largest part of the auxiliary circuit. Since the energy recovery circuit operates at a lower frequency and processes less energy per cycle, it has the possibility of magnetic integration with the magnetic devices of the main circuit under certain conditions.

Based on the analysis above, this strategy has some advantages. Firstly, the approach is effective; the voltage spike is suppressed from bus voltage 600 V to 320 V. Secondly, the strategy realizes energy recovery, which is beneficial for efficiency. Thirdly, the drive strategy is simple; fewer analog devices are used.