An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Abstract

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

1. Introduction

1.1. Background

Ubiquitous smart sensory systems require sub-MHz-bandwidth analog-to-digital converters (ADCs) with high resolution and excellent power efficiency. Generally, the key applications of these sensors demand ADCs with a SNR exceeding 85 dB and a bandwidth of hundreds of kHz. However, for sub-MHz-bandwidth ADCs, a low sampling frequency results in a small oversampling ratio (OSR), thus limiting the achievable resolution of discrete-time (DT) delta-sigma modulators (DSMs). It is unrealistic to blindly increase the quantizer bits as the digital-to-analog converter (DAC) complexity would exponentially increase the power and area. High-order single-loop DSMs are prone to instability, decreasing the achievable high maximum stable amplitude (MSA) [1]. Multi-stage noise shaping (MASH) topology can achieve high-order noise-shaping while avoiding stability issues. However, due to the strict requirement of high DC gain in the integrators, achieving low power is difficult while minimizing the leakage of the first-stage quantization error [2,3]. To overcome these disadvantages, a compelling alternative to MASH is the sturdy MASH (SMASH). They can achieve the same noise-shaping properties without any matching requirements between the analog and digital filters, which significantly eases the stress of the integrators [4]. Therefore, SMASH ADCs offer good immunity to circuit imperfections and non-idealities, making them robust and suitable for practical applications.

1.2. Literature Review

In [4], a DT 2-2 SMASH is proposed with an OSR of only 16. It achieves a maximum stable amplitude (MSA) of −1.5 dBFs while performing fourth-order noise shaping. A 35 dB DC gain is enough to achieve the maximum signal-to-quantization-noise ratio (SQNR). In [5], a continuous-time (CT) 3-1 SMASH is proposed to address quantization error extraction delay. Also, this topology fully cancels the first stage’s quantization noise, resulting in an additional 6 dB signal-to-quantization-noise ratio improvement. However, the previous SMASH topologies require an explicit quantization noise extraction circuit, increasing the design complexity. In [6], the CT-correlated dual-loop SMASH (CDL SMASH) is proposed to remove the quantization noise extraction and the DAC of the second loop. However, the two loop filters need to be the same for the topology to work properly. CT DSMs define the integrators’ coefficients using the resistor–capacitor product, while the capacitor ratio controls the coefficients in the DT DSM. Therefore, a discrete-time (DT) DSM is more robust in achieving a high resolution over process–voltage–temperature (PVT) variations because of the inherently good matching of the analog filter coefficients [7]. These are summarized in

Table 1. Summary of different topologies.

	Topology	Extraction	Resolution	Num. of DACs	Loop Filter Req.	Gain Req.
MASH	DT 2-2	No √	High	2 √	High ｘ	High ｘ
SMASH	CT 3-1 [5]	Yes  ｘ	High	3  ｘ	Low √	Low √
	CT 2-2 [6]	No √	Medium	2 √	High ｘ	Low √
	DT 2-2 [4]	Yes ｘ	Medium	3 ｘ	Low √	Low √
Proposed	DT CDL 2-2	No √	Medium	2 √	Low √	Low √

.

Operational transconductance amplifiers (OTAs) are the most critical component in a DSM since they determine noise performance and power consumption. Dynamic amplifiers (DAs), benefitting from the lack of static current, are preferred in state-of-the-art DSM designs. Among different types of DAs, a floating inverter amplifier (FIA) is power-efficient and does not need common-mode feedback (CMFB), which is widely used in DSMs and successive approximation register (SAR) ADCs [8,9,10,11]. But the DC gain of a single-stage FIA is only about 30~40 dB, and it becomes worse at higher speeds. In [8], a two-stage FIA is proposed to provide a higher DC gain. However, it faces the difficulties of instability and thermal noise. In [9], a three-stage FIA is proposed. Still, it faces the same difficulty as the two-stage FIA. In [10], a single-stage FIA with a correlated level shifting (CLS) technique is proposed, avoiding the extra thermal noise. Because of the self-quenching property of the FIA, dynamic body biasing (DBB) is adopted to help CLS operation. Though a DC gain beyond 60 dB can be ensured, sophisticated timing is needed, which dissipates large power on clock generators. The cascoded FIA is a good choice as it does not generate extra input-referred noise compared to the two-stage FIA and is still able to provide enough dc gain [11].

1.3. Contributions

In this work, a DT SMASH DSM with fourth-order noise shaping employing a self-cascoded FIA is presented. The CDL SMASH is adopted to help remove the explicit first-stage quantization error extraction. In addition, the integrators are designed to work in a ping–pong way to relax the speed requirement on the FIAs. To suppress the nonlinear distortion from the mismatch between the unit capacitors in the capacitive DAC (CDAC), two data-weighted averaging (DWA) circuits are introduced. Together, a prototype achieving 14-bit resolution with 100 kHz signal bandwidth is designed and implemented to meet low power requirements.

This paper is structured as follows. Section 2 briefly presents the CDL SMASH structure. Section 3 proposes the self-cascoded FIA and describes the circuit implementation of this modulator. In Section 4, the measured results of the proposed modulator architecture are presented. Section 5 draws the conclusions.

2. Proposed DT DSM Architecture

2.1. Overview of MASH and SMASH DSMs

For sub-MHz-bandwidth DSMs, a MASH topology can achieve high-order noise-shaping without stability issues. By cascading multiple stages, each with its noise-shaping transfer function, the quantization noise from each stage is shaped and suppressed in subsequent stages, effectively pushing it to higher-frequency regions. The output of MASH is as follows:

$$V_{MASH}=ST{F}_{1A}ST{F}_{2D}X+\left(NT{F}_{1A}ST{F}_{2D}-NT{F}_{1D}ST{F}_{2A}\right)E_1-NT{F}_{1D}NT{F}_{2A}{E}_2$$

(1)

where STF_i and NTF_i are signal and noise transfer functions of the ith-loop, and subscripts A and D represent analog and digital transfer functions, respectively. If the first loop utilizes the low-distortion structure, the output of the H₁ is −Z_nE₁, which is the product of the quantization noise of the 1st loop and the delay of n cycles. As a result, it can feed into the input of the second loop directly without E₁ extraction DACs, as shown in Figure 1. However, these structures require high-gain amplifiers to minimize the quantization error leakage due to the mismatch between analog and digital filters. To overcome this difficulty, the SMASH topology is proposed, as shown in Figure 2a. The DC gain requirements of the amplifiers in SMASH are not as high as those in MASH. The output of the SMASH can be given as in [4,12].

$$V_{SMASH}=ST{F}_{1}X+NT{F}_1\left(1-ST{F}_2\right)E_1-NT{F}_{1}NT{F}_2{E}_2$$

(2)

Instead of eliminating E₁, the quantization noise E₁ and E₂ are both shaped by NTF₁NTF₂ if 1 − STF₂ = NTF₂, which releases a high DC gain requirement. If adopting the low-distortion structure in the SMASH topology, the output of the H₁ is not −Z_nE₁ as the second stage is subtracted from the first loop and changes the NTF of the first loop. As Figure 2b shows, the output of the first loop is V_H1, and it satisfies the following:

$$V_{\mathrm{H}1}=-{\displaystyle \frac{\left(1+H_1+H_2+H_1{H}_2\right)H_1{E}_1}{\left(1+H_1\right)\left(1+H_1+H_2\right)}}+{\displaystyle \frac{H_1{E}_2}{1+H_1+H_2}}$$

(3)

Equation (3) shows that V_H1 is not a simple combination of E₁ and E₂. In contrast, E₁ and E₂ have undergone a series of polynomials. The overall output of the SMASH with low-distortion structure is as follows:

$$\begin{array}{ll}V& =X+{\displaystyle \frac{E_1(1+H_1+H_2+H_1{H}_2)}{(1+H_1)(1+H_1+H_2)}}-{\displaystyle \frac{E_2}{1+H_1+H_2}}\\ & =X+{\displaystyle \frac{NT{F}_1}{NT{F}_1+NT{F}_2-NT{F}_1\cdot NT{F}_2}}{E}_1+{\displaystyle \frac{NT{F}_1+NT{F}_2-NT{F}_1\cdot NT{F}_2}{NT{F}_1\cdot NT{F}_2}}{E}_2\end{array}$$

(4)

It can be seen that the quantization noise E₁ and E₂ are not shaped by NTF₁NTF₂, which is contrary to the principle of SMASH. Therefore, the low-distortion structure is not applicable in a conventional SMASH.

2.2. CDL SMASH DSMs

To avoid the dedicated E₁ extraction operation, the CDL SMASH is proposed in [12]. By adopting the low-distortion structure in the traditional SMASH and removing the feedback DAC in the cascaded loop, the output of the H₁ can be used directly as the input to the second loop and the second-stage quantizer, as shown in Figure 3. The transfer function of V₁, V₂ and V here are given by

$$V_1=X-{\displaystyle \frac{H_1}{1+H_1}}{V}_2+{\displaystyle \frac{1}{1+H_1}}{E}_1$$

(5)

$$V_2=-{\displaystyle \frac{H_1\left(1+H_2\right)}{1+2H_1+H_1{H}_2}}{E}_1+{\displaystyle \frac{1+H_1}{1+2H_1+H_1{H}_2}}{E}_2$$

(6)

$$V=V_1+V_2=X+{\displaystyle \frac{1}{1+2H_1+H_1{H}_2}}(E_1+E_2)$$

(7)

From Equations (5)–(7), H₁ = H₂ = H is necessary for the polynomial 1 + 2H₁ + H₁H₂ to be merged into (1 + H)². Therefore, the quantization noise can be shaped without causing any stability problems, and the resulting output V can be written as follows [12]:

$$V=X+{\left({\displaystyle \frac{1}{1+H}}\right)}^2\left(E_1+E_2\right)$$

(8)

To ensure the system’s stability, the coefficient of the two loops must be equal. However, the resistor R and capacitor C in CT DSM are susceptible, and the degree of variation differs. The capacitor ratio determines the coefficients in the DT DSM, while the coefficients of the CT DSM depend on the resistor–capacitor product [13]. Consequently, DT ADC outperforms CT ADC in terms of PVT stability. As a result, this paper adopts the DT operation to obtain superior PVT stability.

After a closer look, the principle of the CDL SMASH is similar to that of a Zoom ADC. The Zoom ADC combines the advantages of the SAR and DSM that can achieve high DR and high resolution [14,15,16,17]. The input signal is sent into the SAR ADC to obtain a coarse conversion at the first, and the references of the follower ΔΣ ADC are adapted by the result of the SAR. As a result, the requirement of ΔΣ ADC is relaxed as it just needs to deal with the residue of the SAR. The first stage of the SMASH can also be regarded as coarse conversion; then, the quantization noise E₁ is processed by the second loop, which is equivalent to the fine DSM of the Zoom. Finally, the output of the second loop V₂ and the first loop output V₁ are combined to obtain the total output V, which can be modeled as the combination of the Zoom. The comparison between the Zoom ADCs and the adopted SMASH architecture is shown in Figure 4. Zoom ADC’s demand for the gain of the amplifier is higher than that of SMASH. The SQNR_max of the 3-bit 4th-order ZOOM is 10 dB lower than 3 bit 2 + 2 CDL SMASH. The 3-bit 2 + 2 CDL SMASH only requires a 30 dB DC gain to achieve 110 dB SQNR, while the 3-bit 4th-order Zoom structure needs more than 40 dB DC gain to obtain the maximum SQNR, which is still less than that of SMASH. As a result, the adopted 2 + 2 CDL SMASH performs better than the same-order Zoom ADC in both quantization noise suppression and the gain requirements of the amplifiers.

3. Circuit Implementation

3.1. The Proposed Self-Cascoded FIA

FIAs have been widely used in ADCs for their high energy-efficiency owing to their current-reusing nature and lack of static consumption; however, they only have a limited DC gain of around 30 dB at the operating frequency of 10 MHz. In this work, the DC gain of the 1st integrator of 2 + 2 DT SMASH is required to be more than 40 dB, and the swing has to achieve 180 mV to realize the maximum SQNR. To increase DC gain, multi-stage FIAs that cascade two or more single-stage FIAs are proposed in [8,9]. Unfortunately, the input-referred in-band noise is amplified by a product of G_m2R_o1, where G_m2 is the conductance of the second stage, and R_o1 is the output resistance of the first stage. Also, cascading induces stability issue, which leads to design difficulties.

This work adopts a self-cascoded FIA to achieve the required DC gain. The schematic is shown in Figure 5. The gates of the cascoded transistors are connected to the input, avoiding the additional dedicated bias circuits and extra power. The following cascode transistors must be low-voltage threshold (LVT) devices that ensure both main input pairs function properly. As shown in Figure 5, the drain and source voltage of the M1 and M2 should satisfy the following:

$$V_{\mathrm{G}}-V_{\mathrm{S}}-V_{\mathrm{TH}1}>0$$

(9)

$$V_{\mathrm{G}}-V_{\mathrm{X}}-V_{\mathrm{TH}2}>0$$

(10)

One can rewrite Equation (10) as

$$V_{\mathrm{G}}-V_{\mathrm{TH}2}-V_{\mathrm{S}}>V_{\mathrm{X}}-V_{\mathrm{S}}$$

(11)

If V_TH1 = V_TH2, one obtains

$$V_{\mathrm{G}}-V_{\mathrm{TH}1}-V_{\mathrm{S}}=V_{\mathrm{DSAT}1}>V_{\mathrm{X}}-V_{\mathrm{S}}=V_{\mathrm{DS}1}$$

(12)

Thus, the transistor M₁ is in the linear region. Therefore, LVT devices are adopted as the cascode transistors to make the input transistors work in the saturation region. In this way, the proposed structure acts like an ordinary cascode FIA, providing large DC gain.

Figure 6 shows that the simulated DC gain of the self-cascoded FIA is beyond 45 dB and the −3 dB output swing is about 310 mV under a typical NMOS and typical PMOS (TT) corner. The DC gain is sufficient for the SMASH system under different corners even for slow NMOS and slow PMOS (SS) corners. Owing to the higher threshold voltage, the transistors are almost off at the SS corner, the self-cascoded FIA’s DC gain decreases drastically. Though a DC gain of greater than 30 dB is still enough, this can be alleviated by using a larger reservoir capacitor (C_RES) in exchange with larger area and power consumption. Since the amplifiers largely determine the performance of the modulator. The amplifier’s robustness against temperature variations is also significant. Figure 7 shows the simulated DC gain versus temperature. It shows that a DC gain of 30 db can be assured except for SS corner under 0 °C, as low temperature makes the threshold voltages of the transistors even higher.

3.2. 2+2 DT SMASH DSM Implementation

Figure 8 shows a system-level block diagram of the DT DSM comprising two asynchronous SAR ADCs and two second-order loop filters. The first loop utilizes the low-distortion structure to circumvent the extraction of quantization noise E₁ and the DAC of the second loop is removed, as introduced in CDL SMASH. Finally, the outputs of the two second-order loops are summed directly to generate the total output V, which, therefore, realizes fourth-order noise-shaping.

The circuit implementation (single-ended version) and timing diagram of the DT SMASH are shown in Figure 9. The first and second integrators are realized with the proposed self-cascoded FIA. The other integrators are conventional FIA because of the relaxed DC gain requirement of the second stage. This also explains the coarse–fine operation of this modulator. The quantizer of each loop is a 3-bit SAR ADC, further improving the MSA and reducing the internal swing of the loop filter.

Generally, in multi-loop DT DSMs, the passive adders and SAR quantizers occupy a part of the time to finish quantization, sacrificing the integration time of the amplifier. As a result, this places great demand on the settling capability of the amplifiers, which increases power consumption. In this work, all integrators except the first integrator work in a ping–pong method, which is realized by simultaneous sampling (integration) during φ_2A (φ_2B). The duty cycles of φ_2A and φ_2B that are the binary frequencies of φ₂ are one quarter of the value. The quantizers finish the quantization within φ₁, and all the integrators start working during the integration phase φ₂. Taking the second stage as an example, the two sampling capacitors function in a ping–pong way. The output voltage of the first stage V_out1 is stored in C_L11 during φ_2BD initially. Then, the charge would be saved in C_L12 instead during φ_2AD when entering the next cycle, and the charge stored in C_L11 is transformed to CINT2 at the same time.

According to the coefficients of the NTF and the thermal noise requirement, the sampling and integrating capacitance are designed as C_S1 = 2.5 pF. The sampling capacitors are also reused as feedback capacitors, consisting of seven-unit-element capacitors in parallel. To mitigate the mismatch of the CDACs, two DWAs are performed. C_F1 samples the input as the feedforward branch, which is also implemented as the capacitor array of the first SAR quantizer. The passive capacitive adders are used to avoid a dedicated power-hungry amplifier.

4. Measurement Results

The prototype is fabricated using a 55 nm CMOS process. Figure 10 shows the chip photo of the designed DT SMASH DSM with an active area of 0.66 mm².

Figure 11 plots a 2²²-points output spectrum with a 7.2 kHz and −1.4 dBFS input signal. With a sampling frequency of 10 MHz and an OSR of 50, the prototype with DWA OFF achieves an SNDR, SNR, and SFDR of 75.3 dB, 86.9 dB, and 79.2 dB in a signal bandwidth of 100 kHz. The large harmonics are mainly limited by the mismatch between the unit elements of the feedback capacitor. These can be improved to 88.0 dB, 88.6 dB, and 102.2 dB, respectively, with DWA ON.

Figure 12 shows the measured SNR and SNDR as a function of the input amplitude, and the measured dynamic range (DR) is 85.3 dB. As the technology node shrinks, placing more circuits in the digital domain results in better efficiency. Therefore, apart from the four FIAs and the comparators in SAR ADCs, the other circuits are implemented in the digital domain. In this design, as shown in Figure 13, the overall power consumption is 249.1 μW at a supply voltage of 1.2 V and an operating clock speed of 10 MHz, from which 192.24 μW is for the analog part, 36.41 μW is for the reference, and 20.42 μW is for the digital circuitry. The corresponding SNDR-based Schreier figure-of-merit (FoMs) is 174.0 dB.

The low-frequency output spectrum is illustrated in Figure 14. It can be seen that without chopping, the modulator is dominated by the intrinsic 1/f noise of the first amplifier, while the noise of the subsequent stage is suppressed. The flicker noise can be removed by chopping, achieving a 1/f noise corner frequency of less than 50 Hz.

The measured SNDR of the three different chips across different analog supply voltage AVDDs is shown in Figure 15. The proposed modulator can work properly with ±5% supply variation with SNDR variations of less than 3 dB. When the supply voltage is below 1.12 V, the SNDR of the two chips drops sharply because the self-cascoded FIA does not work properly at such a low supply voltage, which is similar with the ss corner.

Table 2. Performance summary and comparison with state-of-the-art works.

	[19]	[20]	[21]	[18]	[2]	This Work
Architecture	Incre- mental	Incre- mental	CTDSM	CT NSSAR	DT SMASH	DT SMASH
Shaping order	3	-	4	1	4	4
Technology [nm]	180	180	180	65	65	55
Chip area [mm2]	0.363	0.716	2.85	0.03	0.34	0.66
Supply [V]	3	3	1.8	1	1.2	1.2
Bandwidth [kHz]	100	625	250	62.5	20,000	100
OSR	150	44	64	16	12	50
SNDR [dB]	86.6	96.6	103.5	77.3	72.9	88.0  ***
* ENOB [bit]	14.1	15.8	16.9	12.5	11.8	14.3
Power [μW]	1098	2770	24,000	13.5	20,400	249.1
** FoMS [dB]	171.1	173.6	173.7	174.0	162.8	174.0

* ENOB = (SNDR − 1.76)/6.02; ** FoM_S = SNDR + 10log10(Bandwidth/Power); *** 84–91 dB over process variation and temperature −25–80 °C. The bold in the table highlights the results of this work.

summarizes the performance and compares it with state-of-the-art DSMs with similar bandwidths. It shows the advantage of the CDL SMASH topology and the proposed self-cascoded FIA in improving energy efficiency. The proposed ADC is a compact and energy-efficient solution for audio and sensor applications that require high resolution at a sub-MHz bandwidth. Compared to the work in [18] with similar energy efficiency, this work avoids the use of sophisticated linearization techniques and is more capable of achieving high resolution because of high-order noise shaping. On the other hand, the implementation of a large C_RES occupies a considerable area.

5. Conclusions

This paper presents a sub-MHz BW DT SMASH DSM for smart sensor systems. The CDL SMASH architecture is adopted for its simplified design as well as the other advantages of using the SMASH structure. The first loop of the SMASH utilizes a low-distortion structure to avoid the extraction of quantization noise E₁. The DAC of the second loop is removed, significantly reducing the area budget. Compared with the traditional MASH, the SMASH has lower requirements for the DC gain of amplifiers. Meanwhile, FIA is an energy-efficient amplifier which does not need extra bias circuits. However, a single-stage FIA can only obtain a modest DC gain of about 30 dB at an operating frequency of 10 M; therefore, this work applies a self-cascoded FIA to obtain a higher DC gain in exchange for the reduced output swing. Moreover, chopping is adopted to remove the 1/f noise without any artifacts. This prototype is fabricated and tested. The measured Schreier FoM of 174.0 dB is competitive compared to that of other state-of-the-art ADCs with similar bandwidths. In conclusion, we presented a highly energy-efficient, robust, and high-performance DT DSM. Furthermore, this work shows the potential of exploring PVT-robust gain-boosting techniques and advanced system architectures in ADC designs.