Smith Chart-Based Design of High-Frequency Broadband Power Amplifiers

Abstract

This paper presents a comprehensive study on the design and performance of a high-power amplifier (PA) covering a broad frequency band from 0.1 to 4.8 GHz. Leveraging a 10 W GaN device, the amplifier achieves output power levels surpassing 10 W across the entire frequency band. Furthermore, the power-added efficiency (PAE) of the amplifier ranges from 47% to 59%, indicating its energy-efficient operation. With consistent gain characteristics varying between 7 and 15 dB, the design ensures reliable signal amplification for diverse applications. Notably, the approach introduces a simplified output matching network based on an LC network, prioritizing practicality without sacrificing performance. Additionally, comprehensive guidance is provided on utilizing the Smith chart for streamlined amplifier design, enabling engineers with an accessible methodology. Through a meticulous analysis, this work contributes to advancing the field of high-power amplification, offering enhanced performance and usability for next-generation wireless communication systems.

1. Introduction

In the rapidly evolving field of wireless communications, the demand for broadband power amplifiers (PAs) capable of operating efficiently across wide frequency ranges has increased significantly. Covering a broad spectrum, these amplifiers are crucial for modern applications, such as telecommunications, radar systems, and satellite communications, which require high performance and reliability. The design of such broadband PAs involves complex challenges, including maintaining efficiency, linearity, and stability across the entire bandwidth. Therefore, there is a growing necessity for simple yet effective methodologies that can address these challenges without adding unnecessary complexity to the design process. Addressing these needs requires innovative approaches and a deep understanding of both theoretical principles and practical implementation strategies.

Recent advancements in PA design have introduced innovative methodologies aimed at achieving high efficiency and broad operating bandwidths. One such approach combines a unique impedance matching structure with three paths (TPs) and inverse continuous modes (SICMs). This methodology not only enhances efficiency but also expands the operating bandwidth [1]. An experimental validation of this approach demonstrates a fractional bandwidth of 155.6% from 0.5 to 4.0 GHz, a saturated output power of 39.5–42.2 dBm, a drain efficiency of 57–79%, and a large signal gain of 9.5–12.2 dB. Similarly, research has explored the integration of negative feedback structures into ultrawideband power amplifiers (UWB PAs) to improve gain and efficiency flatness [2]. An experimental validation of these approaches demonstrates promising outcomes, with the PA achieving an output power between 42 and 44.8 dBm and a drain efficiency ranging from 57.6% to 71.3% over a bandwidth of 0.33–3.7 GHz. Additionally, an S-band high-efficiency continuous Class-F GaN monolithic microwave integrated circuit (MMIC) PA implemented in 0.25-μm GaN-on-Si technology is presented in [3]. This results in a maximum power-added efficiency (PAE) of 48–58.7% and a saturated output power of 36.8–38.5 dBm in the range of 2.5–3.6 GHz.

A design method for harmonic-tuned (HT) GaN MMIC PAs using low-pass filtering (LPF) impedance matching networks (MNs) is presented in [4]. The method achieves optimal impedance matching and harmonics tuning with a real-to-real LPF matching network. The experimental results demonstrate a maximum PAE of 42–50.8% and saturated output power of 39.2–40.8 dBm within the 2.6–3.6 GHz frequency range. The methodology presented in [5] anchors desired load optimal regions at the center of the Smith chart, simplifying the design constraints for broadband output matching networks. An experimental validation of the fabricated UWB PA demonstrates a saturated output power of 39.6–41 dBm, a PAE of 49.8–68.4%, and a saturated power gain of 5–12 dB over a broad range from 0.8 to 5.8 GHz. The work in [6] introduces an extended continuous-mode Class-GF PA design theory and demonstrates its multi-octave, high-efficiency implementation. The results show a saturated output power of 39–42 dBm, a drain efficiency of 63–73.2%, and a gain of 9–12 dB over a 150% bandwidth from 0.4 to 2.8 GHz.

Another study presents a design for ultrawideband power amplifiers using a simple output matching network to achieve a fractional bandwidth of 190.2%. This approach, applied to GaN HEMT devices, achieved a drain efficiency of 52–70% and an output power of 40–42.5 dBm over 67% of the 5G sub-6-GHz band (0.1 to 4 GHz) [7]. The study investigates compensating parasitic output networks over a broad bandwidth using a completely analytical solution. It demonstrates that a series transmission line and open shunt can effectively counteract parasitic effects. The design optimizes transmission line parameters to match the output-reactive parasitics.

The paper in [8] introduces a multi-branch structure for highly efficient ultrawideband harmonic-tuned PAs with over one octave bandwidth. Implementing continuous Class-B/J modes and a 10-W GaN HEMT device, this method achieved a drain efficiency of 56–70%, an output power of 38–42.3 dBm, and a gain of 8–12.3 dB over a 0.4–3.8 GHz band.

This paper introduces a simple Smith chart-based technique to design broadband PAs. It starts with the definition of an optimal external load for the chosen device, then synthesizes a load using an LC network, which is able to approximate this optimal load. This process can be completely carried out using the Smith chart. After that, the obtained intrinsic load is evaluated using an estimated intrinsic 1 dB power contour. Additionally, an estimation of the efficiency is proposed to guarantee a high-efficiency design. As an example, a GaN PA has been designed and implemented. The obtained measurement results show a state-of-the-art fractional bandwidth of 191.8%, together with a PAE between 47% and 59% over the band. With this, the efficacy of the proposed method is demonstrated.

Table 1. State of the art in sub-6-GHz broadband power amplifiers. (* Drain Eff.).

Ref.	BW (GHz)	Fr. BW (%)	G (dB)	${\mathbf{P}}_{\mathbf{out}}$ (dBm)	PAE (%)	Size (mm2)
[1]	0.5–4	115.6	9.5–12.2	39.5–42.2	57–79 *	38 × 91.6
[2]	0.33–3.7	167	7.2–12.8	42–44.8	57.6–71.3 *	N.A.
[3]	2.5–3.6	36.1	9.2–11	36.8–38.5	48–58.7	2.3 × 3.3
[4]	2.6–3.6	32.3	8.5–12.1	39.2–40.8	42–50.8	3.5 × 3.8
[5]	0.8–5.8	151.5	5–12	39.6–41	49.8–68.4	N.A.
[6]	0.4–2.8	150	9–12	39–42	63–73.2	50 × 100
[7]	0.1–4	190.2	9–14	40-42.5	48–68	50 × 120
[8]	0.4–3.8	161.9	8–12.3	38–42.3	56–70 *	35 × 108
This PA	0.1–4.8	191.8	7–16	40.3–42	47–59	49 × 130

compares this work with some state-of-the-art works found in the literature.

This work distinguishes itself through the introduction of a notably simplified methodology, employing the Smith Chart. This approach offers significant advantages in terms of ease of implementation, which we have substantiated with a comparative analysis against current state-of-the-art techniques.

2. Design

2.1. Optimal Load Analysis

While datasheets offer one way of obtaining information about optimal loads, this method advocates for a streamlined analytical approach. This enhances accessibility and understanding of the transistor’s behavior. Thus, let us approximate the output equivalent network of the transistor as a current generator in parallel with its internal output capacitance $C_{out}$ [9,10,11,12,13]. The fundamental optimal load of the transistor, at the generator reference plane, is denoted as $R_{opt}$. Thus, the impedance $Z_{ext}$ that should be synthesized at the drain pin reference plane of the device is given by the conjugate of the parallel combination of $R_{opt}$ and $C_{out}$, as follows:

$$Z_{ext}={\displaystyle \frac{R_{opt}}{1-j\omega C_{out}{R}_{opt}}}.$$

(1)

In this context, selecting $R_{opt}$ as the reference impedance positions $Z_{ext}$ as an arc in the upper region of the ZY Smith Chart, as illustrated in Figure 1. The arc’s size varies based on the desired frequency sweep, with the Smith Chart’s center point corresponding to the DC impedance (0 GHz). As frequency increases, the arc extends along a constant conductance circle. This characterization of the external impedance $Z_{ext}$ holds generality, particularly when dealing with FET-like devices. In Figure 1, the arcs representing $Z_{ext}$ depict two devices with different gate peripheries, ranging from DC up to 5 GHz. These devices are part of the CGH family of unmatched gallium nitride-on-silicon (GaN-on-Si) high-electron mobility transistors (HEMTs). For the CGH40010 and CGH40025 devices, respectively, the value of $C_{out}$ is 1.28 pF and 2.8 pF, while $R_{opt}$ is considered 22 $\Omega$ and 12 $\Omega$. They are offered by MACOM, and their operation spans up to 6 GHz.

The next subsection proposes a methodology to graphically design an output matching network, which nearly synthesizes $Z_{ext}$ for a specific range of frequencies starting from DC.

2.2. Graphically Aided Approach

To perfectly obtain $Z_{ext}$ across the frequency sweep, a capacitor with a susceptance of negative sign would be necessary, a condition not feasible with only passive elements. However, an approximation can be achieved. In Figure 2, the proposed network is shown to synthesize an impedance $Z_{syn}$ close to $Z_{ext}$. This network comprises a resistor with a value of $R_{opt}$ in parallel with a capacitor, along with a series inductor.

At very low frequencies, the selected value of the resistor ensures perfect matching. In practice, this resistor is obtained through the transformation of the 50 $\Omega$ system impedance, using a wideband real-to-real transformer. Here, at very low frequencies, the capacitor is practically equivalent to an open circuit, and the inductor behaves as a short circuit.

In this case, the selected device to design the PA is the CGH40010. However, a similar approach could be applied using the CGH40025. To determine the values of C and L, we begin by assessing the impact on the initial load $R_{opt}$ caused by C. A Smith Chart with $R_{opt}$ as the reference impedance is assumed. Thus, the $R_{opt}$ impedance is positioned at the center of the Smith Chart. As illustrated in Figure 3, the effect of the capacitor C is depicted in red, dispersing the center point into an arc along the constant conductance circle, resulting in different impedances for different frequencies.

Although the value of C might be optimized, this method suggests choosing a value of C such that the impedance $Z_a$ (see Figure 3) mirrors the target impedance $Z_{ext}$ around the real axis. Thus, the value of C is determined to be $C_{out}$. Now, $Z_a$ can be transformed into something close to $Z_{ext}$ by adding a series reactance, which induces motion in the impedance group along the constant-resistance circles in the ZY Smith Chart at each frequency. This clockwise motion can be generated by a series inductor of value L, represented by the green arrows in Figure 3. The value of L could be considered a trade-off with the desired bandwidth. In Figure 3, the desired bandwidth is assumed to be 5 GHz, starting from DC. The graphs in light blue in this figure represent the obtained impedance as the value of L is gradually increased.

For the sake of simplicity, the desired bandwidth can be defined as the frequency point, different to 0 GHz, at which the graphs for $Z_{syn}$ (in pink in Figure 3) and $Z_{ext}$ (in blue in Figure 3) intersect each other. For the case of the CGH40010 device, from Figure 3, the obtained value of L is 0.69 nH. It is worth noting that $Z_{syn}$ and $Z_{ext}$ will form an eye-like figure on the Smith Chart. As can be deduced, if the desired bandwidth is reduced, the size of the eye is also reduced. On the other hand, it can be said that the target bandwidth cannot be increased indefinitely, since the eye would increase too much in size, resulting in poor matching for the frequencies in between. In other words, if the bandwidth increases, the distance between the impedance points of $Z_{ext}$ and $Z_{syn}$ will also increase. To evaluate how much this distance could affect the PA performance, we suggest additionally looking at the intrinsic reflection coefficient. This means the synthesized reflection coefficient at the current generator reference plane [14], which is defined as follows (see Figure 2):

$${\Gamma }_{is}={\displaystyle \frac{Z_{is}-R_{opt}}{Z_{is}+R_{opt}}}.$$

(2)

The intrinsic synthesized impedance $Z_{is}$ is shown on the Smith Chart in Figure 4 for the case of the CGH40010 device and a target bandwidth of 5 GHz. As can be seen, it appears relatively close to $R_{\mathrm{opt}}$, which is represented by the center of the Smith Chart. However, to ensure an output power near the maximum achievable from the device, a constant power contour can be added on the Smith Chart. Let us suppose $V_{\mathrm{DD}}$ represents the drain bias voltage, $V_k$ is the knee voltage, and $I_{\max }$ is the maximum drain current (fully opened channel) [15]. Since the only magnitude of the intrinsic impedance $Z_i$, which, in saturation, allows reaching maximum voltage and current swings simultaneously, is $R_{\mathrm{opt}}$, we generally consider two cases: voltage saturation and current saturation [16,17]. The first case is assumed when $|Z_i|>R_{\mathrm{opt}}$, whereas the second one occurs when $|Z_i|<R_{\mathrm{opt}}$. Thus, assuming class B bias conditions and with $Y_i=1/Z_i$, the output power when saturation is reached can be estimated as follows:

$$P_{out,sat}=\left\{\begin{array}{cc}{\displaystyle \frac{1}{2}}{(V_{DD}-V_k)}^2\mathrm{Re}\left(Y_i\right)\hfill & \mathrm{if} |Z_i| > R_{opt}\\ \\ {\displaystyle \frac{1}{8}}{I}_{max}^2\mathrm{Re}\left(Z_i\right)\hfill & \mathrm{if} |Z_i| < R_{opt}\end{array}\right.$$

(3)

The maximum saturated output power $P_{\mathrm{out},\max }$ is achieved when $Z_i=R_{\mathrm{opt}}$. In this case, either the upper or lower part of Equation (3) can be used interchangeably. For our example, the calculated maximum output power is found to be $P_{\mathrm{out},\max }$ = 14.2 W = 41.5 dBm, where $I_{max}=2,27$ A and $V_{DD}-V_k=25$ V, based on the IV characteristics of the chosen device shown in Figure 5.

From Equation (3), it is evident that a constant saturated output power is attained for loads with a constant conductance in the first case, and with a constant resistance in the second case [18]. These values can be determined for a constant output power $P_{\mathrm{ref}}$ as follows:

$$\left\{\begin{array}{cc}\mathrm{Re}\left(Y_{ref}\right)={\displaystyle \frac{2P_{ref}}{{(V_{DD}-V_k)}^2}}\hfill & \mathrm{if} |Z_{ref}| > R_{opt}\\ \\ \mathrm{Re}\left(Z_{ref}\right)={\displaystyle \frac{8P_{ref}}{I_{max}^2}}\hfill & \mathrm{if} |Z_{ref}| < R_{opt}\end{array}\right.$$

(4)

$Y_{ref}$ and $Z_{ref}$ represent the admitances and impedances on the constant-conductance and constant-resistance circles defined by (4). The arcs represented by Equation (4) are now depicted on the Smith Chart, as illustrated in Figure 4. It is notable that the region formed by the two arcs represents the intrinsic load impedances yielding a power higher than $P_{ref}$. In this case, the selected value of $P_{ref}$ was taken as 1 dB lower than $P_{out,max}$.

Using (4), the obtained values are $\mathrm{Re}\left(Y_{ref}\right)=0.036$ S and $\mathrm{Re}\left(Z_{ref}\right)=17.47\Omega$. It is worth noting that the arcs expand up to the point where $|Z_{ref}|=R_{opt}$, which coincides with the intersection of the two arcs. These points define the highest and lowest points of the contour.

Figure 4 shows how the intrinsic impedance $Z_{is}$ practically resides within the region formed by the two arcs defined by (4), demonstrating the effectiveness of the proposed matching network. The expected saturated output power exceeds 40.5 dBm over a band ranging from 0 to 5 GHz.

To ensure general applicability, exactly the same design process was carried out using two other different devices: CGH40025 and WIN NP15 4 × 100 μm. Target bandwidths of 4.2 GHz and 8 GHz were considered, respectively. For the first case, $R_{opt}=12\Omega$ and $C_{out}=2.8$ pF, while for the second, $R_{opt}=48\Omega$ and $C_{out}=0.36$ pF. Figure 6 shows how $Z_{is}$ stays practically inside the ($P_{out,max}-1$) dBm power contour, which is very similar for the three different devices.

2.3. Efficiency Evaluation

At this point, an estimation of the expected drain efficiency is mandatory, since efficiency is a key characteristic of RF/microwave PAs. Let us start evaluating the efficiency for the loads on the established contour given by (4). Again, considering class B bias conditions, we can estimate the drain efficiency for the left side of the contour ($|Z_{ref}|<R_{opt}$) as follows:

$${\eta }_r\%={\displaystyle \frac{\pi I_{max}\mathrm{Re}\left(Z_{ref}\right)}{8V_{DD}}}.$$

(5)

Using (5), the expected drain efficiency for the loads on the right-side arc of the contour is 56%. On the other hand, for the arc on the right side of the contour ($|Z_{ref}|>R_{opt}$), the efficiency can be estimated as follows:

$${\eta }_l\%={\displaystyle \frac{\pi (V_{DD}-V_k)\mathrm{Re}\left(Y_{ref}\right)}{4V_{DD}\left|Y_{ref}\right|}}.$$

(6)

From (6), it is noticeable that ${\eta }_l$ depends on $|Y_{ref}|$, which is not constant over the constant-conductance circle. However, it is possible to identify the loads on the left-side arc of the contour, where ${\eta }_l$ is the worst. Looking at (6), ${\eta }_l$ is minimized when $|Y_{ref}|$ is maximized. Clearly, this happens on the highest and lowest points of the arc ($|Z_{ref}|=R_{opt}$). Calculating the efficiency for these two points using (6), the obtained value is, again, 56%. This value is completely coherent with the value of ${\eta }_r$, given that these two points are also part of the other arc.

In this framework, based on the observations above, it is possible to say that the efficiency inside the $(P_{out,max}-1)$ dB contour is expected to be higher than ${\eta }_r$.

3. Implementation, Simulations, and Measurements

Having obtained the values for C and L, we can proceed with the materialization of the output matching network (OMN). As mentioned earlier, the resistor with a value of $R_{opt}$ in Figure 2 is obtained through a multisection real-to-real transformer, converting the typical 50 $\Omega$ final load to $R_{opt}$, which, in this case, is equal to 22 $\Omega$.

An open stub is implemented to mimic C due to its simplicity in hybrid implementation. This resulted in a transmission line of 37.7° of electrical length and a characteristic impedance of 44.7 $\Omega$ at 3 GHz.

The inductor L effect is implemented by exploiting the parasitic device inductance $L_{out}$, along with an additional series short transmission line. For the CGH40010 device, $L_{out}=0.63$ nH. Therefore, the contribution of the series transmission line must be $L_x=0.06$ nH. An approximation for this contribution is obtained with an electrical length of 3°, together with a characteristic impedance of 46 $\Omega$.

The PA is implemented on a substrate with ${ϵ}_r=$ 3.5 and $h=0.76$ mm, sourced from Taconic Ltd. (Petersburg, NY, USA) The schematic of the implemented circuit is shown in Figure 7, where the OMN is evidently formed, as explained earlier. Some choke inductors were used as part of the biasing circuit, aiming at low- and high-frequency isolation. To evaluate the appropriateness of the implemented OMN, the implemented intrinsic impedance ($Z_{is}$ implemented) is simulated and compared with the expected one ($Z_{is}$ theoretical). Figure 8 shows this comparison. The effect of the multi-section transformer can be noticed as an additional impedance dispersion. However, the value of the implemented $Z_{is}$ is still close to the center of the Smith Chart over the band, with the exception at low frequencies (<0.5 GHz). At low frequencies, the intrinsic load tends to be near the system impedance 50 $\Omega$, which, for the selected device, is still a high efficiency load (>50%).

The IMN network was designed to keep a small signal gain higher than 10 dB. An RC network was introduced to make the device unconditionally stable for all frequencies. The transistor is biased in a deep class AB with $I_{DD}=100$ mA and $V_{DD}=28$ V.

A picture of the implemented PA is shown in Figure 7. Continuous-wave (CW) characterization was conducted to assess the performance of the implemented PA. The results, including saturated output power, saturated gain, saturated drain efficiency, and saturated power-added efficiency (PAE), are presented in Figure 9, alongside comparative simulation data. Notably, the achieved output power exceeds 40 dBm across a bandwidth spanning from 0.1 to 4.8 GHz. Over this frequency range, the measured saturated PAE ranges from 47% to 59.1%, while the saturated drain efficiency fluctuates between 50% and 59.5%. Additionally, the saturated gain varies from 7 to 16 dB. Figure 10 further illustrates measured gain, output power, and efficiency profiles at selected in-band frequencies. It is important to note that the amplifier actually starts working from a low frequency of 60 MHz, where a PAE of 65% was obtained together with 41 dBm of output power.

The linearity of the designed PA was evaluated using the Keysight ADS DPD Explorer simulation tool under excitation with a 100 MHz 5G NR signal at a carrier frequency of 3 GHz, with 9 dB PAPR and 22 dBm output power. Figure 11 shows the power spectral density at the output of the PA with and without Digital Predistortion (DPD), as simulated in the tool. The simulated ACLR improved from 32.1 dBc to 51.8 dBc with the application of DPD. The simulated average output power was 32.7 dBm, while the average PAE was 19.2%. With DPD, the EVM was reduced to 1.1°.

The improvement in the Adjacent Channel Leakage Ratio (ACLR) with the application of DPD signifies a substantial enhancement in linearity. Such an improvement in ACLR not only reduces interference with adjacent channels but also optimizes spectrum usage, a vital aspect in the crowded 5G frequency bands. The low EVM obtained value is indicative of a high-quality signal that maintains integrity, important for applications requiring a robust performance, such as video streaming and critical communications in 5G networks.

4. Conclusions

In summary, this paper presented a comprehensive study on the design and performance evaluation of a high-power amplifier (PA) operating across a wide frequency band from 0.1 to 4.8 GHz. Leveraging a 10 W GaN device, the amplifier demonstrated output power levels exceeding 10 W across the entire frequency spectrum. Moreover, the power-added efficiency (PAE) of the amplifier, ranging from 47% to 59%, underscores its energy-efficient operation, making it suitable for various applications. With consistent gain characteristics ranging between 7 and 15 dB, the design ensures reliable signal amplification across diverse scenarios.

Of particular note is the innovative approach employed in designing a simplified output matching network using an LC network, prioritizing practicality while maintaining high performance standards. Additionally, given the inherent characteristics of FET devices, it can be inferred that the methodology presented in this paper possesses a degree of generality. This suggests that the principles and techniques discussed herein have broader applicability beyond the specific transistor type and frequency band investigated in this study. As such, the insights gleaned from this research hold promise for guiding the design of high-power amplifiers across various transistor technologies and frequency ranges.