1. Introduction
Design of low power integrated circuits (IC) has become a challenging problem due to the continuous technology scaling. In the design of chips for modern applications like solar [
1,
2], motor control [
3,
4] and smart energy systems [
5], power consumption plays a significant role. Comparatively, the contribution of dynamic power due to the frequent switching action of more number of transistors is more pronounced in these ICs to static power dissipation. Deployment of multiple supply voltages in the ICs is one of the best-known technique for the reduction of dynamic power consumption [
6]. In this technique, the modules in the chip operate at different voltages, in addition to the chip level voltage [
7]. Even though it helps in power savings, this introduces a lot of new challenges in the physical design process. Electronic design automation industries follow a unique design flow to reduces the complexities of the design process. The
Figure 1 depicts the state-of-art design flow for multiple supply voltages (MSV) designs. It involves three essential phases (a) voltage assignment, (b) insertion of level shifters, and (c) floorplanning [
8,
9].
To meet the demand on miniature ICs, the researchers focuses on fixed-outline floorplanning considering reduction of wirelength [
10]. Increase in number of voltage islands increases the routing source and complicates power planning [
11]. Among the various methods, voltage island-based floorplanning provides a better solution with minimization is power routing resource in the layout [
12]. In this method, the floorplanner places the modules of similar operating voltage in a region, named as voltage island. Usually, this voltage island constraint-based floorplanning appears either in post floorplanning/placement stage. The voltage assignment phase determines the suitable operating voltage of the modules in the layout by examining the delay and power characteristic for the predefined set of voltages [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24]. In some cases, the decision making for the selection of appropriate become tough due to the best performance of modules in a group of voltage levels. Lee et al. presents a method which considers reconvergence fan-out for optimal voltage assignment [
8]. As the modification, this work, many papers focus provides a solution for voltage assignment and floorplanning. Sengupta et al. proposed an algorithm for core-based designs and contributed a power state model approach which aids for voltage assignment based on IDLE, ON, OFF states of the cores in the chip. Some of the papers give a significant contribution to the place of level shifters to satisfy the timing constraint [
25].
After the process of voltage assignment, these algorithms perform floorplanning using a data structures available for single supply voltages. The methodologies present in the literature follows the implementation of algorithms either in Gigascale Systems Research Center (GSRC) or Microelectronics Center of North Carolina(MCNC) benchmarks. These algorithms mainly consider wirelength and time complexity as the Figure of merit for evaluating the effectiveness of the methodology. The academic floorplanners use structures like B* tree [
26], Normalized polish expression (NPE) [
27,
28], Transitive closure graph (TCG) [
29], Sequence pair (SP) [
30], and Skewed binary tree (SKB) [
31] to represent the modules in the initial floorplan. Further, upon perturbations and using packaging methodologies for compactness results in a reduction of dead space and wire length. For fast convergence and accurate results, simulated annealing framework is employed with a cost function, consisting of wirelength and deadspace. Some of the other approaches include perturbation of modules in the layout and random positioning and legalization using mathematical formulations. Quadratic and second-cone programming methodologies provide a notable reduction in wirelength in these MSV designs [
32]. Even though these academic benchmarks show betters results in GSRC and MCNC circuits, their performance becomes typical after implementation is commercial Electronic design automation (EDA) tools like CADENCE, SYNOPSYS, etc.
Some of the notable facts after implementation of academic floorplanners are:
In the design of small size chips for various applications, the floorplanning processes require positioning of modules in the layout within the predefined application-specific aspect ratio. After implication of an application specific aspect ratio in an industry tool, the synthesis process it comparatively changes dimensions of the blocks inside the chip from its default area. This transformation is due to the high-level synthesis process involved in the EDA tool and results in the availability of unplaced modules outside the core region of the layout.
Increase in geometric violations while performing design rule check.
Avoids setup and hold time conditions.
Fails to consider the placement of standard cells and other challenges in the physical design after detailed routing.
In addition, conventional design MSV flow shown in
Figure 1 is completely different in a EDA tool. The
Figure 2 shows design flow for MSV design in Cadence Innovus software for digital designs.
This paper devotes to overcome the challenges as mentioned above while implementing MSV design floorplanning algorithm in an EDA tool. The main contributions in this paper are listed below:
Solution to industrial floorplanning: This paper implements the conventional SKB tree meant for academic benchmarks in industrial EDA environment. While implementation of conventional SKB methodology for different aspect ratios, some of the modules are unable to position inside the core area of chip. This is paper overcomes this problem using the proposed algorithm through finding the optimal dimensions of modules in the design.
Elimination of cluster constraint: While fixed-outline floorplanning for various aspect ratios of the chip, there are more number of unplaced modules outside the core area of the layout. The proposed algorithm places those modules inside the core area of the floorplan with short wirelength and reduces the percentage of congestion.
Avoiding re-voltage assignment: This paper performs iterative improvement in positioning of modules inside the voltage island, this results in reduction of wirelength, congestion and power. The conventional SKB tree performs exchange of modules both intra and inter voltage island modes. This process leads to change of assigned voltage to modules and increases wirelength. Since the proposed algorithm accommodates all its modules inside the voltage island, the perturbations were performed within the voltage island. Through iterative improvement, the proposed algorithm reduces wirelength and congestion.
Unoccupied space for post-floorplanning stages: Unlike the previous works, the proposed algorithm performs concurrent fixed-outline floorplanning and voltage island floorplanning for the minimization of wirelength and power consumption under various aspect ratio. The results show a notable contribution to power saving and wirelength compared to state-of-art methods.
The rest of this paper is organized as follows:
Section 2 presents the existing SKB tree methodology for floorplanning with voltage island and fixed outline constraints.
Section 3 gives the proposed algorithm and a placement methodology to formulate the problem while floorplanning in EDA tool.
Section 4 reports the experimental reports. Finally,
Section 5 concludes this paper.
2. Preliminaries
This paper proposes a algorithmic method which is based on the existing the Skewed Binary (SKB) representation in [
31]. Hence this section first reviews floorplanning topology using SKB and
Section 3 presents proposed floorplanning methodology to manage fixed outline and voltage island floorplanning.
2.1. Floorplanning Representation
Consider the tree structure shown in
Figure 3. Modules operating at similar voltage levels are placed at the parent node, one after another, in the left side of every node in a branch. Thus, they form a voltage island. Each node contains modules on the right side of the parent node. The parent node in the tree structure is placed in the left-corner of the voltage island. Every parent node of the branch is connected to the root node due to its inter connectivity. Thus, each branch will have modules at different operating voltages.
Figure 3b illustrates a typical SKB tree representation and
Figure 3a shows the floorplan of a circuit consisting of 10 modules. Modules
operate at voltage level-1 and
at voltage level-2. Similarly,
modules work at voltage level-3.
is considered as a parent node at level-0 since it needs to be placed in the left corner of the floorplan. Similarly, modules
and
represents the parent node for levels 1 and 2, and they are placed in the left corner of their power domain.
In this way, SKB tree helps the designer with the placement of modules in the core area of a chip. In the event of tree traversal, the time complexity is reduced for the placement of modules in the core area of the chip.
2.2. Placement Process
Consider a chip, with N number of modules in its design. Let
, where
are the modules in the design and
is a set containing voltage islands in N. With the dimension of modules in width and height, the tree structure in
Figure 3 is used to allocate a space in the floorplan, based upon its operating voltage. Using the conventional depth first search algorithm, the modules are filled in the voltage island region one after another. The width of the power domain is calculated as
In the above Equation (
1),
refers to the total area of modules in the power domain,
refers to the total area of the chip,
refers to the width of the chip and
refers to the allowable dead-space.
Before a module is placed in a voltage island region, the algorithm determines the fitness of a module in the allotted width of the voltage island
. If the module width
is greater than
, the algorithm pushes in the
queue and traverses the tree for the insertion of the next module
in the
region. Before the placement of module
of
, the algorithm prioritizes the modules in the queue. If the module fails to fill the region, several modules would be combined as a merged block to fill up the region. For the successful placement of that merged module, a contour is drawn, unlike in [
26], to estimate the feasible placement of the module. This procedure is iterative, until all the modules in the queue and voltage islands are placed in its region of
.
Figure 4 depicts the placement process of modules inside the voltage island. In
Figure 4, the width of the module b4 is greater than the width of voltage island W1. This can be avoided through merging the modules b4, b5, as illustrated in
Figure 5.
To avoid the congestion and aforementioned merging of modules, cluster constraint is introduced which serves as an upper bound on the density of modules in the voltage island. Thus, the algorithm limits the number of modules in voltage islands and produces a compact floorplan.
2.3. Our Contributions
This paper proposes a floorplanning methodology based on SKB tree representation and performs voltage island floorplanning eliminating the cluster constraint in the conventional SKB tree methodology. Unlike the conventional SKB tree, the proposed methodology also predetermines the width of voltage island using the Equation (
1). For tight packing of modules within this pre-estimated island width, this paper proposes an algorithm which determines the optimal dimensions of modules. Placement of these modules with their optimal dimensions positions all the modules of voltage island inside this width. However, for the reduction of power, congestion and wirelength, this procedure repeated iteratively. Different from conventional SKB methodology, the proposed methodology is implemented in Cadence EDA tool for the synthesized netlist of IWLS benchmarks to provide solutions to the industrial floorplanning problems. In addition to this voltage island floorplanning, proposed algorithm is also performed for fixed outline floorplanning, and simultaneous fixed and voltage island floorplanning.
Simulations were on both conventional SKB and proposed floorplanning methods using Cadence EDA tool. To compare the effectiveness of the proposed algorithm, four different experiments were performed in this paper. In first experiment for floorplanning with zero deadspace, the proposed methodology gives 18% of reduction in wirelength while satisfying the fixed outline constraint. Second experiment is performed for floorplanning with 15% deadspace on various aspect ratios of chips. The results reveals that the proposed floorplanning method gives average reduction of 29.3% and 63% in wirelength and congestion. In third experiment the proposed algorithm performs voltage island floorplanning with 38.7% reduction of power. Different from conventional SKB method, we perform an experiment to test ability of proposed algorithm to satisfy both fixed and voltage island floorplanning simultaneously. The results show that proposed algorithm provides reduces 22% of power consumption and increases the percentage of power saving compared with conventional SKB tree method.
3. Proposed Methodology
3.1. Step 1: Initial Floorplan
Given the dimensions of modules-in-chip in width and height as well as the operating voltage, we assign the modules in each node of the SKB tree structure. Our proposed floorplanning algorithm overcomes the drawbacks in the SKB tree algorithm for the multiple supply voltage (MSV) design of voltage island floorplanning, without any change in the area of the module.
Table 1 presents the parameters used in our proposed Algorithms 1 and 2.
Given a module-based design, with all its module dimensions in width and height, and its operating voltage, a tree structure is obtained from the initial floorplan as shown in
Figure 3. Modules are arranged in tree structure T, as explained in the
Section 2.1.
3.2. Step 2: Optimal Dimension of Modules
After the arrangement of modules in the tree structure, the optimal dimensions of modules are estimated to fit all the modules in its voltage island. The optimal dimension is obtained using the Algorithms 1 and 2.
Given a tree structure, T, with nodes representing modules, M, and levels of the tree representing voltage levels, we obtain the optimal dimensions for the modules and , using the procedure , where . Finally, after obtaining the optimal dimensions, it is updated to the existing dimensions of and .
The Algorithm 2 describes the procedure to find the optimal dimensions of the modules. Lines (3–14) in the algorithm aims to find the optimal dimension of and . Stock–Meyer’s equation for vertical bisection used for non-slicing methodology is used to find the optimal dimensions of and . It computes the list of possible dimensions, for a given module size in width and height.
Consider the two modules
and
with dimensions
and
present in a voltage island. The proposed algorithm in this paper determines the optimal dimensions of the modules without changing the area of the module. Hence, the algorithm assumes duplicate dimensions of modules
and
as
and
. The dimension of
is assumed as
for width which is height of module
while
for height which is actually the width of module
. Similarly, for module
its duplicate is assumed as
and
. The proposed algorithm finds the optimal area required to floorplan the modules
and
, both width-wise and breath-wise, using the Equations (
2)–(
7). The Equation (
2) helps to determine the optimal dimension required to floorplan two modules with its original dimensions
and
. In this Equation (
2),
u denotes the optimal width and
v denotes optimal height after merging the modules
and
.
For minimum area floorplan, the algorithm compares value of
u and
v. If the value of
u is greater that
v, optimal dimension is determined using duplicate dimensions of module mi. It is given by the Equation (
3),
Algorithm 1 |
- 1
A Tree T, with nodes representing modules in the design, - 2
, where - 3
fordo - 4
; ; - 5
Choose and ; - 6
; - 7
update and ; - 8
end for
|
Algorithm 2 Opt_dimension(mi,mj) |
- 1
// initialize the set S and P; - 2
top: - 3
whiledo // for module find the optimal dimensions length-wise; - 4
//compute the dimension after merging; - 5
// store all the resulting dimensions in set S; - 6
if then - 7
// Compute the new dimensions using ; - 8
// store all the resulting dimensions in set S; - 9
else - 10
// Compute the new dimensions using ; - 11
//store all the resulting dimensions in set S; - 12
end if - 13
end while - 14
find minimum of S; // Find the minimum dimension in set S; - 15
whiledo// for module find the optimal dimensions width-wise; - 16
// compute the dimension after merging; - 17
// store all the resulting dimensions in set S; - 18
if then - 19
// Compute the new dimensions using ; - 20
- 21
else - 22
// Compute the new dimensions using ; - 23
- 24
end if - 25
end while - 26
find minimum of P; // Find the minimum dimension in set P; - 27
find minimum (S,P); // Find the minimum dimension in set S and P; - 28
update minimum area dimension to ; // update these optimal dimensions in ; - 29
- 30
- 31
gototop;
|
For
u less than
v, Equation (
4) is used to find the optimal dimensions to occupy the modules
and
.
The resulting dimensions from Equations (
2)–(
4) are stored in a set
S.
In the above Equation (
4), the algorithm finds the possibilities for optimal dimension with duplicate dimensions of module
. Thus, the algorithm finds the optimal dimension width-wise. In the same way, the algorithm uses the Equations (
5)–(
7) to find the height-wise optimal dimensions.
the resulting dimensions from Equations (
5)–(
7) are stored in a set
P.
A minimal area dimension area is chosen from the set S and P and we update the dimensions of modules and .
Repeating this process with all the modules in the voltage islands, results in placement of all the modules within pre-estimated width of . This helps the proposed algorithm for the placement of modules in the layout eliminating cluster constraint introduced in the conventional SKB tree methodology.
3.3. Example for Determining Optimal Dimensions of Modules
For better understanding of proposed methodology simple illustration is given below for determining optimal dimension of modules in the first level of the SKB tree shown in
Figure 6. It constructed for a design with three voltage islands consisting of eight modules.
The nodes in the tree represents the modules in the layout and the levels of the tree represents voltage domains. The dimensions present above every node are the width and height of the modules. The proposed algorithm in this paper performs the following procedure and determines the optimal dimensions of modules in the tree structure.
From the
Figure 6, let
are the modules with dimensions (width, height) in micro metres.
The algorithm proceeds with the following steps given below.
- 1.
Taking the vertices and . Let , .
For the vertical orientation,
- (i)
join and , we get . Since the maximum is from U, we join and .
- (ii)
join and , we get
The resulting dimensions are μm2 and μm2. The minimum of these is 24 μm2.
For the horizontal orientation,
- (i)
join and , we get . Since the maximum is from V, we join and .
The resulting dimensions is 24 μm2. As a result, the dimensions either and or and can be taken for minimum area.
- 2.
Taking the vertices and , Let , . For the vertical orientation,
- (i)
join and , we get . Since the maximum is from V, we join and .
- (ii)
join and , we get
The resulting dimensions are μm2 and μm2. The minimum of these is 32 μm2.
For the horizontal orientation,
- (i)
join and , we get . Since the maximum is from V, we join and .
- (ii)
join and , we get .
The resulting dimensions are 33 μm2 and 27 μm2. The minimum of these dimensions is 27 μm2. Finally, the minimum of dimensions horizontal 27 μm2 and vertical 32 μm2 is taken as the dimensions.The minimum of these is, 27 μm2. Its co-ordinates are and . The area of the merged modules is fixed as .
- 3.
Taking the vertices and .
Let , For the vertical orientation,
- (i)
join and , we get . Since the maximum is from V, we join and .
- (ii)
join and , we get
The resulting dimensions are μm2 and μm2. The minimum of these is 45 μm2.
For the horizontal orientation,
- (i)
join and , we get . Since the maximum is from V, we join and .
- (ii)
join and , we get .
The resulting dimensions are 39 μm2 and 44 μm2. The minimum of these dimensions is 39 μm2.
From the = 39 μm2, if , the procedure given below is followed i.e., the update on the dimensions of the modules is performed, else, a new module is taken from the tree structure and again the procedure for horizontal and vertical orientation is repeated until the resulting merged dimension is equal to .
Finally, the minimum of dimensions horizontal 39 μm2 and vertical 45 μm2 is taken as the dimensions. The minimum of these is, 39 μm2. Its co-ordinates are and .
The area of the merged modules is fixed as . For the modules and , the updated dimensions are and .
Now, for , the modules and holds the dimensions as and .
Thus the optimum dimension for voltage island 1 is found to be 39 μm2.
3.4. Step 3: Placement
After updating the dimensions in modules for all voltage islands using depth first search, the modules are placed in the core area of layout from the lower left corner within the pre-estimated width. If a module failed to fit in the width , it is pushed in a temporary queue and priority is given for the next module. Before the placement of any module inside the voltage island, modules in the queue are prioritized to check the feasibility of placement within the size of .
Presence of unoccupied space in the layout support placement of standard cells and offers reduction congestion while routing. However, unoccupied space present after placement and routing increases the silicon cost during manufacturing of chip. Hence, this paper analyses the unoccupied space while floorplanning the modules in the layout.
Figure 7 illustrates the proposed methodology for placement of modules with reduction of unoccupied space. In this illustration, the pre-estimated with of voltage island
is assumed as 8 units.
Consider the three modules
(3,8),
(4,4), and
(1,3).
Figure 7a–d shows the possible placement of modules.
Figure 7a shows the placement of module
over the module
. Even though this placement fits inside the width
with total occupied area of 63 square units, it increases the unoccupied space. The
Figure 7b shows a placement when
is vertically placed with respect to module
. This further increases the unoccupied space compared with placement method in
Figure 7a with occupied area of 64 square units. The floorplan in
Figure 7c also depicts a notable unoccupied space with placement of module
adjacent to module
and the module
on top it. The total occupied area of module including unoccupied space is 56 square units.
Figure 7d show the compact floorplan with reduction in occupied area of 48 square units; this floorplan reduces the silicon cost through allocating space for the placement of the new module after
. Hence, a unoccupied space analysis is performed in this paper before placement of every module inside voltage island to aid the process in post-floorplanning stages.
In ordered to obtain optimal reduction in wirelength, congestion and power, a cost function is developed in this paper. Every candidate floorplan is evaluated to the cost function given below in Equation (
8), where P denotes power in mW, WL denotes wirelength in um and congestion in percentage,
To obtain an optimized floorplan, iterative improvement methodology is incorporated in this paper. For every iteration, we alter the positions of node inside the voltage of SKB tree representation. Then, the proposed methodology is implemented on the tree structure which results in optimal dimensions. Based on this optimal dimension, the floorplan is evaluated for reduction in unoccupied space. The conventional physical design flow given in
Figure 2 is followed to obtain the total power, wirelength and congestion. This procedure is repeated until the cost function is minimized.
5. Conclusions
In this paper, a new paradigm has been presented for industrial floorplanning to satisfy both fixed outline and voltage island constraint. Since the proposed methodology shows better results towards power saving and reducing wirelength, the experiment is extended for simultaneous optimization of both constraints. The experimental results demonstrates that the proposed algorithm in this paper is effective in solving industrial floorplanning under various fixed outline and voltage island conditions.
For future SOCs designs, three-dimensional structures are preferred due to its ability to place these two-dimensional layouts in stack-based structures and more integration of modules in the chip. Since fixed outline and voltage island floorplanning is challenging problem, there exist few works considering this issue. The proposed methodology requires dedicated voltage assignment and floorplanning, which will be considered as future work.