**4. Discussion**

#### *4.1. Power Loss Comparison*

A unipolar PWM was used for both the conventional inverter in Figure 1 and the proposed inverter. In both inverters, *S*1 and *S*2 (*S*3 and *S*4) had one turn-on switching loss and one turn-off switching loss during one switching period, respectively, for the positive (negative) grid cycle. Both inverters had two turn-on switching losses and two turn-off switching losses during one switching period. The number of switching times was identical during one switching period, as one of the switching legs operated at grid frequency. The number of conducted switching devices was also identical during one switching period. Then, both inverters had identical switching and conduction losses. Even though they had identical power losses for the switching devices, the conventional inverter in Figure 1 had a high leakage current, while the proposed inverter had a low leakage current. This is the reason why the proposed inverter achieved higher power efficiency than the conventional inverter in Figure 1.

Figure 11a shows the circuit diagram of the previous inverter in [15]. Figure 11b shows its switching signal diagrams for *S*1 ~ *S*4 during one switching period. In the previous inverter in [15], *S*5 (*S*6) was always turned on for the positive (negative) grid cycle. *S*1 and *S*4 (*S*2 and *S*3) operated together during one switching period. In order to generate the shoot-through switching states, *S*1, *S*2, *S*3, and *S*4 had to be simultaneously turned on during one switching period, as shown in Figure 11b. *S*1 and *S*4 (*S*2 and *S*3) had two turn-on switching losses and two turn-off switching losses during one switching period, respectively, for the positive (negative) grid cycle. Meanwhile, *S*2 and *S*3 (*S*1 and *S*4) had one turn-on switching loss and one turn-off switching loss during one switching period, respectively, for the positive (negative) grid cycle. Then, the previous inverter in [15] had six turn-on switching losses and six turn-off switching losses during one switching period. Thus, the previous inverter in [15] had higher switching losses than the proposed inverter, even though the additional switches (*S*5, *S*6) in both inverters operated at the grid frequency. In addition, the conduction losses of the previous inverter in [15] were higher than the proposed inverter because of the use of two additional diodes. This is the reason why the proposed inverter achieved higher power efficiency than the previous inverter in [15]. This is also the reason why the previous inverter in [15] achieved lower power efficiency than the conventional inverter in Figure 1. As the power level decreased, the switching power losses became significant, which reduced the light load efficiency.

**Figure 11.** Circuit and signal diagrams of the inverter in [15]: (**a**) circuit diagram; (**b**) signal diagram for *S*1 ~ *S*4.

## *4.2. Topological Investigation*

The decoupling circuits for reducing the leakage current can be divided into two concepts, namely AC-based and DC-based decoupling techniques [9]. The proposed inverter can be derived from the AC-based decoupling technique as the bidirectional switch (*S*5, *S*6) and two inductors (*L*3, *L*4) provide the current path for clamping the common-mode voltage to the neutral and the grid voltage for the positive and negative grid cycles, respectively. The DC-link voltage between the QZS circuit and the full-bridge inverter pulsates as the shoot-through state is generated. Thus, deriving a DC-based decoupling technique will be quite achievable for the ZS-based inverters. Along with the present state of the art and trend of decoupling circuit techniques [9], the embedded-switch inverter (ESI) [21] and zero-voltage state rectifier (ZVR) [22] concepts can be candidate solutions for extending leakage current reduction schemes to three-phase inverter applications. Furthermore, multilevel inverters using cascaded topologies [23–25] can be advanced approaches for QZS inverters to improve the output power quality.
