**1. Introduction**

Photovoltaic (PV) power generation is one of the ways to e ffectively use energy. Through photovoltaic panels to obtain energy, photovoltaic systems can provide green sustainable solutions [1,2]. In general, energy can be obtained from photovoltaic panels by grid connection of photovoltaic inverters or by connecting transformers. However, the transformer is relatively heavy, sizable, and costly, with undesirable power loss problems. Therefore, the transformerless PV inverters are promising and attractive in industrial and academic fields [3–7]. However, when the transformerless PV inverter is connected to the grid, there are still many technical challenges to be solved, such as the leakage current or ground current. Without the transformer isolation, the electrical connection exists between the photovoltaic panel and the grid, and a leakage current will be generated on the parasitic capacitance between the photovoltaic panel and the ground. Leakage currents can adversely a ffect grid current, personal safety and electro-magnetic interference issues. So, the German standard VDE 0126-1-1 defines that the PV system should be o ff from the grid when the leakage current exceeds 300 mA.

To solve the above problems, many kinds of topologies have been published, such as Heric, H6, oH5, H5 [8–11]. In theory, a constant common-mode voltage would be achieved with the above topologies. In fact, due to the influence of the switch junction capacitance, the switching common-mode voltage changes with high frequency. Consequently, the leakage current cannot be completely eliminated. Nevertheless, most topologies are proposed from the perspective of voltage-type inverters. In a voltage source inverter, the DC-side electrolytic capacitor reduces the reliability and life of the inverter system. Moreover, the voltage source inverter has a risk of short-through, which leads to the reliability issue. In addition, the current source inverter has a unique short-circuit operation capability, which improves the reliability of the system. Aside from that, the DC-link of the current source inverter uses an inductor instead of an electrolytic capacitor, which can be designed to work at high temperatures [12–15]. The current-type inverters, as a matter of fact, have been applied in photovoltaic systems over the past few decades [16–22].

However, due to the switching-frequency common-mode voltage, the leakage current of the conventional current-source four-switch inverter is large. This characteristic limits the application of conventional current source inverters in transformerless photovoltaic systems. Inspired by the bypass-type voltage source inverter topology [23], this paper proposes a novel AC-side clamped current-source inverter topology, which effectively suppresses the switching-frequency common-mode voltage, so as to reduce the leakage current. At the same time, for the new inverter, a new modulation for reducing the switching loss is proposed. In addition, the proposal is proven by the experiment results.

#### **2. Traditional Current Source Inverter**

Figure 1 is a schematic of the conventional current-source inverter circuit. Where, *Ldc*1 and *Ldc*2 are DC-side inductors, *S*1–*S*4 are IGBTs (Insulated Gate Bipolar Transistor), *Cf* is the AC-side filter capacitor, *vg* is the AC-side voltage, and *CPV* is the parasitic capacitance between the PV array and the ground. The voltage change across the parasitic capacitance *CPV* will cause a leakage current, which will affect the grid current.

**Figure 1.** Conventional current-source inverter.

In order to understand the factors affecting the leakage current, a common-mode loop model, as shown in Figure 2, is established. Where, *VCM* represents the common-mode voltage (CMV), and *Z* is the equivalent impedance of the common-mode loop.

$$V\_{\rm CM} = \frac{V\_{\rm PO} + V\_{\rm NO}}{2} \tag{1}$$

$$Z = \frac{sL\_{\rm dc1}L\_{\rm dc2}}{L\_{\rm dc1} + L\_{\rm dc2}} \tag{2}$$

$$i\_{\text{leakage}} = 2C\_{PV} \frac{dV\_{\text{CPV}}}{dt} \tag{3}$$

$$V\_{\rm CPV} = \frac{1}{2s\mathcal{C}\_{PV}Z + 1}V\_{\rm CM} \tag{4}$$

where, *VCPV* represents the voltage across the parasitic capacitance 2*CPV*. According to Equations (3) and (4),

$$I\_{\text{leakage}}(\mathbf{s}) = \frac{2s\mathbb{C}\_{PV}}{2s\mathbb{C}\_{PV}Z + 1}V\_{\text{CM}}\tag{5}$$

**Figure 2.** Common-mode model.

According to Equation (2) and Equations (3)–(5), the leakage current *Ileakage* is dependent on the equivalent common-mode impedance and the rate of the common-mode voltage change. Therefore, reducing the leakage current can be considered from two points, one is to increase the common-mode loop impedance, and the other is to reduce the rate of the common-mode voltage change or to maintain the common-mode voltage constant.

Conventional current-source inverters have four switching states, as shown in Table 1. As shown in Figure 3, the driving signal waveforms of *S*1 and *S*3 are changed by low frequency, and the driving signals of *S*2 and *S*4 are changed at a high frequency.

**Table 1.** Current space vectors, switching states and common-mode voltage (CMV).

**Figure 3.** Gating signals of current-source inverter.

As switch *S*1 and the switch *S*4 are turned on, the common-mode voltage can be derived according to Equation (1):

$$V\_{CM} = \frac{V\_{PO} + V\_{NO}}{2} = \frac{V\_{AO} + V\_{BO}}{2} = \frac{v\_{\mathcal{S}}}{2} \tag{6}$$

where, *VPO* represents the potential of P with respect to O, and *VNO* represents the potential of N with respect to O.

When the switch *S*1 and the switch *S*2 are turned on, the common-mode voltage is:

$$V\_{CM} = \frac{V\_{PO} + V\_{NO}}{2} = V\_{AO} = v\_{\mathcal{g}} \tag{7}$$

As the switch *S*2 and the switch *S*3 are turned on, the common-mode voltage is:

$$V\_{CM} = \frac{V\_{PO} + V\_{NO}}{2} = \frac{V\_{BO} + V\_{AO}}{2} = \frac{v\_{\overline{\mathcal{S}}}}{2} \tag{8}$$

When the switch *S*3 and the switch *S*4 are turned on, the common mode voltage is:

$$V\_{\rm CM} = \frac{V\_{\rm PO} + V\_{\rm NO}}{2} = V\_{\rm BO} = 0\tag{9}$$

In summary, the switching-frequency common-mode voltage in the system leads to serious leakage current problems of the current-type inverter. In order to effectively suppress the leakage current, this paper will propose a new topology in the next section, which can eliminate the switching common-mode voltage variation for the leakage current attenuation.

#### **3. New Current-Source Inverter**

This section introduces a new current-source inverter topology that can eliminate high-frequency common-mode voltage variation from a topological perspective. As shown in Figure 4, a voltage source DC-bypass inverter is proposed in Reference [23]. It uses the diode to clamp the unchancommon-mode voltage unchanged at *Vdc*/2, and thus, the leakage current can be suppressed. The corresponding current-type topology is obtained, as illustrated in Figure 5.

**Figure 4.** Voltage source inverter with DC-side clamping.

**Figure 5.** New current-source inverter with AC-side clamping.

According to Table 1, the common-mode voltage depends on the grid voltage, and the common-mode voltage variation is from 0 to *vg*. For eliminating the high-frequency common-mode voltage, the DC-side positive bus P and the negative bus N are clamped at the midpoint of the AC-side filter capacitors during the freewheeling period. According to Equation (1), the common-mode voltage is *vg*/<sup>2</sup> in the freewheeling cycle.

$$V\_{CM} = \frac{V\_{PO} + V\_{NO}}{2} = \frac{v\_{\mathcal{S}}}{2} \tag{10}$$

During the freewheeling period, the switch *S*5 and the switch *S*6 are on to establish a freewheeling path for the DC-side current. The switching states in the active state are the same as that of the conventional current-source inverter. During the half-positive cycle, the switch *S*1 and the switch *S*4 are turned on. In the half-negative cycle, the switch *S*2 and the switch *S*3 are on. The new current-source inverter switching states and corresponding common-mode voltages are given in Table 2.


**Table 2.** Current space vectors, switch states and CMV.

It can be seen from Table 2 that the new current-source inverter has three switching states, and the common-mode voltages corresponding to each switching state are the same, which are 0.5*vg*, and the common-mode voltage frequency is consistent with the fundamental frequency. Since the frequency of the grid voltage *vg* is smaller than the high switching frequency, the influence of the fundamental-frequency voltage on the switching frequency common-mode characteristics can be ignored. According to Equations (3)–(5), the proposed method eliminates the switching frequency common-mode voltage variation, so that the leakage current is effectively suppressed.

The driving signal waveform of the proposed inverter is shown in Figure 6. The switches *S*1–*S*6 are high-frequency changes and the switching loss is increased. To solve this problem, a novel modulation method for reducing the switching loss based on the characteristics of the new topology is proposed. Taking the half-positive cycle operating state as an example, the active state *I*1 and the zero state *I*0 alternately operate. Figures 7 and 8 are circuit diagrams of the system operating in the active state *I*1 and the zero state *I*0, respectively.

**Figure 6.** Gating signal of new current-source inverter.

**Figure 7.** Schematic of the active state *I*1.

**Figure 8.** Schematic with the active state *I*0.

According to Figure 8, when the system operates in the zero state, the potential at point A is *vg*, the potential at point B is 0, the point P and the point N are clamped at point M, and the potential at point M is *vg*/2. Therefore, in the zero state, if the switch *S*1 and the switch *S*4 are in the on state, the diodes *D*1 and *D*4 are reversely turned <sup>o</sup>ff, and the upper arm and the lower arm are still in the off state, and the circuit is as shown in Figure 9. The switch *S*1 and the switch *S*4 can always be in the on state during the half-positive cycle. In a similar manner, for the half-negative cycle, the switch *S*2 and the switch *S*3 can always be in the on state. The switching states of the new modulation method can be obtained, as shown in Table 3. Figure 10 shows the gating signals' waveform when using the new modulation method. It can be seen that the switches *S*1–*S*4 vary by low frequency, and the switching loss is reduced.

**Figure 9.** Schematic under new modulation method.

**Table 3.** Current space vectors, switching states and CMV.

**Figure 10.** Gating signals with the new modulation.
