**1. Introduction**

With the rapid development of smart grid systems, dc-based distributed power systems and micro grids attract more and more attention due to some clearly good features, e.g., high power transfer efficiency, low system cost, high system stability and easy system control [1,2]. Commonly, the input voltage of these dc interfaces is very high to obtain optimum system performance, which makes high input voltage and high frequency isolated dc-dc converters become hot and causes challenging issues in power electronics. In the high voltage applications, how to reduce the voltage stress on the primary switches is a key point, and several methods can be used to solve this problem. The first way is to connect the power switches in series directly, but this method is seldom used in the high frequency applications due to the serious static and dynamic voltage balance problems [3]. Second, three-level (TL) dc-dc converters (TLDCs) are suitable topologies for high voltage applications due to only half the input voltage stress on the primary switches [4]. The first diode-clamped TLDC was proposed in 1992 [4], and then, many other e fforts have been made on this topic, e.g., novel topologies and corresponding control strategies [4–11], wide range soft switching solutions [12–16] and reduced filter size solutions [16–19]. Finally, modular multilevel dc-dc converters (MMDCs) can also be used in high voltage applications [20]. MMDCs are built of modular cells with input series and output series or parallel connected, and can be extended to higher voltage levels easily due to their modular structure. Many TLDCs, e.g., diode-clamped TLDCs, can also be extended to a higher voltage level. But, as mentioned in [20], the number of achievable voltage levels is limited due to not only the dynamic voltage unbalance problem but also the complexity of the primary circuit structure and modulation strategy. Therefore, MMDCs may be a better choice for applications with super high input voltage, i.e., 1400 V or higher. A half bridge (HB) MMDC was proposed and discussed in [4], which is built of two-level HB modules. Several HB MMDCs for higher input voltage ratings have been proposed [21,22]. In [23], an FB MMDC was proposed, which is composed of two input series and output series connected two-level FB cells. Compared to HB MMDCs, FB MMDCs are more suitable for high input and large power industry applications due to the lower VA rating of the primary components, more modular structure and easy control. A number of new FB MMDCs were proposed and discussed in [20,23–26]. A new FB MMDC with auto-balance ability among series connected primary modules was proposed in [20]. Controlling strategies for output parallel-connected FB MMDCs were analyzed in [27–29]. However, improvements are still required. In the high voltage applications, soft switching performance of the primary switches is a key point to ensure higher efficiency due to the switching loss increases squared with the input voltage. Fortunately, the switching scheme of FB MMDCs is quite similar to that of the two-level phase shift (PS) FB dc-dc converter. Hence, common wide-range soft-switching solutions for conventional two-level PS FB dc-dc converters can be directly used in FB MMDCs. But, the system performance, structure complexity and added cost of di fferent solutions for FB MMDCs are quite di fferent because more primary cells are involved. Therefore, wide-range soft-switching FB MMDCs and a comparative evaluation of these solutions are still interesting subjects.

In this paper, some new wide-range soft-switching FB MMDCs are discussed and compared. The main contributions of this paper are:


This paper is organized as follows. In Section 2, the circuits of the presented converters are described. The operation principles and relevant analysis of an improved zero-voltage switching (IZVS) FB MMDC are provided in Section 3. The operation principles and relevant analysis of a zero-voltage and zero-current switching (ZVZCS) FB MMDC are discussed in Section 4. A comparative evaluation of the presented converters is provided in Section 5. In Section 6, experimental results are presented and analyzed. Finally, some brief conclusions are given.

#### **2. Wide-Range Soft-Switching PWM FB MMDCs**

Figure 1 illustrates a conventional FB MMDC, which is built of two two-level FB cells. The switches in each cell are switched in PS mode. Thus, eight switches in Figure 1 can also be divided into two groups, i.e., the leading and lagging switches. The lagging switches will face more di fficulty to obtain ZVS because only the energy stored in the leakage inductances can be used.

**Figure 1.** Conventional full-bridge (FB) modular multilevel dc–dc converter (MMDC).

As the switching scheme of Figure 1 is quite similar to that of a two-level PS FB dc-dc converter, common wide-range soft-switching solutions for two-level PS FB dc-dc converters can also be

used [30–37]. These solutions can be concluded into two types: IZVS and ZVZCS. IZVS converters extend the ZVS range of the lagging switches by increasing either the value of the primary equivalent inductance or the currents of the switches [30–34]. In the ZVZCS converters, the lagging switches can realize ZCS by resetting the primary current during the free-wheeling mode. According to the di fferent reset voltage generated methods, the ZVZCS converters can be further divided into two kinds, which are primary reset and secondary reset ZVZCS converters [35–37]. Generally, ZVZCS solutions are more suitable for the converters with IGBTs because of the large tailing current during the switching commutation.

#### *2.1. IZVS FB MMDCs*

Figure 2 shows four IZVS FB MMDCs. In IZVS\_CD, the upper FB primary cell is built of the switches S1 to S4, the primary coil T1p, Lr1, Dcl1, Dcl2 and the blocking capacitor CBL1; another primary cell is comprised of the switches S5 to S8, the primary coil T2p, Lr2, Dcl3, Dcl4 and the blocking capacitor CBL2. Lr1 and Lr2 are added to enlarge ZVS range of the lagging switches. Dcl1 to Dcl4 are used to eliminate the oscillation and clamp the secondary rectified voltage reflected to the primary side. The power transformer is built of two independent magnetic cores, two primary coils and two common secondary coils. Each primary coil is wired around an independent magnetic core; while the common secondary coils enclose both cores. Cin1 and Cin2 are the input capacitors with the same value, and these capacitors share the input voltage evenly during the operation stages, i.e., *V*Cin1 = *V*Cin2 = *V*in/2. Llk1 and Llk2 are leakage inductances of T1p and T2p. Do1 and Do2 are the rectifier diodes, and the output filter is built of Lo and Co. Ro is the load resistor.

**Figure 2.** Improved zero-voltage switching (IZVS) FB MMDCs: (**a**) IZVS with clamped diode (IZVS\_CD); (**b**) IZVS with commutation auxiliary circuit (IZVS\_CAC); (**c**) IZVS with small magnetizing inductance (IZVS\_SMI); (**d**) IZVS with secondary modulation method (IZVS\_SMM).

In IZVS\_CAC, two commutation auxiliary circuits (CACs) are added to enlarge the ZVS range of the lagging switches. The secondary rectifier of IZVS\_CAC is identical to that of IZVS\_CD. The configuration of IZVS\_SMI is quite similar to that of Figure 1. However, the magnetic currents of the transformer in IZVS\_SMI are increased to provide more resonant energy. The structure of the power transformers in IZVS\_CAC and IZVS\_SMI is identical to that of IZVS\_CD. IZVS\_SMM shows a secondary modulated FB MMDC. The primary structure of IZVS\_SMM is identical to that of IZVS\_SMI, and the magnetizing currents are also increased to help the ZVS of the primary switches. The transformer in IZVS\_SMM has two primary coils and two secondary coils. Do3 to Do6 are the rectifier diodes. Sse1 and Sse2 are two added secondary switches. The output filter is built of Lo and Co. Ro is the load resistor.

#### *2.2. ZVZCS FB MMDCs*

Figure 3 depicts four ZVZCS FB MMDCs. IZVZCS\_DCF is a primary current reset ZVZCS converter with two cut-o ff diodes in each FB cell. CBL1 and CBL2 are designed to a specific value to reset the primary currents. D3, D4, D7 and D8 are used to block the reverse primary currents. The secondary circuit of IZVZCS\_DCF equals that of IZVS\_CD. IZVZCS\_SAC&CAC and IZVZCS\_SRC&CAC illustrate two secondary reset ZVZCS FB MMDCs. In IZVZCS\_SAC&CAC, Sse and Cse are added to conventional FB MMDC to reset the primary currents; while the secondary reset circuit in IZVZCS\_SRC&CAC has the same function, which is composed of Dse1, Dse2 and Cse. In IZVZCS\_SI, CBL1 and CBL2 are designed to a specific value to reset the primary currents, and two saturable inductors, i.e., Lr1 and Lr2, are used to limit the reverse primary currents. The structure of the power transformers in Figure 3 is identical to that of IZVS\_CD.

**Figure 3.** Improved zero-voltage and zero-current switching (IZVZCS) FB MMDCs: (**a**) IZVZCS with diode cutting-o ff (IZVZCS\_DCF); (**b**) IZVZCS with secondary active clamping and commutation auxiliary circuit (IZVZCS\_SAC&CAC); (**c**) IZVZCS with secondary reactive clamping and commutation auxiliary circuit (IZVZCS\_SRC&CAC); (**d**) IZVZCS with saturable inductance (IZVZCS\_SI).

#### **3. IZVS FB MMDC with Secondary Modulated**

In order to simplify the description, the operation principle and characteristics of IZVS\_CD, IZVS\_CAC and IZVS\_SMI is not presented here, and corresponding information can be found in [30–33]. The IZVS\_SMM is selected as an example to analyze in detail in this part.

## *3.1. Operation Principle*

Key waveforms of IZVS\_SMM are shown in Figure 4. There are six operation stages during the whole switching cycle, and the operation stages in the first half switching cycle are illustrated in Figure 5. Before the analysis, some assumptions are set to simplify the explanation: all the components in the topology are ideal; Cin1 and Cin2 are large enough to be considered as voltage sources valued *V*in/2, and the voltage ripple on them can be neglected; CBL1 and CBL2 are large enough, and the voltage ripple on them can be neglected; *L*m1 = *L*m2 = *L*m; *L*L1K1 = *L*L1K2 = *L*1K; *I*m is the peak value of the magnetizing currents; output filter and load are replaced by a constant current source Io; kT1 and kT2 are the turn ratios *k*T- = (*k*T1 × *k*T2)/(*k*T1 + *k*T2). The output capacitance of each switch is identical and represented as Cos in the following equations.

**Figure 4.** Key waveforms of IZVS\_SMM.

Stage 1 [Figure 5a]: before *t*0, the circuit is operated in steady condition. Input source powers the load. S1, S4, S5 and S8 are on; Do2 is conducted; Sse2 is also on, and the current flowing through Sse2 is zero due to Do4 is <sup>o</sup>ff. *v*BC = *v*DE = *V*in/2; *v*rect = *V*in/*k*T2; *i*1p = *i*2p = *I*o/*k*T2; *i*L1k1 = *i*1p + *i*m1; *i*L1k2 = *i*2p + *i*m2; *i*m1 and *i*m2 increase with time linearly, and the slope is

$$\frac{di\_{\rm m1}}{dt} = \frac{di\_{\rm m2}}{dt} = \frac{V\_{\rm in}}{2L\_{\rm m}}\tag{1}$$

Stage 2 [Figure 5b, *t*0-*t*1]: At *t*0, Sse2 is turned off at zero-current. Primary side powers the load. *v*BC = *v*DE = *V*in/2; *v*rect = *V*in/*k*T2; *i*1p = *i*2p = *I*o/*k*T2; *i*L1k1 = *i*1p + *i*m1; *i*L1k2 = *i*2p + *i*m2; *i*m1 and *i*m2 keep increasing.

Stage 3 [Figure 5c, *t*1-*t*2]: At *t*1, Sse1 is turned on; Do1 is conducted and Do2 is <sup>o</sup>ff. Primary powers the load. *v*BC = *v*DE = *V*in/2; *v*rect = *V*in/2*k*T-; *i*1p = *i*2p = *I*o/*k*T-; *i*L1k1 = *i*1p + *i*m1; *i*L1k2 = *i*2p + *i*m2; *i*m1 and *i*m2 increase with time linearly.

**Figure 5.** Operation stages of IZVS\_SMM: (**a**) stage 1; (**b**) stage 2; (**c**) stage 3; (**d**) stage 4; (**e**) stage 5; (**f**) stage 6.

Stage 4 [Figure 5d, *t*2-*t*4]: At *t*2, S1, S4, S5 and S8 are simultaneously turned off at zero-voltage due to the existence of C1, C4, C5 and C8; *i*Llk1 charges C1 and C4, and discharges C2 and C3 linearly with time; *i*Llk2 charges C5 and C8, and discharges C6 and C7 linearly with time. During this interval, *i*m1 and *i*m2 reach their peak value *I*m and keep constant. Before *v*rect > 0, the energy stored in the output inductor can still be used to charge or discharge the output capacitance of each primary switch. When *v*rect is zero, one half of the final voltage on each primary switch has been charged or discharged [34]. Thus, less resonant energy is required to obtain ZVS for the primary switches, and this is the advantage of IZVS\_SMM. After *t*3, the circuit will be operated into the free-wheeling mode. *i*Llk1 charges C1 and C4, and discharges C2 and C3 linearly with time; *i*Llk2 charges C5 and C8, and discharges C6 and C7 linearly with time. This stage ends until *v*C1 = *v*C4 = *v*C5 = *v*C8 = *V*in/2 and *v*C2 = *v*C3 = *v*C6 = *v*C7= 0.

Stage 5 [Figure 5e, *t*4-*t*5]: At *t*4, D2, D3, D6 and D7 conduct naturally. The circuit operates in the free-wheeling mode; *i*Llk1 and *i*Llk2 decrease due to negative voltage applied to the terminals of Llk1 and Llk2; during this stage, S2, S3, S6 and S7 must be turned on to achieve ZVS. According to Figure 4, S2, S3, S6 and S7 are turned on at *t*5.

Stage 6 [Figure 5f, *t*5-*t*6]: At *t*5, S2, S3, S6 and S7 are switched on; *i*1p and *i*2p increase in the inverse direction. When these currents reach −*I*o/*k*T2, the free-wheeling mode is over. Primary powers load. After *t*6, *v*BC = *v*DE = −*V*in/2; *v*rect = −*V*in/*k*T2; *i*1p = *i*2p = −*I*o/*k*T2; *i*Llk1 equals the sum of *i*1p and *i*m1; *i*Llk2 equals the sum of *i*2p and *i*m2; *i*m1 and *i*m2 decrease with time linearly, and the slope is determined by (1). The current flowing through Sse1 is zero due to Do1 is <sup>o</sup>ff. After stage 6, the circuit will be operated in the second half switching cycle.

#### *3.2. Soft Start*

During the soft-start operation, the IZVS\_SMM can be treated as a conventional FB MMDC in Figure 1. Two secondary switches are <sup>o</sup>ff, and four primary switches in each FB module are switched in PS mode. The output voltage can be regulated down to zero by increasing the phase angle among the primary switches. Detailed operation principle about this procedure can be found in [23,24].

#### *3.3. ZVS Condition of The Primary Switches*

With proper design of *i*1m and *i*2m, all primary switches can obtain ZVS down to 0 load currents. S2 and S3 in the upper module are selected to describe as an example. Figure 5d shows the equivalent circuit of this procedure. Before *v*rect decays to zero, the load current can still be used to charge or discharge corresponding capacitors. As discussed above, 50% of the final voltage across C1 to C4 has been discharged or charged before *v*rect decays to zero. Thus, following equation should be fitted to obtain ZVS.

$$\frac{1}{2}L\_{\rm lk}l\_{\rm m}^2 \ge 2 \times \mathcal{C}\_{\rm cs} \left(\frac{V\_{\rm in}}{4}\right)^2\tag{2}$$

The required *I*m is

$$I\_{\rm m} \ge \frac{V\_{\rm in}}{2} \sqrt{\frac{\overline{\rm C}\_{\rm os}}{L\_{\rm lk}}} \tag{3}$$

The peak to peak value of *i*m is

$$
\Delta i\_{\rm m} = \frac{V\_{\rm in} T\_{\rm s}}{2L\_{\rm m}} = 2I\_{\rm m} \tag{4}
$$

Thus, *I*m is

$$I\_{\rm m} = \frac{V\_{\rm in} T\_{\rm s}}{4L\_{\rm m}} \tag{5}$$

Substituting (5) into (3) yields

$$L\_{\rm m} \le \frac{T\_s}{2} \sqrt{\frac{L\_{\rm lk}}{C\_{\rm os}}} \tag{6}$$

Therefore, S2 and S3 can obtain ZVS down to zero load current with a specific value of Lm decided by (6).

#### *3.4. ZCS Condition of The Secondary Switches*

As proved in Figures 4 and 5, all secondary switches can obtain ZCS independent of the load current. Sse2 is selected to describe as an example. As shown in Figure 5a, Sse2 is on in this stage. But, the current flowing through Sse2 is zero due to the reverse voltage applied to Do4. As shown in Figure 5b, Sse2 is switched off at zero current. Therefore, the switching loss of the secondary switches can be minimized.

#### *3.5. Turn Ratios*

The output is regulated by the phase angle among the primary and secondary switches. The turn ratios of IZVS\_SMM should be designed according to the input voltage range. At maximum input voltage, the phase angle between S1 and Sse1 is zero; primary powers the load through Ts2. With decreasing of the input voltage, the phase angle between S1 and Sse1 is increased, and primary powers the load through both Ts1 and Ts2. Hence, *k*T2 is

$$k\_{\rm T2} \le \frac{V\_{\rm increase}}{V\_{\rm o}}\tag{7}$$

And *k*T1 can be computed by

$$\frac{k\_{\rm T1}k\_{\rm T2}}{k\_{\rm T1} + k\_{\rm T2}} = \frac{V\_{\rm innin}}{V\_{\rm o}}\tag{8}$$

As for a converter with 100 to 300 V input and 50 V output (used in the prototype), *k*T2 can be decided by (7) and the value is 16; according to (8), *k*T1 = 48.

#### *3.6. Duty Ratio Loss*

The time between *t*5 and *t*6 is defined as duty ratio loss time, and corresponding states are plotted in Figures 5e and 5f. The primary side currents are

$$i\_{\rm kp} = \frac{I\_{\rm o}}{k\_{\rm T}'} - \frac{V\_{\rm in}}{2L\_{\rm lk}} \Delta t\_{56\prime} k = 1,2\tag{9}$$

when *i*kp = −*I*o/*k*T2, *k* = 1, 2, the free-wheeling mode is finished. The time of this interval is

$$
\Delta t\_{56} = \frac{2I\_{\rm o}L\_{\rm lk}}{V\_{\rm in}}(\frac{k\_{\rm T}' + k\_{\rm T2}}{k\_{\rm T}'k\_{\rm T2}}) \tag{10}
$$

The duty ratio loss is

$$
\Delta D = \frac{\Delta t\_{56}}{T\_s/2} = \frac{4I\_\text{o}L\_\text{lk}f\_\text{s}}{V\_{\text{in}}}(\frac{k\_\text{T}'+k\_\text{T2}}{k\_\text{T}'k\_\text{T2}}) \tag{11}
$$

#### *3.7. Reduced Filter Size*

The reduction of the output inductance with TL secondary rectified voltage waveform has been discussed in [16–19]. According to these references, the required output inductance of the converters with TL secondary rectified voltage waveform is about one-third of that of conventional two-level converters. Therefore, the volume of the output filter in the IZVS\_SMM can be significantly reduced.

#### **4. ZVZCS FB MMDC with Secondary Active Reset**

The IZVZCS\_SAC&CAC. is selected as an example to analyze in detail in this part. In order to simplify the description, the operation principle and characteristics of IZVZCS\_DCF, IZVZCS\_SRC&CAC and IZVZCS\_SI are not presented here, and detailed information can be found in [35,36] and [37].

## *4.1. Operation Principle*

Key waveforms of IZVZCS\_SAC&CAC are provided in Figure 6.

There are 12 operation stages in each switching cycle, and eight switching stages in the first half switching cycle are provided in Figure 7. Before the analysis, some assumptions are set to simplify the explanation: all the components in the topology are ideal; the voltage ripple on Cin1 and Cin2 can be neglected; *L*L1K1 = *L*L1K2 = *L*1K; *k*T is the turn ratio; the output filter and load are replaced by a constant current source Io. The output capacitance of each primary switch is identical and represented as Cos in the following equations.

Stage 1 [Figure 7a, *t*0-*t*1]: At *t*0, primary powers the load. S1, S4, S5 and S8 are on; Do1 is conducted while Do2 is <sup>o</sup>ff. The secondary rectified voltage is clamped by Cse through the anti-parallel diode of Sse. *i*Llk1 and *i*Llk2 are

$$i\_{\rm L1k1} = i\_{\rm L1k2} = \frac{1}{L\_{\rm lk}}(\frac{V\_{\rm in}}{2} - k\_{\rm T}v\_{\rm C,se})t \tag{12}$$

The current of the clamping capacitor Cse is

$$i\_{\rm Cse} = k\_{\rm T} i\_{\rm L1k1} - I\_{\rm o} \tag{13}$$

This stage ends until *i*Cse is 0.

Stage 2 [Figure 7b, *t*1-*t*2]: At *t*1, the anti-parallel diode of Sse is turned off; primary powers the load. S1, S4, S5 and S8 are on; Do1 is conducted while Do2 is <sup>o</sup>ff. *i*L1k1 = *i*L1k2 = *I*o/*k*T; *v*rect = *V*in/*k*T.

Stage 3 [Figure 7c, *t*2-*t*3]: At *t*2, S1 and S5 are turned off at zero-voltage due to the existence of D1 and D5. *i*Llk1 charges C1 and discharges C2 linearly with time, and *i*Llk2 charges C5 and discharges C6 linearly with time, the voltage of B is

$$v\_{\rm B}(t) = V\_{\rm in} - \frac{I\_{\rm o}}{k\_{\rm T}} \frac{t}{2C\_{\rm os}}\tag{14}$$

And the voltage of D is

$$w\_{\rm D}(t) = \frac{V\_{\rm in}}{2} - \frac{I\_{\rm o}}{k\_{\rm T}} \frac{t}{2C\_{\rm os}}\tag{15}$$

The time of this stage is

$$T\_{32} = \frac{V\_{\text{in}} C\_{\text{co}} k\_{\text{T}}}{I\_{\text{o}}} \tag{16}$$

After *t*3, D2 and D6 are turned on. Then, S2 and S6 should be gated to achieve ZVS, and according to Fig.6, S2 and S6 are switched at *t*3.

Stage 4 [Figure 7d, *t*3-*t*4]: At *t*3, S2 and S6 are turned on at zero-voltage. Sse is also turned on at this time. *v*rect is forced to *V*Cse, and this voltage is applied to the primary leakage inductances. Hence, *i*Llk1 and *i*Llk2 decrease, and the slope is

$$\frac{d\dot{i}\_{\rm L1k1}}{dt} = \frac{d\dot{i}\_{\rm L1k2}}{dt} = -\frac{k\_{\rm T}v\_{\rm C,se}}{L\_{\rm lk}}\tag{17}$$

**Figure 6.** Key waveforms of IZVZCS\_SAC&CAC.

**Figure 7.** Operation principle of IZVZCS\_SAC&CAC: (**a**) stage 1; (**b**) stage 2; (**c**) stage 3; (**d**) stage 4; (**e**) stage 5; (**f**) stage 6; (**g**) stage 7; (**h**) stage 8.

Stage 5 [Figure 7e, *t*4-*t*5]: At *t*4, *i*Llk1 and *i*Llk2 are 0, all rectifier diodes are <sup>o</sup>ff. Io is free-wheeled through Sse and Cse.

Stage 6 [Figure 7f, *t*5-*t*6]: At *t*5, Sse is <sup>o</sup>ff, and all rectified diodes are conducted. *i*Llk1 and *i*Llk2 keep zero.

Stage 7 [Figure 7g, *t*6-*t*7]: At *t*6, S4 and S8 are turned off at zero current.

Stage 8 [Figure 7h, *t*7-*t*8]: At *t*7, S3 and S7 are turned on at zero current due to the existence of Llk1 and Llk2. *i*Llk1 and *i*Llk2 decrease due to negative value applied to Llk1 and Llk2. When these currents reach -Io/*k*T, the free-wheeling mode is over. After stage 8, the circuit is operated in the second half period.

#### *4.2. Duty Ratio Loss*

The time between *t*7 and *t*8 is defined as the duty loss caused by the leakage inductances, and corresponding state is plotted in Figure 7 h. The primary side currents are

$$
\dot{m}\_{\rm L1ki} = 0 - \frac{V\_{\rm in}}{L\_{\rm lk}} \Delta t \gamma\_{\rm 8} \,\mathrm{i} = 1 \,\mathrm{2} \tag{18}
$$

when *i*L1ki = −*I*o/*k*T, the free-wheeling mode is accomplished, and the time of this interval is

$$
\Delta t\_{78} = \frac{2I\_{\text{o}}I\_{\text{tk}}}{V\_{\text{in}}} \tag{19}
$$

$$D\_{\rm L\\_loss} = \frac{\Delta t\_{78}}{T\_{\rm s}/2} = \frac{4I\_{\rm o}L\_{\rm l\&}f\_{\rm s}}{k\_{\rm T}V\_{\rm in}} \tag{20}$$

where *D*L\_loss is the duty ratio loss caused by the leakage inductances.

As shown in Figure 6, the primary currents are reset to zero during the interval of [*t*4, *t*5]. In order to ensure safe ZCS of the lagging switches, the maximum primary duty ratio should be limited as

$$D\_{p\text{-}max} = 1 - D\_{\text{reset}} \tag{21}$$

where *Dp*\_*max* is the maximum primary duty ratio of IZVZCS\_SAC&CAC.

However, as depicted in Figure 6, the primary reset time can be well compensated by the boost effect of secondary clamping, which is defined as *D*Boost in Figure 6. *D*Boost is identical to *D*reset, thus, total duty ratio loss of IZVZCS\_SAC&CAC is

$$D\_{\rm loss} = D\_{\rm L\\_loss} + D\_{\rm reset} - D\_{\rm Boost} = \frac{4I\_{\rm o}L\_{\rm lk}f\_{\rm s}}{k\_{\rm T}V\_{\rm in}} \tag{22}$$

where *D*loss is total duty ratio loss of IZVZCS\_SAC&CAC.

#### *4.3. ZVS Condition of the Leading Switches*

S2 is chosen as an example, the switching instant is provided in Figure 7c. ZVS criteria for S2 is

$$\frac{1}{2}L\_{\mathbb{P}}(\frac{I\_{\rm o}}{k\_{\rm T}})^2 \ge 2C\_{\rm co}(\frac{V\_{\rm in}}{2})^2\tag{23}$$

where *L*p is equal to *L*1k1 + *k*T2*L*o.

> The minimum load current to keep safe ZVS is

$$I\_{\rm o\\_min} = k\_{\rm T1} V\_{\rm in} \sqrt{\frac{\mathcal{C}\_{\rm os}}{L\_{\rm 1k1} + k\_{\rm T1}^2 L\_{\rm o}}} \tag{24}$$

The stored energy in the output inductance is large enough to conduct D2, so S2 can obtain ZVS in wide load range.

#### *4.4. ZCS Condition of the Lagging Switches*

As illustrated in Figure 6, the lagging switches should be turned off after *i*Llk1 and *i*Llk2 decay to zero. The reset time is T43, and its value is

$$T\_{43} = \frac{I\_{\rm o} I\_{\rm lk}}{k\_{\rm T}^2 V\_{\rm Cse}} \tag{25}$$

When IGBTs are used as the lagging switches, the minority carriers in the component can be combined in a specific time, and this interval is determined by the component itself and defined as TCOM. Therefore, the following equation should be confirmed to ensure ZCS operation:

$$T\_{43} + T\_{\text{com}} \le T\_{\text{reset}} \tag{26}$$

## **5. Comparative Evaluation**

In this section, a comparative evaluation of the proposed converters with regard to soft-switching characteristics, duty ratio loss, the current rating of the primary components, power loss distribution, number of added components and added cost is provided to highlight the advantages and disadvantages of each converter and to help the selection of a candidate for a given application.
