**1. Introduction**

Static synchronous compensator (STATCOM) is an effective solution for fast voltage/reactive power support during normal and faulty conditions [1,2]. During the last decades, much research has been carried out on its structure, control, modulation, and application [3–7]. For medium-voltage application, STATCOM usually adopts the multi-level converter topology, including the flying-capacitor multi-level converter [8], diode-clamped multilevel converter [9], and cascaded multi-level converter [10–12]. Since the modular multilevel converter (MMC) topology was proposed and applied [13], MMC-based STATCOM has gained growing attention because of its outstanding performance, such as a low harmonic, low losses, scalability, and redundant design [14–16]. Especially with the development of new energy power generation, it has obtained wide applications and has become the standard configuration in wind farms and photovoltaic power plants to improve low voltage ride through capability [17,18]. In most applications, its capacity is generally 10–100 Mvar. In 2018, South Korea built three ±400 Mvar STATCOMs, which are the world largest [19].

To ensure the safe, reliable, and stable operation of a newly manufactured STATCOM, a complete set of pre-operation tests are necessary. The standard IEEE P1052/08 [20] contains a special chapter to guide STATCOM testing, and specifies the factory test items of STACOM components, such as switching devices and controls. IEC 62927 defined the detailed requirements of electrical testing for STATCOM converter [21]. It lists many test items and objectives of value or value section, but rarely gives the corresponding test circuit or method. For the testing of STATCOM controls, a real-time digital simulator (RTDS) is usually employed to form a hardware- in-the-loop test system where the main circuit part is digitally modeled [22,23]. It can comprehensively test the control and protection systems, but cannot evaluate any main power component. For the testing of STATCOM value, the common method is to employ two submodules to form a back-to-back test platform [24,25]. It can check the converter adequacy with regard to current, voltage, and temperature stresses in various operation conditions. But it requires an extra DC voltage source connected to the DC-bus of one submodule, so that the active power loss of the submodules during operation can be supplemented. It applies to submodules rather than value section, which consist of several submodules, because the latter does not have a common DC-bus. In fact, the most critical difficulty for value section tests is the requirement for energy supplements. A typical test method for value section is that two value sections are connected in parallel to a single-phase source. One section generates inductive reactive current, while the other generates capacitive reactive current; meanwhile the voltage source provides a certain current to supplement the active losses of value sections. Because the medium voltage distribution network is usually three-phase three-wire system, this method requires a single-phase high-power voltage source instead of the grid, resulting in higher test platform cost. In [26], an equivalent testing method was presented for full-power testing of STATCOM converter. It employs an additional high-voltage DC source and two low-voltage DC sources besides two tested STATCOM converters. These DC sources are used to charge the tested converters and compensate their active loss during operation. This also leads to high platform cost and a large footprint.

All these testing methods are for individual component of STATCOM, but not for a complete machine. But the performance of STATCOM depends on, not only individual components, but also component assembly, components wiring, and mutual coordination among devices. Therefore, it is necessary to conduct a whole machine test for a newly manufactured STATCOM. For the testing of whole STATCOM, an intuitive idea is to directly carry out a full-power test in the factory. Since the STATCOM rating is usually far beyond the power supply capacity of a factory, such an idea is not feasible. An alternative option is to employ two STATCOMs to form a back-to-back test platform [27]. One is operated as test object to output the rated reactive current, while the other is used as an accompanying device to output the opposite reactive current to neutralize the former, thereby maintaining the tiny total grid current. It can test the actual performance of the whole STATCOM, but requires an extra STATCOM besides the tested one, resulting in very high cost and poor utilization. Moreover, it has high requirement for synchronous coordinated control of these two STATCOMs. Therefore, such a test is almost impossible in the practical applications. In [28], a current closed-loop test method for ±100 Mvar STATCOM was proposed, based on the principle of equal potential. Firstly, three-phase STATCOM was connected to the grid to charge, and then disconnected from the grid and short-circuit at the three-phase ports to conduct zero-voltage full-current closed-loop operation. It can conveniently verify the capability of current control as well as voltage insulation level of a complete STATCOM. However, under this method, STATCOM operates either, at high voltage or high current and, therefore, cannot test the actual operating characteristics at both the rated voltage and rated current. Moreover, it can only run for a short time so it cannot be used for long-term power assessment of the STATCOM.

To overcome these problems, this paper proposes an individual phase full-power testing method for STATCOM. In this method, three-phase STATCOM was reconstructed into a structure that two phases are in parallel and then series with the third-phase. Then, by rationally matching the voltage and current of each phase, the parallel two phases can steadily operate under both the rated voltage and current, thus realize a phase full-power test. The corresponding math relationship was analyzed and a double-loop control system was designed. A simulation was carried out in Matlab, and the simulation results show that STATCOM can stably operate under the proposed system.

#### **2. Circuit Configuration and Operation Principle**

The circuit configuration of the proposed testing method is shown in Figure 1. It can seem that one phase port of the normal STATCOM is disconnected from the grid, and then shorted to one of the other two phases. Its equivalent circuit model is shown in Figure 2, where the A-phase and B-phase arms are connected in parallel, and then in series, with the C-phase to a single-phase voltage source, whose amplitude equals the rated line voltage rather than the rated phase voltage.

**Figure 1.** Circuit configuration of the proposed STATCOM testing method.

**Figure 2.** Equivalent simplified circuit diagram of the proposed testing system.

Under the aforementioned structure, three phase converters are individually controlled as follows: (1) The output voltage of the C-phase converter was properly adjusted so that the amplitude of the A-phase voltage is just equal to its rated phase voltage, namely, the C-phase voltage is equal to the vector difference between the access line voltage and the expected A-phase voltage.

(2) The currents in the parallel two phases were controlled to perform a phase-to-phase reactive current hedging with the rated current amplitude, namely, one phase follows the rated capacitive reactive current, while the other with the rated inductive reactive current.

In this way, for the A-phase or B-phase arm (including the converter value and filter reactance), both its voltage and current reached the rated values, thus achieving a phase full-power operation. Moreover, since the reactive currents form a circulation between A-phase and B-phase arms, the grid current is tiny and close to zero, thus the power supply capacity of such test platform is relatively small and easy to implement.

Similarly, by changing the shorted phase, the full power test for B-phase or C-phase converter can also be realized. Then all of three phases are individually tested at phase full-power condition, so this method can be named as individual phase full-power testing method.

#### **3. Mathematical Model of the Individual Phase Full-Power Testing System**

#### *3.1. Basic Relationship and Constraints*

In the equivalent circuit model shown as Figure 2, the voltage and current of three phase arms meet the basic relationship as following:

$$\begin{cases} \begin{aligned} \boldsymbol{u}\_{AO} &= R\_A \dot{\boldsymbol{i}}\_A + L\_A \frac{d}{dt} \dot{\boldsymbol{i}}\_A + \boldsymbol{u}\_{tO} \\ \boldsymbol{u}\_{AO} &= R\_B \dot{\boldsymbol{i}}\_B + L\_B \frac{d}{dt} \dot{\boldsymbol{i}}\_B + \boldsymbol{u}\_{tO} \\ \boldsymbol{u}\_{CO} &= R\_C \dot{\boldsymbol{i}}\_C + L\_C \frac{d}{dt} \dot{\boldsymbol{i}}\_C + \boldsymbol{u}\_{tO} \end{aligned} \tag{1}$$

$$\begin{cases} \text{ i}\_{\text{C}} = -(\text{i}\_{A} + \text{i}\_{B})\\ \text{ } u\_{\text{CO}} = u\_{AO} - u\_{AC} \end{cases} \tag{2}$$

where *uAO*, *uCO* represent the arm voltages of A-phase and C-phase (i.e., *uAO* is the voltage difference between the A-phase port **A** and the internal neutral point **O** in Figure 2, similar is *<sup>u</sup>CO*). *iA*, *iB*, and *iC* are the arm currents. *uaO*, *ubO*, and *ucO* are the output voltage of three converters (i.e., *uaO* is the voltage difference between the port *a* in Figure 2 and the neutral point **O**, similar are *ubO* and *ucO*). *RA*, *RB,* and *RC* are the equivalent resistance of each arm, *LA*, *LB*, and *LC* are the inductance of each arm. While, *uAC* represents the grid access voltage between the A-phase and C-phase ports, and depends mainly on the grid rather than the STATCOM.

Considering the defined operating conditions of this test system, the above voltages satisfy the following constraints: (1) The amplitude of A-phase voltage *uAO* (not the A-phase converter output voltage *uaO*) equals to the rated phase voltage of STATCOM to reach the rated voltage condition; (2) the amplitude of line voltage *uAC* equals to the rated line voltage; (3) the amplitude of C-phase converter output voltage *ucO* cannot exceed its maximum allowable range. Since the C-phase current in this test system is far less than its rated value, its voltage drop across resistance and inductance is very tiny. Thus, the amplitude of C-phase arm voltage *uCO* is very close to that of C-phase converter voltage *ucO*. In short, the amplitudes of the above voltages satisfy the following constraints:

$$\begin{cases} \|\mu\_{AO}\| = \mathcal{U}\_{\mathbb{PN}}\\ \|\mu\_{AC}\| = \mathcal{U}\_{\mathbb{IN}} = \sqrt{3}\mathcal{U}\_{\mathbb{PN}}\\ \|\mu\_{CO}\| \le \mathcal{U}\_{\text{cmax}} \end{cases} \tag{3}$$

where *UpN*, and *UlN*, respectively represent the amplitudes of the rated phase and line voltages of STATCOM. While, *Uc*max represents the maximum output voltage of every phase converter, generally, it is larger than the rated phase voltage of STATCOM.

Ideally, there is only the rated amplitude of inductive/capacitive reactive current in A-phase and B-phase arms, while C-phase current is zero (because A-phase and B-phase arms constitute a circulating current). In fact, due to the loop resistance and switching device loss in every phase, each phase requires the absorption of a certain active power from the grid to compensate the resistance losses and convertor losses, and then maintain its active power balance, so that the DC-link voltage of each converter can remain stable. Under typical hardware parameters, the active current is about 1% of the rated current when each phase operates at its rated voltage and current. Although the active current has little effect on the amplitude of phase current, it is essential to maintain the active power balance. Therefore, in the steady state operation, both A-phase and B-phase currents contain reactive and active components, while C-phase current contains the negative sum of the active components in the A-phase and B-phase currents, and it would also contain the remaining reactive components that are not completely neutralized.

In terms of amplitude, the A-phase and B-phase currents are approximately equal to their rated value, while C-phase current is much smaller. Since the active loss of each phase is closely related to its current amplitude, in the steady state operation, the absorbed active power of three phases (not the active power of static converters) can be expressed as:

$$\begin{cases} P\_A = \mu\_{AO} \cdot i\_A = \mathcal{U}\_{PN} I\_{aP} > 0 \\ P\_B = \mu\_{BO} \cdot i\_B = \mathcal{U}\_{PN} I\_{bP} > 0 \\ P\_C = \mu\_{CO} \cdot i\_C \approx 0 \end{cases} \tag{4}$$

where *IaP*, and *IbP*, respectively represent the active components in A-phase and B-phase currents.

Combining the constraints (2)–(4), we can plot the voltage and current vector diagram of the STATCOM as Figure 3. Here the A-phase voltage vector *uAO* is selected as the orientation reference, and then according to the voltage constraints (3), the C-phase voltage vector *uCO* can only be on the circle with point C as the center and the rated line voltage *UlN* as the radius, moreover it has to be within the circle with point O as the center and the maximum converter voltage *Ucmax* as the radius. Combining the two requirements, the C-phase voltage vector has to be on the arcs CC- in Figure 3.

**Figure 3.** The basic voltage and current vector diagram of the testing system.

According to equation (4), the angle between the A-phase voltage *uAO* and current *iA* must be less than 90◦, namely, the A-phase current must contains some positive active component, and the same is true for the B-phase voltage and current. At the same time, because the C-phase voltage and current are not at zero, in order to satisfy the third formula in equation (4), the C-phase voltage vector *uCO* and current *iC* must be basically vertical to each other. Based on the above constraints, we can deduce two conclusions:


#### *3.2. Recommended Voltage-Current Combination*

In the range satisfying the foregoing constraints, there are many alternative combinations of voltage and current. As an example, here we choose a representative combination as Figure 4, and their math expressions are as follows:

$$\begin{cases} \boldsymbol{u}\_{\rm C} = \boldsymbol{\mathcal{U}}\_{\rm pN} \boldsymbol{e}^{j(-120^{\circ})} \\ \boldsymbol{i}\_{A} = \boldsymbol{I}\_{\rm aP} + j\boldsymbol{I}\_{\rm pN} \\ \boldsymbol{i}\_{B} = \boldsymbol{I}\_{\rm bP} - j\boldsymbol{I}\_{\rm pN} + j\boldsymbol{I}\_{\rm add} \end{cases} \tag{5}$$

where *Iadd* represents an additional reactive component in the B-phase current. It is usually negative in steady state but can also be positive or zero during some dynamic process.

**Figure 4.** The voltage and current vector diagram of the recommended voltage-current combination.

Substituting Equation (5) into (2), the C-phase current can be calculated as:

$$i\_{\mathbb{C}} = -(i\_A + i\_B) = -(I\_{aP} + I\_{bP}) - jI\_{\text{add}} \tag{6}$$

while the C-phase absorbed active power from the outside can be calculated as:

$$\begin{split} P\_{\mathbb{C}} &= u\_{\text{CO}} \cdot i\_{\mathbb{C}} = \left[ \mathbb{U}\_{\text{pN}} \text{cos} (-120^{\circ}) + \text{j} \mathbb{U}\_{\text{pN}} \text{sin} (-120^{\circ}) \right] \cdot \left[ - (I\_{\text{aP}} + I\_{\text{bP}}) - j I\_{\text{add}} \right] \\ &= \frac{1}{2} \mathbb{U}\_{\text{pN}} (I\_{\text{aP}} + I\_{\text{bP}}) + \frac{\sqrt{3}}{2} \mathbb{U}\_{\text{pN}} I\_{\text{add}} \end{split} \tag{7}$$

As in (7), by adjusting the additional component *Iadd* in the B-phase current, the active power absorbed by the C-phase arm can be regulated in order to achieve the stability of the DC-bus voltage of C-phase converter. On the other hand, for B-phase arm, this additional component *Iadd* is the reactive current component, so it has no effect on the active power balance of B-phase arm. Of course, it has ye<sup>t</sup> no effect on the active power balance of A-phase arm. In other words, we can independently regulate the C-phase convertor DC voltage without affecting the other two phases.

#### **4. Control System Design**

#### *4.1. Control System Structure*

Based on foregoing analysis, the control structure of the proposed testing system is constructed as Figure 5. Firstly, a phase locked loop (PLL) was employed to extract the phase information of the access port voltage, and then generated a plurality of phase references. Secondly, the individual phase instantaneous control was used to calculate the required voltage of every-phase converter [29,30]. Finally, the carrier phase shifting pulse width modulation (CPS-PWM) [31,32] was used to generate the required drive signals for each MMC submodule. The specific structure is as follows.


**Figure 5.** The control system block of the proposed testing system.

#### *4.2. Soft Power-on Process for the Individual Phase Full-Load Testing System*

Since the circuit configuration of the individual phase full-power testing system is different from conventional three-phase STATCOM, the conventional soft power-on process is no longer applicable for the individual phase testing system. To solve this problem, the paper proposes a soft power-on method applicable for this configuration, and shown as Figure 6.


**Figure 6.** The flow diagram of soft power-on process for the individual phase full-load testing system.

#### **5. Simulation Verification**

In order to verify the proposed STATCOM testing system, a simulation model was built in Matlab/Simulink. Its circuit configuration and control structure are shown as Figures 1 and 5, and the main simulation parameters are listed in Table 1.

In the simulation process, three different operating conditions are set:


The simulation results are shown in Figures 7–10.


**Table 1.** Parameters in the simulation model.

As shown in Figure 7, in the soft power-on process of 0–1.6 s, the DC-bus voltage of each phase converter rises smoothly to its expected value, and each current is far below the rated value. During this process, there are four stages: Firstly, both three phase converters were charging; secondly, A-phase converter charging; thirdly, C-phase converter charging; fourthly, no-load standby. This proves the feasibility of the proposed soft power-on method. It should be noted, in order to speed up the simulation so as to show the overall process in a limited time, the starting resistor in the simulation model is set to be small as 25 Ω. Generally, the actual soft-starting resistance is larger, thus the corresponding inrush current is smaller and the power-on process would be smoother.

As shown in Figure 8, during the transient process when the DC voltage reference steps at *t* = 1.6 s, three phase voltages are significantly different from the soft start process, but both their amplitude and phases are in line with their expectations, as shown Figure 4. The DC-bus voltages of three phase converters gradually rise to their set values and then remain stable, and each phase current is also gradually reduced from the initial sinusoidal waveform to near zero. During this period, both the amplitude and phase of A-phase current are different from that of B-phase current. This is because the B-phase current contains an additional component to regulate the C-phase DC-bus voltage.

As shown in Figure 9, during the third stage, three-phase currents quickly reach their steady state and then remain stable, while three-phase DC voltages remain stable. Among them, both A-phase and B-phase current quickly reach their rated value, their amplitudes are substantially equal, and their phases are approximately opposite. At the same time, the C-phase current is far less than the A-phase current. In Figure 9, the A-phase and C-phase voltage deals with a low-pass filter to show the low frequency components. In order to show the harmonic distortion in the proposed system, the original voltage and current without filtering are given in Figure 10. It can be seen that the fundamental component of the C-phase current is about 3% of the rated value (23 A/800 A = 2.9%).

**Figure 7.** Simulation results of the proposed soft power-on process.

As in Figure 10 shown, the original output voltages of three-phase converters are typical multi-level waveform. Because the number of submodules in this simulation are only four in each phase, there are various high-frequency ripples. It can be expected that when the submodules number increases, the output voltage would be smoother, thus the current ripple will be smaller. Although, there are obvious high-frequency components in A-phase and C-phase voltage, their fundamental components are still consistent with the expected values, indicating that these high-frequency harmonic components do not affect the feasibility of the testing system.

**Figure 8.** Simulation results when the DC-bus voltage reference is step.

**Figure 9.** Simulation results at the individual phase full-power operation state.

**Figure 10.** Original voltage and current without filtering at the full-power operation state.
