**1. Introduction**

Five-level inverters are power electronic converters that play important roles in applications of mechanical-electrical systems, transportation, power quality management, renewable energy conversion system, and motor drives [1–4]. In the design of five-level inverters, di fferent topologies have been evolved, including the diode-clamped [5–9], flying capacitor [10–13], cascaded H bridge [14–16], and T type topologies [17–20]. A new single-phase five-level T-type inverter can reduce the harmonic components compared with that of the traditional full-bridge three-level PWM inverter under the same conditions of DC voltage source and switching frequency [18]. In [19] the DC-DC boost converter is connected to a five-level inverter and PI control is used, to control the inverter with much less total harmonic distortion (THD) and near unity power factor. To enhance the input voltage, three PV strings in cascade and parallel configurations with the five-level inverter are found in [19]. To maintain the power factor at near unity, the inverters in [19] and [20] use a proportional–integral (PI) current control scheme. The main solutions for the small-scale rooftop PV applications are proposed in [20]. That paper presents a comparison of four multilevel converters based on the T-type topology.

The switching loss is very important to evaluate the performance of the inverter, especially when multilevel inverter operates at a high frequency. Several studies on switching loss reduction have been introduced in recent years [21–26]. The complete analytical calculation of the switching loss is proposed in [23] for the basic inverters. The switching losses of the IGBT depend on switching frequency, load current, input DC voltage, and characteristics of switches are presented in [24]. The paper [24] shows that the total switching losses of the inverter on a control voltage period are proportional to switching frequency, load current, and DC voltage supply. The switching frequency depends on the carrier frequency and the modulation method. Note that the switching frequency is opposite to the total harmonic distortion (THD) of the output voltage. So that, lower carrier frequencies based switching loss reduction can increase THD value. Therefore, a new technique for switching loss reduction without THD increment is needed to be solved. As a result, the switching energy of the switches when the switches operate is turned on (Ec(on)) or turned off (Ec(off)) mode, are determined by current and voltage across the switch (*IC* and *VCE*) [25].

The average switching loss in the switch (*PS*) during each period *Ts* is calculated as Equation (1) [25].

$$P\_S = \frac{1}{6} \left( V\_{CE} I\_s \frac{t\_{\rm c(on)} + t\_{\rm c(off)}}{T\_s} \right) - \frac{1}{3} \left( V\_{out} I\_s \frac{t\_{\rm c(on)} + t\_{\rm c(off)}}{T\_s} \right) \tag{1}$$

where:

> *fs*—switching frequency

*VCE*—voltage across the switch when the switch is turned off *Von*—voltage across the switch when the switch is turned on *Is*—current through the switch when the switch is turned on *tc(on)*—turn-on cross-over interval *tc(o*ff*)*—turn-off cross-over interval

From Equation (1), it can be seen that to reduce switching losses it needs to reduce switching frequency (*fs*). Or for reduction switching loss, it needs to choose a switching state based on *IC* and *VCE* of phase to have the smallest value in the three-phase. As a result, *fs*, *IC* and *VCE* are three basic elements that affect to reduce switching loss. A new space vector modulation strategy with two PI regulators is used in both DC voltage and load voltage sides for controlling the PWM parameters. So, the non-switching state can be controlled by these parameters to generate pulses as found in [26]. The switching losses are reduced by reducing either switching frequency or instantaneous current and voltage values at the time of switching in [26]. Since using two PI regulators, the control technique is very complex and hard to control for the system.

A reduced switching loss PWM strategy to eliminate common mode voltage in multilevel inverters is presented in [27]. This PWM method has increased switching times for the phase with the smallest load current by comparing the three-phase load current to eliminate common mode voltage. Simulation and experimental results in [27] are performed based on the standard models with the collector-emitter voltage of the IGBTs equaled. Therefore, for application to other models, which the voltage crossed IGBTs is not the same, as if the 5L-HBT2I, its effect of loss reduction may not be very high. The two modified space vector modulation strategies were proposed in [28] for the reduction of the qZSI number of switch commutations at high current level with shorter periods during the fundamental cycle, i.e., reducing the switching loss, simplifying the generation of the gate signals by utilizing only three reference signals, and achieving a single switch commutation at a time were also presented in [28].

This paper proposes a new modulation technique to reduce the number of switch commutations for switching losses reduction. There is no switching on the phase which the control voltage has the smallest displacement to top or bottom of the carrier, and the absolute of the load current being the first or second large. In addition, reducing turn on and off the switch that has a large across voltage, will be done to reduce switching losses. The paper is organized as follows: in Section 2, the topology, operating principles, and circuit analysis of the three-phase 5L-HBT2I are presented. Section 3 presents switching loss calculation for 5L-HBT2I. Section 4 presents the proposed PWM scheme. Simulation and experimental results are shown in Section 5. Finally, the result is summarized in Section 6.

#### **2. Three-Phase Five-Level H-Bridge T-Type Inverter Topology**

Figure 1 shows the three-phase 5L-HBT2I. As shown in Figure 1a, the 5L-HBT2I consists of three DC sources (*U*a, *U*b, *U*c), six capacitors (*C*a1, *C*b1, *C*c1, *C*a2, *C*b2, and *C*c2), and three T-type H-bridge circuits.

**Figure 1.** Five-level T-type H-bridge inverter topologies. (**a**) Three-phase inverter and (**b**) One phase module.

Define *TSxi* is status of the *i*th switch on phase *x* (*x* = a, b, c); where *i* is the index of switches (1 to 5), with conditions:

$$T\_{\text{Sxi}} = \begin{cases} \ 0 \text{ if } \text{Sxi} \text{ off} \\ \ 1 \text{ if } \text{Sxi} \text{ or} \end{cases} \tag{2}$$

$$T\_{\text{Sx5}} + T\_{\text{Sx4}} = 1\tag{3}$$

$$T\_{\rm Sx1} + T\_{\rm Sx2} + T\_{\rm Sx3} = 1\tag{4}$$

Figure 1b shows a structure of phase *x*, where a leg of 5L-HBT2I is built from two single-phase inverters: two-level and three-level T-type.

From Equations (3) and (4), the pole voltage of two-level ( *Ux2-cx*) and three-level T type inverter (*Ux3-cx*) are determined:

$$
\Delta I\_{\rm x2-cx} = (2T\_{\rm Sx5} - 1)\frac{V\_{\rm dc}}{2} \tag{5}
$$

$$\mathcal{U}\_{\rm x3-cx} = \left(2T\_{\rm Sx3} + T\_{\rm Sx2} - 1\right) \frac{V\_{dc}}{2} \tag{6}$$

Hence, the voltage from phase to pole (Uxg) is determined as

$$V\_{\rm x\%} = \mathcal{U}\mathbf{1}\_{\rm x3-cx} - \mathcal{U}\mathbf{1}\_{\rm x2-cx} = \left(2T\_{\rm Sx3} + T\_{\rm Sx2} - 2T\_{\rm Sx5}\right)\frac{V\_{\rm dc}}{2} \tag{7}$$

Set *TSx* is status of phase *x*:

$$T\_{\rm Sx} = 2T\_{\rm Sx3} + T\_{\rm Sx2} - 2T\_{\rm Sx5} \tag{8}$$

So, the phase to pole voltages is given as Equation (9).

$$
\begin{bmatrix} V\_{\text{ag}} \\ V\_{\text{bg}} \\ V\_{\text{cg}} \end{bmatrix} = \frac{V\_{\text{dc}}}{2} \begin{bmatrix} T\_{\text{Sa}} \\ T\_{\text{Sb}} \\ T\_{\text{Sc}} \end{bmatrix} \tag{9}
$$

The output phase and line-to-line voltages of this inverter is given as Equations (10) and (11).

$$
\begin{bmatrix} V\_{an} \\ V\_{bn} \\ V\_{cn} \end{bmatrix} = \frac{1}{3} \begin{bmatrix} 2 & -1 & -1 \\ -1 & 2 & -1 \\ -1 & -1 & 2 \end{bmatrix} \begin{bmatrix} V\_{a\circ} \\ V\_{b\circ} \\ V\_{c\circ} \end{bmatrix} \tag{10}
$$

$$
\begin{bmatrix} V\_{ab} \\ V\_{hc} \\ V\_{ca} \end{bmatrix} = \begin{bmatrix} 1 & -1 & 0 \\ 0 & 1 & -1 \\ -1 & 0 & 1 \end{bmatrix} \begin{bmatrix} V\_{an} \\ V\_{bn} \\ V\_{cn} \end{bmatrix} \tag{11}
$$

As a result, the third order harmonic does not appear in the output phase voltage ( *Vxn*), while it appears in both pole voltage ( *Vxg*) and line-to-line voltage. Therefore, the proposed algorithm has o ffset the function at the third order harmonic, which will not a ffect the third order harmonic magnitude of the load. From Equation (8) to Equation (11), the values of *Vxg* can be determined in Table 1. As shown in Table 1, the pole voltage *Vxg* has five levels including two positive, two negative, and one zero.

**Table 1.** Switching state of five-level H-bridge T-type inverter (5L-HBT2I) for phase-*x* index.


#### **3. Switching Loss Calculation for 5L-HBT2I**

The switching loss depends on the load current and collector-emitter voltage of the power switches and the number of commutations during the entire fundamental cycle [24,25]. Therefore, the switching losses of the 5L-HBT2I will be calculated based on the switching losses of the power switches of each phase, where phase *x* consists of five switches: *Sx*1–*Sx*5, *x* = a, b, c.

Figure 1b and Table 1 can be seen that

$$V\_{CE1} = V\_{CE2} = V\_{CE3} = V\_{C2}/2 = V\_{C2}/2 = V\_{\&}/2\tag{12}$$

where *VCE,i* is the voltage across switch *Sxi* when *Sxi* is turned-off (*i* = 1, 2, 3, 4, 5).

And the current through switches, *is* is determined as

$$\dot{i}\_{\rm si} = \left| \dot{i}\_{\rm Lx}(\theta) \right| \qquad \text{where } \theta \text{ is phase angle, } \propto a \text{, } b \text{, } c \tag{13}$$

In Equation (13), *iSi* and *iLx* are current through switch *Sxi* when *Sxi* is turned-on (*i* = 1, 2, 3, 4, 5) and the load current over phase *x* (*x* = a, b, c), respectively.

Hence, the average value of the local (per control voltage cycle) switching loss over switches *Sx*1–*Sx*5 (for instance, for phase-a) can be calculated as [27]

$$P\_{S1} = \frac{1}{2\pi} (t\_{\varepsilon(on)} + t\_{\varepsilon(off)}) \int\_0^{2\pi} \left( \frac{V\_{CE1}}{6} - \frac{V\_{on}}{3} \right) i\_{s1} d\theta = \frac{1}{2\pi} (t\_{\varepsilon(on)} + t\_{\varepsilon(off)}) \left( \frac{V\_{dc}}{12} - \frac{V\_{on}}{3} \right) \int\_0^{2\pi} i\_{s1} d\theta \quad (14)$$

Similarly, we have

$$P\_{S2} = \frac{1}{2\pi} (t\_{c(on)} + t\_{c(off)}) \left(\frac{V\_{dc}}{12} - \frac{V\_{on}}{3}\right) \int\_0^{2\pi} i\_{s2} d\theta \tag{15}$$

$$P\_{S3} = \frac{1}{2\pi} (t\_{c(on)} + t\_{c(off)}) \left(\frac{V\_{dc}}{12} - \frac{V\_{on}}{3}\right) \int\_0^{2\pi} i\_{s3} d\theta \tag{16}$$

$$P\_{\rm S4} = \frac{1}{2\pi} (t\_{c(on)} + t\_{c(off)}) \left(\frac{V\_{dc}}{6} - \frac{V\_{on}}{3}\right) \int\_{0}^{2\pi} i\_{s4} d\theta \tag{17}$$

$$P\_{S5} = \frac{1}{2\pi} (t\_{c(on)} + t\_{c(off)}) \left(\frac{V\_{dc}}{6} - \frac{V\_{on}}{3}\right) \int\_0^{2\pi} i\_{s5} d\theta \tag{18}$$

where *PSi* is an average value of the local (per carrier cycle) switching loss over the switch (*i* = 1, 2, 3, 4, 5). *Von,i is* voltage across switch *Sxi* in turned-on state.

Equations (14)–(18) can show that switching loss decreases if the switching is on the phase, which has a small load current. Due to the decrement of the number of commutations on two-level inverter switches (*Sx*5 or *Sx*4), the switching loss will be smaller when compared with three-level T-type inverter switches (*Sx*1 or *Sx*2 or *Sx*3).

As a result, the proposed technique helps to reduce the switching loss by reducing the number of commutations on the phase, which has the absolute of the load current are first or second large in three-phase and by reducing the number of commutations on two level inverter.

#### **4. Proposed Algorithm**

#### *4.1. Principle of the Proposed Algorithm*

The switching loss depends on the current through power switches, the voltage across the switch, and the number of commutations in the period of control voltage is shown in Equations (14)–(18). Since the switching loss can be decreased by reducing switching frequency of *Sx*5 and *Sx*4 and reducing the number of commutations on the phase, which has the absolute of the load current is high or medium in comparison to another phase. Therefore, in the first stage, the new control voltages are determined with a non-switching state on the phase, which has the smallest displacement to top or bottom peak (of the carrier) and the absolute of the load current being the first or second largest. In addition, in the second stage, the control voltages that have been determined in the previous stage, are divided into the control voltage for the two-level inverter and three-level T-type inverter for reducing switch turn-on/turn-off on the two-level inverter.

The first stage:

It is defined that *vx* is the initial control voltage phase *x* (*x* = a, b, c) and *vrx* is control voltage that it is determined as the new control voltage by adding voffset into *vx* from first stage of proposed algorithm. The maximum ampplitude of carrier is selected by 1. Due to the 5-level inverter, threshold comparison of the carrier is 0, 1, 2, 3 and 4. The initial control voltage of phase *vx* is determined as Equation (19).

$$v\_x = m \frac{4}{\sqrt{3}} \cos(\omega t + \theta\_{0x}) + 2\tag{19}$$

where *vx*, *m*, ω and θ*0x* are the initial control voltage of phase *x*, modulation index, angular velocity, and initial phase angle, respectively.

The error of *vx* and *Lx* are determined:

$$L\_{\mathbf{x}} = \begin{cases} \begin{array}{c} \int \text{int}(\upsilon\_{\mathbf{x}}) \text{ if } \inf(\upsilon\_{\mathbf{x}}) < 4 \\ \text{int}(\upsilon\_{\mathbf{x}} - 1) \end{array}; \ H\_{\mathbf{x}} = L\_{\mathbf{x}} + 1 \end{cases} \tag{20}$$

$$e\_{\mathbf{x}} = \upsilon\_{\mathbf{x}} - L\_{\mathbf{x}} \tag{21}$$

Call *IxABS* is the absolute of current across phase *x*, then

$$\dot{\mathbf{u}}\_{\mathbf{x},\mathbf{A}\mathbf{S}} = \left| \dot{\mathbf{u}}\_{\mathbf{L}\mathbf{x}}(\theta) \right| \tag{22}$$

where θ is phase angle, *ILx* is the load current of phase *x* (*x* = a, b, c).

The maximum, minimum, medium of error (*emax*, *emin*, *emed*) and the maximum and medium of absolute of load current (*Imax*, *Imed*) are defined:

$$\mathfrak{e}\_{\max} = \mathsf{max}(\mathfrak{e}\_{\mathfrak{a}\prime} \ \mathfrak{e}\_{\mathfrak{b}\prime} \mathfrak{e}\_{\mathfrak{c}}), \ \mathfrak{e}\_{\min} = \min(\mathfrak{e}\_{\mathfrak{a}\prime} \ \mathfrak{e}\_{\mathfrak{b}\prime} \mathfrak{e}\_{\mathfrak{c}}), \ \mathfrak{e}\_{\max} = \mathsf{med}(\mathfrak{e}\_{\mathfrak{a}\prime} \ \mathfrak{e}\_{\mathfrak{b}\prime} \mathfrak{e}\_{\mathfrak{c}}) \tag{23}$$

$$i\_{\text{max}} = \max(i\_{a\text{ABS}\_{\prime}}, i\_{b\text{ABS}\_{\prime}}, i\_{c\text{ABS}}), \ i\_{\text{med}} = \text{med}(i\_{a\text{ABS}\_{\prime}}, i\_{b\text{ABS}\_{\prime}}, i\_{c\text{ABS}}) \tag{24}$$

Case 1: When the *ixABS* is the largest and (*ex* = *emin*) or (*ex* = *emax*), the none switching phase is *x* and the offset voltage (*vo*ff*set*) is determined through the value ex as Equation (25)

$$
v\_{offset} = \begin{bmatrix} -\mathbf{e}\_x \text{ if } \mathbf{e}\_x = \mathbf{e}\_{min} \\ 1 - \mathbf{e}\_x \text{ if } \mathbf{e}\_x = \mathbf{e}\_{max} \end{bmatrix} . \tag{25}$$

Case 2: When *iaABS* is the largest and *ea* equal the *emed*, for reducing error of output voltages, the offset voltage will be not equal to *ea*. In this case, another phase has the absolute of the load current as medium (assuming it is phase b) and the error (*eb*) of *vb* and *Lb* fix the maximum or minimum. Then, the offset voltage is calculated following *ibABS* and *eb* as Equation (26)

$$v\_{offset} = \begin{array}{l} 1 - c\_b \text{ if } (c\_b = c\_{max}) \text{ and } (i\_{bABS} = i\_{mcd})\\ -c\_b \text{ if } (c\_b = c\_{min}) \text{ and } (i\_{bABS} = i\_{mcd}) \end{array} \tag{26}$$

Thus, the offset values can be determined as *ixABS* and *ex* in Table 2.


**Table 2.** The offset voltage of the 5L-HBT2I.

*NA*: Not applicable.

If the matrixes from Equation (27) to Equation (31) are defined, the offset voltage will be calculated as Equation (32).

> ⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

⎧⎪⎪⎪⎨⎪⎪⎪⎩

$$\begin{aligned} \begin{bmatrix} I\_{\text{max}} \end{bmatrix} &= \begin{bmatrix} a\_{\text{max}} & b\_{\text{max}} & c\_{\text{max}} \end{bmatrix} \\ \mathbf{x}\_{\text{max}} &= \begin{bmatrix} 1 \text{ if } i\_{\text{x}ABSS} = i\_{\text{max}} \\ 0 \text{ else} \end{bmatrix} \end{aligned} \tag{27}$$

$$\begin{cases} \begin{array}{cc} \begin{bmatrix} I\_{mcd} \end{bmatrix} = \begin{bmatrix} a\_{mcd} & b\_{mcd} & c\_{mcd} \end{bmatrix} \end{array} \end{cases} \right] $$
 
$$\begin{array}{c} \begin{array}{c} \begin{array}{c} \text{1} \ i \ i\_{xABS} = i\_{mcd} \end{array} \end{array} \end{cases} \begin{array}{c} \begin{array}{c} \text{1} \ i \ i\_{xABS} = i\_{mcd} \end{array} \end{array} \tag{28}$$

$$\begin{cases} \begin{array}{|c|c|} \hline \begin{Bmatrix} E\_{\text{max}} \end{Bmatrix} = \begin{Bmatrix} \mathcal{c}\_{\text{argmax}} & \mathcal{c}\_{\text{bmax}} \end{Bmatrix} \\\\ \mathcal{c}\_{\text{xmax}} = \begin{bmatrix} 1 \text{ if } \mathcal{c}\_{\text{x}} = \mathcal{c}\_{\text{max}} \\\ 0 \text{ else} \end{bmatrix} \end{cases} \end{cases} \tag{29}$$

$$\begin{cases} \begin{array}{cc} \begin{array}{c} \begin{array}{c} \begin{array}{c} \begin{array}{c} \varepsilon\_{\text{mcd}} \end{array} \end{array} \end{array} \end{cases} \begin{array}{c} \begin{array}{c} \varepsilon\_{\text{bmd}} \end{array} \end{array} \begin{array}{c} \begin{array}{c} \varepsilon\_{\text{cmd}} \end{array} \end{array} \right] \end{cases} \end{cases}$$

$$\varepsilon\_{\text{xmcd}} = \begin{bmatrix} \begin{array}{c} 1 \ if \ e\_{\text{x}} = e\_{\text{mcd}} \\ 0 \text{ else} \end{array} \end{bmatrix} \tag{30}$$

$$\begin{aligned} \begin{bmatrix} E\_{\text{min}} \end{bmatrix} &= \begin{bmatrix} \mathfrak{e}\_{\text{amin}} & \mathfrak{e}\_{l \text{min}} \, \mathfrak{e}\_{\text{cmin}} \end{bmatrix} \\ \begin{array}{l} \mathfrak{e}\_{\text{x} \text{min}} = \begin{bmatrix} 1 \; \text{if } \mathfrak{e}\_{\text{x}} = \mathfrak{e}\_{\text{min}} \\ 0 \; \text{else} \end{bmatrix} \end{aligned} \tag{31}$$

$$\boldsymbol{w}\_{offset} = \begin{bmatrix} \left[I\_{\max}\right] \left[E\_{\max}\right]^T \left(1 - \varepsilon\_{\max}\right) - \left[I\_{\max}\right] \left[E\_{\min}\right]^T \boldsymbol{e}\_{\min} \ \boldsymbol{i} \ \boldsymbol{f} \ \left[I\_{\max}\right] \left[E\_{\max}\right]^T = \boldsymbol{0} \\\ \left[I\_{\max}\right] \left[E\_{\max}\right]^T \left(1 - \varepsilon\_{\max}\right) - \left[I\_{\max}\right] \left[E\_{\min}\right]^T \boldsymbol{e}\_{\min} \ \boldsymbol{e} \ \boldsymbol{else} \end{bmatrix} \tag{32}$$

The new control voltage *vrx* is determined

$$
\upsilon\_{rx} = \upsilon\_x + \upsilon\_{offset} \tag{33}
$$

Since matrixes [*Imax*], [*Imed*], [*Emax*], [*Emed*] and [*Emin*] have "0" and "1" values, which can be determined by simple comparison commands lead to the calculation of the offset voltage easy and quick. The new control voltage (*vrx*) is the old control voltage (*vx*) add the offset voltage. The new control voltages (*vrx*) on the phase which the absolute of the load current are first or the second large in three-phase and *ex* equal *emax* or *emin* will be shifted to the top or bottom peak of the carrier.

Figure 2 shows the shift of the control voltages according to the conditions of the proposed algorithm. As shown in Figure 2a, when (*iaABS* = *imax*) and (*ea* = *emin*), the offset voltage is <sup>−</sup>*ea*. This offset voltage is added to the original control voltages so the new control voltages will shift down to the new positions. The new position of the control voltage of phase-a will be *La*. Therefore, there will be no switching on the phase-a when (*iaABS* = *imax*) *and* (*ea* = *emin*) as shown in Figure 2b. Similarly, the switching state on the phase-b is off if (*IaABS* ≥ *IbABS* ≥ *IcABS*), (*ea* = *emed*) *and* (*eb* = *emin* or *emax*), as shown in Figure 2c or 2d.

**Figure 2.** Offset voltages under the proposed algorithm. (**a**) (*iaABS* = *imax*) *and* (*ea* = *emin*); (**b**) (*iaABS* = *imax*)*and* (*ea* = *emax*); (**c**) (*iaABS* ≥ *ibABS* ≥ *icABS*), (*ea* = *emed*) *and* (*eb* = *emin*); (**d**) (*iaABS* ≥ *ibABS* ≥ *icABS*), (*ea* = *emed*) *and* (*eb* = *emax*).

The second stage:

In the second stage, the control voltages that were created in the previous stage will be divided into the control voltage for the two-level inverter and three-level T-type inverter. Since the two-level inverter is operated in six-step mode, its control voltage can be calculated as

$$
v\_{\mathbf{x},2l} = \begin{bmatrix} 1 \ if \ v\_{rx} \ge 2 \\ & 0 \ els\varepsilon \end{bmatrix} \tag{34}$$

In addition, from Equation (7), it is easy to determine the control voltages for three-level T type, which are:

$$
v\_{x,\ \mathcal{U}} = v\_{rx} - 2v\_{x,\mathcal{U}}\tag{35}$$

where *vrx* is the control voltage, created form first stage; *vx*,2*l* and *vx*,3*l* are the control voltages for two-level inverter and T-type inverter on phase *x*.

#### *4.2. Flow Chart*

Figure 3 shows a flow chart of the proposed algorithm using simple commands such as subtraction, and comparison on the program. The comparison of the phase currents can be done by comparing hardware circuits that do not require the use of expensive sensors. Thus, calculation time of the algorithm is low and suitable for closed-loop control or other control methods.

For example, assuming that control voltages *va*, *vb*, and *vc* are 1.12 V, 0.64 V and 3.24 V, respectively, from Equation (22), the error of *vx* and *Lx* are *ea* = 0.12, *eb* = 0.64, and *ec* = 0.24. From Equation (24), *emin* = 0.12, *emax* = 0.64, *emid* = 0.24.

Assuming that *IaABS* > *IbABS* > *IcABS*, from Equations (27) and (28), [*Imax*] = [100], [*Imid*]=[010]. From Equations (30)–(32), [*Emax*] = [010], [*Emed*]=[001], [*Emin*]=[100]. From Equations (22)–(32), the offset voltage is *vo f f det* = −*emin* = −0.12. Then, new control voltages are *vra* = *va* − *emin* = 1 V, *vrb* = *vb* − *emin* = 0.52 V, *vrc* = *vc* − *emin* = 3.12 V.

When *vra* = 1 V, switches S1, S3, and S5 are turned off while switches S2 and S4 are turned on. Thus, the phase-a switches will not be switched in one cycle *T*. Similarly, when *vrc* = 3.12 V, S1, S3, and S4 are turned off while S2 and S5 are switching. As a result, the phase-c switches will be switched in one cycle *T*. Therefore, the proposed algorithm can reduce the switching times of the switches.

**Figure 3.** The flow chart of the proposed scheme.

#### **5. Simulation and Experimental Results**

#### *5.1. Simulation Results*

Parameters used in simulation is shown in Table 3. Figure 4 shows the simulation results of the proposed algorithm when modulation index are 0.4 and 0.9, respectively. The waveforms from top to bottom in Figure 4 are three-phase absolute current, three-phase error (*ea, eb, ec*), maximum and minimum errors (*emax* and *emin*), the initial voltage (*vx*) and new control voltage (*Vrx*), control voltage of two-level inverter (*va*2*L*), and control voltage of three-level T-type inverter (*va*3*L*), the next waveforms are gating signals of *Sx*1 to *Sx*5 and the bottom is the pole voltage output. It can be seen that from *t*1 to *t*2, *iaABS* is maximum and *ea* hit maximum (*emax)*, then *vo*ff*set* will be 1 − *ea* lead to the control voltage of phase a move up to 3*V*; see Figure 4a and obtain 4V; see Figure 4b. As shown in Figure 4a, during a time interval of [*t*1 to *t*2], the control phase-a voltage is 4 *V*. As a result, the switching states on phase-a are (*S*5*a* = 0, *S*4*a* = 1, *S*3*a* = 1, *S*2*a* = 0 and *S*1*a* = 0) and its phase pole voltage is *Vag* = *Vdc* = 100 V. Similarly, in Figure 4b, the phase-a to pole voltage is *Vag* = *Vdc* 2 = 50 V when (*S*5*a* = 0, *S*4*a* = 1, *S*3*a* = 0, *S*2*a* = 1 and *S*1*a* = 0). From *t*3 to *t*4, *ibABS* is maximum, the *eb* is medium. Simultaneously, the absolute of phase a current load (*iaABS*) is medium and *ea* is emin as analyzed in the above section, the offset voltage is –ea and the new control voltage of phase a shift down 0 V (*m* = 0.9) and 1 V (*m* = 0.4), so there is no switching in phase-a. Similarly, the phase-b and phase-c in the situation have no switching.


**Table 3.** Parameters used in simulation.

#### **Figure 4.** *Cont.*

**Figure 4.** Control voltage generation, gating signals of Sa1 to Sa5 and the phase pole voltage in the proposed technique with (**<sup>a</sup>**,**<sup>c</sup>**) *m* = 0.4 and (**b**,**d**) *m* = 0.9.

To evaluate the efficiency of switching loss reduction, IGBT CM1000HA-24H module (Mitsubishi Electric., Tokyo, Japan) in PSIM's device database is used in the simulation. Figure 5 shows the conduction loss (*Pc-sinPWM*), switching loss (*Ps-sinPWM*) using sine PWM algorithm and conduction loss (*Pc-proposed*), switching loss (*PS-proposed*) using the proposed algorithm on a phase on changing carrier frequency. As a result, the proposed technique can reduce switching losses. The switching loss reduction value is maximized when *m* = 0.5, equivalent to 78% reduction. There is no significant difference in conduction loss (*Pc*) between the proposed algorithm and sinPWM algorithm, especially at low carrier frequencies. The difference in conduction loss is due to the difference in the high harmonic amplitude between the proposed algorithm and sinPWM algorithm. When the carrier frequency is not high enough (e.g., at *fc* = 5 kHz), the load phase voltage that applies the proposed technique has the high harmonic amplitude at some modulation index values. Therefore, the conduction loss in this case is greater than that in the sinPWM method as in Figure 5c,d. The harmonics spectrum of the proposed and sinPWM algorithms are presented in Figure 6. The harmonics with a large amplitude in the proposed technique focus around the carrier frequency, while they are around twice the carrier frequency in the sinPWM algorithm. The THD of the phase current in the two algorithms is slightly different, as seen in Figure 7.

**Figure 5.** *Cont.*

**Figure 5.** Power loss on a phase under sinPWM method and proposed algorithm at carrier frequency of (**a**) 20 kHz, (**b**) 15 kHz, (**c**) 10 kHz, and (**d**) 5 kHz.

**Figure 6.** Harmonics spectrum of phase voltage at *fs* = 20 kHz using (**a**) sinPWM method with *m* = 0.4, (**b**) proposed method with *m* = 0.4, (**c**) sinPWM method with *m* = 0.9, and (**d**) proposed method with *m* = 0.9.

**Figure 7.** Total harmonic distortion (THD) comparison between sinPWM method and proposed technique at *fs* = 20 kHz.

Figure 7 shows a comparison of THD values of the phase current between sinPWM method and the proposed technique. As shown in Figure 7, THD value of the phase voltage of 5L-HBT2I under the proposed algorithm is smaller than that with the sinPWM method at *fc* = 20 kHz. This can explain that the two-level inverter only operates in a six-step mode with rarely rapid changes of phase voltage on this inverter. As a result, the output harmonics have a small amplitude and conductive losses are also lower than sinPWM techniques, as shown in Figure 5.

Under the load of 40 Ω and 10 mH at the output frequency of 50 Hz, the calculated load power factor is 0.997. Table 4 shows the power factor (PF) and the power factor displacement (PFD) in simulation. As shown in Table 4, the simulated power factor of the inverter is lower than the calculated load power factor of 0.997. This is due to the harmonics distortion of load current and voltage.


**Table 4.** Simulated power factor and power factor displacement.

## *5.2. Experimental Results*

An experimental model based on the DSP TMS320F28335 microcontroller (Texas Instruments, Dallas, TX, US) is built in the laboratory to verify the effectiveness of the proposed control technique with the elements in Table 5. Figure 8 shows a laboratory prototype. The input voltage is 100 V. The output frequency is 50 Hz, while the switching frequency of the inverter circuit is 5 kHz. A three-phase inductive load of 40 Ω and 10 mH is used in the experiment.

**Table 5.** Elements used in experiment.


**Figure 8.** Experimental setup of the prototype.

Figure 9 shows the experimental result of the proposed algorithm when *m* = 0.9 and *m* = 0.4. In Figure 9, the waveforms from the top to the bottom are the gating control signals of the power switches SA5, SA3, SA2 and SA1, the pole voltage (*Vag*), the phase voltage that its harmonic spectrum is in Figure 10. The experimental result of the proposed algorithm in Figure 9 are under modulation index *m* = 0.4 (Figure 9a) and *m* = 0.9 (Figure 9b).

**Figure 9.** Experimental results at (**a**) *m* = 0.4 and (**b**) *m* = 0.9.

The experimental results are close to the simulation results. Figure 9a,b show the position "no switching" in the phase, which has the absolute of its load current hitting maximum or medium in three phases. The gating signal of SA5 is similar to that of SA4, that is the switch of the two-level inverter. This is similar to its waveform in the six-steps mode.

Figure 10 shows the experimental results of the load current fast Fourier transform (FFT) and its THD at *m* = 0.4 and 0.9. The experimental results are close to the simulation results. As shown in Figure 10, the THD of the load current with the proposed algorithm at *m* = 0.4 is bigger it at *m* = 0.9. Since the THD of the load current under the proposed algorithm is smaller than 5%, this complies in the standard IEC61000-4-30 Edition 2 Class A. The experimental results in Figure 10 show that the amplitude of lower harmonics is very small. That is one of the advantages of the proposed technique. The measured THD values in Figure 10 are close to the simulation results shown in Figure 7.

**Figure 10.** The load current fast Fourier transform (FFT) and its THD. (**a**) *m* = 0.4 and (**b**) *m* = 0.9.
