**1. Introduction**

At present, with the consumption of fossil fuels and environmental pollution, people are increasingly persistent in the development of renewable distributed energy generation systems such as photovoltaic (PV), fuel cell (FC), and so on [1–5]. Among them, photovoltaic power generation, which is used to convert solar energy into electricity, is the most widely applied [6–8]. However, the output electricity is DC, and therefore an inverter is necessary for the photovoltaic power generation system [9].

Based on the availability of transformers, inverters are divided into isolated inverters and non-isolated inverters [10]. Isolated inverters have the advantage of isolating, which can eliminate leakage current and ensure the safety of staff. However, the isolated inverters will have a large volume and loss due to the existing transformers [11], which do not meet the concept of energy saving. As such, more people have turned their attention to non-isolated inverters [12].

Many interesting non-isolated topologies, such as H5 [13], H6 [14], and ZVR [15], have been presented in the literature. Although constantly improving topologies or control methods can reduce their leakage currents to a certain extent, the existing leakage currents in their topologies cannot be eliminated from the source. Furthermore, the voltage gain of these topologies is often unsatisfied.

A grea<sup>t</sup> deal of attention has been paid to the Z-source inverter (ZSI) since it was first proposed [16]. The characteristic of the Z-source inverter is that it has very high boost capacity. Therefore, many quasi and semi Z-source inverters have been developed [17–19], but they still cannot deal thoroughly with the problem of leakage current. As a result, some inverter topologies that are combined with Z-source topologies and have the feature of dual-grounding are proposed [20]. Based on the analysis of leakage current [21], dual-grounding can completely solve the problem of leakage current. Although the proposed inverters in [20] have their advantages, they are not suitable for some field applications.; the buck–boost-based type of three-switch three-state (TSTS) ZSIs cannot produce reactive power and the boost-based type of TSTS ZSIs cannot filter well, due to the lack of a filter inductor, which results in higher total harmonic distortion (THD). A new Z-source inverter-based on a CUK converter is proposed in [22], which has a better filter compared to the inverters in [20], but there is a current spark in the S1 switch when the topology starts. The SEPIC-based Z-source inverter is proposed in [23], but its performance is not verified by experiments.

According to the above analysis, this paper puts forward a novel Z-source inverter based on a SEPIC converter. Compared with traditional semi and quasi Z-source inverters, the proposed inverter has the feature of dual-grounding, which is valid for thoroughly eliminating leakage current. Furthermore, the voltage gain of the proposed inverter is more than 1, which can be applied well for a flexible output situation. Furthermore, the proposed inverter is based on a SEPIC converter. The SEPIC converter has the superiority of having the same polarity of input and output, the isolation of input and output, and a complete turn-off. At the same time, the proposed topology has solved the current spark problem in the S1 switch. Therefore, a new topology named "SEPIC-based ZSI" is presented. This topology can be used in situations where flexible control voltage is required. At the same time, the sine output is negative first and then positive, which can meet some application requirements.

This paper is organized as follows: Firstly, the operation modes of the proposed inverter are analyzed and the design of the components is presented in Section 2. Section 3 displays the control diagram of the proposed inverter and some key waveforms under the driven signal. Secondly, the theoretical analysis is proved through corresponding simulations and experiments, which are shown in Section 4. Finally, a complete summary of the proposed topology is given in Section 5.

#### **2. Operation Mode and Analysis of the Novel Inverter**

The operation mode, including the mode analysis and the design of the proposed SEPIC-based ZSI, including the parameters calculation, is discussed in this section.

#### *2.1. Structure and Operation Mode*

The structure of the proposed SEPIC-based ZSI, which is derived from a combination of a Z-source inverter and a SEPIC converter, is shown in Figure 1. Z-source inverters have an outstanding buck–boost capacity and the SEPIC converter has advantages including the same polarity of input and output, the isolation of input and output, and a complete turn-off. Furthermore, the negative terminal of the PV array is connected to the load side, which is necessary for eliminating leakage current, as shown in Figure 1. Three operation modes are shown in Figure 2.

**Figure 1.** Proposed SEPIC-based Z-source inverter (ZSI).

**Figure 2.** Equivalent circuits of the SEPIC-based ZSI in one switching period (**a**) S1 and S3 are ON, S2 is OFF; (**b**) S1 and S2 are ON, S3 is OFF; and (**c**) S2 and S3 are ON, S1 is OFF.

The operation modes are discussed as follows: In mode I, as shown in Figure 2a, switch S1 and switch S3 are on, whereas switch S2 is off. The inductor, *Lf*, is magnetized by input voltage *Vin*, and capacitors *C*1, *C*2, and *C*3 are charged. According to Kirchhoff's law of voltage and current, the expression of this mode is shown in Equations (1) and (2). In mode II, switch S3 is off and switches S1 and S2 are on, as shown in Figure 2b. The inductor, *Lf*, is magnetized by input voltage *Vin*, and capacitors *C*1, *C*2, and *C*3 are discharged. Equations (3) and (4) show the expression of mode II. In mode III, switches S2 and S3 are turned on while switch S1 is turned off, as depicted in Figure 2c. Capacitors *C*1, *C*2, and

*C*3 are charged. The equations of this mode are expressed as shown in Equations (5) and (6). In Figure 2, the dashed line direction represents the current direction of the inductors.

$$\begin{cases} V\_{Lf} = V\_{in} \\ V\_{L1} = -(V\_{\rm C0} + V\_{\rm C2} + V\_{\rm C3}) \\ V\_{L2} = -(V\_{\rm C0} + V\_{\rm C1} + V\_{\rm C3}) \\ V\_{L3} = -V\_{\rm C3} \end{cases} \tag{1}$$

$$\begin{cases} \ i\_{\rm C1} = i\_{L2} \\ \ i\_{\rm C2} = i\_{L1} \\ \ i\_{\rm C3} = i\_{L1} + i\_{L2} + i\_{L3} \\ \ i\_{\rm C0} = i\_{L1} + i\_{L2} - i\_o \end{cases} \tag{2}$$

where *Vin* denotes the input voltage; *VC*0, *VC*1, *VC*2, and *VC*3 are the voltage of capacitors *C*0, *C*1, *C*2, and *C*3; and *iC*1, *iC*2, and *iC*3 are the current of capacitors *C*1, *C*2, and *C*3. Similarly, *VL*1, *VL*2, *VL*3, and *VL f* are the voltage of inductors *L*1, *L*2, *L*3, and input inductor *Lf*, and *iL*1, *iL*2, and *iL*3 are the current of inductors *L*1, *L*2, and *L*3. *io* is the output current.

$$\begin{cases} V\_{Lf} = V\_{in} \\ V\_{L1} = V\_{C1} \\ V\_{L2} = V\_{C2} \\ V\_{L3} = -V\_{C3} \end{cases} \tag{3}$$

$$\begin{cases} \begin{aligned} i\_{C1} &= -i\_{L1} \\ i\_{C2} &= -i\_{L2} \\ i\_{C3} &= -i\_{L3} \\ i\_{C0} &= -i\_o \end{aligned} \tag{4} \end{aligned} \tag{4}$$

$$\begin{cases} V\_{Lf} = V\_{in} - (V\_{C0} + V\_{C1} + V\_{C2} + V\_{C3}) \\ V\_{L1} = V\_{C1} \\ V\_{L2} = V\_{C2} \\ V\_{L3} = V\_{C0} + V\_{C1} + V\_{C2} \end{cases} \tag{5}$$

$$\begin{cases} i\_{C1} = i\_{Lf} - i\_{L1} - i\_{L3} \\ i\_{C2} = i\_{Lf} - i\_{L2} - i\_{L3} \\ i\_{C3} = i\_{Lf} \\ i\_{C0} = i\_{Lf} - i\_{L3} - i\_{o} \end{cases} \tag{6}$$

where *iLf* is the current of inductor *Lf*.

#### *2.2. Voltage in Capacitors and Current in Inductors*

In order to simplify calculation, we suppose that the value of inductor *L*1 is equal to the value of inductor *L*2, similarly, we suppose the value of capacitor *C*1 is equal to capacitor *C*2. At the same time, all passive components are ideal. Then, based on the volt-second balance principle, the voltage of capacitors and the current of inductors can be expressed easily as follows:

$$\begin{cases} \begin{array}{c} \frac{V\_{\text{C1}}}{V\_{iv}} = \frac{V\_{\text{C2}}}{V\_{iv}} = \frac{1 - D\_2}{1 - D\_1} \\ \frac{V\_{\text{C3}}}{V\_{iv}} = 1 \\ \frac{V\_o}{V\_{iv}} = \frac{D\_1 + 2D\_2 - 2}{1 - D\_1} \end{array} \tag{7}$$

$$\begin{cases} \ i\_{L1} = i\_{L2} = i\_o \\ \ i\_{L3} = -i\_o \\ \ i\_{Lf} = \frac{2 - D\_1 - 2D\_2}{D\_1 - 1} i\_o \end{cases} \tag{8}$$

where *D*1 is the duty cycle of switch S1, *D*2 is the duty cycle of switch S2, and *Io* is the output current.

#### *2.3. Design of Inductors*

According to mode I, the input inductor *Lf* is magnetized by input voltage, so the current ripple of inductor *Lf* can be calculated by combining the equations in mode I with the expression of inductor voltage, *VL* = *LdiL*/*dt*. The equation of the current ripple of inductor *Lf* is shown as follows:

$$
\Delta i\_{L\_f} = \frac{V\_{in} D\_1 T\_s}{Lf},
\tag{9}
$$

where Δ*iLf* is the current ripple of inductor *Lf* and *Ts* denotes the switching period. Δ*iLf* is related to the input voltage *Vin*, duty cycle *D*1, switching frequency, and the value of inductor *Lf*.

Then, according to Equation (9), inductor *Lf* can be calculated as follows:

$$Lf = \frac{V\_{\rm in} D\_1 T\_s}{\Delta \dot{t}\_{Lf}}.\tag{10}$$

Similarly, inductors *L*1 and *L*2 are related to *D*2. Then, combining Equation (7), inductors *L*1 and *L*2 can be calculated as follows:

$$L1 = L2 = \frac{V\_{\subset 1} D\_2 T\_s}{\Delta i\_{L1}} = \frac{V\_{\text{in}} (1 - D\_2) D\_2 T\_s}{\Delta i\_{L1} (1 - D\_1)},\tag{11}$$

where Δ*iL*1 denotes the current ripple of inductor *L*1.

At the same time, by combining Equation (8), inductor *L*3 can be expressed as follows:

$$L3 = \frac{V\_{C3} D\_1 T\_s}{\Delta i\_{L3}} = \frac{V\_{in} D\_1 T\_s}{\Delta i\_{L3}},\tag{12}$$

where Δ*iL*3 denotes the current ripple of inductor *L*3.

#### *2.4. Design of Capacitors*

According to the above calculations of the inductors, the voltage ripple of the capacitor *C*1 is affected by the current of inductor *L*1, the duty cycle of switch S2, switching frequency, and the value of *C*1. Therefore, the same principle is applied to capacitors and, based on *ic* = *CdVc*/*dt*, the value of capacitors can be calculated as follows:

$$C1 = C2 = \frac{i\_{L1}(1 - D\_2)T\_s}{\Delta V\_{C2}} \, , \tag{13}$$

where Δ*VC*2 is the voltage ripple of capacitor *C*2.

As for the value of capacitor *C*3, it is associated with the current of inductor *L*3. The equation is shown as follows:

$$\text{C3} = \frac{i\_{L3}(1 - D\_2)T\_s}{\Delta V\_{C3}},\tag{14}$$

where Δ*VC*3 is the voltage ripple of capacitor *C*3.

Finally, the value of output capacitor *C*0 can be calculated as follows:

$$\text{CO} = \frac{2I\_0 D\_3 T\_s}{\Delta V\_{\text{CO}}},\tag{15}$$

where Δ*VC*0 is the voltage ripple of capacitor *C*0.

#### *2.5. Peak Voltage and Current in Switches and Analysis*

According to Figure 2 and Equations (1), (2), (7) and (8), the peak voltage and current of switches can be concluded as follows:

$$V\_{S-\text{max}} = (1+k)V\_{\text{in}}.\tag{16}$$

$$I\_{S-\max} = (A+1)I\_{0\prime} \tag{17}$$

where *VS*−max and *IS*−max are the maximum voltage stresses and current stresses, respectively. *k* and *A* represent maximum boost ratio and voltage gain, respectively. *Io* is the output current, which can be expressed as follows:

$$I\_o = I\_m \sin \omega t,\tag{18}$$

where *Im* is the maximum output current.

#### **3. Control Method**

The expression of the duty cycle, key waveforms, and control diagram are displayed in this section. At the same time, the implementation of control in MATLAB is also shown.

#### *3.1. Expression of Duty Cycle*

The output voltage of the SEPIC-based TSTS Z-source inverter is defined as follows:

$$v\_o = V\_o \sin \omega t = AV\_{\text{in}} \sin \omega t\_\prime \tag{19}$$

where *A*, or the peak voltage gain, is defined as *A* = *Vo*/*Vin* and the maximum output voltage is *Vo*.

Regarding boost, *D*1 is set as a constant value and *k* as the maximum boost ratio, defined as follows [20]:

$$k = \frac{D\_1}{1 - D\_1} \Rightarrow D\_1 = \frac{k}{1 + k}.\tag{20}$$

Regarding the inversion part, the sinusoidal output voltage, *vo*, is generated by *D*2 as a varied sinusoidal value. *D*3 can be written from *D*1 and *D*2, and they are defined as follows [20]:

$$D\_2 = \frac{k+2}{2(k+1)} - \frac{A}{2(k+1)}\sin\omega t,\tag{21}$$

$$D\_3 = 2 - D\_1 - D\_2.\tag{22}$$

#### *3.2. Key Waveforms in the Switching Cycle and Analysis*

According to the above analysis, it is easy to ge<sup>t</sup> the key theoretical waveforms of the proposed topology, as shown in Figure 3. The values *vgs*1, *vgs*2, and *vgs*3 are the switching statuses of switches S1, S2, and S3, respectively. The values *Vs*1, *Vs*2, and *Vs*3 are the voltages of switches S1, S2, and S3. When the switch is turned on, the voltage of the switch will be equal to zero. In contrast, there will be voltage in the switch when it is turned off and the value of voltage is equal to *Vin*(1 + *k*), based on Equation (16). Furthermore, *VLf*, *VL*1, and *VL*3 are the voltages of inductors *Lf*, *L*1, and *L*3, respectively. According to the operation modes in Figure 2, when *D*1 is at a high level, *Lf* is magnetized by *Vin*, so *VLf* = *Vin*. When *D*1 is at a low level, according to the loop analysis, *VLf* = *Vin* − *Vs*1. As for *VL*1 and *VL*3, the same analysis method is applied and the value is shown in Figure 3. Similarly, *iLf*, *iL*1, and *iL*3 represent the inductors' currents and they are changed following their voltage.

**Figure 3.** Key waveforms in one switching period.

## *3.3. Control Diagram*

Figure 4 shows the control diagram of the proposed inverter. The result of Equation (20) is a constant, it is then compared with the carrier signal to produce the switch S1 pulse, which is used to boost the input voltage. However, the result of Equation (21) is a sinusoidal variable. The driven signal of switch S2 is generated by comparing the resulting varying duty cycle with the carrier signal, which generates a sinusoidal output. According to the operation modes, only two switches are turned on at the same time. Therefore, the pulse of switch S3 can be determined by the driven signal of switches S1 and S2. The pulse of switch S3 is obtained by the XOR gate. Through the XOR gate, it is guaranteed that only two switches are turned on at a time.

**Figure 4.** Control block diagram of the proposed inverter.

#### **4. Simulation and Experimental Results**

The simulation and experimental results of the proposed inverter are displayed in this section.

#### *4.1. Simulation Results*

The proposed inverter, under resistive load, was simulated in MATLAB/Simulink, assuming the current ripple of all inductors was calculated by Δ*iL* = 20%*IL*. Similarly, Δ *VC* = 7% *VC* was used to calculate the voltage ripple of all capacitors. Therefore, based on Equations (7)–(15), the value of inductors and capacitors could be calculated as shown in Table 1. Considering the laboratory conditions, in order to experiment conveniently, the switches were IGBT and the switching frequency, *fs*, was 20 kHz. The output of the simulation was 124 V, 50 Hz under the condition of 100 V input voltage.

**Table 1.** Parameters selected for the inverter simulation.


Figure 5 shows the key waveforms of the proposed inverter in MATLAB/Simulink. Figure 6 shows the output voltage, output current, and Fast Fourier transform (FFT) analysis of the proposed inverter. The voltage of the capacitors is shown in Figure 7. Additionally, to better test the proposed inverter the output results of the proposed inverter are displayed in Figure 8, under the condition that the load changed suddenly.

Based on the above results, the simulation results verified the theoretical analysis. According to Figure 5, the key waveforms were consistent with the theoretical waveforms shown in Figure 3 and, at the same time, the values of the voltage satisfied the theoretical calculation. The output voltage satisfied the voltage gain and the voltage of the switches was about 300 V, which is consistent with Equation (16). Similarly, Figure 7 demonstrates Equation (7). Furthermore, the THD = 1.48%, which is well below 5%. According to Figure 8 it still worked normally, although there will be fluctuations and harmonics in the process of change. In summary, the proposed inverter can operate with satisfying performance under complex conditions.

**Figure 5.** *Cont.*

**Figure 5.** *Cont.*

**Figure 6.** *Cont.*

**Figure 6.** Input voltage at 100 V and load at 30 Ω for SEPIC-based ZSI: (**a**) load voltage, (**b**) load current, (**c**) Fast Fourier transform (FFT) analysis, (**d**) output voltage with inductive load, and (**e**) output current with inductive load.

**Figure 7.** Input voltage at 100 V and load at 30 Ω for SEPIC-based ZSI. Voltage wave of (**a**) capacitor *C*1, (**b**) capacitor *C*2, (**c**) capacitor *C*3, and (**d**) capacitor *C*0.

**Figure 8.** Input voltage at 100 V and load changed (30–10–30 Ω) for SEPIC-based ZSI: (**a**) load voltage and (**b**) load current.

## *4.2. Experimental Results*

The corresponding experiments were also done. The IGBT, named K40T1202 IGBT, was used for each switch in the experiment. The experimental key waveforms are shown in Figure 9. Figure 10 shows the experimental results of output voltage and output current, which correspond with Figure 6. Similarly, Figure 11 shows the experimental results of the voltage of capacitors. The experimental output waveforms of half load changed to full load and full load changed to half load are shown in Figure 12. Furthermore, in order to verify that the proposed inverter can suppress the leakage current well, a capacitor with the value of 0.15 μF was used for *C*PV. Figure 13 shows the experimental waveform of the leakage current.

**Figure 9.** *Cont.*

**Figure 9.** Experimental waveforms: (**a**) driven signal of the switches; (**b**) the voltage of switch S1 (CH1: Time (10 μs/div), *V*s1 (50 V/div)); (**c**) the voltage of switch S2 (CH2: Time (10 μs/div), *V*s2 (50 V/div)); (**d**) the voltage of switch S3 (CH3: Time (10 μs/div), *V*s3 (50 V/div)); (**e**) the voltage and current of inductor *Lf* (CH1: Time (10 μs/div), *VLf* (50 V/div), CH2: Time (10 μs/div), *iLf* (5 A/div)); (**f**) the voltage and current of inductor *L*1 (CH1: Time (10 μs/div), *VL*1 (50 V/div)), CH2: Time (10 μs/div), *iL*1 (5 A/div)); and (**g**) the voltage and current of inductor *L*3 (CH1: Time (10 μs/div), *VL*3 (50 V/div), CH2: Time (10 μs/div), *iL*3 (5 A/div)).

The experimental waveforms in Figure 9 prove the theoretical key waveforms in Figure 3 and the simulation waveforms in Figure 5. Since the switches in the simulation were ideal and the experimental switches were not ideal, there are voltage spikes in Figure 9. The output voltage and current satisfied the analysis and simulation results. Furthermore, it can be seen from Figure 12 that the proposed inverter still worked well when the load changed suddenly. According to Table II in [24], compared to the traditional single-phase H4 inverter with UPWM and BPWM, the HERIC and H5 topology has lower leakage current. According to the experimental results of the HERIC topology, the max value of leakage current was more than 100 mA under the output power of 160 W. However, the leakage current of the proposed inverter was only about 48 mA under the output power of 500 W which had a good performance for eliminating leakage current and benefited from the dual-grounding.

**Figure 10.** Input voltage at 100 V and load at 30 Ω. Experimental waveforms of *vo* (CH1: Time (5 ms/div), *vo* (50 V/div)) and *Io* (CH2: Time (5 ms/div), *Io* (5 A/div)).

**Figure 11.** Input voltage at 100 V and load at 30 Ω. Experimental waveforms of (**a**) *Vc*1 (CH1: Time (5 ms/div), *Vc*1 (50 V/div)) and *Vc*2 (CH2: Time (5 ms/div), *Vc*2 (50 V/div)); (**b**) *Vc*3 (CH3: Time (5 ms/div), *Vc*3 (50 V/div)) and *Vc*0 (CH4: Time (5 ms/div), *Vc*0 (50 V/div)).

**Figure 12.** Input voltage at 100 V and sudden load changes: (**a**) from 60 to 30 Ω, (**b**) from 30 to 60 Ω. Experimental waveforms of *vo* (CH1: Time (5 ms/div), *vo* (50 V/div)) and *Io* (CH2: Time (5 ms/div), *Io* (5 A/div)).

**Figure 13.** The waveform of leakage current (CH2: *I* (50 mA/div)).

Table 2 shows the efficiency of the proposed inverter. However, the efficiency of this topology was relatively low due to the use of IGBT as the switches, which are not appropriate for low–medium power converters, and the limitation of the laboratory conditions. A good device can be used to enhance the efficiency of the proposed topology.

**Table 2.** The measured efficiency of the proposed inverter.


In conclusion, from the above experimental results, it can be observed that the experimental results were in good agreemen<sup>t</sup> with the theoretical analysis and the simulation results, again verifying the effectiveness of the proposed inverter.
