**1. Introduction**

Quasi-Z-source (QZS) inverters have been widely used for grid-tied applications, due to their advantages over the traditional voltage-source inverters (VSIs) using a DC-DC converter [1–7]. Figure 1 shows the circuit diagram of the QZS inverter for single-phase grid-tied applications [2–4]. It has a QZS circuit (*L*1, *L*2, *C*1, *C*2, *D*1) and a full-bridge inverter (*S*1, *S*2, *S*3, *S*4, *L*3, *L*4). As it is connected to the grid *vg* without an isolation transformer, a leakage current *ip* flows through the parasitic capacitance *Cp* between the inverter and the grid [5]. This leakage current originated from the common-mode voltage *vp*, which changes rapidly as the inverter operates with high switching frequency [6]. Due to shoot-through states, the common-mode voltage in the QZS inverter can be higher than that in the conventional VSIs [7]. This leads to a higher leakage current, which decreases the power efficiency of the inverter.

A simple way to reduce the leakage current is to use bipolar pulse-width modulation (PWM) [8]. Power switches are diagonally operated when bipolar PWM is adopted. The common-mode voltage requires only a grid frequency component, yielding a low leakage current. However, as the voltage *vAB* has two levels *VPN* and <sup>−</sup>*VPN*, the output filter inductors *L*3 and *L*4 should have high current ripples and high core losses. Despite its low leakage current characteristic, a QZS inverter with bipolar PWM is not suitable for grid-tied applications because of its reduced power efficiency.

Another method is to use a decoupling circuit to disconnect the inverter from the grid [9–15]. The decoupling circuit technique has been described for single-phase transformerless inverter applications in [9]. Many advanced transformerless inverters have been developed for voltage source inverters, such as the H5 inverter [10], the highly efficient and reliable inverter concept (HERIC) inverter [11], and the H6 inverter [12]. Many efforts have also been made to develop transformerless inverters by applying decoupling circuits to the current source inverters [16,17].

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To date, however, only a few studies [13–15] have been reported that apply decoupling circuits to ZS inverters. In [13], a symmetric ZS HERIC inverter was proposed. It uses an additional two power switches for maintaining the common-mode voltage constant. In [14,15], a QZS HERIC inverter was suggested. It uses an additional two power switches and two power diodes for clamping the common-mode voltage. The inverters in [13–15] commonly have three distinct switching states, namely powering, freewheeling, and shoot-through states. During powering states, the inverter delivers the DC power into the grid. During shoot-through states, the inverter is decoupled from the grid by turning on all power switches simultaneously in full-bridge inverter legs. After every powering state and shoot-through state, freewheeling states are necessary. During freewheeling states, the grid current circulates through extra power switches, which operate with the grid frequency. However, the previous inverters [13–15] have drawbacks such as (1) they still use the bipolar PWM for power switches in full-bridge inverter legs; and (2) they always need freewheeling states for every powering state and shoot-through state. These drawbacks increase the number of switching times for the power switches, causing high switching power losses.

**Figure 1.** Circuit diagram of the QZS inverter for single-phase grid-tied applications.

To address the above-mentioned drawbacks, this paper proposes a transformerless QZS inverter, which can effectively reduce the leakage current for single-phase grid-tied applications. Figure 2 shows the circuit diagram of the proposed inverter. The idea behind the proposed inverter was to relate two high-frequency switching legs (*S*1, *S*2 and *S*3, *S*4) with the grid using a bidirectional switch (*S*5, *S*6) and two inductors (*L*3, *L*4). The bidirectional switch operates with the grid frequency, providing a current path for clamping the common-mode voltage *vp* to the neutral and the grid voltage *vg*, for positive and negative grid cycles, respectively. The leakage current *ip* can be reduced due to the absence of high-frequency components for *vp*. Shoot-through states are implemented by turning on two power switches simultaneously in only one switching leg. This leads to low switching power losses compared to the previous inverters in [13–15]. A control scheme is suggested for regulating the DC-link voltage *VPN* and the grid current *ig*. Since the peak DC-link voltage is controlled by a voltage controller, the grid current control can be directly implemented to regulate *ig*. In this paper, Section 2 describes the operation principle and the control strategy of the proposed inverter. Section 3 presents the experimental results for a 1.0 kW prototype inverter. Silicon carbide (SiC) power devices were applied to the proposed inverter to increase the power efficiency. Section 4 ends the paper by presenting the conclusion.

**Figure 2.** Circuit diagram of the proposed inverter.

#### **2. Proposed Inverter**

## *2.1. Operation Principle*

Figure 2 shows a circuit diagram of the proposed inverter. It has a QZS circuit (*L*1, *L*2, *C*1, *C*2, *D*1), a full-bridge inverter (*S*1, *S*2, *S*3, *S*4, *L*3, *L*4), and a bidirectional switch (*S*5, *S*6). *Cp* is modeled as the parasitic capacitance between the inverter and the grid voltage *vg*. *Vin* is the DC voltage. *VPN* is the DC-link voltage. *VC*1 and *VC*2 are the capacitor voltages for *C*1 and *C*2, respectively. *iL*1 and *iL*2 are the inductor currents for *L*1 and *L*2, respectively. *iL*3 and *iL*4 are the inductor currents for *L*3 and *L*4, respectively. *iL*1 ~ *iL*4 are assumed to be continuous. *C*1 and *C*2 are assumed to have large capacitance so that their ripple components are negligible.

The proposed inverter has three switching states, namely the powering, freewheeling, and shoot-through states. For a positive grid cycle, *S*6 is always turned on. *S*1 and *S*2 operate complementarily during the non-shoot-through states. Figure 3 shows the switching circuit diagrams of the proposed inverter for a positive grid cycle. During the powering state in Figure 3a, *S*1 is turned on. The DC voltage source supplies electric power to the grid as *D*1 is turned on. *ig* flows through *vg*, *S*6, *VPN*, *S*1, and *L*3. The following voltage equation is obtained as in:

$$-V\_{PN} + V\_{L3} + \upsilon\_{\mathcal{S}} = 0\tag{1}$$

*iL*1 flows through *L*1, *DSb*, *C*1, and *Vin*. *iL*2 flows through *L*2, *C*2, and *D*1. The following voltage equations are obtained as in:

$$V\_{L1} = V\_{in} - V\_{C1} \tag{2}$$

$$V\_{\rm L2} = -V\_{\rm C2} \tag{3}$$

During the freewheeling state in Figure 3b, *S*2 is turned on. The energy stored in *L*3 is transferred to *vg*. *ig* freewheels through *vg*, *S*6, *S*2, and *L*3. The following voltage equation is obtained as in:

$$V\_{L3} + v\_{\mathcal{S}} = 0\tag{4}$$

As *L*1 and *L*2 are discharged, *C*1 and *C*2 are charged. During the shoot-through state in Figure 3c, *S*1 and *S*2 are turned on simultaneously. As *D*1 is turned off, *L*1 and *L*2 are charged. The following voltage equations are obtained as in:

$$V\_{L1} = V\_{\text{in}} + V\_{\text{C2}} \tag{5}$$

$$V\_{l\mathbb{Z}} = V\_{\mathbb{C}1} \tag{6}$$

*ig* flows through *vg*, *S*6, *S*2, and *L*3, as in the freewheeling state.

**Figure 3.** Switching circuit diagrams of the proposed inverter for a positive grid cycle: (**a**) powering state; (**b**) freewheeling state; (**c**) shoot-through state.

Figure 4 shows the switching circuit diagrams of the proposed inverter for a negative grid cycle. *S*5 is always turned on for a negative grid cycle. *S*3 and *S*4 operate complementarily during the non-shoot-through states. The operation principle for a negative grid cycle is not described here because it can be analogously explained as the operation principle for a positive grid cycle.

As shown in Figure 3, *S*6 provides a closed path for *Cp* to be clamped to the zero voltage for a positive grid cycle. On the other hand, as shown in Figure 4, *S*5 provides a closed path for *Cp* to be clamped to the grid voltage for a negative grid cycle for a negative grid cycle. Then, the common-mode voltage *vp* can be represented as in:

$$v\_{\mathcal{P}} = \begin{cases} 0 & \text{when } v\_{\mathcal{S}} > 0 \\\ v\_{\mathcal{S}} & \text{when } v\_{\mathcal{S}} \le 0. \end{cases} \tag{7}$$

The parasitic capacitance *Cp* can be free from the high-frequency components for both positive and negative grid cycles. This leads to the low leakage current *ip*, regardless of the high-frequency switching operation of the inverter.

**Figure 4.** Switching circuit diagrams of the proposed inverter for a negative grid cycle: (**a**) powering state; (**b**) freewheeling state; (**c**) shoot-through state.

Figure 5 shows the signal diagrams for *S*1 ~ *S*4 when they operate with high switching frequency. *S*1 and *S*3 are the main control switches for positive and negative grid cycles, respectively. *S*1 (*S*3) and *S*2 (*S*4) operate complementarily during the non-shoot-through states, respectively. A simple boost modulation scheme is adopted for generating the shoot-through duty cycles [18]. The shoot-through state is equally distributed into two parts adjacent with the on-time of the main control switch. Shoot-through states are implemented by turning on two power switches simultaneously in only one switching leg, which leads to low switching power losses, compared to the previous inverters in [13–15]. Given that the on-time interval for the main control switch is *TON* for one switching period *TS*, from (1) and (4), the average voltage *VL*3,*avg* for *L*3 over *TS* should be zero, respectively, as in:

$$V\_{L3\,\text{avg}} = \frac{(V\_{PN} - \upsilon\_{\%})\,\,T\_{ON} - \upsilon\_{\%}(T\_S - T\_{ON})}{T\_S} = 0. \tag{8}$$

**Figure 5.** Signal diagrams for *S*1 ~ *S*4 when they operate with high switching frequency.

The ratio between *TON* and *TS* is obtained as in:

$$\frac{T\_{\rm ON}}{T\_S} = \frac{v\_{\rm g}}{V\_{\rm PN}} = \frac{V\_{\rm g}|\sin\omega t|}{V\_{\rm PN}}\tag{9}$$

where *Vg* is the positive peak value of *vg*, and *ω* is the angular frequency of *vg*. Given that the time interval during the shoot-through state is *TST* for *TS*, the average voltages *VL*1,*avg* and *VL*2,*avg* for *L*1 and *L*2 over *TS* should be zero, respectively, as in:

$$V\_{L1, \text{avg}} = \frac{(V\_{in} + V\_{C2}) \ T\_{ST} + (V\_{in} - V\_{C1}) \ (T\_S - T\_{ST})}{T\_S} = 0,\tag{10}$$

$$V\_{L2,avg} = \frac{V\_{C1}T\_{ST} - V\_{C2}(T\_S - T\_{ST})}{T\_S} = 0.\tag{11}$$

From Equations (10) and (11), we have:

$$V\_{\mathbb{C}1} - V\_{\mathbb{C}2} = V\_{\text{in}}.\tag{12}$$

From Equation (11), the shoot-through duty cycle *DST* is represented as in:

$$D\_{ST} = \frac{T\_{ST}}{T\_S} = \frac{V\_{C2}}{V\_{C1} + V\_{C2}}.\tag{13}$$

From Equations (12) and (13), *VC*1 and *VC*2 are represented as in:

$$V\_{\mathbb{C}1} = \frac{1 - D\_{ST}}{1 - 2D\_{ST}} V\_{\text{in}\prime} \tag{14}$$

$$V\_{C2} = \frac{D\_{ST}}{1 - 2D\_{ST}} V\_{\text{in}}.\tag{15}$$

Since *VPN* = *VC*1 + *VC*2, from Equations (14) and (15), we have:

$$\frac{V\_{PN}}{V\_{in}} = \frac{1}{1 - 2D\_{ST}}.\tag{16}$$

## *2.2. Control Strategy*

As the proposed inverter steps down the DC-link voltage *VPN* to the level of *vg*, it regulates the DC-link voltage and controls the grid current *ig*. From Equations (3) and (6), the average voltage for *L*2 over *TS* is obtained with the inductor current deviation Δ*iL*2 as in:

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$$L\_2 \frac{\Delta i\_{L2}}{T\_S} = V\_{C1} D\_{ST} - V\_{C2} (1 - D\_{ST}).\tag{17}$$

Since *VPN* = *VC*1 + *VC*2, *DST* is derived as in:

$$D\_{ST} = \frac{V\_{C2}}{V\_{PN}} + L\_2 \frac{\Delta i\_{L2}}{V\_{PN} T\_S} \,. \tag{18}$$

Suppose that *L*1 = *L*2 = *Li* and *iL*1 = *iL*2 = *ii*, *DST* can be represented as in:

$$D\_{ST} = D\_{ST,N} + D\_{ST,\mathbb{C}} \tag{19}$$

where *DST,N* is the nominal shoot-through duty cycle and *DST,C* is the controlled shoot-through duty cycle as in:

$$D\_{ST,N} = \frac{V\_{C2}}{V\_{PN}^\*} \, ^\prime \tag{20}$$

$$D\_{ST,C} = L\_i \frac{|\Delta i\_l|}{V\_{PN}^\* T\_S}.\tag{21}$$

*V\*PN* is the reference value for the peak DC-link voltage. To make the peak DC-link voltage to track its reference *V\*PN*, the following proportional-integral (PI) voltage control is used as in:

$$D\_{\rm ST,C} = k\_p (V\_{\rm C2}^\* - V\_{\rm C2}) + k\_i \int \left( V\_{\rm C2}^\* - V\_{\rm C2} \right) dt \tag{22}$$

where *kp* and *ki* are the PI control gains, respectively. Here, *V\*C*2 is the reference value for the capacitor voltage *VC*2, which is utilized for the DC-link voltage control as *VPN* is a pulsating voltage [19]. *V\*C*2 is given as in:

$$V\_{C2}^{\*} = \frac{V\_{PN}^{\*} - V\_{in}}{2},\tag{23}$$

which is obtained from the following relations as *VPN* = *VC*1 + *VC*2 and *Vin* = *VC*1 – *VC*2.

For the positive grid cycle, from Equations (1) and (4), the average voltage for *L*3 over *TS* is obtained with the grid current deviation Δ*ig* as in:

$$L\_{\overline{\mathcal{S}}} \frac{\Delta \dot{i}\_{\mathcal{S}}}{T\_{\mathcal{S}}} = \left(V\_{\text{PN}} - v\_{\mathcal{S}}\right) D\_1 - v\_{\mathcal{S}} (1 - D\_1) = 0\tag{24}$$

where *D*1 is the duty cycle of *S*1 without considering *DST*. From Equation (24), *D*1 is represented as in:

$$D\_1 = \frac{v\_{\mathcal{S}}}{V\_{\rm PN}} + L\_3 \frac{\Delta i\_{\mathcal{S}}}{V\_{\rm PN} T\_{\mathcal{S}}}, \text{when } v\_{\mathcal{S}} > 0. \tag{25}$$

Similarly, the duty cycle *D*3 of *S*3 without considering *DST* for a negative grid cycle can be represented as in:

$$D\_3 = -\frac{v\_{\mathcal{S}}}{V\_{PN}} - L\_4 \frac{\Delta i\_{\mathcal{S}}}{V\_{PN}T\_{\mathcal{S}}}, when \ v\_{\mathcal{S}} < 0. \tag{26}$$

Supposed that *L*3 = *L*4 = *Lg*, *D*1 and *D*3 without considering *DST* can be represented as the sinusoidal PWM duty cycle *DSPWM* as in:

$$D\_{SPWM} = D\_{SPWM,N} + D\_{SPWM,\mathbb{C}} \tag{27}$$

where *DSPWM,N* is the nominal sinusoidal PWM duty cycle and *DSPWM,C* is the controlled sinusoidal PWM duty cycle as in:

$$D\_{SPWM,N} = \frac{V\_{\mathcal{K}} |\sin \omega t|}{V\_{PN}^\*},\tag{28}$$

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$$D\_{SPWM,C} = L\_{\%} \frac{\left| \Delta i\_{\%} \right|}{V\_{PN}^{\*} T\_{S}}.\tag{29}$$

To make the grid current to track its reference *i\*g*, the following proportional (P) current control is used as in:

$$D\_{SPWM,\mathcal{C}} = k\_{\mathcal{S}}(i\_{\mathcal{S}}^\* - |i\_{\mathcal{S}}|) \tag{30}$$

where *kg* is the P control gain. *i\*g* is given as in:

$$I\_{\mathcal{K}}^{\*} = I\_{\mathcal{K}}^{\*} |\sin \omega t| \tag{31}$$

where *I\*g* is the peak magnitude of the current reference. Figure 6 shows the control block diagrams of the proposed inverter. Figure 6a shows the control block diagram for the DC-link voltage control. Figure 6b shows the control block diagram for the grid current control. The phase-locked loop (PLL) control is used for the grid synchronization [20]. The duty cycle for the main control switch can be finally obtained by summing *DSPWM* and *DST*.

**Figure 6.** Control block diagrams of the proposed inverter: (**a**) DC-link voltage control; (**b**) grid current control.

#### **3. Experimental Results**

A 1.0 kW prototype inverter was designed for the proposed inverter for *vg* = 60 Hz/220 Vrms. The valve regulated lead-acid batteries were used for the DC voltage *Vin*, the nominal voltage of which was 250 V. The *V\*PN* was set to 500 V for *DST* = 0.25. SiC metal-oxide field-effect transistors (MOSFETs) (C2M0080120D, CREE) were used for *Sb*. A SiC Schottky diode (C4D20120D, CREE) was used for *D*1. A digital signal controller (dsPIC30F6015, Microchip) was used for implementing the DC-link voltage and grid current controllers and for generating the duty cycle signals.

The inverter in Figure 1 and the inverter in [15] were designed using insulated gate bipolar transistors (IGBTs). In the conventional inverter in Figure 1, an IGBT (IKW25T120, Infineon) was used for *S*1 ~ *S*4 with a switching frequency of 10 kHz. A unipolar PWM was adopted for the conventional inverter, due to its better switching performance than a bipolar PWM. In the inverter in [15], IKW25T120 was used for *S*1 ~ *S*4 with a switching frequency of 10 kHz. IKW25T120 and C4D20120D were used for the extra power switches and extra power diodes, respectively. The proposed inverter used IKW25T120 for *S*1 ~ *S*4 with a switching frequency of 10 kHz and for *S*5 and *S*6 with a switching frequency of 60 Hz, respectively. Figure 7 shows a picture of the prototype inverter. The inductance for *L*1 ~ *L*4 was selected as 1.0 mH. *L*3 and *L*4 were implemented as a coupled inductor, which simplified the circuit layout. The capacitance for *C*1 and *C*2 was selected as 560 μF.

**Figure 7.** Picture of the prototype inverter.

Figure 8 shows the experimental waveforms of the conventional inverter in Figure 1 and the proposed inverter, respectively. Figure 8a shows *vg* and *vp* in the conventional inverter. Figure 8b shows *vg* and *ip* in the conventional inverter. Figure 8c shows *vg* and *vp* in the proposed inverter. Figure 8d shows *vg* and *ip* in the proposed inverter. The leakage current in the proposed inverter was greatly reduced compared to that in the conventional inverter.

**Figure 8.** Experimental waveforms: (**a**) *vg* and *vp* in the conventional inverter; (**b**) *vg* and *ip* in the conventional inverter; (**c**) *vg* and *vp* in the proposed inverter; (**d**) *vg* and *ip* in the proposed inverter.

Figure 9 shows the experimental waveforms of the proposed inverter. Figure 9a shows the *Vin*, *VPN*, *vg*, and *ig*. The proposed inverter steps up *Vin* to *VPN*, and controls *ig* with high power factor. Figure 9b shows the *Vin*, *VC*2, and *VPN*. The peak DC-link voltage was regulated and the grid current was controlled in the proposed inverter. Figure 9c shows the *Vin*, *VC*12, *VC*2, and *iL*1. Since the proposed inverter operates in the grid-tied mode, a twice grid frequency DC ripple current was observed on the DC input side. If active power decoupling schemes [17] are adopted, the ripple components as well as the reactive component sizes can be reduced.

**Figure 9.** Experimental waveforms of the proposed inverter: (**a**) *Vin*, *VPN*, *vg*, and *ig*; (**b**) *Vin*, *VC*2, and *VPN*; (**c**) *Vin*, *VC*1, *VC*2, and *iL*1.

Figure 10 shows the power efficiency curves of the inverters. Figure 10a shows the power efficiency curves when the IGBTs have been adopted for the power switches. The inverter in Figure 1 achieved an efficiency of 91.7% at the rated power. The inverter in [15] achieved an efficiency of 92.1% at the rated power. The proposed inverter achieved an efficiency of 92.6% at the rated power, obtaining the highest efficiency of 92.9% at 0.6 kW. The proposed inverter obtained higher power efficiency than the previous inverters. The proposed inverter not only improved the power efficiency by reducing the leakage current, but also alleviated switching power losses by reducing the number of switching times for power switches. Figure 10b shows the power efficiency curves when the SiC MOSFETs were adopted for the power switches. It is observed that the power efficiency was improved when the SiC MOSFETS were used for the power switches. The inverter in Figure 1 achieved an efficiency of 93.6% at the rated power. The inverter in [15] achieved an efficiency of 94.0% at the rated power. The proposed inverter achieved an efficiency of 94.7% at the rated power, obtaining the highest efficiency of 95.1% at 0.6 kW. Regardless of the types of power switches, the proposed inverter achieved higher power efficiency than previous inverters.

**Figure 10.** Power efficiency curves: (**a**) when IGBTs were adopted; (**b**) when SiC MOSFETs were adopted.
