*5.1. Specifications*

The presented converters are compared based on the specifications listed as follows. The input voltage is varied from 100 to 300 V. The rated output voltage is 50 V, and the output current is 20 A. The switching frequency is 20 kHz. 1000 V/60 A IGBTs are used as the primary switches, and the output capacitance of IGBTs is estimated as 1nF. The equivalent leakage inductances of the transformer in each converter are set to be 10 μH. The ideal value of *k*T1 in IZVS\_SMM is 48 regardless of the effect of the leakage inductances, while *k*T2 = 16. The ideal value of kT in other converters is 12. The peak value of the magnetic currents of IZVS\_CD and IZVS\_SMM are set as 0.6 times of the primary rate current, and the magnetic currents of other converters can be omitted.

#### *5.2. Duty Ratio Loss*

The duty ratio loss caused by the leakage inductances is a disadvantage of PS-controlled dc-dc converters. Large duty ratio loss requires the transformer turn ratio to comprise, which degrades the performance of the converter. Table 1 shows the duty ratio loss comparison. As an additional inductor is series-connected with each primary coil, the duty ratio loss of IZVS\_CD is highest among all the converters. The primary currents of IZVS\_SMM are TL waveforms, thus, the duty ratio loss of IZVS\_SMM is smallest among all IZVS converters. The primary currents in ZVZCS converters are reset to zero during freewheeling stages, and the duty ratio loss caused by leakage inductances of ZVZCS converters is smaller than that of IZVS converters. However, as a specific time for primary current resetting is required, thus, the duty ratio loss of IZVZCS\_DCF, IZVZCS\_SRC&CAC and IZVZCS\_SI is a little higher. As proved in Figure 6, the primary reset time of IZVZCS\_SAC&CAC can be compensated by the duty ratio boost effect, thus, the duty ratio loss of this converter is smallest. Figure 8 shows the duty ratio loss at rated load current. As shown in Figure 8, when *I*o = 20A, the duty ratio loss of IZVS\_CD is about 0.089. Considering the duty ratio loss, the turn ratios of the proposed converters should be revised, and detailed information is listed in Table 2.



**Figure 8.** Duty ratio loss at rated output current.

**Table 2.** Turn ratios after considering the duty ratio loss.


#### *5.3. Soft Switching Load Range*

The soft switching load range is defined as

$$\eta\_{\rm L.R} = \frac{I\_{\rm o\\_rate} - I\_{\rm o\\_min}}{I\_{\rm o\\_rate}} \tag{27}$$

where *I*o\_rate represents the rated output current, and its value is 20A in this paper;*I*o\_min is the minimum load current to ensure ZVS of the switches.

(1) Leading switches:

As the energy stored in the output inductance can be used, all leading switches can obtain ZVS in wide load range. As proved in [31], the minimum load of the leading switches in IZVS\_CD is

$$I\_{\rm o\\_min} = k\_{\rm T} V\_{\rm in} \sqrt{\frac{\mathcal{C}\_{\rm os}}{L\_{\rm r} + L\_{\rm 1k} + k\_{\rm T}^2 L\_{\rm o}}} \tag{28}$$

As proved in [32] and [35–37], the minimum load of the leading switches in IZVS\_CAC and Figure 3 is

$$I\_{\rm o\\_min} = k\_{\rm T} V\_{\rm in} \sqrt{\frac{\mathcal{C}\_{\rm co}}{L\_{\rm 1k} + k\_{\rm T}^2 L\_{\rm o}}} \tag{29}$$

As the magnetizing current of the leading switches is increased in IZVS\_SMI and IZVS\_SMM, the leading switches in IZVS\_SMI and IZVS\_SMM can obtain ZVS down to 0 load current. Thus, the ηLR of the leading switches is concluded in Table 3.


**Table 3.** ηLR (leading-switches, 300 V).

(2) Lagging switches:

A resonate inductance is added to enlarge the ZVS load range of the lagging switches in IZVS\_CD, and, as shown in [31], the minimum load of the lagging switches in IZVS\_CD is

$$I\_{\rm o\\_min} = k\_{\rm T} V\_{\rm in} \sqrt{\frac{C\_{\rm os}}{L\_{\rm r} + L\_{\rm 1k}}} \tag{30}$$

With proper design, the lagging switches of IZVS\_CAC, IZVS\_SMI and IZVS\_SMM can obtain ZVS down to zero loads. The lagging switches in Figure 3 are operated in ZCS mode, and the ZCS operation can be ensured under *<sup>D</sup>*p\_max at rated load current. Thus, the ηLR of the lagging switches is listed in Table 4.

**Table 4.** ηLR (lagging-switches, 300 V).


*5.4. Relative Current Rating of the Primary Components*

The rate primary current is defined as

$$I\_{\rm P\\_rate} = I\_{\rm o\\_rate}/k\_{\rm T\\_ideal} = 20/12 = 1.667 \text{(A)}\tag{31}$$

where *<sup>I</sup>*p\_rate is the primary rate current; *k*T\_ideal is 12.

The primary relative average absolute current rating is

$$
\pi\_{\text{C\\_AV}} = \frac{I\_{\text{p\\_AV}}}{I\_{\text{p\\_rate}}} \tag{32}
$$

where *<sup>I</sup>*p\_AV is the primary average absolute current.

The primary relative RMS current rating is

$$
\tau\_{\text{C\\_RMS}} = \frac{I\_{\text{P\\_RMS}}}{I\_{\text{P\\_rate}}} \tag{33}
$$

where *<sup>I</sup>*p\_RMS is the primary RMS current.

Table 5 illustrates <sup>τ</sup>C\_AV and <sup>τ</sup>C\_RMS of the primary components. The magnetizing currents of IZVS\_SMI are increased to help ZVS of the lagging switches, and these currents keep their peak value during the whole free-wheeling time. Thus,<sup>τ</sup>C\_AV and <sup>τ</sup>C\_RMS of IZVS\_SMI is highest, which results highest primary side conduction loss. The magnetizing currents of IZVS\_SMM are also enlarged, but, the average value in the half switching cycle of these currents is zero, and these currents are not in phase with the load current. Hence, <sup>τ</sup>C\_AV and <sup>τ</sup>C\_RMS of IZVS\_SMM are much smaller than that of IZVS\_SMI. The IZVZCS\_SAC&CAC has the smallest <sup>τ</sup>C\_AV and <sup>τ</sup>C\_RMS.


**Table 5.** <sup>τ</sup>C\_AV and <sup>τ</sup>C\_RMS of the primary components.

#### *5.5. Power Loss Distribution*

The losses of soft-switching FB converters mainly include switching losses, transformer losses, output rectifier diode losses, resonance inductance losses, and other losses. The switching loss model mainly covers light-load and heavy-load senarios. The losses of a MOSFET can be calculated by (34), where *P*Driver is the driving loss, *P*SW is the switching loss of the MOSFET, *P*MOS\_Lead is the conduction loss of the leading MOSFET, *<sup>P</sup>*MOS\_Lag is the conduction loss of the lagging MOSFET.

$$\begin{cases} \begin{aligned} P\_{\text{MOSFET}} &= P\_{\text{Drive}} + P\_{\text{SW}}\\ P\_{\text{MOSFET}} &= P\_{\text{MOS\\_Lcad}} + P\_{\text{MOS\\_Lag}} \end{aligned} \tag{34}$$

Transformer loss mainly includes copper loss(*P*Winding) and iron loss, which includes eddy-current loss(*P*e) and hysteresis loss(*P*h). Then, the total transformer loss, defined as *P*T, is

$$P\_T = P\_{\text{Winding}} + P\_{\text{h}} + P\_{\text{e}} \tag{35}$$

The output rectifier diode loss includes three parts: turn-off loss(*P*D\_off), turn-on loss(*P*D\_on), and on-state loss(*P*Con). The total loss of a diode, defined as *P*D\_loss, is

$$P\_{\rm D\\_loss} = P\_{\rm D\\_off} + P\_{\rm D\\_on} + P\_{\rm C\infty} \tag{36}$$

Inductor losses mainly include copper loss,*P*Cu\_lo and iron loss *P*Fe\_lo. Then the total inductor loss of Lo and Lr are

$$P\_{\rm Lo\\_loss} = P\_{\rm Fe\\_lo} + P\_{\rm Cu\\_lo} \tag{37}$$

$$P\_{\rm Lr\\_loss} = P\_{\rm Fe\\_lr} + P\_{\rm Cu\\_lr} \tag{38}$$

Relative switching loss is

$$\delta\_{\rm S\\_loss} = \frac{\sum\_{\rm n} P\_{\rm S\\_Loss}}{P\_{\rm o}} \tag{39}$$

where *P*o is the output power and δS\_loss is the corresponding switching loss.

Relative conduction loss is

$$
\delta\_{\rm C\\_loss} = \frac{\sum\_{\rm n} P\_{\rm C\\_Loss}}{P\_{\rm o}} \tag{40}
$$

where *P*o is the output power and *P*C\_Loss is corresponding conduction loss.

The power loss distribution of the proposed converters is estimated in Table 6. The magnetizing currents of IZVS\_SMM are enlarged to help the ZVS of the primary switches and the peak value of these currents can provide more resonant energy with increasing of the input voltage, thus, the switching loss of the primary switches of IZVS\_SMM is smallest among all IZVS converters. When *V*in= 300V, the phase angle between the primary switches and secondary switches is zero, and the primary currents of IZVS\_SMM are much smaller than that of other IZVS converters. Therefore, the primary conduction loss of IZVS\_SMM is also smallest among all IZVS converters. As depicted in Table 6, some secondary conduction loss and switching loss is added to the converter in IZVS\_SMM because two secondary switches are required. However, the efficiency of IZVS\_SMM is still highest among all IZVS MMDCs. As shown in Table 6, the IZVZCS\_SAC&CAC has the smallest conduction loss among all ZVZCS MMDCs due to smaller duty ratio loss. In addition, the turn-off loss of the leading switches of IZVZCS\_SAC&CAC is also smaller, which results in smaller switching loss of the primary switches. Hence, the efficiency of IZVZCS\_SAC&CAC is highest among all ZVZCS converter.


**Table 6.** δS\_loss and δC\_loss (*V*in= 300V).

#### *5.6. Structure and Cost Comparison*

Table 7 shows a comparison of added components of the proposed converters. The IZVS\_SMI, IZVS\_SMM, IZVZCS\_SAC&CAC and IZVZCS\_SRC&CAC have no added primary components, which means the primary circuits of these converters are simpler and more compact compared to that of other converters. A smaller number of primary components means not only cheaper BOM cost but also simpler and more compact primary structure. In addition, less area in the primary side of these converters is required to ensure safe electrical clearance due to the smaller number of primary components and simpler connection between these components. Therefore, the primary circuit volume of the IZVS\_SMI, IZVS\_SMM, IZVZCS\_SAC&CAC and IZVZCS\_SI is smaller and more compact, which are attractive features for high input voltage industry applications. As depicted in Table 7, the IZVS\_CD, IZVS\_CAC, IZVS\_SMI, IZVZCS\_DCF and IZVZCS\_SI require no added secondary components. In some industrial applications, the input voltage may be 1400 V or higher. Due to the modular structure, the proposed converters can be extended to higher voltage levels easily. As shown in Table 7, the added primary components of the extension topologies of the IZVS\_CD, IZVS\_CAC, IZVZCS\_DCF and IZVZCS\_SI increase linearly with the number of the primary modules. However, as depicted in Table 7, the added secondary components of the extension topologies of the IZVS\_SMI, IZVS\_SMM and IZVZCS\_SRC&CAC are not increased with primary cells. Thus, the IZVS\_SMI, IZVS\_SMM, IZVZCS\_SAC&CAC and IZVZCS\_SI are more suitable for super-high-voltage applications due to smaller added components and a simpler primary structure. The added cost of the proposed converters is listed in Table 8.

From above analyses, some brief conclusions can be drawn as follows. The IZVS\_SMM and IZVZCS\_SRC&CAC show some clear advantages compared to other solutions, e.g., smaller duty ratio loss, wide range soft switching operation, less conduction loss, simpler and more compact primary circuit, and lower added cost. Thus, these two converters are more suitable for high input voltage applications with more primary modules. The current stress of Sse and Cse in IZVZCS\_SRC&CAC increases with the output current, which may arise several implementation problems. Hence, the IZVS\_SMM is a better choice for large output current applications. The IZVS\_SMM has some special characteristics. The secondary rectified voltage is a TL waveform, which results lower input and output filter requirements. The IZVS\_SMM is the only topology, which can be used in the high input applications with controllable multi-output ports.


**Table 7.** Added component comparison. (N is series-connected primary modules number).

**Table 8.** Added cost comparison. (Two series-connected primary modules).


#### **6. Experimental Results**

The IZVS\_SMM and IZVZCS\_SAC&CAC are selected as examples to test in this section, and the conventional FB MMDC in Figure 1 is also tested in the efficiency comparison. The main parameters of the prototype are listed in Table 9. The waveforms of IZVS\_SMM and IZVZCS\_SAC&CAC are provided in Figure 9.


**Table 9.** Main parameters of the prototypes.

**Figure 9.** Experimental waveforms: (**a**) *v*CE(S1) and *v*CE(S5) of IZVS\_SMM; (**b**) *v*cin1, *v*in2 and *i*o of IZVS\_SMM; (**c**) *v*BC and *i*Llk1 of IZVS\_SMM; (**d**) *i*Lo and *v*rect of IZVS\_SMM; (**e**) *i*Llk2 of IZVS\_SMM; (**f**) *v*BC and *i*Llk1 of IZVS\_SMM (soft start); (**g**) *v*GE(S1) and *v*CE(S1) of IZVS\_SMM (turn-on); (**h**) *v*GE(S1) and *v*CE(S1) of IZVS\_SMM (turn-off); (**i**) *v*DS(Sse1) and *i*DS(Sse1) of IZVS\_SMM; (**j**) *v*BC, *i*Llk1and *i*Lo of IZVZCS\_SAC&CAC; (**k**) *v*BC and *i*se of IZVZCS\_SAC&CAC; (**l**) *v*GE(Sse) and *i*Llk1 of IZVZCS\_SAC&CAC; (**m**) *v*GE(S1) and *v*CE(S1) of IZVZCS\_SAC&CAC; (**n**) *v*CE(S1) and *v*CE(S5) of IZVZCS\_SAC&CAC.

A conventional circuit of a phase-shifted full-bridge includes IZVS and ZVZCS operation modes. IZVS implement ZVS on both the leading switches and the lagging switches. Due to the existence of the transformer leakage inductance and the output inductance, the current does not change suddenly when the leading switches are turned <sup>o</sup>ff, and only ZVS. IZVS mode has good switching characteristics and high on-state loss. For the ZVZCS mode, it achieves ZVS of the leading switches and ZCS on the lagging switches. ZVZCS mode has low on-state loss and current overshoot. Some of the proposed FB-MMDCs discussed in this paper have clear advantages compared with conventional FB MMDC. For example, IZVZCS-SAC&CAC (see Figure 3b) has less voltage stress on the primary switch no additional primary clamping device and modular primary structure. In addition, the primary switch in all converters can achieve ZVS or ZCS over a wide load range.

As shown in Figure 9a, the o ff-state voltage of the primary switches in IZVS\_SMM is even during normal operation stages, and the midpoint voltage of the input capacitors is stable and equals Vin/2. *v*in, *v*Cin2 and Io are depicted in Figure 9b, and the mid-point voltage of the input capacitors is balanced even during the output dynamic instant. As proved in Figure 9c, *i*Llk1 is not a constant value because *i*1m is enlarged to help the ZVS of the primary switches. As *i*1m is not in phase with the load current, the added primary RMS current is smaller. Thus, added conduction loss is also smaller. As depicted in Figure 9 c, *v*BC does not have free-wheeling time. Therefore, the input current ripple is smaller. As proved in Figure 9d, the secondary rectified voltage is a TL waveform, which can significantly reduce the volume of output filter. The *i*Llk2 is provided in Figure 9e, and *v*BC and *i*Llk1 during the soft-start operation are shown in Figure 9f. The voltage waveforms of the gate-emitter and the collector-emitter of S1 are depicted in Figure 9g and 9h. In Figure 9g, the gate-emitter voltage of S1 is much lower than gate-emitter threshold voltage when the collector-emitter voltage of S1 decreases to zero, thus, S1 can obtain ZVS. According to Figure 9i, Sse1 can obtain ZCS.

The waveforms of IZVZCS\_SAC&CAC are depicted in Figure 9j to 9n. As proved in Figure 9j, *i*Llk1 is reset by the secondary clamping capacitor and keeps zero during the whole free-wheeling stage. Thus, the lagging switches can obtain ZCS. In addition, the primary circling energy is zero. *i*se is provided in Figure 9k. The gate signal of Sse and the primary current is depicted in Figure 9l, the secondary switches are turned on at the beginning of the free-wheeling stages to reset the primary currents. In Figure 9m, the gate-emitter voltage of S1 is much lower than the gate-emitter threshold voltage when the collector-emitter voltage of S1 decreases to zero; thus, S1 can obtain ZVS. As shown in Figure 9n, the o ff-state voltage of the primary switches in IZVZCS\_SAC&CAC is even during normal operation stages, and the mid-point voltage of the input capacitors is stable and equals Vin/2.

Figure 10 shows the e fficiency comparison between the converters in the conventional FB MMDC (Figure 1), the IZVS with secondary modulation method (IZVS\_SMM, Figure 2d) and the IZVZCS with secondary active clamping and commutation auxiliary circuit (IZVZCS\_SAC&CAC, Figure 3b). During the e fficiency test, the auxiliary power of the controller and driver are taken into account, and the power of the force air cooling fan is also included. As depicted in Figure 10a, the e fficiency of IZVS\_SMM and IZVZCS\_SAC&CAC is higher than that of Figure 2 because of wide-range soft-switching for all primary switches. As illustrated in Figure 10a, the light-load e fficiency of IZVZCS\_SAC&CAC is a bit lower than that of IZVS\_SMM because the switching loss of the leading switches is a little higher, and the high load e fficiency of IZVZCS\_SAC&CAC is a bit higher than that of IZVS\_SMM due to the smaller turned o ff loss of the lagging switches and lower conduction loss. Figure 10b shows the efficiency curves with larger output capacitance of the primary switches. Turn-o ff loss of the switches decreases with the increasing of the output capacitance, but, turn-on loss may increase due to narrow ZVS load range. As all primary switches in IZVS\_SMM can still obtain ZVS turned-on in wide load range with less added conduction loss, the e fficiency of IZVS\_SMM is higher than others. Hence, the converter in IZVS\_SMM can gain optimum e fficiency performance by more flexible selecting of the trade-o ff among turn-on loss, turn-o ff loss and conduction loss. Figures 10c and 10d show the efficiency comparison with variable input voltage. The e fficiency curves decrease with the increasing of the input voltage. As the magnetizing inductances can provide more resonant energy, the converter in IZVS\_SMM has higher e fficiency under high input voltage condition.

**Figure 10.** Efficiency comparison: (**a**) variable output current (Vin = 300 V, Cos = 1 nF); (**b**) variable output current (Vin = 300 V, Cos = 10 nF);(**c)** variable input voltage (Io = 20 A, Cos = 1 nF); (**d**) variable input voltage (Io = 20 A, Cos = 10 nF).
