**1. Introduction**

With the high penetration of intermittent energy, such as solar and wind [1–3], a power electronic interface for distributed energy storage is becoming increasingly attractive. The bidirectional DC/DC converter (BDC) is an important piece of equipment for distributed energy storage in DC microgrids, which helps to promote intermittent energy scale applications. The BDCs are widely used in DC microgrids, due to their simple structure, easy expansion, and transmission power being independent of transformers [4–7].

In particular, it plays a large irreplaceable role in the distributed energy storage of high voltage and high power. For BDCs, current research focuses on buck/boost two-level converters and control strategies for suppressing load disturbances [8,9]; however, switches are subject to low-voltages applications. The voltage and current stresses of the converter are relatively high, so a multilevel converter is required. A multiplexed multiphase and multilevel BDC is used for a wide range of voltage variations (voltage conversion level less than 10 times); different from multilevel converters

required for a high-voltage DC transmission (voltage conversion level more than 10 times), relying on transformer boosting to achieve a higher level of voltage conversion [10–12]. The n-level structure of the multiplexed multilevel BDC reduce voltage stress only 1/n of the high-side voltage; the m-phase of the multiplexed multiphase BDC reduce current stress only 1/m of the low-side current [13]. The multiphase and multilevel BDC adopts the interleaved phase modulation technology to improve the output current ripple frequency, reduce the filter capacitor ripple value in a DC microgrid [14–17].

When a battery is connected to a DC microgrid by a BDC, the BDC needs to have strong input and output impedance matching capability to keep the system stable. In particular, when the BDC operates in buck mode, the input impedance is large; when operating in boost mode, the input impedance is small; when operating in bidirectional mode, the impedance adjustment range is wider, and the response speed is faster, which is beneficial to the system stability [18].

H. L. Do. [19] proposed a soft-switching DC/DC converter with high voltage gain by a boost cell and a coupled inductor cell. Soft-switching characteristic reduces the switching loss of active power switches and increase the converter e fficiency. However, the converter can only work in boost mode, and only S2 and D4 can achieve ZVS turn-on. The S1-D4 current stress is uneven, and S1 has a higher current stress. In high-voltage and high-power distributed energy storage, it is necessary to consider the equalization and current sharing problems. X. S. Zhang et al. [20] proposed the idea of battery energy storage systems (BESSs) with integrated wind farms to stabilize the grid power. High-power BDCs are required to meet high power requirements.

R. Naderi et al. [21] proposed a dual flying capacitor active-neutral-point-clamped (DFC-ANPC) DC/AC inverter with a five-level modulation method that achieves soft switching and neutral point voltage balancing. More importantly, the five-level modulation method eliminates the transient voltage balancing issue by series-connected switches of S5 and S6 and decreases the switching loss. F. Mohammadi [22] discussed the configuration, operation and decoupled control mode of a VSC-HVDC. Compared to the pulse width modulation (PWM) strategies, the vector control method generates fewer voltage harmonics and allows to control the active and reactive power independently. The vector control method is used to control the VSC-HVDC system, which is based on transforming a 3- ϕ system into a 2- ϕ system by d-q frame. Droop control is easily a ffected by the line impedance and the frequency fluctuation of the power grid, which reduces the distribution accuracy of the active and reactive power. In the future, the bidirectional DC/DC converter (BDC) will be connected to a bipolar DC microgrid by droop control.

Reference [23] used a DC bus capacitor to provide a three-level state (buck/boost synchronous PWM modulation). However, the converter operates at high gain, and S1 is subjected to high current stress, which exacerbates the switching losses. In Reference [24], a two-level buck/boost converter is cascaded to form a three-level bidirectional DC/DC converter. However, the modulation method easily causes inconsistent duty ratios of the upper and lower half bridges to be inconsistent, thereby a ffecting the voltage equalization e ffect of the DC bus, and requires an additional voltage equalization control loop at boost mode, which increases the complexity of the control structure.

This paper proposes a multiplexed modulation technique of the flying capacitor DC/DC converter to meet the high-voltage and high-power requirements. The BDC has many advantages: (1) the bus capacitor voltage is easily stabilized by the midpoint potential balance control of the rear inverter circuit; (2) the BDC is easy to combine by the PWM sequence to achieve multiple modulations; (3) it is easy to design the control loop and suppress phase-to-phase circulation; and (4) the BDC has a strong fault tolerance ability, and failure of any one of the arms does not a ffect the operation of other arms. The BDC is suitable for battery energy storage systems in bipolar DC microgrids.

This paper organized as follows. The Flying capacitor type three-level DC/DC basic unit in Section 2. Multiple modulation techniques are presented in Section 3. Controller design in Section 4. Experimental verifications in Section 5. Some conclusions are given in Section 6.

#### **2. Flying Capacitor Type Three-level DC-DC Basic Unit**

This paper proposes a bidirectional DC/DC converter (BDC) topology with multiplexed modulation strategy for a high-power system, as shown in Figure 1. The parallel operation improves the current capability of the BDC; the voltage level is increased in series operation; and the high-voltage and large-capacity characteristics are realized in series-parallel operation. The symbols and reference directions are indicated in the figure. The basic unit of the flying-capacitor-type three-level bidirectional DC/DC converter (3L\_BDC) easily forms a bipolar BDC of high-voltage and high-current systems.

**Figure 1.** The proposed bidirectional DC/DC converter. (**a**) Flying capacitor type three-level DC-DC basic unit. (**b**) Two basic units parallel. (**c**) Two basic units parallel. (**d**) Four basic units mixed.

In Figure 1a, *U*L is the input-side voltage, *U*H is the DC bus side voltage, *C*L is the battery-side capacitance, and *C*H is the DC bus side capacitance. The conduction time of S3 and S4 is defined as *T*on in the switching period *T*s, and the duty ratio is *D* = *T*on/*T*s. To facilitate the analysis, define the switch function as follows:

$$M\_k = \begin{cases} \begin{array}{llll} 00 \ (\text{S}\_{1\prime} \ \text{S}\_2 \ \text{ON}\_{\prime} \ \text{S}\_3 \ \text{S}\_4 \ \text{OFF}) \\\ 01 \ (\text{S}\_{2\prime} \ \text{S}\_4 \ \text{ON}\_{\prime} \ \text{S}\_{1\prime} \ \text{S}\_3 \ \text{OFF}) \\\ 10 \ (\text{S}\_{1\prime} \ \text{S}\_3 \ \text{ON}\_{\prime} \ \text{S}\_{2\prime} \ \text{S}\_4 \ \text{OFF}) \\\ 11 \ (\text{S}\_{3\prime} \ \text{S}\_4 \ \text{ON}\_{\prime} \ \text{S}\_{1\prime} \ \text{S}\_2 \ \text{OFF}) \end{array} \tag{1}$$

The modal analysis is performed on the basic unit of the flying-capacitor-type three-level bidirectional DC/DC converter. The key waveform is shown in Figure 2. When the operating mode at *D* > 0.5, the switching mode of S3 and S4 is only 01, 10, 11, and not 00. The voltage at the two points of AB is 0.5*U*H or 0; at *D* < 0.5, the switching mode of S3 and S4 is only 00, 01, 10, and not 11. The voltage of AB is *U*H or 0.5*U*H. The inductive current flowing from the low-voltage side to the high-voltage side is defined as the positive direction.

**Figure 2.** The main waveform of the basic unit. (**a**) Mode *D* > 0.5. (**b**) Mode *D* < 0.5.

*2.1. Operational Modal Analysis D* > *0.5*

> During the switching cycle, there are three modes of 11, 01, and 10 for each arm.

1. Mode *M*3 = 11, *S*1 and *S*2 are turned <sup>o</sup>ff, *S*3 and *S*4 are turned on, *S*1 and *S*2 voltage stress are *U*H/2, the voltage of AB two-point is *U*AB = 0, the inductor voltage across *L*1 is *U*L, and *i*L flows to the high-voltage side and linearly increases:

$$\begin{cases} \dot{i}\_{\rm L} = -\frac{r\_{\rm L}}{L} \dot{i}\_{\rm L} + \frac{1}{L} \mathcal{U}\_{\rm L} \\ \dot{\mathcal{U}}\_{\rm H} = -\frac{1}{\mathcal{R}\_{\rm H} \mathcal{C}\_{\rm H}} \mathcal{U}\_{\rm H} \\ \dot{\mathcal{U}}\_{\rm f} = 0 \end{cases} \tag{2}$$

2. Mode *M*1 = 01, *S*1 and *S*3 turn <sup>o</sup>ff, *S*2 and *S*4 turn on, the *S*1 and *S*3 voltage stresses are *U*H/2, the flying capacitor *C*f1 charge according to the differential equation *C*f1 d*U*f1/d*t* = *I*c, that is Δ*U*f1<sup>=</sup>*t*2*I*c/*C*f1 = *Q*c/*C*f1, *U*AB = *U*f1 = *U*H/2, the inductor *L*1 is *U*L - *U*AB < 0, the inductor current *i*L decreases linearly, and the average inductor current is *I*L = *I*c.

$$\begin{cases} \dot{\mathbf{i}}\_{\mathcal{L}} = -\frac{\eta\_{\mathcal{L}}}{\mathcal{L}} \dot{\mathbf{i}}\_{\mathcal{L}} + \frac{1}{\mathcal{L}} \mathcal{U} \mathbf{I}\_{\mathcal{L}} - \frac{1}{\mathcal{L}} \mathcal{U} \mathbf{f}\_{\mathcal{f}}\\ \dot{\mathcal{U}}\_{\mathcal{H}} = -\frac{1}{\mathcal{R}\_{\mathcal{H}} \mathcal{C}\_{\mathcal{H}}} \mathcal{U}\_{\mathcal{H}}\\ \dot{\mathcal{U}}\_{\mathcal{f}} = \frac{1}{\mathcal{C}\_{\mathcal{f}}} \dot{\mathbf{i}}\_{\mathcal{L}} \end{cases} \tag{3}$$

3. Mode *M*3 = 11, *S*1 and *S*2 are turned <sup>o</sup>ff, *S*3 and *S*4 are turned on, the *S*1 and *S*2 voltage stresses are *U*H/2, the voltage of the two-point of AB is *U*AB<sup>=</sup>0, the voltage of the inductance *L*1 is *U*L, and *i*L flows to high voltage side and linearly increase, as shown in Equation (2).

4. Mode *M*2 = 10, *S*2 and *S*4 are turned <sup>o</sup>ff, *S*1 and *S*3 are turned on, the *S*2 and *S*4 voltage stresses are *U*H/2, flying capacitor *C*f1 is discharged, *U*AB = *U*H − *U*f1 = *U*H/2, the voltage across inductor *L*1 is *U*L − *U*AB < 0, and *i*L flows to the high-pressure side and decreases linearly. The column differential equation can be obtained as:

$$\begin{cases} \dot{i}\_{\rm L} = -\frac{r\_{\rm L}}{L}i\_{\rm L} + \frac{1}{L}\ell I\_{\rm L} + \frac{1}{L}\ell I\_{\rm f} - \frac{1}{L}\ell I\_{\rm f} \\\ \dot{\mathcal{U}}\_{\rm H} = \frac{1}{\mathcal{C}\_{\rm H}}i\_{\rm L} - \frac{1}{\mathcal{R}\_{\rm H}\mathcal{C}\_{\rm H}}\ell I\_{\rm f} \\\ \dot{\mathcal{U}}\_{\rm f} = -\frac{1}{\mathcal{C}\_{\rm f}}i\_{\rm L} \end{cases} \tag{4}$$

According to the duty cycle definition, each equation group for the modal action time can be listed during the switching period:

$$\begin{cases} t\_1 + t\_2 + t\_3 = D \mathbf{T}\_8 \\ t\_1 + t\_3 + t\_4 = D \mathbf{T}\_8 \\ t\_1 + t\_2 + t\_3 + t\_4 = \mathbf{T}\_8 \end{cases} \Rightarrow \begin{cases} t\_2 = (1 - D) \mathbf{T}\_8 \\ t\_4 = (1 - D) \mathbf{T}\_8 \\ t\_1 + t\_3 = (2D - 1) \mathbf{T}\_8 \end{cases} . \tag{5}$$

The inductance satisfies the volt-second balance condition:

$$\mathrm{L}\mathrm{L}\_{\mathrm{L}}(2D-1)\mathrm{T}\_{\mathrm{s}} + (\mathrm{L}\mathrm{I}\_{\mathrm{L}} - \mathrm{L}\mathrm{I}\_{\mathrm{H}}/2)(2-2D)\mathrm{T}\_{\mathrm{s}} = 0 \Rightarrow \frac{\mathrm{L}\mathrm{I}\_{\mathrm{H}}}{\mathrm{L}\mathrm{I}\_{\mathrm{L}}} = \frac{1}{1-D}.\tag{6}$$

#### *2.2. Operational Modal Analysis D* < *0.5*

During the switching cycle, each arm has three modes of 00, 10, and 01.

1. Mode *M*0 = 00, *S*3 and *S*4 are turned <sup>o</sup>ff, *S*1 and *S*2 are turned on, the voltage of AB is *U*AB = *U*H, *S*3 and *S*4 voltage stress are *U*H/2, the voltage of inductance *L*1 is *U*L − *U*H, *i*L flows to the high-voltage side and decreases linearly, and the corresponding differential equation can be expressed as:

$$\begin{cases} \dot{\mathbf{i}}\_{\mathcal{L}} = -\frac{\eta\_{\mathcal{L}}}{L} \dot{\mathbf{i}}\_{\mathcal{L}} + \frac{1}{L} (\mathcal{U}\_{\mathcal{L}} - \mathcal{U}\_{\mathcal{H}})\\ \dot{\mathcal{U}}\_{\mathcal{H}} = -\frac{1}{\mathcal{R}\_{\mathcal{H}} \mathcal{C}\_{\mathcal{H}}} \mathcal{U}\_{\mathcal{H}}\\ \dot{\mathcal{U}}\_{\mathcal{f}} = 0 \end{cases} \tag{7}$$


$$\begin{cases} \quad t\_2 = D \mathbf{T}\_s \\ \quad t\_4 = D \mathbf{T}\_s \\ \quad t\_1 + t\_3 = (1 - 2D) \mathbf{T}\_s \end{cases} \tag{8}$$

The inductance satisfies the volt-second balance:

$$2D\mathcal{T}\_s(\mathcal{U}\_\mathcal{L} - \mathcal{U}\_\mathcal{H}/2) + (1 - 2D)\mathcal{T}\_s(\mathcal{U}\_\mathcal{L} - \mathcal{U}\_\mathcal{H}) = 0 \Rightarrow \frac{\mathcal{U}\_\mathcal{H}}{\mathcal{U}\_\mathcal{L}} = \frac{1}{1 - D} \quad . \tag{9}$$

#### **3. Multiple Modulation Technique**

#### *3.1. Two Arms Interleaved Parallel Modulation*

Two arms are paralleled, as shown in in Figure 1b, to increase the overcurrent capability and reduce the input side ripple. Arm 1 is composed of *S*1-*S*4, the inductor *L*1 and the flying capacitor *C*f1; and arm 2 is composed of *S*5, *S*6, *S*7, *S*8, the inductor *L*2 and the flying capacitor *C*f2. Among them, *S*1 and *S*4 are turned on complementarily, *S*2 and *S*3 are turned on complementarily, the modulated waves of *S*1 and *S*2 are interleaved 180◦, and the *S*3 and *S*4 modulated waves are interleaved 180◦, as shown in Figure 3. Arm 2 is modulated in the same manner as arm 1 with a phase lag of 90◦.

Two arms are interleaved 90◦ in parallel; eight modes are used at 0.5 < *D* < 0.75, and other eight modes are used at 0.25 < *D* < 0.5. The working mode of the space ratio is shown in Table 1. In the forward power flow (Boost mode), the inductor currents *i*L1 and *i*L2 are positive and flow from the low voltage side to the high voltage side. When the negative power flows (Buck mode), the inductor currents of *i*L1 and *i*L2 are negative, and the high voltage side flows to the low voltage side. The driving signal between the two arms is interleaved 90◦, and the other side bridge arm switch maintains the

original state when one side bridge arm is operated. After the inductor current is superimposed, the low-voltage side current is *i*L = *i*L1 + *i*L2 doubling the pulsation frequency, and the ripple of the *i*L is reduced.

**Figure 3.** The main waveform of two parallel arms. (**a**) Mode 0.5 < *D* < 0.75, (**b**) Mode 0.25 < *D* < 0.5.


**Table 1.** Two arms interleaved parallel coding.

Then the inductor current is superimposed, the low-voltage side current is *i*L = *i*L1 + *i*L2 doubling the pulsation frequency, and the ripple of the *i*L is reduced. According to Equations (2)–(9), the ripple current of three-level bi-directional DC/DC(3L-BDC) in Figure 1b, Δ*I*L1\_3L\_LBDC, can be calculated as

$$
\Delta I\_{\rm L1\\_3L\\_BDC} = \begin{cases}
\frac{(\rm Ll\_H - 2\rm Ll\_L)(1-D)}{2L\_1f\_s}, & (D > 0.5) \\
\frac{(2\rm Ll\_L - ll\_H)D}{2L\_1f\_s}, & (D \le 0.5)
\end{cases} . \tag{10}
$$

Correspondingly, the ripple current of the inductor of two-level bidirectional DC/DC (2L\_ BDC) can be calculated as

$$
\Delta I\_{\rm L1\\_2L\\_BDC} = \frac{(\mathcal{U}\_{\rm H} - \mathcal{U}\_{\rm L})D}{L\_1f\_{\rm s}}.\tag{11}
$$

To reduce currents ripple, *n* arms can be cascaded, and the drive signals between the arms are interleaved 180◦/*<sup>n</sup>*. The more arms that participate in interleaved parallel connection, the more obvious the ripple reduction effect, and the more characteristic points of zero ripple appear at the same time—these zero ripple points show a uniform distribution law. The aforementioned analysis shows that the voltage stress on the switches and the flying capacitors of the 3L\_BDC is half of *U*H, which is just half of the traditional 2L\_BDC. To reduce the voltage stress, it is necessary to employ a series connection.

#### *3.2. Two Arms Complementary Series Modulation*

The topology is connected in series with two inductors to reduce the inductor current ripple amplitude; the low voltage side is isolated from the output side by two inductors, which can improve the energy storage unit safety; the series structure can reduce the voltage stress of the switches and increase the voltage level of the DBC, as shown in Figure 1c. The inductor current waveform during complementary modulation is shown in Figure 4. *S*4 and *Q*1 are the same drive signal, *S*3 and *Q*2 are the same drive signal, *S*2 and *Q*3 are the same drive signal, and *S*1 and *Q*4 are the same drive signal; that is, the switch modulation is based on the topology. The switching period inductance fluctuation frequency is equal to twice of the switching frequency, the inductance fluctuation amplitude is half of that of the single submodule, and the remaining mode complementary series modulation is shown in Table 2.

**Figure 4.** The key waveform of two arms series. (**a**) Mode 0.5 < *D* < 0.75, (**b**) Mode 0.25 < *D* < 0.5.

**Table 2.** Two arms complementary series coding.


The voltage stress on the switches and the flying capacitors is 0.25 *U*H in Figure 1c. In order to reduce the voltage and current stress, it is necessary to increase the series and parallel bridge arms simultaneously. The ripple current of *L*1 in Figure 1c, Δ*I*L1\_3L\_LBDC, can be calculated as

$$
\Delta I\_{\rm L1\\_3L\\_BDC} = \begin{cases}
\frac{(\underline{lL\_\rm H} - 2\underline{lL\_\rm L})(1 - D)}{2(L\_\rm L + L\_3)f\_\*}, & (D > 0.5) \\
\frac{(2\underline{lL\_\rm L} - \underline{lL\_\rm H})D}{2(L\_\rm L + L\_3)f\_\*}, & (D \le 0.5)
\end{cases} \tag{12}
$$

#### *3.3. Four Arms Mixed Modulation*

To meet the large-capacity requirements in the bipolar DC bus, the voltage and current stress of the switching tube should be reduced, so a four-arms mixed converter is proposed, that is, the cascaded form of the interleaved parallel flying-capacitor type three-level converter, as shown in Figure 1d. The left and right parallel arms are interleaved 90◦ parallel modulation, and the upper and lower series arms are complementarily connected in series. For example, when 0.5 < *D* < 0.75, in mode 0101/1010, it means *S*3 is <sup>o</sup>ff, *S*4 is on, *S*7 is <sup>o</sup>ff, *S*8 is on; while, *Q*3 is on, *Q*4 is <sup>o</sup>ff, *Q*7 is on, and *Q*8 is <sup>o</sup>ff. The modulation rule of the BDC is shown in Figure 5.

**Figure 5.** The key waveform of the four arms mixed. (**a**) Mode 0.5 < *D* < 0.75, (**b**) Mode 0.25 < *D* < 0.5.

By mixed modulation, the average inductor current is only half of the single-arm current, the ripple frequency is doubled, the flying capacitor voltage is 0.25 *U*H, and the voltage stress of the switch is only 0.25 *U*H compared to the 2L\_BDC. The modulation is shown in Table 3. To compare the characteristics of the structure, shown in Figure 1, the voltage and current stress conditions are listed in Table 3, and the four arms mixed modulation is more suitable for bipolar high-power applications. This modulation strategy helps to control and protect the design of the circuit. A topological comparison of the proposed BDC in this paper with others are shown in Table 4.

**Table 3.** Four arms mixed modulation coding.


#### **4. Controller design**

Define the state variable as *x* = [ *i*L, *U*H, *U*f ]T, the input variable as *u* = *U*L, the transfer function as *G*id(s) from the duty cycle *d* to the inductor current *i*L and the transfer function *G*ud(s) from the duty cycle *d* to the output voltage *U*H, according to Equations (2)–(9).

$$\mathcal{G}\_{\rm id}(s) = \frac{\frac{\mathcal{U}\_{\rm L}\mathbb{C}\_{\rm H}\mathbb{R}\_{\rm H}}{1 - D}s + \frac{2\mathcal{U}\_{\rm I}}{1 - D}}{\mathcal{C}\_{\rm H}LR\_{\rm H}s^2 + Ls + R\_{\rm H}(1 - D)^2 + r\_{\rm L}},\tag{13}$$

$$\mathcal{G}\_{\rm ud}(s) = \frac{-\frac{L\mathcal{U}\_{\rm L}}{(1-D)^2}s + R\_{\rm H}\mathcal{U}\_{\rm L} - \frac{r\_{\rm L}\mathcal{U}\_{\rm L}}{\left(1-D\right)^2}}{\mathcal{C}\_{\rm H}L R\_{\rm H}s^2 + Ls + R\_{\rm H}\left(1-D\right)^2 + r\_{\rm L}},\tag{14}$$

where, *R*H is *R*load, and *r*L is the inductance parasitic resistance.

The main circuit *parameters* of the converter are shown in Table 5. Due to the inconsistent impedance of the IGBT parasitic parameters and the inductor winding process, the main loop has a certain degree of impedance difference. The controller's PI regulator is *G*c(s) = *k*1 + *k*2/s, where *k*1 = 0.1, *k*2 = 50, and the control block diagram is shown in Figure 6.


**Table 4.** Topological comparison.

(**b**) **Comparison in terms of out capacitor, flying capacitor voltage, voltage across switch, inductor current and fault tolerant capabilities**


**Figure 6.** The control strategy. (**a**)&(**c**) are single voltage loop and its Bode without current loop control. (**b**)&(**d**) are double voltage-current loop and its Bode with current loop control.

The Bode diagram of the proposed control strategy by a single voltage loop, as shown in Figure 6c. The low frequency range is 30 dB, the high frequency band traverses 0 dB with a slope of −20 dB/dec, and the corner frequency is 120 Hz. The gain crossover frequency is 4 kHz, the phase margin is 90◦, and the system is stable; however, the gain is higher than 0dB at 0.1 times of switching frequency. The current inner loop uses inductor current feedback, as shown in Figure 6d. The PI regulator is *G*c(s) = 0.1 + 50/s, the crossing frequency of the open-loop transfer function is 449 Hz when crossing the 0 dB line, and the phase margin is 70◦ at the crossing frequency. It can be judged that the closed loop system is stable. A first-order low-pass filter is added to the loop due to the influence of high frequency noise. The cutoff frequency of the first-order low-pass filter (<sup>ω</sup>c = 2πfc) is set at 0.1 times the switching frequency, and the gain margin kg (*f* c = 2 kHz) is 13.4 dB, which is ideal. The pole introduced by the first-order LPF is far from the real axis, and has little effect on the bode diagram and can be ignored.


**Table 5.** The Parameters of BDC.

#### **5. Experimental result**

The experimental platform is shown in Figure 7. In the platform, the DC power supply E and resistance *R* are used to simulate the power generation change of the renewable energy source. The rated voltage of the DC power supply *E* is 450 V, and the DC bus voltage rating is 400 V. Super capacitor rated voltage is 250 V, rated capacity is 10 F, maximum discharge current is 15 A, charging current is 10 A, super capacitor voltage *U*L range is 150~220 V; switching frequency *f* s is 20 kHz. DC power supply Chroma 62050H-600 (Chroma Systems Solutions, Inc., Foothill Ranch, CA, USA), DC probe YOKOGAWA 701934 (Yokogawa Electric, Inc., Tokyo, Japan), oscilloscope Tek DPO2024B (Tektronix, Inc., Beaverton, OR, USA). The control chip uses DSP (TMS28335) combined with FPGA (EP3C25Q240); DSP is used for signal sampling and control signal generation, and FPGA is used to generate the modulated wave. To test the feasibility of multiple applications, super capacitor *U*L = 200V, high side load *R*H = 200 Ω, adjustable power supply *E* = 450 V, resistance *R* = 10 Ω; during switch *S* disconnection, super capacitor discharge, converter operates on boost 0.5 < *D* < 0.75 mode, the high side capacitor voltage is stable to *U*H = 400 V. Super capacitor *U*L = 250 V, high-voltage-side load *R*H = 200 Ω, adjustable power supply *E* = 450 V, resistance *R* = 10 Ω; during switch *S* closing, super capacitor charging.

**Figure 7.** Experimental setup. (**a**) The experimental system, (**b**) Control system logic.

In the project, due to the inconsistent IGBT parasitic parameters and the inconsistent impedance caused by the inductor winding process, the main loop objectively has impedance differences.

The voltage and current double closed-loop PI regulators are used for impedance matching. The two control loops share the voltage outer loop, and the current inner loop uses respective inductor current feedback. The control loop is shown in Figure 7b. The difference in the modulation signals generated by the control loop adjusts the respective output impedances to achieve current sharing control. The left and right arms are interleaved 90◦ parallel, the two inductor current ripples cancel each other, and the output voltage is stable, as shown in Figures 8 and 9. The current *i*L fluctuating frequency is twice of the switching frequency, and the inductor current fluctuation amplitude is reduced, due to *i*L through two inductors evenly. Two arms series, the flying capacitor voltage is 0.25 *U*H, as shown in Figure 10. The inductor current ripple is small, and the flying capacitor voltage is equal to 0.25 *U*H.

**Figure 8.** Left and right arms interleaved 90º parallel without circumferential inhibition. (**a**) Boost mode. (**b**) Buck mode.

E%XFNPRGHZLWKFLUFXPIHUHQWLDOLQKLELWLRQ

**Figure 9.** Left and right arms interleaved 90º parallel with circumferential inhibition. (**a**) Boost mode, (**b**) Buck mode.

Switch *S* is turned on at *t*ON, and the supercapacitor charging power is 800 W in buck mode. Switch S is turned off at *t*OFF, and the supercapacitor discharging power is 1200 W in boost mode, as shown in Figure 11. The dynamic response time is less than 20 ms from charging to discharging. The dynamic response time is

400 ms from discharging to charging in the four-arms mixed modes. The flying capacitor voltage is always stable, and the DC bus voltage fluctuation is less than 20 V. The input voltage varies between 150–220 V, the output voltage is stable at 400 V, and the change range of *D* is 0.63–0.45. From the experimental results in Figures 8–11, it can be seen that the input and output side voltage ripple is less than 1%, and the current ripple frequency is relatively small, which is beneficial to the stable operation of the energy storage unit. When *Q*7 shorted, *i*L4 ripple is only once per cycle, losing the advantage of three levels. However, the overall performance of the converter remains stable, and the input and output voltage ripples are low, as shown in Figure 12. Therefore, the BDC has a strong fault tolerance ability, and failure of any one of the arms does not affect the operation of other arms.

E%XFNPRGH

**Figure 10.** Two arms complementary series. (**a**) Boost mode, (**b**) Buck mode.

**Figure 11.** Transient response for bidirectional operation. (**a**) Two arms interleaved parallel transientresponse, (**b**) Two arms complementary series transient response.

E7ZRDUPVVHULHV

**Figure 12.** Switch Q7 short circuit experiment.

The efficiency is reduced, due to the inherent loss increase with a light load. Since there is a dead time of 1.5 μs when the converter is actually running, energy can be transferred from the low voltage side to the high voltage side through the IGBT body diode during dead time, as shown in Figure 13. Thus, the boost mode efficiency is higher than the buck mode. The efficiency curve is more than 90% from light load to heavy load, meeting design requirements.

**Figure 13.** The efficiency curves.
