**1. Introduction**

High power density/efficiency dc/dc converters [1,2] have been proposed to reduce unnecessary power loss in order to reduce environmental pollution and met global energy demands. Clean and renewable energy sources meet these requirements to provide available ac or dc power to ac utilities, dc micro-grids, residential houses and commercial buildings by using power electronic based converters or inverters. High-voltage pulse width modulation (PWM) converters have been presented for industry power units [3,4], dc micro-grid systems [5–7] and dc traction or dc light rail transportation systems [8,9]. For these applications, the dc bus voltage is regulated between 750 V and 800 V. Full bridge circuits with a high switching frequency high-voltage rating SiC MOSFET or high-voltage rating insulated gate bipolar transistor (IGBT) devices can be adopted for high dc voltage applications. However, 1200 V SiC MOSFET devices are expensive and 1200 V IGBT devices have low switching frequency problems. Cost and performance are always the two main issues in the development of the available and high reliability power converters. Therefore, MOSFET power devices have been widely adopted in high e fficiency power electronics. To improve the low-voltage drawback of MOSFETs in high-voltage applications, zero voltage switching, multi-level circuit topologies [10–14] have been developed and proposed to decrease conduction and switching losses. The phase shift pulse width modulation (PSPWM) and frequency modulation have normally been adopted to regulate duty cycle or switching frequency. However, the main disadvantage of conventional PSPWM is high circulating current losses at low e ffective duty cycle. In order to reduce circulating current, an active or passive snubber used on the low-voltage side has been proposed in [15–17]. A modular dc/dc converter [18] using low power rating modular circuits in series or parallel connection has been proposed to increase circuit e fficiency and power rating. However, the current between each modular circuit may be unbalanced. To accomplish current balance issue, several current balancing approaches have been presented in [19,20].

A series/parallel-connected dc/dc converter is proposed to accomplish reduced primary circulating current, a soft switching operation, and balanced input voltages and output currents. Two full bridge circuits with series/parallel connection on input/output side are used in the studied circuit to achieve voltage and current sharing for the high voltage input and current output. Therefore, power devices on each full bridge circuit have *V*in/2 voltage stress. To prevent input split voltages imbalance, a voltage balance capacitor was used on the input side to automatically achieve split voltages balance. Passive snubber circuits were employed on output side to create a positive voltage on the secondary rectified terminal under the commutated state so that the primary current at the commutated state can be reduced. To realize current sharing of two full bridge circuits, a current-balance magnetic component was adopted on the high-voltage side. If two currents are unbalanced, then one induced voltage of MC component is decreased to lessen the larger converter current. Therefore, two converter currents can be compensated automatically. PSPWM was adopted to control power devices and accomplish soft switching operation of active switches. The organization of this paper is as follows: The circuit structure and the principle of operation are discussed in Section 2. The steady state operation of the presented converter is shown in Section 3. Test results with a laboratory prototype are presented and investigated in Section 4. The conclusions of the studied converter are discussed in Section 5.

#### **2. Circuit Structure and Principle of Operation**

High-voltage converters were researched and presented for industry power supplies, dc traction vehicle and dc micro-grid systems. Ac/dc power converters with low harmonic currents, high power factor (PFC) and a stable dc voltage shown in Figure 1a are required for industry power converters. Normally, the dc voltage *VH* is controlled at 760 V. Then, a high-frequency link converter is adopted to provide low-voltage output. Figure 1b illustrates the basic power distributed diagrams on dc light rail vehicle. A high-voltage dc converter can convert a 760 V input to supply a low-voltage output for battery charger, control, and communication demands. Figure 1c demonstrates the blocks of a bipolar dc micro-grid system to integrate ac utility system, clean energy generators and industry load and residential load into a common dc bus voltage.

Figure 2 gives the converter configuration of the developed circuit with series/parallel connection of full bridge circuits to achieve low circulating current loss, soft switching for power MOSFETs, and balanced input split voltages and output current sharing. The first full bridge circuit has power MOSFETs *S*1-*S*4 with the output capacitors *C*1-*C*4, leakage or external inductor *Lr*1, transformer *T*1, magnetic core *MC*, filter inductor *Lo*1, secondary-side rectifier diodes *D*1 and *D*2, and passive circuit including *Ca*1, *Da*1 and *Db*1. Likewise, the second full bridge circuit includes the components *S*5-*S*8, *C*5-*C*8, *Lr*2, *T*2, *MC*, *Lo*2, *D*3, *D*4, *Ca*2, *Da*2 and *Db*2. *Cin*,<sup>1</sup> and *Cin*,<sup>2</sup> are input split capacitors and *Cb* is the balance capacitor. Each circuit can transfer one-half rated power to the secondary side. The magnetic core [20] is used to balance *iLr*1 and *iLr*2. Under the balanced primary currents (|*iLr*1|=|*iLr*2|), the induced voltages *VL1* and *VL2* are zero. If *iLr*1 and *iLr*2 are unbalanced (such as |*iLr*1|>|*iLr*2|), the induced voltage *VL*1 of MC cell is decreased in order to decrease *iLr*1 and *VL*2 is increased to increase *iLr*2. Thus, *iLr*1 will equal *iLr*2 and *VL*1 = *VL*2 = 0. PSPWM is used to control *S*1~*S*8 and have zero voltage switching on the MOSFETs. Power switches *S*1~*S*4 and *S*5~*S*8 have identical PWM waveforms. The balance capacitor *Cb* is linked between points *a* and *c*. If *S*1 and *S*5 are on and *S*2 and *S*6 are o ff, then *VCb* = *VCin*,1. Likewise, *VCb* = *VCin*,<sup>2</sup> if *S*2 and *S*6 are on and *S*1 and *S*5 are in the o ff. Since the duty cycle *dS*1 = *dS*2 = 0.5, it is obvious that *VCb* = *VCin*,<sup>1</sup> = *VCin*,<sup>2</sup> = *V*in/2. Thus, the drain voltages of *S*1~*S*8 are *Vin*/2. To decrease the primary-side circulating currents, passive snubbers, *Ca*1, *Da*1, *Db*1, *Ca*2, *Da*2, *Db*2, are used on the presented circuit. At the same time, the filter inductor voltages *vLo*1 = *vCa*1 − *Vo* and *vLo*2 = *vCa*2 − *Vo* rather than −*Vo* in the traditional full bridge duty cycle converters.

**Figure 1.** High-voltage dc/dc converters in (**a**) ac/dc converters, (**b**) dc light rail transportation vehicle, (**c**) dc micro-grid system with bipolar voltages.

**Figure 2.** Circuit configuration of the studied converter.

The operation principle of the presented circuit is discussed with the assumptions: (1) *Cin,*1 = *Cin,*2; (2) *C*1 = ... .<sup>=</sup> *C*8 = *Coss*; (3) *Ca*1 = *Ca*2 = *Ca*; (4) *Lm*1 = *Lm*2 = *Lm*; (5) *Lo*1 = *Lo*2 = *Lo*; (6) *Lr*1 = *Lr*2 = *Lr*; (7) *VCb* = *VCin,*1 = *VCin,*2 = *V*in/2; and (8) *n*1 = *n*2 = *n*. Figure 3 shows the PWM waveforms of the studied converter. The duty cycle of *S*1~*S*8 is 0.5. The gating signals of *S*4 (*S*3) is shifted to *S*1 (*S*2), respectively. Due to the switching states of power devices, the converter has fourteen steps in a

switching period. The PWM waveforms are symmetrical for every half cycle. Therefore, only the first seven steps are discussed and the circuits of first seven operating steps are illustrated in Figure 4.

**Figure 3.** Pulse width modulation (PWM) waveforms of the presented converter.

**Step 1 [***t***0***, t***1]:** Before *t*0, *S*1, *S*4, *S*5, *S*8, *D*1 and *D*3 conduct, *iLr*1 > 0 and *iLr*2 > 0. After *t*0, power MOSFETs *S*1 and *S*5 turn <sup>o</sup>ff. *C*1 and *C*5 are charged and *C*2 and *C*6 are discharged. The energy on *Lr*1, *Lr*2, *Lo*1 and *Lo*2 can discharge *C*2 and *C*6. Equations (1) and (2) give the soft switching conditions of *S*2 and *S*6.

$$\mathbf{u}\_{\rm r}(L\_{r1} + n\_1^2 L\_{v1}) \mathbf{i}\_{Lr1}^2(t\_0) \ge \mathbf{C}\_{\rm oss} \mathbf{V}\_{\rm in}^2 / 2 \tag{1}$$

$$(L\_{r2} + n\_2^2 L\_{v2}) i\_{Lr2}^2(t\_0) \ge C\_{\text{ess}} V\_{in}^2 / 2 \tag{2}$$

If these conditions are satisfied, then *vC*1 = *vC*5 = *V*in/2 and *vC*2 = *vC*6 = 0 at *t*1. The time duration in step 1 is obtained in Equation (3).

$$
\Delta t\_{01} = t\_1 - t\_0 = \frac{C\_{\text{cos}} V\_{\text{in}}}{i\_{Lr1}(t\_0)} \approx \frac{n\_1 C\_{\text{cos}} V\_{\text{in}}}{i\_{Lo,\text{peak}}} \approx \frac{2 n\_1 C\_{\text{cos}} V\_{\text{in}}}{I\_o} \tag{3}
$$

The time duration Δ*t*01 is related to the load current and input voltage.

**Step 2 [***t***1***, t***2]:** At *t*1, *v*C2 = *v*C6 = 0. The positive primary currents *iLr*1 and *iLr*2 will flow through the body diode of *S*2 and *S*6. Thus, power MOSFETs *S*2 and *S*6 can achieve zero-voltage switching after *t*1. The ac side voltages *vab* = *vcd* = 0 and *iLr*1 and *iLr*2 decrease. Therefore, *Da*1 and *Da*2 conduct at this freewheeling state. The magnetizing voltages *vLm*1 and *vLm*2 are clamped at *vCa*1 and *vCa*2, respectively. The primary inductor voltages *vLr*1 = −*n*1*vCa*1 and *vLr*2 = −*n*2*vCa*2 and the filter inductor voltages *vLo*1 = *vCa*1 − *Vo* < 0 and *vLo*2 = *vCa*2 − *Vo* < 0. Therefore, *iLr*1, *iLr*2, *iLo*1 and *iLo*2 are all decreased in this step.

$$i\_{Lr1}(t) \approx i\_{Lr1}(t\_1) - \frac{n\_1 v\_{\text{Ca1}}}{L\_{r1}}(t - t\_1) \tag{4}$$

$$i\_{Lr2}(t) \approx i\_{Lr2}(t\_1) - \frac{n\_2 v\_{Cu2}}{L\_{r2}}(t - t\_1) \tag{5}$$

$$i\_{Lo1}(t) \approx i\_{Lo1}(t\_1) + \frac{v\_{\text{Ca1}} - V\_o}{L\_{o1}}(t - t\_1) \tag{6}$$

$$i\_{La2}(t) \approx i\_{La2}(t\_1) + \frac{v\_{Ca2} - V\_o}{L\_{o2}}(t - t\_1) \tag{7}$$

Thus, the circulating current is decreased under the commutated state. In this step, the balance capacitor voltage *VCb* = *VCin,*2.

**Step 3 [***t***2***, t***3]:** At time *t*2, *iD*1 = *iD*3 = 0 and *D*1 and *D*3 are <sup>o</sup>ff. Then, *iCa*1 = −*iLo*1, *iCa*2 = −*iLo*2, *iLr*1 = *iLm*1(*t*2) and *iLr*2 = *iLm*2(*t*2). Since *iLm*1(*t*2) and *iLm*2(*t*2) are close to zero, the circulating current is removed. The filter inductor voltages *vLo*1 = *vCa*1 − *Vo* < 0 and *vLo*2 = *vCa*2 − *Vo* < 0. The secondary-side currents *iLo*1 and *iLo*2 are lessened.

**Step 4 [***t***3***, t***4]:** At *t*3, power MOSFETs *S*4 and *S*8 turn <sup>o</sup>ff. *C*3 and *C*7 are discharged and *C*4 and *C*8 are charged. The energy on *Lr*1 and *Lr*2 can discharge *C*3 and *C*7 and the soft switching conditions of *S*3 and *S*7 are expressed in Equations (8) and (9).

$$\|L\_{r1}\|\_{Lr1}^2(t\_3) \ge C\_{\text{ess}} V\_{\text{in}}^2 / 2 \tag{8}$$

$$\|L\_{r2}\|\_{L^2}^2(t\_3) \ge C\_{\text{ess}}V\_{\text{in}}^2/2\tag{9}$$

**Step 5 [***t***4***, t***5]:** This step starts at *t*4 when *vC*3 = *vC*7 = 0. Due to *iLr*1(*t*4) > 0 and *iLr*2(*t*4) > 0, the body diodes of *S*3 and *S*7 conduct. Then, *S*3 and *S*7 naturally conduct at zero-voltage switching after *t*4. In this step, *vab* = −*VCin,*1, *vcd* = −*VCin,*2, *VCb* = *VCin,*2, *vLm*1 = −*n*1*vCa*1, *vLm*2 = −*n*2*vCa*2, *vLo*1 = *vCa*1 − *Vo* and *vLo*2 = *vCa*2 − *Vo*. In order to balance *iLr*1 and *iLr*2, the magnetic core MC is employed on the high-voltage side. Under current balance condition, *VL*1 = *VL*2 = 0. Therefore, *vLr*1 ≈ *n*1*vCa*1 − *V*in/2 and *vLr*2 ≈ *n*2*vCa*2 − *V*in/2. It can be observed that *iLr*1, *iLr*1, *iLo*1 and *iLo*2 all decrease in this step. When the secondary-side diode currents *iD*2 = *iLo*1 and *iD*4 = *iLo*2 at time *t*5, diodes *Da*1 and *Da*2 are reverse biased. In this step, *iD*2 and *iD*4 increase from zero to *iLo*1 and *iLo*2, respectively and the time duration in step 5 can be obtained as:

$$
\Delta t\_{45} = \frac{L\_{r1} I\_{Lo1, \text{min}}}{n\_1 V\_{in} / 2 - n\_1^2 v\_{\text{Ca1}}} \approx \frac{L\_{r1} I\_o}{n\_1 V\_{in} - 2 n\_1^2 v\_{\text{Ca1}}} \tag{10}
$$

Since *Da*1 and *Da*2 are still conducting in this step, the duty loss is calculated in Equation (11).

$$d\_{5,loss} \approx \frac{L\_{r1} I\_0 f\_{sw}}{n\_1 V\_{in} - 2n\_1^2 v\_{Cu1}} \tag{11}$$

**Step 6 [***t***5***, t***6]:** At time *t5*, *iD*2 = *iLo*1 and *iD*4 = *iLo*2. Then, the secondary-side diodes *Da*1 and *Da*2 are off and *Db*1 and *Db*2 are on in this step. The inductances *Lr*1/(*n*1)<sup>2</sup> (*Lr*2/(*n*2)2) and *Ca*1 (*Ca*2) are resonant with frequency *fR* = *n*1/(<sup>2</sup>π √*Lr*1*Cca*1). Since *vLo*1 = *vCa*1 and *vLo*2 = *vCa*2, *iLo*1 and *iLo*2 both increase in this step. In order to force *iDb*1 = *iDb*2 = 0 at *t*6, the half resonant cycle 1/(2*fR*) must be less than *de*ff*,minTsw*/2. The primary magnetizing voltages *vLm*1 = *<sup>n</sup>*1(*vCa*1 + *Vo*) and *vLm*2 = *<sup>n</sup>*2(*vCa*2 + *Vo*) and the primary inductor current *iLr*1 ≈ −(*iLo*<sup>1</sup> + *i*C*a*1)/*<sup>n</sup>*<sup>1</sup> and *iLr*2 ≈ −(*iLo*<sup>2</sup> + *i*C*a*2)/*<sup>n</sup>*2.

**Step 7 [***t***6***, t***7]:** At time *t*6, *iD*2 = *iLo*1 and *iD*4 = *iLo*2. Then diodes *Db*1 and *Db*2 are <sup>o</sup>ff. The filter inductor voltages *vLo*1 ≈ *V*in/(2*n*1) − *Vo* and *vLo*2 ≈ *V*in/(2*n*2) − *Vo* so that *iLo*1 and *iLo*2 increase. At *t*7, *S*2 and *S*6 turn <sup>o</sup>ff.

(**a**) 

**Figure 4.** *Cont*.

(**b**) 

(**e**) 

**Figure 4.** *Cont*.

**Figure 4.** Equivalent circuits in first seven steps (**a**) step 1, (**b**) step 2, (**c**) step 3, (**d**) step 4, (**e**) step 5, (**f**) step 6, (**g**) step 7.

#### **3. Steady State Analysis**

Each full bridge converter in the presented converter supplies one-half of load power to low-voltage side. To balance *iLr*1 and *iLr*2, the magnetic component MC is employed in the studied converter. Under current balance condition, *VL*1 = *VL*2 = 0. It can be observed that the average voltages *VCa*1<sup>=</sup> *VCa*2 = *V*in/(2*n*1) − *Vo* in step 6. Under steady state operation, *iLo*1 and *iLo*2 at *t0* and *t0* + *Tsw* in every switching period are identical, *iLo*1(*t*0) = *iLo*1(*<sup>t</sup>*0 + *Tsw*) and *iLo*2(*t*0) = *iLo*2(*<sup>t</sup>*0 + *Tsw*). Thus, Equation (12) is derived according to voltage-second balance condition.

$$(d - d\_5 - d\_6)(\frac{V\_{\text{in}}}{2n\_1} - V\_o) + d\_6 V\_{\text{Ca1}} = (\frac{1}{2} - d + d\_5)(V\_o - V\_{\text{Ca1}}) \tag{12}$$

where *d*5 and *d*6 are duty cycles in steps 5 and 6, respectively. Based on *VCa*1 = *V*in/(2*n*1) − *Vo*, *Vo* can be derived in Equation (13) under steady state.

$$V\_o = \frac{V\_{in}}{4n\_1(1 - d + d\mathfrak{s})} = \frac{V\_{in}}{4n\_1(1 - d\_{eff})} \tag{13}$$

where *de*ff = *d* − *d*5 is an effective duty ratio and δ is duty ratio when *S*1 (*S*2) and *S*4 (*S*3) are conducting. From Equation (13), the voltage gain is expressed in Equation (14).

$$G\_{d\varepsilon} = V\_o / V\_{in} = \frac{1}{4n\_1(1 - d\_{eff})} \tag{14}$$

From the given input and output voltages, the turns ratio *n* is derived as:

$$n = n\_1 = n\_2 = \frac{V\_{\rm in}}{4V\_o(1 - d\_{eff})} \tag{15}$$

Therefore, the minimum primary turns *np* and secondary turns *ns* are derived in Equation (16).

$$m\_p \ge \frac{V\_{L,w} dT\_{sw}}{\Delta B\_{\text{max}} A\_\varepsilon}, \ n\_s = \frac{n\_p}{n} \tag{16}$$

where Δ*Bmax*: maximum flux density range, *Ae*: effective cross area, and *VLm*: primary voltage. In steady state, *ILo*1 = *ILo*2 = *Io*/2, *VCin*,<sup>1</sup> = *VCin*,<sup>2</sup> = *VCb* = *V*in/2 and *vS*1,*ds* = ... = *vS*8*,ds* = *V*in/2. If the effective duty cycle is defined, then the ripple currents Δ*Lo*1 and Δ*Lo*2 can be obtained in Equation (17).

$$
\Delta \dot{\mathbf{i}}\_{\rm Lol} = \Delta \dot{\mathbf{i}}\_{\rm Lol2} = (V\_o - V\_{\rm Cu1})(0.5 - d\_{eff})\mathbf{T}\_{\rm sun}/\mathbf{L}\_o \approx (2V\_o - \frac{V\_{\rm in}}{2n\_1})(0.5 - d\_{eff})\mathbf{T}\_{\rm sun}/\mathbf{L}\_o \tag{17}
$$

If the ripple currents Δ*iLo*1 = Δ*iLo*2 = Δ*iLo* are given or selected, then output inductances are achieved in Equation (18).

$$L\_{o1} = L\_{o2} = L\_o \ge (2V\_o - \frac{V\_{in}}{2n\_1})(0.5 - d\_{eff})T\_{sw} / \Delta i\_{Lo} \tag{18}$$

The winding turns of filter inductors *Lo*1 and *Lo*6 are expressed as:

$$m\_{L\alpha1} = m\_{L\alpha2} \ge \frac{L\_{\upsilon1} i\_{L\alpha1,\text{peak}}}{B\_{\text{max}} A\_{\text{c}}} \tag{19}$$

The voltage ratings and average currents on *D*1~*D*4 are expressed in Equations (20)–(23).

$$V\_{D1, \text{rating}} = \dots = V\_{D4, \text{rating}} \approx V\_{\text{in}} / n\_1 \tag{20}$$

$$V\_{\text{Dt1,rating}} = V\_{\text{Dt2,rating}} = V\_{\text{Dt1,rating}} = V\_{\text{Dt2,rating}} \approx V\_o \tag{21}$$

$$I\_{D1, \text{av}} = I\_{D2, \text{av}} = I\_{D3, \text{av}} = I\_{D4, \text{av}} \approx I\_0 / 4 \tag{22}$$

$$I\_{Da1, \text{av}} = I\_{Da2, \text{av}} = I\_{Db1, \text{av}} = I\_{Db2, \text{av}} \approx dI\_0/2 \tag{23}$$

Based on Equation (11), the necessary inductances *Lr*1 and *Lr*2 are obtained as:

$$L\_{r1} = L\_{r2} \approx \frac{d\_{5,loss}(n\_1 V\_{in} - 2n\_1^2 v\_{Cu1})}{l\_o f\_{sw}} \tag{24}$$

#### **4. Test Results**

The studied circuit was verified through a prototype. In the prototype circuit, *V*in was between 750 V and 800 V, *Vo* was 24 V, *Io,rated* was 70 A, *fsw* is 60 *k*Hz, the effective duty cycle *de*ff was 0.35, and the duty loss in step 5 was 0.01. Therefore, the turn-ratio and the primary-side inductances were obtained as:

$$n = n\_1 = n\_2 = \frac{V\_{in, \text{min}}}{4V\_o(1 - d\_{eff})} \approx 12\tag{25}$$

$$L\_{r1} = L\_{r2} \approx \frac{d\_{5, \text{loss}}(n\_1 V\_{i \text{min}} - 2n\_1^2 v\_{\text{Cu1}})}{l\_0 f\_{\text{sw}}} \approx 16.5 \text{ } \mu\text{H} \tag{26}$$

In the prototype circuit, the actual magnetizing inductance, *Lm*1 = *Lm*2 = 2 mH, the primary turns *<sup>n</sup>*1*,p* and *<sup>n</sup>*2*,p* were 48 and the secondary turns *<sup>n</sup>*1*,<sup>s</sup>* and *<sup>n</sup>*2*,<sup>s</sup>* were 4 with TDK EER-42 magnetic core. The maximum ripple currents Δ*iLo* was assumed as 4 A. The *Lo*1 and *Lo*2 can be obtained in Equation (27).

$$L\_{v1} = L\_{v2} = (2V\_o - \frac{V\_{in,\text{min}}}{2n\_1})(0.5 - d\_{eff})T\_{sw}/\Delta i\_{La} \approx 10.5\,\mu\text{H} \tag{27}$$

MOSFETs SiHG20N50C with 500 V/20 A ratings were selected for *S*1~*S*8. MBR40100PT with 100 V/40 A ratings were selected for *D*1*~D*4 and *Da*1~*Db*2. The magnetic coupling (MC) transformer *np*:*ns* = 24 turns:24 turns. The adopted capacitors were *Cin,*1 = *Cin,*2 = 240 μF/450 V, *Cb* = 1 μF, *Ca*1 = *Ca*2 = 8.8 μF and *Co* = 2200 μF/100 V. The PSPWM integrated circuit UCC3895 was selected as a controller to control *S*1~*S*8.

The experimental test bench is given in Figure 5. The dc power source was using a two Chroma 62016P-600-8 programmable dc power supply connected in series to supply 800 V at the input side of the proposed circuit. The dc electronic load was a Chroma 63112A programmable dc load. The digital oscilloscope Tektronix TDS3014B was adopted to measure the test waveforms. Figure 6 illustrates the test waveforms of the gate voltages of switches *S*1~*S*4 in first full bridge circuit at rated power. The phase-shift angle between *S*1 and *S*4 depended on the input voltage. The gating voltages of *S*5~*S*8 in second full bridge circuit were identical to *S*1~*S*4, respectively. The gating voltages *vS*1*,g* and *vS*4*,g* and ac voltages *vab* and *vcd* at rated power are demonstrated in Figure 7. Three-level voltages were observed on *vab* and *vcd*. Figure 8 illustrates the test waveforms *vab*, *vcd*, *iLr*1 and *iLr*2 under 20% power and rated power. Two primary-side currents were well balanced with each other due to the current balance magnetic core is used to achieve current sharing. Figure 9 gives the test results of *VCin*1, *VCin*2 and *VCb* at rated power. Split capacitor voltages were well balanced with *VCin*1 = 401.6 V and *VCin*2 = 398.4 V. Figure 10 gives the measured waveforms of output side currents. Figure 11 provides the test waveforms of *iLo*1, *iDb*1, *io*1 and *io*2 under di fferent load conditions. It is clear that *io*1 and *io*2 were balanced. Figure 12 provides the measured results of *S*1 under 20% power and rated power. The soft switching of *S*1 was succeeded from 20% power to rated power. The other switches such as *S*2, *S*5 and *S*6 had the same characteristics as *S*1. Therefore, *S*2, *S*5 and *S*6 were also turned on with soft switching turn-on from 20% power. Figure 13 demonstrates the measured waveforms of *S*4 under half and full loads. The soft switching of *S*4 are realized from 50% load due to the energy on *Lm*1 and *Lm*2. Likewise, *S*3, *S*7 and *S*8 have same characteristics as *S*4 and *S*3, *S*7 and *S*8 with soft switching turn-on from 50% power. The test e fficiencies of the presented circuit are 91.7% at 20% power, 93.5% at 50% power and 92.9% at 100% power and shown in Figure 14.

**Figure 5.** Pictures of the presented circuit in the laboratory: (**a**) experimental setup and (**b**) prototype circuit.

(**b**) **Figure 6.** Measured gate voltages of S1~S4 in first full bridge circuit at full load and (**a**) Vin = 750 V and (**b**) Vin = 800 V (vS1,g~vS4,g: 10 V/div; time: 4 μs/div).

**Figure 7.** Experimental results of vS1,g, vS4,g, vab and vcd at full load (**a**) Vin = 750 V and (**b**) Vin = 800 V (vS1,g, vS4,g: 10 V/div; vab, vcd: 500 V/div; time: 4 μs/div).

**Figure 8.** Measured waveforms of vab, vcd, iLr1 and iLr2 at 800 V input (**a**) 20% load (vab, vcd: 500 V/div; iLr1, iLr2: 2A/div; time: 4 μs/div) and (**b**) full load (vab, vcd: 500 V/div; iLr1, iLr2: 5A/div; time: 4 μs/div).

**Figure 9.** Measured waveforms of split voltages VCin1 and VCin2 and balance capacitor voltage VCb at 800 V input and full load (VCin1, VCin2, VCb: 200 V/div; time: 4 μs/div).

**Figure 10.** Measured waveforms of the secondary-side currents in first full bridge circuit (**a**) 20% load (iD1, iD2, iLo1, iDa1, iDb1: 5A/div; time: 4 μs/div) and (**b**) full load (iD1, iD2, iLo1, iDa1, iDb1: 20 A/div; time: 4 μs/div).

**Figure 11.** Measured waveforms of the secondary-side currents iLo1, iDb1, io1 and io2 (**a**) 20% load (iLo1, iDb1: 5A/div; io1, io2: 10 A/div; time: 4 μs/div) and (**b**) full load (iLo1, iDb1, io1, io2: 20 A/div; time: 4 μs/div).

**Figure 12.** Measured waveforms of the leading-leg switch S1 at 800 V input (**a**) 20% load (vS1,g: 10 V/div; vS1,d: 200 V/div; iS1: 1A/div; time: 2 μs/div) and (**b**) full load (vS1,g: 10 V/div; vS1,d: 200 V/div; iS1: 2 A/div; time: 2 μs/div).

(**b**)

**Figure 13.** Measured waveforms of the lagging-leg switch S4 at 800 V input (**a**) 50% load and (**b**) full load (vS4,g: 10 V/div; vS4,d: 200 V/div; iS4: 2A/div; time: 2 μs/div).

**Figure 14.** Measured circuit efficiencies of the proposed circuit.
