**1. Introduction**

Up to now, much research on the accuracy of the pulse width modulation (PWM) has been conducted. The reason why the development of the high-resolution PWM is needed is described below. One reason is that the PWM resolution should be higher than the analog-to-digital converter (ADC) resolution to avoid limit cycle oscillation [1–3]. The other reason is that under the fixed system clock, the PWM accuracy is inversely proportional to the switching frequency. However, PWM accuracy should be not too low. Consequently, under this constraint, the more the switching frequency is, the more the system clock, which is proportional to the switching frequency. Accordingly, due to limitations on the integrated circuit (IC) process, the dissipation power will be increased abruptly, including the charging/discharging of the complementary metal-oxide-semiconductor (CMOS) gate and the leakage current due to the miniature process. Based on the above two reasons, the PWM accuracy and the switching frequency are limited to some extent. It is possible that a special process, such as silicon-on-isolator (SOI) [4,5], may reduce the leakage current, and may keep low power dissipation and low temperature under the high-speed system clock of the miniature process. However, the corresponding cost is high, and this special process is usually used in the manufacture of the central processing unit (CPU) or the graphic processing unit (GPU). There is a lot of research on high-accuracy PWM. For example, the literature [6–21] focus on how to reduce the number of digital pulse width modulation (DPWM) steps, where the high-switching clock, e.g., counter-based DPWM, is achieved based on special structures [7,19–21]. Most of these structures are multiple interleaved to achieve high-switching clock or use very short delay elements, e.g., hybrid DPWM [1,22]. Although the delay line based DPWM can achieve high accuracy, the corresponding silicon area is relatively large compared with the traditional counter-based DPWM. In addition, the delay line based DPWM is sensitive to the operating temperature, process, and power interference [12].

On the other hand, some researches increase the e ffective duty cycle to achieve high-accuracy resolution, for example, digital dither [23], sigma-data [8,10,18], special modulation [24], and PFM [25]. The method taken by the literature [23] may cause the output voltage ripple to be small or large, thereby influencing the controller performance. The method followed in [24] tends to vary the turn-on and

turn-o ff periods of the switch so the ADC sampling is di fficult. As for the method shown in [25], it is restricted to PFM operation.

Based on aforementioned, this paper is an extension of the paper [26]. The latter takes the one-comparator counter-based PWM control, whereas the former takes the one-comparator counter-based PWM control with PFM control. By doing so, the former can increase pseudo-1-bit resolution under constant-frequency operation, so that system stability will be improved greatly. In addition, the di fference in on-chip hardware between the two control strategies is slightly small, whereas there is no di fference in o ff-chip circuit complexity between the two control strategies.

#### **2. Problem Description**

In many papers, the problem of limit cycle oscillation has been discussed as shown in Figure 1a. Most people say that this is because the resolution of PWM is larger than that of ADC. In fact, the answer to this problem is too brief. This is because the gain of the control loop should be taken into account. The solution of the limit cycle oscillation that is only based on high-resolution DPWM is not enough. Therefore, the detailed overall calculations and the corresponding program flow are discussed. From Figure 1b, it can be seen that although the output voltage *VO* keeps up with the voltage reference *Vref*, *VO* swings up and down around *Vref* due to the DPWM resolution being lower than ADC resolution. From the point of view of control, the di fference in oscillation between *VO* and *Vref* is quite small, but *VO* cannot keep up with *Vref*. As the DPWM resolution is higher than the ADC resolution, the feedback error can be kept as small as possible, and hence no limit cycle oscillation occurs. From Figure 1, it gives us a hint that the traditional controller needs an integral gain so as to make *VO* approach to *Vref* as near as possible.

**Figure 1.** Quantization resolution in a digitally controlled pulse width modulation (PWM): (**a**) with limit cycle oscillation; (**b**) without limit cycle oscillation.

#### **3. Discussion of Compensator Gain**

Figure 2 shows the digital closed-loop system block diagram. There are three block diagrams. One is an analog-to-digital converter (ADC) block, another is a compensator block, and the other is a digital-to-analog converter (DAC) block. The last block includes the controlled plant. The gains for the ADC, compensator, and DAC blocks are described as (1), (2) and (3), respectively. In order to avoid limit cycle oscillation, Equation (4) must hold:

$$ADC\_{\text{Gain}} = \frac{LSB\_{ADC}}{Vo} \tag{1}$$

$$\text{DAC}\_{\text{Gain}} = \frac{Vo}{LSB\_{\text{DAC}}} \tag{2}$$

$$Comp\_{\text{Gain}} = \frac{LSB\_{\text{DAC}}}{LSB\_{\text{ADC}}} \tag{3}$$

$$ADC\_{\text{Gain}} \times Comp\_{\text{Gain}} \cdot DAC\_{\text{Gain}} \le 1$$

 (4)

**Figure 2.** Digital closed-loop system block diagram.

#### **4. ADC Strategy**

Figure 3 shows the proposed system configuration, constructed by one synchronously-rectified (SR) buck converter and one feedback control circuit. The latter is built up by the field-programmable gate array (FPGA). Inside the FPGA, there are one proportional-integral-derivative (PID) control block, one DPWM controller, and one feedback control block. Outside the FPGA, there is one voltage divider, one saw-tooth generator, one analog circuit, and one comparator. The saw-tooth generator is constructed by one charging switch *Q*3, one constant current source, one capacitor *Cramp*, one DC-blocking capacitor *Cb* and one operational amplifier (OPA) with a voltage gain of −1. Furthermore, the feedback counter is a digital counter, which is inside the FPGA. As the output signal from the comparator, named *VFB*, is "1", the counter counts one, whereas the *VFB* signal is reset to zero as synchronized with the *PWM* signal. In addition, the sensed output signal *v*- *O* is obtained by one feedback voltage divider built up by two resistors.

**Figure 3.** System configuration.

#### **5. Basic Operating Principles**

Prior to this section, there are some assumptions and symbol definitions described. It is assumed that the voltage ripple of the output voltage is quite small so the output voltage *vO* can be regarded as an average value *VO*. The triggering signal for *Q*3 is signified by *vramp*\_*rst*. The sawtooth waveform is represented by *vramp* which has a minimum value of zero and a peak value of *Vramp*\_*pp*. The signal *vramp* after the AC coupling capacitor *Cb* is signified by *vramp*. Therefore, the signal −1 <sup>2</sup>*Vramp*\_*pp* is the minimum value of *vramp* whereas the signal 1 <sup>2</sup>*Vramp*\_*pp* is the maximum value of *vramp*. The signal *vramp* is changed to −*vramp* after the OPA with gain= −1. Afterwards, the sum of −*vramp* and *v*- *O* has a minimum value of *v*- *O* − 1 <sup>2</sup>*Vramp*\_*pp* and a maximum value of *v*- *O* + 1 <sup>2</sup>*Vramp*\_*pp* . Finally, the output of the comparator is a digital signal, determined by *v*- *O* − *vramp* and *Vre f* . If the *v*- *O vO* = *Gfb*, then the voltage range of *VO* can locate between *Vre f* − 1 <sup>2</sup>*Vramp*\_*pp* /*Gf b* and *Vre f* + 1 <sup>2</sup>*Vramp*\_*pp* /*Gf b*. Figure 4 shows the associated circuit waveforms, which are described based on the time sequence, that is, the operating states. There are four operating states in this circuit, to be shown below:

**Figure 4.** Waveforms relevant to sampling sequence.

(1) State 1 [t0~t1]: Let the voltage *Vramp*\_*rst* be high, thereby making the switch Q3 turned on and the voltage across *Cramp* zero. At the same time, the PWM is high, causing Q1 to be turned on and Q2 to be turned <sup>o</sup>ff. This time interval is short, smaller than 1% of the PWM switching period. The signal *vramp* is blocked by the DC-blocking capacitor Cb, and after the OPA with a gain of −1, the resulting signal −*vramp*, which is added to *v*-*O* so as to obtain *v*-*O* − *vramp*, which is subtracted from *Vre f* to obtain the signal VFB.

(2) State 2 [t1~t2]: The signal PWM keeps high. Let *Vramp*\_*rst* be low, thereby making Q3 turned off and *Cramp* is linearly charged. If *v*-*O* − *vramp* > *Vre f* , then VFB = "high", thereby making the counter value increased by one. As the preset turn-on time in the N period is reached, the operating state proceeds to state 3.

(3) State 3 [t2~t3]: At the time instant of t2, let the signal PWM be "low." If (*v*-*O* − *vramp*) > *Vre f* , then VFB = "high", thus rendering the counter value keeping increased by one. If *v*-*O* − *vramp* < *Vre f* , then the operating state goes to state 4.

(4) State 4 [t3~t0]: At the time instant of t3, VFB = "low," the corresponding counter value will be saved in the feedback register, and then the counter value is set to zero. During this state, the PID calculates the control force for the next period, according to the information in the feedback register. At the same time, the duty cycle information is downloaded to the DPWM. At the time of t0, the next cycle begins. In addition, from Figure 4, it can be seen that as *v*-*O* = *Vre f* , the counter value is 50%, which is a full scale.

Under the ideal condition, if the counter value locates within the sampling range of the comparator, *VFB* is linearly proportional to *v*-*O*. For example, in Figure 4, if the range of the counter value is *n*-bit, the sampling resolution can be represented by *Vramp*\_*pp counter value*, that is, *Vramp*\_*pp n bits* is the sampling resolution of the least significant bit (LSB). The smaller the *Vramp*\_*pp* is or the larger the bit number of the counter value is, the more the resolution. It is suggested that in order to enhance the linearity, *Vramppp* > 10 × *vO*\_*ripple* should hold in design.

If the sensed output voltage *v*-*O* is out of the sampling range of the comparator, the sampled data will be saturated. For example, as *v*-*O* ≥ *Vre f* + 12*Vramp*\_*pp*, the comparator keeps *VFB* = "high", and hence the counter value keeps the maximum error. By the same way, as *v*-*O* ≤ *Vre f* − 12*Vramp*\_*pp*, the comparator keeps *VFB* = "low", and hence the counter value keeps the minimum error.

#### **6. Resolution Design**

#### *6.1. Requirements of Resolution of DPWM and ADC*

In the traditional buck converter with digital control, if the DPWM has *NDPWM* bits, then the resolution of DPWM can be expressed by

$$\text{Resolution}\_{\text{DPWM}} = \frac{V\_{in}}{2^{N\_{\text{DPWM}}}} \tag{5}$$

Each bit in DPWM causes a voltage variation to be ΔVDPWM = *Vin* 2*NDPWM* .. By the same way, if ADC has *NADC* bits, then ADC resolution can be represented by

$$\text{Resolution}\_{\text{ADC}} = \frac{V\_{\text{ramp\\_pp}}}{2^{\text{NADC}}} \tag{6}$$

Each LSB in ADC causes a voltage variation to be ΔVADC = *Vramp*\_*pp* 2*NADC* .

According to the literature [20], the resolution of DPWM and ADC is mainly influenced by the limit cycle oscillation. This is because when the DPWM resolution is lower than the ADC resolution, the DPWM cannot satisfy the sampled value of the ADC for any operating point such that the feedback error is not zero. Therefore, the controller outputs a keeping-jumping control force to the DPWM, to force the average output voltage to satisfy the voltage reference. However, such a keeping-jumping PWM control force will cause the output voltage to oscillate. When the DPWM resolution is higher than the ADC resolution, the DPWM can find some operating point to satisfy the sampled value of the ADC and to make the feedback error zero. By doing so, the limit cycle oscillation phenomenon can be avoided.

Therefore, the minimum requirement for the limit cycle oscillation is shown in (7):

$$\text{Resolution}\_{\text{DPWM}} = \frac{V\_{in}}{2^{\text{NDPVM}}} = \frac{V\_{\text{ramp}\_{pp}}}{2^{\text{NADC}}} \tag{7}$$

Accordingly, the minimum value of *Vramp*\_*pp* is *Vramp*\_*pp*\_*min* = *Vin* × 2*NADC* 2*NDPWM* . Based on *Iramp* × *Ts* = *Cramp* × *vramp*, *Vramp*\_*pp*\_*min* can be signified by

$$V\_{ramp\\_pp\\_min} = V\_{in} \times \frac{2^{N\_{ADC}}}{2^{N\_{DPP}}} = \frac{I\_{ramp} \times T\_s}{\mathcal{C}\_{ramp}} \tag{8}$$

#### *6.2. Calculation of VFB Duty*

From Figure 5, it can be seen that the relationship between the comparator output signal and the feedback counter value are as shown in (9):

$$Duty\_{(VFB)} = \frac{T\_{VFB\\_Hi}}{T\_S} = \frac{AD\mathbb{C}\_{VFB}}{AD\mathbb{C}\_{fullscale}}\tag{9}$$

where

*ADCfullscale*: Full-scale value of feedback counter.

*ADCVFB*: Feedback value of *N* period

\_

*TVFB Hi*: High level of the *VFB* signal

*Duty*(*VFB*): Duty cycle of the *VFB* signal

On the other hand, Figure 6a is under the condition that *Duty*(*VFB*) is 100%. In this case, *VOmax* = *Vre f* + *Vramp*\_*pp* 2 . Figure 6b is under the condition that *Duty*(*VFB*) is 0%. In this case, *v*-*Omin* = *Vre f* − *Vramppp* 2 . Thus, based on the geometry theory, it can be found that any value of *Duty*(*VFB*) within the interval of !*Vre f* − *Vramp*\_*pp* 2 " < *v*-*O* < !*Vre f* + *Vramp*\_*pp* 2 " can be expressed as

$$Duty\_{(VFB)} = \frac{v\_O^{\prime} - V\_{ref} + \frac{V\_{nump,p}}{2}}{v\_{O^{max}}^{\prime} - v\_{O^{min}}^{\prime}} = \frac{\left(v\_O^{\prime} - V\_{ref} + \frac{V\_{nump,p}}{2}\right)}{V\_{nump,pp}} = \frac{\left(v\_O^{\prime} - V\_{ref}\right)}{V\_{nump,pp}} + \frac{1}{2} \tag{10}$$

Combining (9) and (10) yields

$$Duty\_{(VFB)} = \frac{ADC\_{VFB}}{ADC\_{full scale}} = \frac{\left(v\_O' - V\_{ref}\right)}{V\_{nump\,pp}} + \frac{1}{2} \tag{11}$$

 *f* −

2

Taking the output voltage divider transfer function into account, (11) can be rewritten to be

2 *O* =

$$Duty\_{(VFB)} = \frac{ADC\_{VFB}}{ADC\_{full scale}} = \frac{\left(V\_O \times G\_{fb} - V\_{ref}\right)}{V\_{nump,pp}} + \frac{1}{2} \tag{12}$$

Substituting *Vramp*\_*pp*\_*min* shown in (8) into (12) yields

*O* =

 *f*

$$Duty\_{(VFB)} = \frac{ADC\_{VFB}}{ADC\_{full scale}} = \frac{\left(V\_O \times G\_{fb} - V\_{ref}\right)}{V\_{ramp\,pp\,-min}} + \frac{1}{2} = \frac{\left(V\_O \times G\_{fb} - V\_{ref}\right)}{\left(\frac{I\_{pump} \times T\_s}{C\_{pump}}\right)} + \frac{1}{2} \tag{13}$$

#### **7. Gain Analysis of Digital Compensator**

Figure 7 shows the block diagram of the PID compensator. Inside this compensator, there is one rounded number block, one anti-saturation block, and one right z shift block beside the PID calculation.

**Figure 7.** Proportional–integral–derivative (PID) compensator block diagram.

#### *7.1. PID Calculation*

The proportional gain *Kp*, the integral gain *Ki,* and the derivative gain *Kd* all have the data register form. This form implies an n-bit integer and an m-bit decimal fraction. For example, if *n* = 5, *m* = 3 and *Kp* = 1, then the corresponding digital value is "00001.000". If the bus width of e[*n*] is (*x*) and the bus widths of *Kp*, *Ki,* and *Kd* are all the same (*n.m*), then after PID calculation, the corresponding bus width is (*x* + *n.m*).

#### *7.2. Rounded Number Block*

The decimal bits are removed without any conditions, but there is no change of LSB gain, implying that the corresponding output bus width is still (*x* + *n.m*).

#### *7.3. Anti-Saturation Block*

This block is used as a protection of the arithmetic overflow of the register. There is no change of LSB gain and the corresponding output bus width is (2 + *x* + *n*).

#### *7.4. Right z-Bit Shift Block*

As the division is operated, redundant bits are removed. This is because the DPWM does not need so many bits. The right shift number is expressed by the symbol z. For each shift, the corresponding LSB gain is divided by two. The output bus width of this block is (y-z) and the corresponding LSB gain is 2-z.

Accordingly, if *Kp* = 2 and *z* = 1, then the total LSB gain is one. If *Kp* = 4 and *z* = 0, then the total LSB gain is four. The LSB gain of the PID calculation is determined by the minimum value of {*Kp*, *Ki*, *Kd*}. For example, if *Kp* = 2, *Ki* = 0.01 and *Kd* = 3, then the LSB gain of the PID block is two. This is because the decimal fraction, created from the integrator, will be removed directly.

#### **8. PWFM Control Concept**

The PWFM strategy, combining the pulse width modulation (PWM) and the pulse frequency modulation (PFM), can improve 1-bit resolution. This strategy does not need to change the original control structure and circuit. In the following, one example, together with Table 1, is given. The first two columns are associated with traditional duty cycles and periods, respectively. There are three cases with duty cycles of 30%, 50%, and 80%. According to the traditional PWM, the jumping interval is about 0.195%. The last two columns are associated with the proposed duty cycles and periods, respectively. Under the condition of the period of 512 clocks (CLK), both the corresponding duty cycle for the PWM and PFWM are the same, whereas, under the condition of the period of 511 CLK, the corresponding duty cycle for the PFWM is larger than that for the previous PWM but smaller than that for the next PWM. By doing so, the resolution of the DPWM strategy is larger than that of the PWM strategy. In other words, a higher resolution can be achieved and expressed by (*n* + 0.5) CLK, which is different from the PWM strategy with a resolution expressed by *n* CLK. From Table 1, it can be seen that there are no errors in the duty cycle of around 50%, but there are some errors in the duty cycle of 30% and 80%. Whether these errors are useful or not depends on actual applications. For an example of a buck converter, it normally works with the duty cycle locating between 15% and 85%, so a little large error in duty cycle calculation is OK. Furthermore, the extreme duty cycle is used in a large transient response so the duty cycle linearity is not so important. From Figure 8, both the curves of duty cycle versus control force for the PWFM and PWM are almost the same. In Figure 9, it shows that the errors in the duty cycle locating between zero and 100%, where not all points have errors. For *n* CLK, there are no errors in duty cycle calculation if *n* CLK is activated, whereas, for (*n* + 0.5) CLK, there are some errors in duty cycle calculation if (*n* + 0.5) CLK is activated. From Figure 9, it can be seen that the maximum error is within 0.1%, showing that the proposed strategy possesses industrial applications to some extent.


**Table 1.** Duty cycle comparison between (PWM) and pulse width and frequency modulation (PWFM).

**Figure 8.** Curves of duty cycle versus control force for the PWFM and PWM strategies.

**Figure 9.** Curves of duty cycle error versus control force for the PWFM strategy.

#### **9. PWFM Procedure**

Figures 10 and 11 show the program flow charts for the traditional PWM strategy and the proposed PWFM strategy, respectively. From Figure 10, since the traditional 9-bit PWM has a period of 512 CLK, the 11-bit control force will be saved in a register with the last two bits cut <sup>o</sup>ff. At the same time, there is an up counter to be activated as PWM is equal to one, counting from zero. As soon as the counter value is equal to the duty cycle value, this counter will be set to zero. As for the PWFM shown in Figure 11, the 11-bit control force will be saved in a register with the last bit cut <sup>o</sup>ff. The first nine bits are integral values, similar to 9-bit PWM but the last bit is not an integral value, called 0.1bit, which will be finely modulated according to the PFM. The first nine bits will be put into a register and compared with the value of the up counter, and at the same time, the last bit will be checked. If the 0.1bit is equal to one, the accompanying period is 511 CLK, leading to the resolution of (*n* + 0.5); otherwise, the integral bit information is obtained and the duty cycle is 512 CLK.

**Figure 10.** Program flow chart for the traditional PWM strategy.

**Figure 11.** Program flow chart for the proposed PWFM strategy.

#### **10. Experimental Results**

Prior to this section, some specifications for a buck converter are given as follows: (i) The input voltage is 12 V; (ii) The output voltage is 5 V; (iii) The rated output current is 8 A; (iv) The switching frequency is 195 kHz; (v) The ADC is 9-bit with a peak-to-peak voltage of 1.7 V; (vi) The PWM is 9-bit and PWFM is 9-bit plus 1-bit; (vii) The value of the output inductor is 5 μH; (viii) The output capacitor is constructed by two 470 μF electrolytic capacitors and two 10 μF multilayer ceramic capacitors (MLCC), with all capacitors paralleled together; (x) The part names of the main switch Q1 and synchronous rectifier Q2 are the same, called IRL8113; (xi) The FPGA, belonging to Altera Cyclone 3 with operating clock of 100 MHz, has the part name of EP34C5T44.

Figures 12 and 13 show the waveforms relevant to the traditional PWM control strategy and the proposed PWFM control strategy under different loads, respectively. The controller is not well designed herein. The purpose of the controller is to show the limit cycle oscillation under the traditional PWM control strategy. Therefore, the transient part is not so important. As for the proportional gain *kp*, it may affect the experimental results but may not be needed. As for the integral gain *ki*, it must be needed to make the DC output voltage stable at a given value. In the following experiments, the value of *ki* is 0.0625. From Figures 14 and 15, the limit cycle oscillation is removed, and the transient parts are almost the same as those shown in Figures 12 and 13. The features of the proposed PWFM control strategy are the same as those of the traditional PWM control strategy except that both the resolutions are different. Figures 16–19 show the zoom-in waveforms for Figures 12–15, respectively. From these figures, it can be seen that due to the switching frequency, the output voltages have high-frequency ripples, and the inductor currents also have high-frequency ripples.

**Figure 12.** Waveforms based on the traditional PWM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 25% to 75%; (**b**) from 75% to 25%.

**Figure 13.** Waveforms based on the traditional PWM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 50% to 100%; (**b**) from 100% to 50%.

**Figure 14.** Waveforms based on the proposed PWFM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 25% to 75%; (**b**) from 75% to 25%.

**Figure 15.** Waveforms based on the proposed PWFM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 50% to 100%; (**b**) from 100% to 50%.

**Figure 16.** Zoom-in waveforms based on the traditional PWM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 25% to 75%; (**b**) from 75% to 25%.

**Figure 17.** Zoom-in waveforms based on the traditional PWM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 50% to 100%; (**b**) from 100% to 50%.

**Figure 18.** Zoom-in waveforms based on the proposed PWFM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 25% to 75%; (**b**) from 75% to 25%.

**Figure 19.** Zoom-in waveforms based on the proposed PWFM control strategy: (1) load enable; (2) AC output voltage; (3) inductor current, due to (**a**) from 50% to 100%; (**b**) from 100% to 50%.
