**2. Device Structure**

The 2D schematic cross-sections of the DR-MESFET and PLDC-MESFET structures are shown in Figure 1a,b, respectively. The difference between the two devices is that the PLDC-MESFET has a partially low doped channel under the gate. The PLDC was realized by high-energy ion implantation and high-temperature annealing processes. It should be noted that the P-type impurity is implanted to compensate for the formation of lightly doped regions [13]. The thickness and the concentration of the PLDC are denoted as *H* and *N*PLDC, respectively. The *N*PLDC was set to 1 × 10<sup>17</sup> cm<sup>−</sup>3, 1 × 10<sup>16</sup> cm<sup>−</sup><sup>3</sup> and 1 × 10<sup>15</sup> cm<sup>−</sup>3. The *H* was set from 0 to 0.25 μm in a step of 0.05 μm.

**Figure 1.** Schematic cross-sections of the (**a**) DR 4H-SiC MESFET, (**b**) partially low doped channel (PLDC) 4H-SiC MESFET.

The main physics models were applied in ISE-TCAD tools simulation [14], including Mobility (Doping Dep, HighFieldSat Enormal), Effective Intrinsic Density (Band Gap Narrowing (OldSlotboom), Incomplete Ionization, Recombination (SRH (Doping Dep) and Auger Avalanche (Eparallel). The criterion of breakdown was Break Criteria {Current (Contact = "gate" Absval = 1e3)}. The main solving model was Coupled {Poisson Electron Hole}. Mobility models were used to solve the phenomenon of the mobility of carriers being degraded by many factors. Recombination models were used to calculating the lifetime of carriers. The Effective Intrinsic Density model was used to calculate the effective band gap. Incomplete Ionization must be considered, as this occurs in the case of aluminum acceptors in silicon carbide. The temperature of the simulations was 300 K. The major parameters of the device measured were saturation current (*I*d), threshold voltage (*V*t), gate–source capacitance (*C*gs) and transconductance (*g*m). Those parameters are used in ADS to modify the EE\_FET3 model. The modified EE\_FET3 model and "Load-Pull PAE, Output Power Contours" model [15] were used to measure the PAE of the device under the same bias conditions. The working bias conditions were set as follows: *<sup>V</sup>*gs was −8.0 V, *V*ds was 28 V, RF was 850 MHz and Pavs\_dBm was 28 dBm. Keeping the bias condition and changing the parameters obtained from ISE-TCAD, the PAE of the device under different thicknesses and doping concentrations can be calculated as follows [16].

$$\eta(\text{PAE}) = \frac{P\_{\text{out}} - P\_{\text{in}}}{P\_{\text{dc}}} \tag{1}$$

where *P*out is output power, *P*in is input power and *P*dc is DC power.

#### **3. Results and Discussion**

#### *3.1. The E*ff*ect of Doping Concentration and Thickness On the Device Parameters*

As showing in Figure 2, the parameters of the device are greatly a ffected by the doping concentration (*N*PLDC) and thickness ( *H*) of the PLDC. The e ffect of *N*PLDC and *H* on *V*t is shown in Figure 2a. With the decrease of *N*PLDC, the absolute value of *V*t decreases obviously. When *H* increases, the *V*t overall trend is also decreasing. This is because the changes in *N*PLDC and *H* directly control the total carrier concentration in the channel, and *V*t is proportional to the total carrier. Figure 2b shows the e ffects of *N*PLDC and *H* on *<sup>C</sup>*gs. With the decrease of *N*PLDC and the increase of *H*, *<sup>C</sup>*gs decreases. On the one hand, the PLDC suppresses the under-gate depletion layer extending to the source side, and on the other hand, it reduces the total number of carriers in the channel, thereby reducing the input capacitance of the device. In the Figure 2c, *g*m increases first and then decreases. The reason for this formation may be that the thinner low doped layer can increase the gate's ability to control the current by inhibiting the di ffusion of the depletion layer to some extent. When *H* is thick enough, the ability of the gate to control the current will be reduced. So, *g*m decreases. In Figure 2d, *I*dsat is roughly decreased as *H* increases and *N*PLDC decreases. This is mainly caused by the decrease of the channel carrier concentration. When *H* is 0.25 μm, the parameters exhibit a sharp decrease and the DC characteristic of the device becomes poor. It is indicated by the simulation results that the PLDC-MESFET has smaller values of *<sup>C</sup>*gs, *g*m, *V*t and *I*dsat as compared to those of the original device.

**Figure 2.** The effect of *N*PLDC and *H* on the device parameters: (**a**) *V*t-*N*PLDC and *H*, (**b**) *<sup>C</sup>*gs-*N*PLDC and *H*, (**c**) *g*m-*N*PLDC and *H*, (**d**) *I*dsat-*N*PLDC and *H*.

#### *3.2. The Influences of Doping Concentration and Thickness on the PAE*

The influences of the doping concentration and thickness on the PAE are shown in Figure 3. It can be seen that when *H* is smaller than 0.20 μm, the PAE of the device increases with the decrease of *N*PLDC. When *H* is 0.20 μm and *N*PLDC is 1 × 10<sup>15</sup> cm<sup>−</sup><sup>3</sup> or 1 × 10<sup>16</sup> cm<sup>−</sup>3, the PAE of the device decreases sharply. When *H* is 0.20 μm and *N*PLDC is 1 × 10<sup>17</sup> cm<sup>−</sup>3, the PAE of the device increases. When *H* is 0.25 μm, the simulation results show that the DC characteristics and AC characteristics of the device are poor, and the PAE of these structures is low. The maximum value of the PAE is obtained when the *N*PLDC is 1 × 10<sup>15</sup> cm<sup>−</sup>3, the *H* is 0.15 μm. The PAE of the new device is 43.67% while the PAE of the original device is 23.43%. The optimized PAE is increased by 86.38%. The PAE of the IUU-MESFET and DRBL AlGaN/GaN HEMT increase 18% and 48%, respectively. So, the PLDC has a grea<sup>t</sup> effect on improving the PAE of the device. In the paper *107 W CW SiC MESFET with 48.1% PAE,* the experimental PAE of the device at 2 W (33 dBm) is close to 25% [17]. The PAE of the DR-MESFET is 23.43% at 0.63 W (28 dBm). This is essentially consistent with the simulation results. 1017

**Figure 3.** The effects of *NPLDC* and *H* on the PAE.
