**2. Experiment background**

#### *2.1. Introduction of the Developed SiC Power Module*

The structure design of the 1200V/200A full-SiC power module with standard package outline is shown in Figure 1a. The diameter of gate wire is 8 mil while other wires inside power module are 14 mil. The footprint of DBC is 34 mm × 25 mm, and the thickness of upper copper, AlN ceramic, and lower copper are 0.3 mm, 0.63 mm, and 0.3 mm, respectively.

The power module has a half-bridge structure topology as shown in Figure 1b, there are four SiC-MOSFET dies (CPM2-1200-0025B, Cree, Inc., Durham, NC, USA) in parallel connection and four SiC-SBD dies (CPW5-1200-Z050B, Cree, Inc., Durham, NC, USA) anti-paralleled with SiC-MOSFETs within each leg of power module.

This high-power high-frequency SiC power module is developed for the boost converter for hybrid electric vehicles. With an increased switching frequency, the volume of inductor in the boost converter can be reduced, which is desirable for downsizing the power control unit for hybrid electric vehicles. In order to acquire an optimized switching performance in high-power high-frequency application, the design of the power module is optimized from two aspects: One is the symmetry of the structure, the other is the common source inductance.

**Figure 1.** The structure design of the developed 1200V/200A full-SiC power module: (**a**) Design structure; (**b**) circuit topology.

For the symmetry design, the two parallel-connected DBCs (direct bonding copper) for both upper-side and lower-side are symmetrical, the two parallel-connected pair of SiC-MOSFET and anti-parallel SiC-SBDs for both upper-side and lower-side are also symmetrical. The symmetry of the gate loops between the parallel chips is realized by placing the gate and source routings of the lower-side near the central line of the module as shown in Figure 2a. When compared to some commercial power module (Figure 2b) where the gate and source routings of the lower-side are placed to one side of the power module, our design has an enhanced symmetry for the gate-source routings of the parallel-connected chips. On the other hand, the parasitic inductance of the gate-source loop of our design is also reduced.

(**a**) (**b**) 

**Figure 2.** Comparison of common source paths inside the developed SiC power module with the commercial one. (**a**) Developed module in this work (design structure), (**b**) commercial module (physical structure).

The common source inductance is the parasitic inductance of the common source path of drain routing and gate driver routing inside the power module. Due to its negative feedback effect, a large common source inductance can suppress the change of *vgs* and slow down the drain current slew rate, which results in a significant increase of switching loss and a decrease of switching frequency [6,24,30–33]. This means that reducing common source inductance must be considered to speed up the switching of the power module.

In order to minimize the common source inductance, the gate-source routing and drain-source routing are separated in our design, as shown in Figure 2a, where the red lines and green lines stand for the gate driver routing inside the power module for upper-side and lower-side, respectively. The drain routing inside the power module for upper-side starts from DC+ terminal, then goes through MOSFET chips, and crosses SBD chips by wire and copper bridge, and finally goes to AC terminal. For lower-side, the drain routing starts from AC terminal, then goes through MOSFET chips, and crosses SBD chips by wire, and finally goes to DC- terminal (see Figure 2a). There is no common path between the gate-source and drain-source routings inside our power module except the power chips themselves, this means that the common source inductance is minimized in our power module. Thus, switching power loss can be reduced and switching speed can be increased.

#### *2.2. Introduction of Double Pulse Testing Platform*

The clamped inductive double-pulse test rig is shown in Figure 3a. The DUT is the developed 1200V/200A full-SiC power module. The electrolytic capacitor of FG810K901-1 from VDTCAP (Shenzhen, China) is used as the DC bus capacitor. Two capacitors from KEMET (Fort Lauderdale, FL, USA) is used as decoupling capacitor. Two serial-connected self-fabricated inductors are used as load inductor with a total inductance of 160 μH. The voltage and current signals are acquired by a Teledyne Lecroy HDO6104 1GHz high definition oscilloscope (Teledyne LeCroy, Chestnut Ridge, New York, USA). A Rogowski current waveform transducer CWT miniHF 1B (Power Electronic Measurements Ltd (PEM), Nottingham, UK) with bandwidth 30 MHz is utilized to measure the drain current of the DUT. A passive voltage probe PP026-2 with bandwidth of 500 MHz and a high voltage di fferential probe HVD3106 with the bandwidth of 120 MHz from Teledyne Lecroy are used to obtain the waveforms of *vgs* and *vDS* of DUT respectively.

**Figure 3.** The clamped inductive load double pulse testing circuit platform: (**a**) Physical picture, (**b**) schematic diagram of circuit.

The values of the components in the testing rig are listed in Table 1. Figure 3b shows the schematic diagram of the testing circuit. The output resistance of the gate driver circuit, *RS*, is 0.6 Ω. The gate-source voltage is −2.3 V and 17.5 V for turning o ff and turning on switches, respectively.


**Table 1.** The circuit parameters of components of the testing rig.

#### *2.3. Turn-on Switching Process of SiC Power Module*

The typical turn-on switching transient of SiC power module can be divided by four intervals as shown in Figure 4.

**Figure 4.** Typical diagram of turn-on switching transient for SiC power module.

• Interval 1: From *t*0 to *t*1

The yellow region from *t*0 to *t*1 is the turn-on delay interval, τ*D* (on). In this interval the gate voltage charges up the input capacitance of SiC-MOSFETs, the *iDS* keeps the off-state value until the *vgs* reaches the threshold voltage, the *vDS* reduces 10% ×*VDD* when approaching the end of this period.

• Interval 2: From *t*1 to *t*2

The green region from *t*1 to *t*2 is the turn-on interval 1, τ1 (on). In this interval, the gate voltage continues to charge up the input capacitor of SiC-MOSFETs, the *vDS* continues to reduce while the *iDS* rose to *Io* at the end of this period.

• Interval 3: From *t*2 to *t*3

The red region from *t*2 to *t*3 is the turn-on interval 2, τ2 (on). During the τ2 (on), the gate voltage continues to charge up the input capacitor of SiC-MOSFETs, the *iDS* continues to change, and the *vDS* reduces to *VDS*(*on*) with a higher *dvDS*/*dt* in this period. The anti-parallel SiC-SBDs begin to regain reverse blocking capability, the rise in voltage across the anti-parallel SiC-SBD causes the SiC-MOSFET voltage to fall rapidly.

• Interval 4: From *t*3 to *t*4

The gray region from *t*3 to *t*4 is used to indicate that the power module is fully turned on, and the time *t*4 is at any moment after *t*3 during turn-on interval. During the fully turn-on interval, all *vgs*, *vDS*, *iDS* characteristics are kept in oscillation state with their respective frequencies which are determined by the parasitic parameters in the circuit. Due to the different parasitic parameters in drain circuit and gate driver loop, the oscillation frequency of *vgs* was different from that of *vDS* and *iDS*.

During the period from *t*1 to *t*3, the increasing drain current *iDS* makes *vDS* fall. When *iDS* is less than *IO* the freewheeling diodes are forced to conduct current. If the slew rate of *vDS* is too high before *iDS* rising to *Io*, the *vDS* will be limited to a voltage platform. This means the slew rate of *vDS* is not too high in this sub-interval of τ1 (on). When *iDS* is increased to be higher than *IO*, the rise in blocking voltage across the anti-parallel SiC-SBD causes the SiC-MOSFET voltage to fall rapidly. This means the slew rate of *vDS* will be higher in this sub-interval of τ2 (on). Considering the coupling effect of gate-drain capacitor *Cgd* of SiC-MOSFETs inside the power module, the waveform of *vgs* is affected by the d*vDS*/*dt* of drain loop in this period. Meanwhile, the d*vDS*/*dt* of drain circuit has greater impacts on the waveform of *vgs* of gate driver loop during turn-on interval τ2 (on) rather than τ1 (on). It will be discussed in the following section.

#### **3. Experimental Results and Comparison**

In order to confirm whether our design can reduce the switching time of the power module, our module and one commercial SiC power module (Figure 2b) were tested based on the built double pulse test platform and gate driver circuit. Their transient waveforms are compared in Figure 5.

**Figure 5.** Comparison of transient waveforms between the module developed in this work and one commercial SiC power module (*VDD* = 400 V, *IO* = 200 A). (**a**) Developed SiC power module in this work; (**b**) commercial SiC power module.

As shown in Figure 5, with the same gate driver and double pulse testing platform, the turn-on process of the developed SiC power module was faster than that of the commercial SiC power module. The turn-on times of these two SiC power modules are listed in Table 2. The total turn-on time of the developed module was 110 ns for the upper-side and 117.6 ns for the lower-side. When compared to that of the commercial module, the turn-on time was reduced by 56.4% and 52.0% for the upper-side and lower-side, respectively. Thus, the developed power module is suitable for high frequency application. However, when the turn-on process of the developed power module was speeded up, a severe oscillation and negative voltage spike was observed from the *vgs* waveforms during the turn-on transient even though the common source inductance was minimized. Therefore, to optimize the high-power high-frequency SiC power module, it is necessary to study the *vgs* characteristic and find proper designs to address the oscillation and negative voltage spike issues.


**Table 2.** Comparison of turn-on time for SiC power module.

First of all, the factors that take effects on the *vgs* characteristic will be discussed in the following. It is well known that the increased *VDD* and *IO* affects the slew rate of *vDS*. Due to the coupling effects of the drain-gate capacitors, the *vgs* characteristic will change along with the rise of *VDD* and *IO*. In order to investigate thoroughly the influences of *VDD* and *IO* (i.e., output power) on *vgs* characteristics at turn-on transient for the developed high frequency SiC power module, and clarify the difference between the *vgs* characteristics of upper-side and lower-side of the SiC power module, some experiments were conducted. The conditions of these experiments are listed in Table 3. As shown in Table 3, the output power of SiC power module in experiment is increased gradually from case\_1 to case\_3.


**Table 3.** *VDD* and *IO* parameters for the three cases.

In the experiment of case\_1, the switching waveforms of *vgs* were almost normal for both upper-side and lower-side though there was minor di fference between them as shown in Figure 6. The *vgs* of upper-side was pulled down by 12.76 V during the <sup>τ</sup>2(*on*) interval (as shown in Figure 4) while the lower-side's was pulled down by 8.8 V during the <sup>τ</sup>1(*on*) interval. The *vgs* spikes for both sides were kept positive during the turn-on transient, negative *vgs* spike was absent from the waveforms for both upper-side and lower-side of the SiC power module.

**Figure 6.** Turn-on transient waveform of case\_1.

As output power of the power module rose, the *vgs* spike started to show di fferent characteristics between the upper-side and lower-side. As shown in Figure 7, the *vgs* spike of the upper-side was pulled down to an excessively negative voltage (−9.94 V) and accompanied by a significant oscillation with 83.3 MHz frequency during the τ2 (on) interval. On the other hand, the *vgs* spike of the lower-side was only pulled down to a negative voltage slightly, and no oscillation was observed from the waveform.

**Figure 7.** Turn-on transient waveform of case\_2.

As we all know, the oscillation is typically a high frequency signal which put stringent requirements on the bandwidth of probes and the contact quality. In our testing experiment, the bandwidth of the voltage probe was 500 MHz, which is five times the oscillation frequency (83.3 MHz); it is also far greater than the minimum bandwidth requirement for fetching this kind of waveform. In order to eliminate the suspicion that the oscillation was a false waveform, we re-examined and adjusted the connection and contact between the oscilloscope probe and the test point, finding out that oscillation still exists.

For the experiment of case\_3, the transient waveforms are shown in Figure 8. The *vgs* spike of the upper-side oscillated more seriously than case\_1 and case\_2. Both the excessively positive and negative voltage spikes were observed from *vgs* characteristics of the upper-side, which resulted from the serious oscillation. On the other hand, the *vgs* of the lower-side was pulled down to a lower negative voltage (−13.7 V), and no oscillation was observed from the waveform.

 **Figure 8.** Turn-on transient waveform of case\_3.

From the experimental results, it is found that the increase of output power of the SiC power module amplifies the difference of *vgs* characteristics between upper-side and lower-side. When the output power is relatively low, such as that in case\_1, no negative *vgs* spike appeared; the characteristics of *vgs* in upper-side are almost the same as that of lower-side. As the output power rises, the negative voltage spike issue of *vgs* becomes more serious. On the other hand, the difference between the *vgs* characteristics of the upper-side and lower-side appears. Firstly, the pulling down process of *vgs* for the upper-side is occurred in the <sup>τ</sup>2(*on*) interval or the whole period of *vDS* falling, while that of the lower-side always appears in <sup>τ</sup>1(*on*) interval. Secondly, the process of *vgs* pulling down for the upper-side is superimposed by a high frequency oscillation while the lower-side's is absent from oscillation. Thirdly, the oscillation becomes more serious in upper-side and the negative *vgs* spike becomes lower in lower-side with an increasing output power (from case\_1 to case\_3).

The turn-on transient waveforms of *vgs* under different output power conditions are compared in Figure 9, where Figure 9a shows the results of the upper-side and Figure 9b shows the results of the lower-side. The detailed information related to the *vgs* pulling down process are extracted from Figure 9 and summarized in Table 4, such as amplitude of oscillation, voltage of *vgs* starts to pull down, the lowest *vgs* spike and the pull-down amplitude.

**Figure 9.** Comparison of turn-on transient waveform of *vgs* under different output power conditions: (**a**) Turn-on *vgs* of the upper-side; (**b**) turn-on *vgs* of the lower-side.


**Table 4.** Comparison of trainset waveform of *vgs* at turn-on transient.

As shown in Table 4, with an increased output power, the lowest *vgs* spike continues to decrease, and the amplitude of the *vgs* pulling down rises significantly for the lower-side. On the other hand, for the upper-side, the pulling down amplitude of *vgs* in case\_3 is smaller than that of case\_2. This is because the oscillation of *vgs* in case\_3 is more serious than that of case\_2 and the highest *vgs* spike is up to 29.0 V. These differences of the *vgs* characteristics between the upper-side and the lower-side is probably attributed to the different *dvDS*/*dt* of drain loop for the upper-side and lower-side.

As analyzed in reference [26], the parameters such as gate resistance, gate loop inductance, input capacitance *Ciss*, and positive gate-source voltage *Vgs* take effects on the *vgs* characteristics. In our experiment, the gate driver and testing circuit are the same. This means that the different characteristics of *vgs* spike between the upper-side and lower-side could be correlated to the different gate-source paths and coupling effects of the d*vDS*/*dt* from drain loop to the gate driver loop in the SiC power module.

Meanwhile, we must notice the load current and bus voltage (output power) will influence the switching performance [25]. In other words, even for the same power device, coupling effects between drain loop and gate driver loop by *dvDS*/*dt* could be different under different operation conditions. Namely, the different slew rate of *vDS* during the turn-on transient could bring different extent of coupling influence.

From the experimental results in Figures 6–8, the slew rates of *vDS* at turn-on switching transient can be extracted. The experimental results of *dvDS*/*dt* are summarized in Table 5. It is shown that the slew rate of *vDS* of the upper-side is slightly larger than that of the lower-side, which means the coupling effect of drain loop to gate loop in the upper-side is more significant than that of the lower-side during turn-on transient.


**Table 5.** Comparison of *dvDS*/*dt* between upper and lower sides.

#### **4. Modeling and Simulation**

#### *4.1. Equivalent Model of Gate-Source Path of SiC Power Module*

The equivalent circuit model of the gate loop is obtained based on the analysis of the actual physical structure of the power module and the output stage of the gate driver circuit. For the standard package outline of the half-bridge module, the internal structure of the upper-side is di fferent from that of the lower-side. The routings of drain circuit and gate circuit inside the power module are shown in Figure 10a,b, respectively. Since all the gate input terminals are placed to the outer edge area of the upper-side of the power module, the gate routings of the lower-side must pass through the upper-side before connecting to the power chips of the lower-side.

**Figure 10.** Circuit routings inside the power module (red lines for upper-side; green line for lower-side). (**a**) Drain circuit routings, (**b**) gate loop routings.

Compared with gate-source path of the upper-side, the gate-source path of the lower-side is much longer, the input signal must pass through the whole power module before connecting to the power chips (see Figure 2a, Figure 10). As a result, the location of the lumped parasitic inductance of the gate loop in upper-side is di fferent from that of lower-side in our equivalent circuit models at turn-on transient. That is to say, the topology of the equivalent circuit model of the gate driver loop is di fferent between upper-side and lower-side for the developed half-bridge module.

In the previous analysis of the experimental results, we found that the output power of power module a ffects the characteristics of *vgs*. As the common source inductance is minimized in our design, the e ffect of common source inductance on turn-on transient can be ignored. We put emphasis on the coupling e ffect of drain circuit to gate driver loop, and it will be discussed in the following.

Based on the internal structure of the power module in Figure 10, the equivalent RLC circuit models of the gate driver loop in turn-on transient for the upper-side and lower-side are established

and shown in Figure 11a, b, respectively. The coupling effect is equivalent to a short-time current source. As this short-time current source is an external factor for the gate driver loop, it is parallel-connected to the equivalent circuit in the model. With the help of the models, *vgs* characteristics at the turn-on transient can be simulated.

**Figure 11.** The equivalent circuit models of gate loop path at turn-on transient: (**a**) Upper-side, (**b**) lower-side.

In Figure 11, *Lg* stands for the total stray inductance of gate driver loop, it includes the gate-source routings inside module, *Lgs*, and the stray inductance of output paths of gate driver circuit, *Ls*, which can be expressed by Equation (1),

$$L\_{\mathbb{X}} = L\_{\mathbb{X}^\sf s} + L\_{\mathbb{S}} \tag{1}$$

The *Rdriver* is the resistance of the whole gate driver loop, it includes the stray resistance of gate-source routings, *Rgs*, the external gate resistance *Rgext* and internal resistance of SiC-MOSFET, *Rgint*, and the output resistance of gate driver circuit, *Rs*, which can be expressed by Equation (2),

$$R\_{driver} = R\_{\text{gs}} + R\_{\text{gext}} + R\_{\text{gint}} + R\_S \tag{2}$$

The *Cdriver* is the parasitic capacitance of the total routings of the gate driver loop. The parasitic parameters can be extracted by Q3D software and they are listed in Table 6.


**Table 6.** Parasitic parameters extracted by Q3D software.

The value of the equivalent current source stands for the extent of this influence, which is designated as *iD*→*G*. The higher the slew rate of *vDS*, the higher the *iD*→*G*. The *iD*→*<sup>G</sup>* is given by Equation (3),

$$i\_{D \to G} = C\_{\mathbb{S}^d} \frac{dv\_{DS}}{dt} \tag{3}$$

The value of *iD*→*<sup>G</sup>* is determined by *Cgd* and *dvDS dt* . The capacitance *Cgd* of power chips increases sharply as the voltage *vDS* decreases at the turn-on transient, and the value of *iD*→*<sup>G</sup>* is also increased. Therefore, the coupling effect between the drain loop and gate driver loop is enhanced significantly due to the sharply rising *Cgd* at turn-on transient.

If the increase in output power is equivalent to a rise of *dvDS dt* , *iD*→*<sup>G</sup>* is getting higher at an increased output power. Thus, the current *iD*→*<sup>G</sup>* can reflect the extent of influence of output power on gate driver loop in our equivalent circuit model. The equivalent current *iD*→*<sup>G</sup>* at the turn-on transient for the experiment can be calculated by Equation (3) and they are summarized in Table 5.

Based on the RLC circuit model, the extracted parameters of the power module and gate driver circuit, as well as the calculated *iD*→*<sup>G</sup>* from the experimental results, the generation mechanism of the characteristics of *vgs* voltage spike for full-SiC power module at turn-on transient can be studied quantitatively by LTspice software. The respective values of *iD*→*<sup>G</sup>* for case\_1, case\_2, and case\_3 in simulation are the same with those in experiment (Table 5), while the values of the parasitic parameters used in simulation are from Table 6.

For the upper-side, *Vgs* is set to 15 V, the current source *iD*→*<sup>G</sup>* starts to output pulse at time of 5 ns and it lasts a time interval of 7 ns in the simulation, the value of *iD*→*<sup>G</sup>* is as listed in Table 5. The simulation results for the three cases as studied by the experiments in Section 3 are shown in Figure 12.

**Figure 12.** Simulation results of *v gs* voltage spike for upper-side.

As the output power increases, the *iD*→*<sup>G</sup>* rises from 0.47 A to 1.85 A accordingly, the gate-source voltage minus the DC voltage bias (*v gs*) is pulled down to a lower value. At the meantime, the gate source voltage is accompanied with a high frequency oscillation. The oscillation frequency is 83.3 MHz, which is the same as that of the experimental results. The oscillation frequency doesn't vary with the *iD*→*<sup>G</sup>* values as it is only related to the parasitic parameters of both the gate driver circuit and gate-source routings inside the power module. When the equivalent current source starts to output pulse the *v gs* tumbles, and the *v gs* rebounds immediately when the current source output is terminated.

For the lower-side, the *Vgs* is set to 15 V, the equivalent current source of *iD*→*<sup>G</sup>* starts to output pulse at time of 6 ns and it lasts a time interval of 5 ns in the simulation. The simulation results for the three cases as studied by the experiments in Section 3 are shown in Figure 13. As the output power increases, the *iD*→*<sup>G</sup>* rises from 0.35 A to 1.34 A accordingly, *v gs* is pulled down to a lower value. There is no high frequency oscillation observed.

**Figure 13.** Simulation results of *v gs* voltage spike for lower-side.

The characteristics of *v gs* pulling down in simulation are compared with the experimental results (as shown in Figure 9). The amplitude of *vgs* pulling-down and oscillation for the upper-side and lower-side in di fferent cases are listed in Table 7. For the characteristics of high frequency oscillation, the simulation is in good agreemen<sup>t</sup> with the experimental results. For the characteristics of the pulling down amplitude of *vgs* spike, the simulation is almost in agreemen<sup>t</sup> with the experimental results except the upper-side.


**Table 7.** Comparison of characteristics for simulation and experimental results at turn-on transient.

The pulling down amplitude of *vgs* spike of the lower-side increases as the output power rises in both simulation and experiment, but the pulling down amplitude of *vgs* of the upper-side in simulation is di fferent from the experiment. In simulation, the pulling down amplitude of *vgs* rises as output increases, but in experimental results the largest pulling down amplitude of *vgs* occurred in case\_2 rather than case\_3. This abnormal phenomenon in the experiment is mainly attributed to the high frequency oscillation on the pulling down waveform of *vgs*. As shown in Figure 9a, there is an excessively positive voltage spike of 29.0 V in case\_3 during the high frequency oscillation process, while the high frequency oscillation doesn't bring the voltage spike back to a lower point as that in case\_2.

Overall, the characteristics of *vgs* spike in simulation almost coincide with that of the experiment results. This proves the rationality of our modeling and analysis about the generation mechanism of *vgs* voltage spike characteristics for SiC power module.

As depicted previously, the negative *vgs* voltage spike is correlated to the slew rate of *vDS* and the resistance of the gate driver loop. On one hand, the increased gate resistance can reduce *dvDS*/*dt*, and decrease the coupling between the drain loop and gate driver loop due to a lower *iD*→*<sup>G</sup>* at a slower slew rate of *vDS*. On the other hand, the larger the gate resistance of the gate driver loop, the smaller the gate current and voltage spike, and less serious the oscillation at turn-on switching transient. Although the coupling e ffects are di fferent between the upper-side and lower-side, both the negative *vgs* spike and high frequency oscillation could shrink as the resistance of the gate driver circuit rises. Another experiment and simulation with a higher external gate resistance are carried out to further verify our RLC circuit model and analysis.

#### *4.2. Verification for the Proposed RLC Circuit Model and Analysis*

A resistor of 5 Ω instead of the previous external gate resistor of 2.4 Ω is used in the new experiment. The case\_3 is selected for the case study as the output power is highest and the negative spike/oscillation is the most significant in this case. The experimental results are shown in Figure 14.

**Figure 14.** Transient waveform at the condition for output power of case\_3 and the external gate resistor equal to 5 Ω: (**a**) Upper-side, (**b**) lower-side.

There is neither voltage pulling down nor high frequency oscillation observed for the upper-side (Figure 14a), but a pulling down e ffect and a spike of *vgs* is observed for the lower-side (Figure 14b). When the external gate resistance is increased from 2.4 Ω to 5 Ω, the negative spike of *vgs* in lower-side is decreased from −13.7 V (in Figure 8 and Table 4) to −2.5 V (Figure 14b). Accordingly, the amplitude of *vgs* pulling down is reduced from 28.66 V (in Figure 8 and Table 4) to 10.28 V (Figure 14b).

The experimental results show that the relatively larger external gate resistor can damp the high frequency oscillation in the upper-side and weaken the amplitude of pulling down of *vgs* at turn-on transient in SiC power module.

The slew rate of *vDS* at the turn-on transient are extracted from the experiments and listed in Table 8. The introduced extra current of *iD*→*<sup>G</sup>* is calculated with Equation (3) and listed in Table 8 as well.


**Table 8.** Comparison of *dvDS*/*dt* between the cases with external gate resistance of 5 Ω and 2.4 Ω.

Compared with that of 2.4 Ω, the slew rate of *vDS* in the condition of gate resistor of 5 Ω reduces significantly; accordingly, the equivalent current *iD*→*<sup>G</sup>* from drain loop to gate driver loop due to the coupling e ffect at the turn-on transient also decreases dramatically.

With the proposed equivalent RLC circuit models shown in Figure 11 and Equations (1)–(3), simulation study with an external gate resistor of 5 Ω is carried out. In this simulation all the parameters are the same as that of the previous simulation except the gate resistance. The simulation results under di fferent external gate resistance conditions are compared in Figure 15. For the upper-side, the high frequency oscillation is alleviated by the higher gate resistance (5 Ω vs. 2.4 Ω), and the amplitude of *vgs* tumbling is reduced from 25.24 V to 6.92 V (72.5% lower). For the lower-side, the amplitude of *vgs* tumbling is reduced by ~50% from 6.62 V to 3.25 V.

The characteristics from simulation results (in Figure 15) are extracted and compared with those from the experimental results in Figure 8, 14. The compared characteristics contains the amplitude of *vgs* pulling down and oscillation. The comparison results are listed in Table 9.

**Figure 15.** Simulation results of *vgs* voltage spike for *Rgext* = 5 Ω and *Rgext* = 2.4 Ω: (**a**) Upper-side, (**b**) lower-side.


**Table 9.** Comparison of *vgs* characteristics between experiment and simulation.

As the gate resistance rises, the characteristics of high frequency oscillation in the upper-side disappears for both experiment and simulation, the amplitude of the pulling down of *vgs* in the upper-side is lowered significantly for both experiment and simulation. The pulling down amplitude in the experiment reduces from 28.20 V to zero while it decreases from 25.24 V to 6.92 V in the simulation. The amplitude of the pulling down of *vgs* in the lower-side is also reduced significantly for both experiment and simulation, which reduces from 28.66 V to 10.28 V in the experiment and decreases from 6.62 V to 3.25 V in the simulation.

The specific amplitudes of the pulling down of *vgs* between the simulation and experiment are different, the error could come from the read of d*vDS*/*dt* and the parameter extraction by Q3D software. As shown in Table 9, the trend of changes in the amplitude of *vgs* pulling down and oscillation along with the increase of output power in simulation generally agrees with those of the experimental results. This further confirms the validity of the proposed equivalent RLC circuit model and the rationality of the analysis about the mechanisms behind the *vgs* characteristics at turn-on transient for the SiC half-bridge power module.

As guided by the proposed model, the gate driver design must be considered together with the power module design for obtaining an optimized switching performance for the high-power high-frequency SiC power module. For a fabricated power module, we can set the parameters in the model related to the gate driver circuit, such as the *LS* in Equation (1), the *Rgext* and *RS* in Equation (2). Then the *vgs* characteristic can be simulated and optimized by tuning the parameters. Thus, a proper design of the gate driver circuit matched with the power module design and output power level can be obtained in a short design cycle.
