**5. Conclusions**

In this paper, a 1200V/200A full-SiC half-bridge power module was fabricated for high-power high-frequency application. The power module is designed with a symmetrical structure and minimized common source inductance to pursue a faster switching. However, severe oscillation and negative voltage spike issues are observed from the *vgs* waveforms during the turn-on transient, especially at higher output power level.

The characteristics of *vgs* at turn-on transient under different output power were investigated and their comparison between the upper-side and lower-side was conducted. From experiments, the *vgs* characteristics show negative spike issue and it becomes severe under higher output power conditions. On the other hand, the upper-side and lower-side show different characteristics, namely, the *vgs* spike of upper-side is superimposed by a 83.3 MHz high frequency oscillation during the process of *vgs* being pulled down, while the *vgs* spike of lower-side contains no oscillation.

The mechanisms behind the influence of output power on the *vgs* characteristics and the difference of *vgs* characteristics between upper-side and lower-side were studied via modeling and simulation. Equivalent RLC circuit models were proposed and established for the gate driver loop based on the internal structure of the power module. In the models, the coupling effects between drain circuit and gate driver loop is considered and equalized by a current source (*iD*→*<sup>G</sup>*). The value of the equivalent current source is determined by gate-drain capacitance *Cgd* and *dvDS*/*dt*. As the increase of output power will contribute to a higher *dvDS*/*dt*, *iD*→*<sup>G</sup>* in the model is increased, i.e., the coupling effect between the drain circuit and gate driver loop is enhanced. Thus, the negative *vgs* spike issue becomes severe in higher output power conditions. On the other hand, when comparing the upper-side and lower-side, the models are different for them as the gate-source path routings are different. Thus, they show different *vgs* characteristics. And, the higher output power (higher *iD*→*<sup>G</sup>*) will enhance the difference.

With the help of the proposed models, *vgs* characteristics of the upper-side and lower-side were simulated and compared with the experimental results. The pulling down amplitude of *vgs* spike in the lower-side increases as the output power rises in both simulation and experiment, as well as the amplitude of the oscillation in the upper-side. Therefore, the trend of changes in the *vgs* characteristics along with the increasing output power from simulation are consistent with that of the experimental results.

In addition, different conditions of gate resistance for the SiC power module are compared. A higher gate resistance can reduce *dvDS*/*dt*, thus the *vgs* spike issue and oscillation can be alleviated. Based on the proposed models, the trend of changes in the *vgs* characteristics along with the increasing gate resistance can be simulated, and the results are shown to be consistent with that of the experimental results. This further confirms the validity of the proposed equivalent RLC circuit model and the rationality of the analysis about the mechanisms behind the *vgs* characteristics at turn-on transient for the SiC half-bridge power module. Based on the model, a proper design of the gate driver circuit matched with the power module design and output power level can be obtained in a short design cycle.

**Author Contributions:** Conceptualization, M.Z.; formal analysis, N.R.; funding acquisition, Q.G. and K.S.; project administration, Q.G.; resources, X.Z.; supervision, K.S.; validation, K.S.; writing—original draft, M.Z.; writing—review and editing, M.Z., N.R., J.Z. and K.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This study is supported by the State Key Laboratory of Advanced Power Transmission Technology (Grant No. GEIRI-SKL-2018-009) and National Key Research & Development Program of China (2018YFB0905700).

**Conflicts of Interest:** The authors declare no conflict of interest.
