*3.3. Mechanism Discussion*

Figure 4a,b shows the influence of the parameters on PAE at the same bias when *<sup>V</sup>*gs is −8.0 V, *V*ds is 28 V, RF is 850 MHz and Pavs\_dBm is 28 dBm. As shown in Figure 4a, the PAE increases with the increase of *V*t when *g*m is a constant. When *V*t is a constant, the PAE also increases with the increase of *g*m. When *g*m is between 40 and 60 mS, the PAE of the device has the biggest change. This can be observed by the distance between the two curves. Figure 4b shows the influence of *I*dsat and *<sup>C</sup>*gs on the PAE. With the increase of *<sup>C</sup>*gs, the PAE decreases. With the increase of *I*dsat, the PAE increase. Furthermore, the larger *I*dsat is, the slower PAE increases.

**Figure 4.** The effect of device parameters on PAE: (**a**) PAE-*Vt* and *gm*, (**b**) *PAE*-*Cgs* and *Idsat*.

From the analysis above, it can be concluded that the smaller the absolute value of *V*t, the bigger the PAE, and the smaller the *<sup>C</sup>*gs, the bigger the PAE. For *g*m, a bigger *g*m means a higher current gain, so it a larger output can be obtained under the same input. According to Figure 4a, the PAE is proportional to *g*m. This is the reason why the PAE of the device decreases sharply when *H* is 0.20 μm and *N*PLDC is 1 × 10<sup>15</sup> cm<sup>−</sup><sup>3</sup> or 1 × 10<sup>16</sup> cm<sup>−</sup>3. When *H* is 0.20 μm and *N*PLDC is 1 × 10<sup>17</sup> cm<sup>−</sup>3, the PAE of the device increases because *g*m is not the key factor compared with *V*t, *I*dsat and *<sup>C</sup>*gs. The PAE of the device is decided by the influences of those parameters.

It can be seen that the doping concentration and thickness of the PLDC are optimized to be *N*PLDC = 1 × 10<sup>15</sup> cm<sup>−</sup><sup>3</sup> and *H* = 0.15 μm. Table 1 shows some main parameters of the two devices. It can be seen that the PAE of the PLDC-MESFET is 43.67%, which is higher than the PAE of 23.43% of the DR-MESFET. Compared the two devices, the PLDC-MESFET has a smaller threshold voltage, smaller input capacitance, smaller transconductance and smaller saturation current than the DR-MESFET. The increase of the PAE is influenced by the combination of these parameters. When the absolute value of *V*t decreases, the device is easier to turn on and gains a larger output current. So, the output power *P*out increases and a higher PAE is reached. According to Formula (2) [16], a smaller input capacitance *<sup>C</sup>*gs means the device has less energy loss when working in RF (charging and discharging).

$$P\_{\rm dyn} = E\_{\rm VD} - E\_{\rm c} = \int\_0^\infty i\_{\rm vd}(t) V\_{\rm d} dt - \int\_0^\infty i\_{\rm vd}(t) v\_{\rm out} dt = \mathcal{C} V\_{\rm D}^2 - \frac{\mathcal{C} V\_{\rm D}^2}{2} = \frac{\mathcal{C} V\_{\rm D}^2}{2} \tag{2}$$

where *<sup>P</sup>*dyn is the dynamic power consumption flipped once, *E*VD is the energy obtained from the power source, *E*c is the capacitor stored energy, *C* is the gate–source capacitor and *V*D is the drain voltage. A small *<sup>C</sup>*gs also increases the input impedance of the device. Therefore, *P*out of the device increases and *P*in decreases. For *I*dsat, a small *I*dsat indicates a small *P*out. Under the influence of these parameters, the device has a big PAE. In there, *g*m is sacrificed to obtain a higher PAE. Though a larger *g*m is helpful to increase PAE, the influences of the other parameters on PAE are more obvious. So, the maximum value of PAE is 43.67% when *N*PLDC is 1 × 10<sup>15</sup> cm<sup>−</sup><sup>3</sup> and *H* is 0.15 μm, as obtained by sacrificing some of the DC performances of the device.


**Table 1.** Comparison of performance parameters of the two structures.
