*4.4. High-temperature Packaging Technology*

SiC converters and MEMS devices face the challenge of a minimum of parasitic parameter and capability of operating in a high-temperature environment. Due to the fast switching speed and low threshold voltage, SiC devices are deeply a ffected by the inherent and line parasitic parameters, which requires the packaging design to minimize the length of pin and wire, but the compact layout reduces the area of dissipation [91]. Likewise, the packaging technology is also a challenge to the fabrication of SiC devices for high-temperature applications. The high-temperature welding technique is one of the critical factors to improve the high-temperature capability of SiC devices [92]. The advanced material technique and the innovative structure design need to be developed to approach the SiC physical limitation.

Packaging materials and structures with improved reliability at higher temperatures are imperative for the implementation of SiC devices, mentioning the high-temperature die attach, high-conductivity TIM, and aggressive heat rejection system. For the die attach, CTE, melting temperature, porosity feature, as well as electrical and thermal conductivity are not the only indices [93]. The mechanical properties such as the modulus of elasticity, ductility, and yield strength are of equal importance [94]. Lead-free gold-based solders are a good choice for niche applications, but their mechanical sti ffness is as a limiting factor, which can transfer stresses to SiC devices resulting in die cracking. The thermal resistance of TIM is still the bottleneck in most power electronics packaging, so the high-performance filler materials should be further investigated as both an enhancement and a basis for TIMs. Double-sided cooling structures, two-phase cooling methods and novel coolants can improve the cooling capability for SiC modules, which need further demonstration and understanding of long-term reliability before industrial applications.
