*3.1. Computation Offloading Model*

When an IoT device requests computation offloading to the EH MEC system, the EH MEC system can either allow offloading or pass the request to the cloud server. When the EH MEC system offloads all computation tasks, the service QoE will increase and the network overhead will be reduced. However, it is impossible to offload all the computation tasks due to the constraints of the EH MEC in terms of energy or computing performance. Therefore, the scheduler of the EH MEC system controls the admission of offloading requests, i.e., it determines whether it needs to be executed by the MEC or passed to the cloud server.

Figure 2 shows the proposed EH MEC scheduler. As shown in the figure, the proposed EH MEC scheduler consists of two sub-schedulers (offloading and MEC scheduler), three buffers (request, cloud, and MEC buffers), and two managers (battery and backhaul managers). At time *t*, the requests from the IoT devices are stored in the request buffer, and the request buffer is modeled as R*<sup>t</sup>* . Similarly, the MEC buffer can be modeled as

$$\mathcal{M}^{t} = \{m\_{1}^{t}, m\_{2}^{t}, m\_{3\prime}^{t} \cdot \cdot \cdot, m\_{M}^{t}\},\tag{5}$$

where *M* is the number of unexecuted tasks in the MEC buffer. Analogously, the cloud buffer can be modeled as

$$\mathcal{C}^{t} = \{c\_1^t, c\_2^t, c\_{3'}^t \cdot \cdot, c\_{\subset}^t\},\tag{6}$$

where *C* is the number of tasks in the cloud buffer.

Based on the SoC and MEC state, the offloading scheduler performs task scheduling (i.e., admission control) and updates the MEC buffer and cloud buffer.

For offloading scheduling, this paper introduces the following mathematical models. A request for computation offloading *r<sup>t</sup> <sup>i</sup>* is defined as follows:

$$r\_i^t \stackrel{\Delta}{=} [L\_i^t, d\_i^t]\_\prime \tag{7}$$

where *L<sup>t</sup> <sup>i</sup>* is the input bit size of the task and *<sup>d</sup><sup>t</sup> <sup>i</sup>* is the execution deadline.

In this paper, we assume that *d<sup>t</sup> <sup>i</sup>* represents only the execution time in the MEC server. If we denote the number of CPU cycles required to process the bit input in the MEC server as *X*, then the number of CPU cycles required to execute *r<sup>t</sup> <sup>i</sup>* successfully can be obtained as

$$\mathcal{W}\_{\mathcal{R},i} = L\_i^t \cdot X. \tag{8}$$

The CPU frequency of the MEC server at *t* and the delay for the execution of *r<sup>t</sup> <sup>i</sup>* are denoted as *<sup>f</sup> <sup>t</sup>* and *D<sup>t</sup>* R,*i* , respectively. Therefore, *D<sup>t</sup>* <sup>R</sup>,*<sup>i</sup>* can be obtained as

$$D^t\_{\mathcal{R},i} = \frac{\mathcal{W}\_{\mathcal{R},i}}{f^t}. \tag{9}$$

In addition, the offloading schedule of R*<sup>t</sup>* can be represented by

$$\mathcal{S}^t \triangleq [\mathbf{s}\_{1\prime}^t \mathbf{s}\_{2\prime}^t \mathbf{s}\_{3\prime}^t \cdots \mathbf{s}\_{\prime}^t \mathbf{s}\_R^t]\_\prime \tag{10}$$

where

$$s\_i^t = \begin{cases} 1, & \text{if } r\_i^t \text{ is allocated to the MEC server,} \\ 0, & \text{if } r\_i^t \text{ is allocated to the cloud server.} \end{cases}$$

**Figure 2.** The proposed architecture of the EH MEC scheduler. The EH MEC scheduler includes two sub schedulers: (1) offloading scheduler; and (2) MEC scheduler.

Based on the above definitions and notations, the execution delay can be computed as follows:

$$D\_{schedulle}^t = \sum\_{m=1}^M D\_{\mathcal{M},m}^t + \sum\_{r=1}^R s\_r^t \cdot D\_{\mathcal{R},r\prime}^t \tag{11}$$

where *D<sup>t</sup>* <sup>M</sup>,*<sup>i</sup>* is the execution delay of task *<sup>m</sup><sup>t</sup> <sup>i</sup>* in the MEC buffer and can be computed similarly to Equation (9). Therefore, the scheduling constraint for the task deadline can be derived as follows:

$$s\_i^t \cdot D\_{schedulle}^t \le d\_{i\prime}^t \,\forall i. \tag{12}$$

In addition, the energy consumed for executing the task *r<sup>t</sup> <sup>i</sup>* can be obtained as follows:

$$E^t\_{\mathcal{R},i} = \kappa \times \mathcal{W}\_{\mathcal{R},i} \times (f^t)^2,\tag{13}$$

where *κ* is the effective switched capacitance, which depends on the chip architecture. Therefore, the scheduling constraint for energy consumption can be expressed as

$$E\_{\text{offload}}^t = \sum\_{r=0}^R s\_r^t \cdot E\_{\mathcal{R},r}^t + \sum\_{m=1}^M E\_{\mathcal{M},m}^t \le B^t,\tag{14}$$

where *E<sup>t</sup>* <sup>M</sup>,*<sup>i</sup>* is the energy consumption for task *<sup>m</sup><sup>k</sup> <sup>i</sup>* in the MEC buffer and can be computed similarly to Equation (13).

We assume that the MEC system charges the offloading bill according to the number of instruction executions, and the offloading pricing per instruction is denoted as *p*. Therefore, the computation offloading bill of *r<sup>t</sup> i* , denoted as *P<sup>t</sup>* R,*i* , can be obtained as

$$P\_{\mathcal{R},i} = p \cdot W\_{\mathcal{R},i}.\tag{15}$$

This paper also assumes that the EH MEC system wishes to maximize the bill as well as satisfy the execution delay and energy constraints. Therefore, the objective function of the offloading scheduling can be derived as follows:

$$\text{maximize } \sum\_{r=1}^{\mathbb{R}} s\_r^t \cdot P\_{\mathcal{R}, i^\star}^t \tag{16}$$

subject to

$$s\_r^t \cdot D\_{schudule}^t \quad \le \quad d\_{r\prime}^t \forall r \in \mathcal{R}\_\prime \tag{17}$$

$$\sum\_{r=0}^{\overline{R}} \mathbf{s}\_r^t \cdot E\_{\overline{\mathcal{R}},r}^t + \sum\_{m=1}^M E\_{\mathcal{M},m}^t \le \quad B^t. \tag{18}$$
