3.2.1. Module 1

The block diagram in Figure 9 shows that Module 1 comprises six sets of BF2 units and two banks of 32-element RAM modules for radix-2 operations. The path-routing control of multiplexers (M1–M5) allows Module 1 to perform six-path addition and the subtraction of the input for BF2 execution or route the read/write the data of six-set RAM banks for I/O data delivery. Module 1 operations were more complex than those conventionally used for SDF or MDF radix-2 stages [9,24–26] because this process enables data access for W128 multiplications by using the shared CMU (Figure 8).

**Figure 9.** Block diagram of Module 1.

Referring to the top radix-2 related portions in Figure 8, Figure 10 details the operations of Module 1 and the controls of multiplexers M1–M5 for the first (the initial) and second 128-point input sequences of the six streams. Figure 10 presents addresses based on the schedule of clock cycles and radix-2 operations with W128 multiplication (Figure 8).

**Figure 10.** Detailed operations of Module 1 and control of multiplexers (M1–M5) based on clock cycles.
