*4.1. Design Implementation*

The evaluated signal is used to evaluate the proposed kernel accuracy. After fixed-point simulation using MATLAB, the signal-to-quantization-noise ratio (SQNR) was approximately 40 dB by using the proposed FFT kernel. This was implemented in a 1.0-V UMC 90-nm 1P9M complementary metal-oxide semiconductor process, the proposed FFT kernel used the Synopsys Design Compiler to synthesize the RTL code and employed Cadence SOC Encounter for placement and routing. The proposed FFT kernel consumed 10.72 mW of power and was operated at 80 MHz, and the core area of the proposed kernel was 739 × 734 μm2. Figure 15 shows the core layout of the proposed kernel and its characteristics. The kernel test chip could perform 128/64-point FFT in 4–6 streams depending on the GI duration. A test module was included in this kernel chip to enable the serial storage of test patterns from the I/O and to send them to the kernel circuit along multiple paths. Moreover, the FFT results were sent to the test module and then sequentially read out through I/O for data evaluation. The post-layout simulation was performed based on the idea that the FFT kernel continuously processes the pattern stored in the test module.


**Figure 15.** Layout and performance summary of FFT kernel test chip.
