*Article* **Miniature DC-DC Boost Converter for Driving Display Panel of Notebook Computer**

**Seok-Hyeong Ham <sup>1</sup> and Hyung-Jin Choe 2,\***


Received: 26 June 2019; Accepted: 29 July 2019; Published: 30 July 2019

**Abstract:** This paper proposes a miniature DC-DC boost converter to drive the display panel of a notebook computer. To reduce the size of the circuit, the converter was designed to operate at a switching frequency of 1 MHz. The power conversion efficiency improved using a passive snubber circuit that consisted of one inductor, two capacitors, and two diodes; it reduced the switching losses by lowering the voltage stress of the switch and increased the voltage gain using charge pumping operations. An experimental converter was fabricated at 2.5 cm × 1 cm size using small components, and tested at input voltage 5 V ≤ *VIN* ≤ 17.5 V and output current 30 mA ≤ *IO* ≤ 150 mA. Compared to existing boost converters, the proposed converter had ~7.8% higher power conversion efficiency over the entire range of *VIN* and *IO*, only ~50% as much voltage stress of the switch and diodes, and a much lower switch temperature *TSW* = 49.5 ◦C. These results indicate that the proposed converter is a strong candidate for driving the display panel of a notebook computer.

**Keywords:** backlight; DC-DC converter; passive snubber; voltage stress

#### **1. Introduction**

Notebook or tablet computers are powered by a Li ion battery pack [1–4]. Typically, the battery pack is composed of 2–4 Li ion battery cells. Each Li ion cell has a terminal voltage of 2.6–4.2 V depending on the charging state, so the voltage of the battery pack changes in the range of 5–17 V [5–7]. To supply power to each part of the computer, the pack voltage is converted to several voltages by DC-DC converters.

Many computers use a light-emitting diode (LED) backlight unit (BLU) for the liquid crystal display (LCD) panel. For a 17 inch panel, the voltage required to drive the LED backlight can be as high as 40 V [8]. The DC-DC boost converter for the LED BLU in a notebook or tablet computer should have a circuit topology that can reduce the overall size and weight [9–16]. The conventional boost converter (Figure 1) has the simplest structure, and can be implemented in small sizes by operating at a high switching frequency *fS*. However, the switching loss increases as *fS* increases, and thereby decreases the power conversion efficiency η*<sup>e</sup>* and can cause overheating of the switch. This problem has been solved using soft-switching converters [17–21].

**Figure 1.** Schematic of conventional DC-DC boost converter.

Soft-switching converters [17–21] use active snubbers to reduce switching loss. These snubbers are implemented using an auxiliary switch, diodes, and energy storage elements. The auxiliary switch requires a separate gate drive circuit that is controlled by a sophisticated algorithm. The snubber of Reference [17] discharges the drain-source capacitor *CDS* of the main switch before the switch turns on, so zero-voltage (ZV) turn-on of the switch is possible. The snubbers of References [18,19] force the switch current to zero before the switch turns off, so zero-current (ZC) turn-off of the switch is possible. The snubber of Reference [20] achieves ZV turn-off of the switch by reducing the rate of voltage increase during the turn-off transient, and achieves ZC turn-on of the switch by reducing the rate of current increase during the turn-on transient. However, the converters of References [17–20] have some limitations when they operate at high *fS*; they use a resonance between an inductor (*L*) and a capacitor (*C*) in the active snubber, the inductance *L* of L should be small enough to achieve ZV or ZC switching in a short time; the current peak of the switch or diodes increases as *L* decreases, therefore, this change increases the conduction loss and reduces the maximum output power. In the converter of Reference [21], the capacitance *CDS* discharges through L of the snubber when the auxiliary switch turns on. The ZV turning on of the main switch is achieved by discharging *CDS* completely. The *L* required to achieve the ZV turning on of the switch decreases as *fS* increases; as a consequence, the switching loss in the auxiliary switch increases. Therefore, simultaneous reduction of switching losses in the main and auxiliary switches is very difficult at high *fS*. The converter of Reference [9] uses a passive snubber to reduce the switching loss. The switching loss is reduced by lowering the turn-on slope of the switch current; the inductor *LS* that is connected in series with the switch controls the turn-on slope. However, the energy stored in LS is released as a voltage spike because the current path of *LS* is blocked when the switch is turned off. To ensure that this voltage spike does not exceed the maximum voltage limit of the switch, *LS* should be less than 50 nH at high switching frequencies; This value of *LS* was calculated using Equation (9) of the design guide in Reference [9]. The low value of the chip type inductor has a low maximum current limit. This low inductance also causes undesired resonance due to the parasitic inductance or capacitance of the circuit. Because of this, the converter of Reference [9] is difficult to use at high switching frequencies. Additionally, the switch current significantly increases the conduction loss in *LS* because the components of small size have non-negligible series resistance.

To improve upon the aforementioned drawbacks in the existing converters, this paper proposes a miniature DC-DC boost converter for the display panel of a notebook computer. The proposed converter (Figure 2) uses a passive snubber to reduce the switching loss; the capacitor *C*<sup>2</sup> is connected in parallel with the switch, and the inductor *L*<sup>1</sup> is connected in series with *C*2, and the value of *L*<sup>1</sup> and *C*<sup>2</sup> are large enough to prevent resonance at high *fS*. This lowers *VSW* to *VO*-*VC*<sup>1</sup> and eliminates the switching loss. In addition, *L*<sup>1</sup> is placed apart from the main current path to reduce the conduction loss in the passive snubber. The switch operates under a hard-switching condition to achieve fast switching, but the switching loss is reduced by lowering *VSW* (Figure 3). The switching loss *PSW* is calculated using the waveforms of *iSW* and *VSW* as:

$$P\_{sw} = \frac{1}{T\_s} \int\_{t\_0}^{t\_2} V\_{sw}(t)i\_{sw}(t)dt + \frac{1}{T\_s} \int\_{t\_3}^{t\_5} V\_{sw}(t)i\_{sw}(t)dt$$

Compared with the conventional converter, the proposed converter has a similar current peak, but has *VSW*(*t*1) and *VSW*(*t*4) lowered by ~1/2, so *PSW* is reduced.

**Figure 2.** Schematic of proposed DC-DC boost converter.

**Figure 3.** Voltage and current waveforms of the switch: (**a**) conventional boost converter, (**b**) proposed converter.

The proposed converter has a higher voltage conversion ratio than the conventional boost converter, and therefore has a wide range of output voltage for a given range of input voltage. Section 2 describes the circuit structure and operating principle of the proposed converter, Section 3 gives the design guidelines, Section 4 shows the experimental results, and Section 5 concludes the paper.

#### **2. Circuit Structure and Operating Principles of the Proposed Converter**

The proposed converter consists of two capacitors *C*<sup>1</sup> and *C*2, two diodes *D*<sup>1</sup> and *D*2, and an inductor *L*1, in addition to the conventional boost components *Lb*, *DO*, *CO*, and a switch (SW). *C*<sup>1</sup> is located between boost inductor *Lb* and output diode *DO*, and acts as a charge pump capacitor to increase the voltage gain. *L*<sup>1</sup> and *C*<sup>2</sup> reduce the voltage stress of SW by dividing the output voltage *VO*. *D*<sup>1</sup> and *D*<sup>2</sup> provide a charging or discharging path for *C*2.

The operating modes (Figure 4) and key waveforms (Figure 5) of the proposed converter include three sequential modes of operation.

*Mode* 1 (*t*0~*t*1): The first operation (Figure 4a) starts at *t* = *t*<sup>0</sup> by turning ON SW. During this operation, *D*<sup>2</sup> turns ON, and *D*<sup>1</sup> and *D*<sup>O</sup> turn OFF. *vLb* = *VIN* and *vL*<sup>1</sup> = *VC*<sup>2</sup> − *VC*1, so

$$i\_{Lb}(t) = \frac{V\_{IN}}{L\_{\emptyset}}(t - t\_0) + i\_{Lb}(t\_0) \tag{1}$$

$$i\_{L1}(t) = i\_{\rm C1}(t) = -i\_{\rm C2}(t) = \frac{V\_{\rm C2} - V\_{\rm C1}}{L\_1}(t - t\_0) \tag{2}$$

*C*<sup>1</sup> is charged and *C*<sup>2</sup> is discharged when SW is turned ON. *Mode* 1 ends when SW is turned OFF.

*Mode* 2 (*t*1~*t*2): The second operation (Figure 4b) starts at *t* = *t*<sup>1</sup> when SW turns OFF. During *mode* 2, *D*<sup>2</sup> stays ON, and *D*<sup>1</sup> and *DO* are turned ON. When SW is turned OFF, the anode voltage of *D*<sup>1</sup> is *VC*<sup>2</sup> because *VLb* = *VC*<sup>2</sup> − *VIN* according to the voltage second valance law. The cathode voltage of *D*<sup>1</sup> is *VC*<sup>2</sup> − Δ*VC*<sup>2</sup> because C2 was discharged in *Mode* 1, so *D*<sup>1</sup> is turned ON. After *D*<sup>1</sup> is turned ON, the anode voltage of *DO* is *VC*<sup>1</sup> + *VC*<sup>2</sup> and cathode voltage is *VO* − Δ*VO* because *CO* was discharged in *Mode* 1. Therefore, *DO* is turned ON because *VC*<sup>1</sup> + *VC*<sup>2</sup> = *VO* in steady state. In the same manner, after *D*<sup>1</sup> and *DO* are turned ON, *D*<sup>2</sup> is turned ON because the anode voltage of *D*<sup>2</sup> is *VC*<sup>1</sup> + *VC*<sup>2</sup> and the cathode voltage is *VO* − Δ*VO*. *vLb* = *VIN* − *VC*<sup>2</sup> and *vL*<sup>1</sup> = −*VC*1, so

$$i\_{Lb}(t) = \frac{V\_{IN} - V\_{C2}}{L\_b}(t - t\_1) + i\_{Lb}(t\_1), \ i\_{L1}(t) = -\frac{V\_{C1}}{L\_1}(t - t\_1) + i\_{L1}(t\_1).$$

**Figure 4.** Modes of operation: (**a**) *Mode* 1 (*t*<sup>0</sup> < *t* < *t*1), (**b**) *Mode* 2 (*t*<sup>1</sup> < *t* < *t*2), (**c**) *Mode* 3 (*t*<sup>2</sup> < *t* < *t*3).

**Figure 5.** Operating waveforms of the proposed DC-DC boost converter.

The voltage stress of SW is *VC*<sup>2</sup> because *D*<sup>1</sup> is turned ON when SW is turned OFF. The output voltage *VO* is divided into *VC*<sup>1</sup> and *VC*2, so the voltage stress of SW is smaller than *VO*, which is the voltage stress of the conventional boost converter.

*Mode* 3 (*t*2~*t*3): The last operation (Figure 4c) starts at *t* = *t*<sup>2</sup> when *D*<sup>2</sup> turns OFF. *D*<sup>1</sup> and *DO* stay ON during this mode. *vLb* = *VIN* − *VC*2, so

$$i\_{Lb}(t) = \frac{V\_{IN} - V\_{C2}}{L\_b}(t - t\_1) + i\_{Lb}(t\_1)$$

In this mode, *vL*<sup>1</sup> = 0 because *iL*<sup>1</sup> = 0. *Mode* 3 ends when SW is turned ON for the next switching cycle.

The voltage–second balance law of inductances *Lb* and *L*<sup>1</sup> yields

$$(V\_{IN}D + (V\_{IN} - V\_{C2})(1 - D) = 0\tag{3}$$

$$(V\_{C2} - V\_{C1})D - V\_{C1}(1 - D - \alpha) = 0\tag{4}$$

where *D* is the duty of switching and α*TS* is the duration of *Mode* 3. Solving Equations (3) and (4) for *VC*<sup>1</sup> and *VC*<sup>2</sup> yields

$$V\_{C2} = \frac{V\_{IN}}{1 - D},\ V\_{C1} = \frac{D}{1 - a} \frac{V\_{IN}}{1 - D}.\tag{5}$$

Equation (5) and *VO* = *VC*<sup>1</sup> + *VC*<sup>2</sup> then give the voltage conversion ratio as

$$\frac{V\_O}{V\_{IN}} = \frac{1}{1-D} \frac{1-a+D}{1-a} \tag{6}$$

The average current of *L*1, *IL*<sup>1</sup> for one switching period *TS* is equal to the average output current *IO*, so

$$I\_O = \frac{V\_{C2} - V\_{C1}}{2L\_1} D^2 T\_S + \frac{V\_{C1}}{2L\_1} (1 - D - a)^2 T\_S \tag{7}$$

Inserting Equation (5) into Equation (7) and solving for α yields

$$\alpha = \frac{(V\_{IN}DT\_S - 2I\_OL\_1)(1 - D)}{V\_{IN}DT\_S} \tag{8}$$

Combining Equations (6) and (8) yields the output voltage

$$V\_O = \frac{2V\_{IN}(V\_{IN}D^2T\_S + I\_OL\_1(1-D))}{(1-D)(V\_{IN}D^2T\_S + 2I\_OL\_1(1-D))}\tag{9}$$

*VO* versus *D* (Figure 6) for *L*<sup>1</sup> = 10 μH, *fS* = 1 MHz, *IO* = 150 mA, *VIN* = 5 V, and 0.1 ≤ *D* ≤ 0.9 was calculated using Equation (9) for the proposed converter, but the conventional boost converter was calculated using their voltage gain equations. To have *VO* = 40 V for given *VIN*, *D* = 0.775 was applied to the proposed converter, whereas *D* = 0.875 was applied to the conventional boost converter. At given *VIN* and *D*, the proposed converter had higher *VO* than the conventional boost converters.

**Figure 6.** *VO* versus duty *D* for the experimental boost converters; *VIN* = 5 V, 0.1 ≤ *D* ≤ 0.9.

#### **3. Design Guideline**

#### *3.1. Boost Inductor Lb*

The inductance *Lb* of *Lb* should be determined so that the proposed converter operates in a continuous conduction mode (CCM). The current through *Lb* is minimum at *t*<sup>0</sup> and maximum at *t*1. The following equation is obtained using the average of *iLb* and Equation (1),

$$i\_{Lb}(t\_1) - i\_{Lb}(t\_0) = \frac{V\_{IN}DT\_S}{L\_b},\ i\_{Lb}(t\_1) + i\_{Lb}(t\_0) = 2I\_{IN}.\tag{10}$$

Solving Equation (10) for *iLb*(*t*0) yields

$$i\_{Lb}(t\_0) = I\_{IN} - \frac{V\_{IN}DT\_S}{2L\_b}$$

The condition *iLb*(*t*0) > 0 should be satisfied to operate the proposed converter in CCM. This condition yields

$$L\_b > \frac{V\_{IN} D T\_S}{2I\_{IN}}\tag{11}$$

For 5 ≤ *VIN* ≤ 17.5 V, *VO* = 40 V, *fS* = 1 MHz, and 30 ≤ *IO* ≤ 150 mA, *Lb* = 33 μH was determined using Equations (9) and (11).

#### *3.2. Snubber Inductor L1*

A small value of *L*<sup>1</sup> causes a drastic current decrease of *D*<sup>2</sup> in mode 2. Therefore, the limit of *L*<sup>1</sup> is calculated using the following condition for a soft turn-off of *D*2.

$$\frac{V\_{C1}}{L\_1} << \frac{I\_{D2,\text{max}}}{t\_{D2,full}}$$

where *ID2,max* is the highest diode current and *tfall* is the diode turn-off time; *L*<sup>1</sup> 0.2 μH for*ID2,max* = 1 A and *tfall* = 10 ns. The diode turn-off loss increases as *L*<sup>1</sup> decreases, so *L*<sup>1</sup> = 10 μH was chosen to provide an operating margin and to reduce turn-off loss of *D*2.

#### *3.3. Snubber Capacitors C1 and C2*

The capacitance of *C*<sup>1</sup> is determined by the condition that Δ*VC*<sup>1</sup> << *VC*<sup>1</sup> because *VC*<sup>1</sup> should be almost constant for one switching period *TS*, where Δ*VC*<sup>1</sup> is the voltage ripple of *C*1. During *Mode 1*, *C*<sup>1</sup> charges through *L*1; this results in a voltage ripple Δ*VC*<sup>1</sup> of C1; Δ*VC*<sup>1</sup> = (*VC*<sup>2</sup> − *VC*1)(*DTS*) 2 /(2*C*1*L*1) because the current through *C*<sup>1</sup> decreases linearly from 0 A at *t*<sup>0</sup> to (*VC*<sup>2</sup> − *VC*1)*DTS*/*L*<sup>1</sup> at *t*1.

Therefore,

$$C\_1 >> \frac{V\_{C2} - V\_{C1}}{2V\_{C1}L\_1} \left(DT\_S\right)^2. \tag{12}$$

For *VIN* = 5 V, *VO* = 40 V, *fS* = 1 MHz, and *L*<sup>1</sup> = 10 μH, *C*<sup>1</sup> = 1 μF was determined using Equations (5) and (12). *C*<sup>2</sup> has been chosen to be the same as *C*<sup>1</sup> because Δ*VC*<sup>1</sup> = Δ*VC*<sup>2</sup> and *iC*<sup>1</sup> = −*iC*<sup>2</sup> in *Mode 1*.

#### **4. Experimental Results**

The proposed boost converter (Figure 7) was designed to operate at *VIN* = 5 V, *VO* = 40 V, 30 ≤ *IO* ≤ 150 mA, and *fS* = 1 MHz. The inductances were set at *Lb* = 33 μH and *L*<sup>1</sup> = 10 μH. Capacitances *C*<sup>1</sup> and *C*<sup>2</sup> were both set at 1 μF. The experimental circuit was implemented using the following miniature components (Table 1): TPS55340 DC-DC controller (Texas Instruments Inc., Dallas, TX, USA), which has an internal *n*-MOS switch (40 V, 5A), RB160M-60TR diodes (Rohm Co.), IFSC-1515AH-01 (Vishay Inc.) and SSMC252008R47SC (SST Inc.) chip inductors, and multilayer ceramic chip capacitors of a size 3.2 mm × 1.6 mm. The chip inductors and capacitors have series resistances given in the parentheses. To ensure a fair comparison, the conventional boost converter used the same components.

**Figure 7.** Photograph of the proposed DC-DC boost converter.


**Table 1.** Component values for the experimental boost converters.

The TPS55340 regulates the output voltage with current mode PWM control, and has an internal oscillator. The pulse width modulation of the gate pulse *Vg* is achieved in the control circuit for the proposed converter (Figure 8) as follows; each clock pulse resets the flip-flop and the ramp generator, which sets *Vg* to the 'high' state; the output *Vc* of the error amplifier increases as *VO* increases; the comparator output changes from 'low' to 'high' when the output voltage of the ramp generator exceeds *Vc*, which changes the inverter output *Vg* to the 'low' state. When the output current *IO* increases/decreases abruptly, *VO* decreases/increases instantly, which increases/decreases *Vc*. Thus, the pulse width of *Vg* increases/decreases to keep *VO* constant.

**Figure 8.** Block diagram of the control circuit for the proposed converter.

The voltage and current waveforms of SW (Figure 9) were measured at *VIN* = 5 V, *VO* = 40 V, *IO* = 150 mA, and *fS* = 1 MHz. The voltage stress of the proposed converter (Figure 9a) was lower than that of the conventional boost converter (Figure 9b) because the voltage stress was *VO* − *VC*<sup>1</sup> in the proposed converter but *VO* in the conventional boost converter. The current stresses of the proposed converter and the conventional boost converter were similar. The current waveforms of the diodes are shown in Figure 10. The diodes current stresses of the proposed converter was lower than the conventional boost converter. The time-averaged values <*iD*1>, <*iD*2>, and <*iD*o> were all equal to *IO*.

The curves of η*<sup>e</sup>* on *IO* (Figure 11a) were measured at 30 ≤ *IO* ≤ 150 mA, *VIN* = 5 V, *VO* = 40 V, *fS* = 1 MHz. At *IO* = 30 mA, η*<sup>e</sup>* was 84.0% for the proposed converter and 76.9% for the conventional boost converter. At *IO* = 150 mA, η*<sup>e</sup>* was 80.4% for the proposed converter and 72.6% for the conventional boost converter. The curves of η*<sup>e</sup>* on *VIN* (Figure 11b) were measured at 5 ≤ *VIN* ≤ 17.5 V, *IO* = 150 mA, *VO* = 40 V, *fS* = 1 MHz; η*<sup>e</sup>* at *VIN* = 17.5 V was 89.1% for the proposed converter and 88.6% for the conventional boost converter. The η*<sup>e</sup>* of the proposed converter was up to 7.8% higher than the conventional boost converter at *VIN* = 5 V. The proposed converter had a high η*<sup>e</sup>* over the entire input voltage and output current ranges.

**Figure 9.** Voltage and current waveforms of switch measured at *VIN* = 5 V, *VO* = 40 V, *IO* = 150 mA, and *fS* = 1 MHz. (**a**) Proposed converter, (**b**) conventional boost converter.

**Figure 10.** Diode waveforms of the proposed converter. (**a**) *Do*, (**b**) *D*1, (**c**) *D*2, and diode waveform of the conventional boost converter. (**d**) *Do* measured at *VIN* = 5 V, *VO* = 40 V, *IO* = 150 mA and *fS* = 1 MHz.

**Figure 11.** (**a**) η*<sup>e</sup>* versus *IO* at *VIN* = 5 V, *VO* = 40 V, *fS* = 1 MHz, and 30 ≤ *IO* ≤ 150 mA. (**b**) η*<sup>e</sup>* versus *VIN* at *IO* = 150 mA, *VO* = 40 V, *fS* = 1 MHz, and 5 ≤ *VIN* ≤ 17.5 V.

The temperatures of SW and inductors (Figure 12) were measured for 30 min using a digital temperature recorder (GL-220, GRAPHTEC), while the converters were operated at *VIN* = 5 V, *VO* = 40 V, *fS* = 1 MHz, and *IO* = 150 mA. In the conventional boost converter the switch stabilized at 86.6 ◦C and the inductor stabilized at 91.7 ◦C, but in the proposed converter, the switch stabilized at 49.5 ◦C and the inductor stabilized at 62.9 ◦C. These data indicate that the proposed converter generated less heat loss than the conventional boost converter.

**Figure 12.** Temperature of switch and inductors versus operation time for the experimental converters, measured at *VIN* = 5 V, *VO* = 40 V, *IO* = 150 mA, and *fS* = 1 MHz.

The circuit losses were calculated using a circuit simulator at *VO* = 40 V, *IO* = 150 mA, *fs* = 1 MHz, and *VIN* = 5 V (Figure 13a) and 15 V (Figure 13b). The total power losses were 1.59 W (proposed) and 2.31 W (conventional) at *VIN* = 5 V, and they were 0.68 W (proposed) and 0.78 W (conventional) at *VIN* = 15 V. These results show that the proposed converter had lower power loss than the conventional boost converter at both *VIN* = 5 V and 15 V. The losses in the switch were 0.65 W (proposed) and 1.41 W (conventional) at *VIN* = 5 V, and they were 0.38 W (proposed) and 0.63 W (conventional) at *VIN* = 15 V. The proposed converter reduced the switching loss by decreasing *VSW.* Additionally, the snubber loss of the proposed converter was 0.16 W at *VIN* = 5 V, and it was 0.15 W at *VIN* = 15 V. The proposed converter reduced the snubber losses by placing *L*<sup>1</sup> at the output stage and eliminating the resonant current in the snubber circuit.

**Figure 13.** Circuit losses for *VO* = 40 V, *IO* = 150 mA and *fS* = 1 MHz, calculated at (**a**) *VIN* = 5 V and (**b**) *VIN* = 15 V.

The voltage and current stress (Table 2) of the proposed and conventional boost converter were measured at *VIN* = 5 V, *VO* = 40 V, *IO* = 150 mA, and *fS* = 1 MHz. Without parasitic components, the voltage stress of SW and diodes were as follows: (1) in the conventional boost converter, *VSW* = *VO* because *DO* was turned ON when SW was turned OFF, and *VDo* = *VO* because SW was turned ON when *DO* was turned OFF; (2) in the proposed converter, *VSW* = *VO* − *VC*<sup>1</sup> because *DO*, *D*1, and *D*<sup>2</sup> were turned ON when SW was turned OFF, *VDo* = *VD*<sup>1</sup> = *VO* − *VC*<sup>1</sup> because SW was turned ON when *D*<sup>O</sup> and *D*<sup>1</sup> are turned OFF, and *VD*<sup>2</sup> = *VO* − *VC*<sup>2</sup> because *D*<sup>1</sup> and *D*<sup>O</sup> were turned ON, and SW was turned OFF when *D*<sup>2</sup> was turned OFF. The proposed converter had lower voltage stress of SW and diodes than the conventional boost converter because *VO* = *VC*<sup>1</sup> + *VC*2. The current stress of SW was similar in the conventional boost converter and the proposed converter. The current stresses of diodes were lower by half in the proposed converter than in the conventional boost converter.


**Table 2.** Voltage and current stresses of components in the experimental boost converters.

The voltage stress, current stress, voltage gain, and efficiency of the existing boost converter were calculated using a circuit simulator at *VIN* = 5 V, *VO* = 40 V, *IO* = 150 mA, and *fs* = 1 MHz (Table 3). The efficiency η*<sup>e</sup>* was 72.6% for the conventional boost converter, 80.4% for the proposed converter, 75.1% for the converter of Reference [12], and 76.6% for the converter of Reference [21]. The proposed converter had the highest η*<sup>e</sup>* for given input and output conditions. The converters of References [12,21] had a lower efficiency than that of the proposed converter due to a high current stress and the loss of auxiliary switch, respectively. The voltage stress of the proposed converter was lower than that of the other converters because the voltage stress is *VO*-*VC*<sup>1</sup> in the proposed converter but *VO* in the other converters. The current stresses of the proposed converter and the conventional boost converter were similar, but the converter of Reference [12] had a high current stress because it used resonance to

reduce the switching loss at high frequency. At given *VIN* and *VO*, the proposed converter had the smallest duty, so the proposed converter had the highest voltage gain.


**Table 3.** Comparison with existing boost converters.

#### **5. Conclusions**

A miniature DC-DC boost converter for driving a display panel of a notebook computer was proposed. This converter operates at a switching frequency of 1 MHz to miniaturize the circuit. The switching loss is reduced by using a passive snubber that lowers the voltage stresses of the switch. The conduction losses of the snubber and switch is also minimized by preventing high peak current due to the resonance at high *fS*. The experimental converter was fabricated in 2.5 cm × 1 cm size and tested at 5 ≤ *VIN* ≤ 17.5 V, 30 ≤ *IO* ≤ 150 mA. Compared to previous boost converters, the proposed converter had a higher voltage conversion ratio, ~7.8% higher power conversion efficiency over the entire range of *VIN* and *IO*, ~1/2 as much voltage stress of the switch and diodes, and a much lower switch temperature. The results indicate that the proposed converter is a strong candidate for driving the display panel of a notebook computer.

**Author Contributions:** S.-H.H. conceived the main idea for the proposed converter and performed overall analysis and experiment. H.-J.C. led the project and gave technical advice.

**Acknowledgments:** This research was supported by the Tongmyong University Research Grants 2019(2019A003-1).

**Conflicts of Interest:** The authors have no conflict of interest.

#### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

*Article*
