**A Modified High Voltage Gain Quasi-Impedance Source Coupled Inductor Multilevel Inverter for Photovoltaic Application**

**Madasamy Periyanayagam 1,\*, Suresh Kumar V 2, Bharatiraja Chokkalingam 3,5,\*, Sanjeevikumar Padmanaban 4, Lucian Mihet-Popa <sup>6</sup> and Yusu**ff **Adedayo <sup>5</sup>**


Received: 19 January 2020; Accepted: 12 February 2020; Published: 17 February 2020

**Abstract:** The quasi-impedance source inverters/quasi-Z source inverters (Q-ZSIs) have shown improvement to overwhelmed shortcomings of regular voltage-source inverters (VSIs) and current-source inverters (CSIs) in terms of efficiency and buck-boost type operations. The Q-ZSIs encapsulated several significant merits against conventional ZSIs, i.e., realized buck/boost, inversion and power conditioning in a single power stage with improved reliability. The conventional inverters have two major problems; voltage harmonics and boosting capability, which make it impossible to prefer for renewable generation and general-purpose applications such as drive acceleration. This work has proposed a Q-ZSI with five-level six switches coupled inverter. The proposed Q-ZSI has the merits of operation, reduced passive components, higher voltage boosting capability and high efficiency. The modified space vector pulse width modulation (PWM) developed to achieve the desired control on the impedance network and inverter switching states. The proposed PWM integrates the boosting and regular inverter switching state within one sampling period. The PWM has merits such as reduction of coupled inductor size, total harmonic reduction with enhancing of the fundamental voltage profile. In comparison with other multilevel inverters (MLI), it utilizes only half of the power switch and a lower modulation index to attain higher voltage gain. The proposed inverter dealt with photovoltaic (PV) system for the stand-alone load. The proposed boost inverter topology, operating performance and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for the stand-alone and grid-connected system.

**Keywords:** impedance source; multilevel inverter; coupled inductors; space vector pulse PWM; photovoltaic connected inverter

### **1. Introduction**

Photovoltaic (PV) energy, extracted through solar cells is a mandatory power generation technology to meet out the global power demand [1]. The most prominent merits in PV generation are reduction of fossil fuel usage, less impact on the environment and reduction in power generation cost [2,3]. The large-scale deviation occurs in the floating power generations that abide by climatic conditions. Unfortunately, the main drawback of the PV array panels is a wide range of drop-in voltage. However, the power electronics devices overcome the voltage drops and floating power generation [4]. The power electronics converter and inverter combinations make PV power transfer an efficient process. The traditional power electronics inverters; voltage-source inverter (VSI), and current-source inverter (CSI) defeats options in the PV power generation with the addition of DC-DC converters. This two-stage power conversion needs more semiconductor switches and passive components; hence they may cause the abrupt disturbance on voltage profile [5]. To prevail over the demerits of traditional inverters, single-stage power conversion is introduce named as Z (impedance) source inverter (ZSI). Impedance networks offer an effective power transformation between the source (input) and an extensive range of loads with high efficiency. However, the ZSI lags in the performance like producing discontinuous nature in the input current; inductors do not withstand high current, and voltage stress on the capacitors [6]. The quasi-Z source has been expected to inherit the merits of the ZSI with reduced passive components, continuous input current, constant DC rail voltage for the inverter, and so on. Before embarking on the investigation of the Z source inverter, it is helpful to look into its evolution. Impedance source topology-based researches have proliferated, from the time it was proposed by Peng et al. in 2003; the variety of alterations and novel Z-source topologies has matured exponentially [7]. In the advancement of ZSI, it finds variety of applications such as; variable-speed electrical drives [8,9], uninterruptible power supply [10], in distributed power generations (such as photovoltaic (PV), fuel cell, and wind, etc.), energy storage system (such as battery and supercapacitor), and electric vehicles [11–13]. An earned mark of the Z-source inverter has lost its capability in the form of the input and output voltage ratio profile, switching stress and utilization of higher modulation. These lagging structure needs to be remarked with a quasi (Q)-Z source. The development in the Q-Z source with coupled inductor achieves most compromising effect towards upright of power quality, lower switching dv/dt, better electromagnetic influence, and negligible switching losses [14].

Owing to the advantages and challenges, power electronics researchers have given much interest in impedance-source topology development. The first Z-source was proposed during 2003 (Peng et al.); the variety of alterations, as well as novel topological inventions that have been developed exponentially, are chosen based on the applications and requirements. Concerning power conversion, it is separated into four groups: AC to DC (rectifier), AC to AC (AC voltage regulator), DC to DC (DC chopper), and DC to AC (inverter). This classification is further divided into two-level (conventional VSI) and multi-level DC to AC, AC to AC matrix converters [15] and DC to DC converters in isolated and non-isolated arrangement [16]. Based on the input source (current or voltage), the impedance source topology is further divided into the voltage source and current source Z-source [17]. Besides, considering the impedance components (inductors arrangements), this group can be distributed into coupled inductor (magnetically coupled) or transformer-based [18] and non-transformer (non-magnetically coupled) based [19]. There are selected limitations present in non-magnetically coupled topologies such as lower modulation proportion and lesser, output gain. Therefore, non-transformer topology needs higher boosting inductor and DC-link voltage rating, which may increase the converter switching stress superfluously. Besides, the circuit cost and size for these converters are undesirable. To minimize these concerns, the uses of magnetically coupled inductors or transformers are attractive to increase the operating range and output voltage gain concurrently. The Q-ZSIs proposed in [19,20] offer additional improvement of traditional X shape network topology. Besides the rewards inherited from X shape ZSIs, Q-ZSIs also has its own merits such as continuous current mode operation, reduction of component selection ratings, structured with common DC-rail in the middle of the input and inverter. There are modified Q-ZSI topologies comprehensibly investigated within their improvement

to provide continuous input current [21]. Yang et al. propose the current-fed Q-ZSI., including the benefits of the combined buck-boost operation, enhanced reliability, reduced component ratings, as well as single-stage regeneration capability. This topology provides consistency with the input current control and performs better than Q-ZSI.

In the current era, the interests of multilevel inverters (MLIs) have increased than the conventional VSIs, due to their merits [22]. Particularly the development of power semiconductor technology makes it easy to tradeoff the selection of power devices. New MLIs have been recommended in a hybrid approach by involving MOSFETs, IGCTs or GTOs and IGBTs [23–27]. Recently, the interleaved converter topology using coupled-inductors is proposed and extensively applied in low-power claims. These topologies are mostly used to increase the output current with lesser current ripple.

Additionally, the interleaved converter reduces the size of passive components (inductors and capacitors), and the output voltage harmonic profile is considerably increased [28–39]. Banaei et al. discussed the switching stress reduction in Z source-based MLI [36]. Alexandre Battiston et al. deliberated the withdrawal of the ripples in the input current with the suitable coupled inductors arrangement [37]. Li et al. proposed the use of the cascading magnetic cells to obtain a high voltage gain [38] and investigated the voltage gain achievement against smaller duty time. Followed by the authors, Lei et al. offered optimized pulse width modulation (PWM) technique with reduction of switching loss, current ripple, low total harmonic distortion (THD) and high boost gain [39]. The space vector PWM is extensively reviewed for impendence sourced VSIs and MLIs [40–49]. The creation of shoot-through (ST) and placing them in the active switching states, these PWM methods perform better than other carrier-based PWM methods. The ZSI space vector PWM is also studied with two-level MLIs for altering the active and ST switching vector in the space vector diagram for the enhancement of inverter output [44]. However, when connecting a coupled inverter with an impedance network, the PWM methods need to be modified.

Based on this technical background and coupled MLI and control scheme requirements of ZSI, this paper suggests a single-phase MLI coupled inverter topology with five-level output for PV application. This PV tied five-level coupled inverter topology is connecting the modified Q-ZSI with a six-switch coupled inverter, making a single stage DC to AC conversion topology. The proposed Q-ZSI has the merits of operation, namely reduced passive components, voltage boosting capability and high efficiency. The modified space vector PWM is proposed to realize the desired control in impedance network shoot-through and regular inverter switching state to make five-level output. The proposed PWM is integrating the boosting and regular inverter switching state within one sampling period. The PWM has the merits like a reduction of coupled inductor size and triplen harmonic reduction with the enhancement of the fundamental voltage profile.

In comparison with other MLIs, it utilizes only half of the power switch, lower modulation index to obtain high voltage gain. The proposed inverter is simulated and experimentally validated for single phase induction motor load with off-grid fashion. Nevertheless, the proposed inverter topology is a suitable version for both off-grid and on-grid applications.

The paper flow is organized in this way. Section 2 deals with the review of traditional Z-source inverter. The proposed modified Q-impedance converter fed coupled inductor multilevel inverter is explained in Section 3. The modified Space Vector PWM concept and control methods of the proposed inverter are shown in Sections 4–7 explain the simulation and experimentation, respectively. The conclusion is given in Section 8.

### **2. Review of Traditional Z-source Inverter**

### *2.1. Review of X-Z Source Topology*

Figure 1 illustrates the general impedance-source configuration with the impedance-source network for VSI. The basic Z-source network structure is generalized as a necessary X shaped two-port network using two L and C (linear energy storage elements) (Peng et al. 2003). Perhaps designing different Z-source network configurations to expand the converter performance, non-linear elements (switches, diodes, or/and combination of both) is added in the shape two-port network (Peng et al. 2003).

**Figure 1.** Impedance source inverter basic block diagram.

According to Figure 2, the impedance-source network has two modes of work. During the mode-1, inverter switch is short-circuited to provide the charging loop for an inductor with input DC source. This state is called the 'shoot-through (ST) state'. The second mode is the active mode, where energy stored in the inductors is supplied the load via inverter active mode switching. To connect this ST state with regular inverter active switch, there are a variety of modulation methods available. The modulation methods are distributing the ST states equally based on the modulation index of the inverter (Ma). The upper limit of the modulation index is *1-DS*. For the maximum boost modulation method, the modulation index is operated in extensive range (*Ma* ≥ *1*); however, the state involves larger (high rating), passive (L and C) elements [8], and correspondingly distributing the active states, the *Ma* has its maximum *Ma* ≤ *1–DS* [14]. Therefore, *VC1* = *VC2* = *VPL*. During this time, high-frequency generation in the active states causes higher frequency ripples, as shown in Figure 2a. According to the characteristics of Z-source inverter boost mode operation, the performance of inductor and capacitor components and DC-link voltage estimation related to input voltage function are shown in Figure 2b. From the characteristics curve, it is understood that the inverter matches the maximum DC-link voltage with the least input voltage. The inductor curve has a challenging dependency with ST time, and the quick capacitance value raise with the decreasing input voltage is essential. Hence, it is noted that passive elements (inductor and capacitor) are carefully chosen based on the input source voltage and power profile. The voltage rating capacitors are required since the voltage across the capacitors is always greater than the input voltage. Similarly, starting current and voltage surge happens because of the enormous inrush input current. Due to the resonance conditions, these surges are not avoidable, and the absence of bidirectional and soft-start capability limits the application for conventional Z-source topology.

**Figure 2.** Impedance source inverter operation: (**a**) impedance source circuit, shoot through (ST) state, an active state, (**b**) inductor current and capacitor voltage idealized condition waveforms.

To get improvement in the conventional ZSIs, Q-ZSIs are significantly improved to make use of single-stage power conversions. Considering the circuit operations and boosting, characterizes Q-ZSIs as having similar belongings with conventional ZSIs. Figure 3 illustrates the boost-mode characteristics of ZSIs. The Q-ZSIs differ from the conventional X shape-ZSIs by providing continuous input current through lower capacitor C2 [10]. Regardless of the control strategy of Q-ZSIs, during ST states, the duty ratio is limited concerning inductor rating directly. Hence, there is a possibility of continuous conduction with reduced input inductor current ripples. Besides, Q-ZSI provides the cross conduction switching states to provide the boosting by mutual sharing of inverter switching (top and bottom), which improves the inverter reliability [11]. The Q-ZSI has advantages of reduced component (*L* and *C*) ratings, lower switching stress, and continuous current mode operation. The standard ground-sharing option in the Q-ZSI is an additional feature, which is high indeed for PV modules [19]. Even though Q-ZSI has several advantages over conventional X-shape ZSI; it has low DC-link utilization in constant boost operation. To overcome this weakness, Q-ZSIs modified with additional passive components have been proposed [19,20].

**Figure 3.** Boost-mode characteristics of Z-source inverter; (**a**) DC-link voltage versus input voltage, (**b**) inductance versus input voltage, and (**c**) input voltage response versus change in capacitances.

### *2.2. Di*ff*erent Advanced Z-Source Topologies*

Due to the advantages and challenges, power electronics researchers have given much interest in impedance-source topology development. These topologies are categorized into two ways; 1. Transformer based and 2. Without transformer (non-magnetically coupled). Figure 4a–f shows the basic different impedance source topologies.

Selected limitations are present in non-magnetically coupled topologies such as low modulation ratio and lesser input-to-output gain. Therefore, this topology needs higher DC-link voltage, which may increase the semiconductors stress needlessly. Besides, the circuit cost and size for these converters are undesirable. Even though the magnetically coupled converters are attractive for their boosting performance, due to the higher DC ripple, the inverter suffers from high harmonics. The disadvantages of magnetically coupled topologies are; (1) raising the shoot-through and magnetizing current while switching; (2) the tightly coupled transformer leads to low leakage impedance; and (3) the need for the snubber circuit is mandatory when the coupling is not fulfilled. Hence, non-magnetic type converters are not highly preferred for PV fed applications [6]. Considering the non-magnetic type converters group, X-shape and Q- impedance converters offer low passive components rating, less duty cycle conversion ratio, and direct conversion. However, it has the poor performance to maintain the input current, reverse blocking capability for the switch, buck-boost operation, absence of bidirectional conversion and direct current control ability. Hence, the paper proposes a coupled inverter connected modified Q-impedance converter to provide single conversion mode power flow operation with multi-level output.

**Figure 4.** Different Z-source topologies; (**a**) Z-source network, (**b**) Quasi-source network, (**c**) Modified Quasi-source network, (**d**) Trans Z-source network, (**e**) T-source network, (**f**) Y-source network.

### **3. Proposed Modified Q- Impedance Converter Fed Coupled Inductor Multilevel Inverter.**

The traditional Z source inverters can only allow unidirectional power conversion flow with boosting operation. Nevertheless, the proposed topology is different from the conventional Z source inverter or Q-ZSI family to exchange the diode for bi-directional power flow; the proposed Q-ZSI achieve the boosting capability with single-stage conversion associated with the inverter switching scheme as shown in Figure 5. The first suggestion of a proposed modified Q-impedance network is to obtain the continuous input current is controlled possibility. It consists of the three operating states; (1) active state, (2) shoot-through state, and (3) open-zero states. When related to the conventional X-Z/Q-Z topology, the proposed structure streams the minimum DC voltage on capacitor C2 as well as deliver continuous input current [11,19]. Acknowledging straightforwardness in the control strategy for the proposed quasi-Z-source MLI functions with two operating modes; (1) shoot-through (ST) and, (2) non-shoot-through (NST). In ST mode, among all inverter phase leg, only one leg is conducting for providing ST. In NST mode, all the three leg switches in the inverter are forming the switching states to make a level in MLI. Hence, the inverter is working similar to a standard inverter. The current Z-source inverter switching states are premeditated with two zero states, and six active states. Figure 6 shows the Proposed modified Q-impedance network. The proposed inverter possesses the two open-zero, six active, and one shoot-through states.

**Figure 5.** Proposed modified Q-impedance converter fed coupled inductor multilevel inverter (MLI).

**Figure 6.** Proposed modified Q-impedance network.

State-1: Figure 7a shows the active states of the inverter. This mode assumes inductors, *L*<sup>1</sup> and *L*<sup>2</sup> and capacitors, *C*<sup>1</sup> and *C*<sup>2</sup> with chosen identical values as *VC*<sup>1</sup> = *VC*<sup>2</sup> = *VC, VL*<sup>1</sup> = *VL*<sup>2</sup> = *VL* to maintain a symmetrical output nature. The Kirchhoff's voltage law is applied in Figure 7a,

$$V\_{C1} + V\_{L1} = V\_{C2} + V\_{L2} = V p V + V\_{L5} = V\_{ab} \tag{1}$$

**Figure 7.** States of proposed Q- impedance network topology; (**a**) State-1: active state, (**b**) State 2: shoot-through states, (**c**) State-3: open-zero states.

Considering the steady-state average voltage of the inductors in one switching event must be zero. *VL*<sup>1</sup> = *VL*<sup>2</sup> = *VLs* = *VL* = <sup>1</sup> *T T* <sup>0</sup> *VL*(*t*)*dt* <sup>=</sup> *<sup>0</sup>*. From Equation (1), the steady-state voltage average of inductors is zero at one single switching period. Hence,

$$V\_{\mathbb{C}1} = V\_{\mathbb{C}2} = V\_{\mathbb{C}} = V\_{\mathbb{P}V} \tag{2}$$

State-2: In this shoot-through state, when any inverter leg is shorted, the PV array voltage is zero, and the diode is off. Thus, the inverter output voltage is zero due to short circuit as shown in Figure 7b, from the equivalent circuit of Figure 7b the KCL equation is given below,

$$V\_{\mathbb{C}1} = V\_{\mathbb{C}2} = V\_{\mathbb{C}} = V\_{PV} = 0 \tag{3}$$

State-3: This is considered to be an open-zero state, where the inverter is switching legs act as an open circuit, and therefore the added capacitor voltages (*VC*<sup>1</sup> and *VC*2) appear across the *Vab*. Now, the inductor (*L*<sup>1</sup> and *L*2) currents flow through diode D1 to charge the capacitors (*C*<sup>1</sup> and *C*2) as exposed in Figure 7c.

From the circuit operation of the proposed inverter, the total switching period is classified as *TA* (active state switching time), *Tsh* (shoot-through state switching time), and *Top* (open-zero state switching time) within one switching cycle, *TA*+*Tsh*+*Top* =1. Considering any of the three inductors voltage, *VL* in different states; state-1: *VL*= *Vin-Vout*, state-2: *VL*= *Vin*, state-3: *VL*= *Vin*−*2VC*.

Since, *VL* = <sup>1</sup> *T T* <sup>0</sup> *VL*(*t*)*dt* <sup>=</sup> <sup>0</sup>

$$V\_L = T\_A(V\_{in} - V\_{out}) + T\_{sh}V\_{in} - T\_{op}V\_{in} = 0\tag{4}$$

$$V\_{b\text{boost}} = \frac{\left(T\_A + T\_{sh} - T\_{op}\right)}{T\_A} V\_{PV} \tag{5}$$

From *TA*+*Tsh* = 1 − *Top* Hence,

$$V\_{\text{boost}} = \frac{\left(1 - 2T\_{\text{op}}\right)}{T\_A} V\_{PV} \tag{6}$$

The converter DC output voltage boosting (*Vboost)* has two control degrees of choice (*TA and Tsh*). Figure 8a shows the graphical understanding between *Vboost* and input voltage (*VPV*) concerning duty cycle *DA*. Here, the operation is split into two modes as (1) Mode-1: without open-zero states, and (2) Mode-2: towards short-zero states to open-zero states.

**Figure 8.** (**a**) Converter operation in different modes, Vboost / input voltage (VPV) for duty cycle DA, (**b**) energy storage capability and voltage stress radar graph of conventional QZ and proposed QZ.

**(a) (b)**

In mode 1 the *Top* = 0 output voltage depends on the parameter *TA* = 1 − *(Top*+*Tsh).* The entire range of the operation depends on the *TA* active state switching time. The controlling of the parameter *TA* decides the boosting capability of the MLI.

In Mode-2, the converter is in shoot-through states, where *Top* = 1 − *TA*. Hence the converter provides minimum voltage gain with a specified duty ratio of *TA*. When converter operation moves from shoot-through states to the open-zero states, the output gain would be situated in the middle of the Mode-1 and Mode-2. The marked red area in Figure 8a shows the mode shift of the converter. Therefore, the converter voltage output can be adjusted to the desired values with two control degrees of freedom *Top* and *TA*. Figure 8b shows the radar graph of energy storage capability on *C*, *L*, diode voltage stress and switch voltage stress in boost mode for conventional QZ and proposed QZ. It shows the proposed QZ have better energy storage capability and lesser diode and switching voltage stress than conventional QZ.

### **4. Modes of Operation of Coupled Inductor MLI**

The proposed coupled inductor MLI contains a structure having six switches in three legs (u, v and w). The leg v and leg w are connected with identical turns coupled inductor (LM1 and LM2). The ST operation is done through any leg. If the leg u is used for ST, then the switch S1 and S2 are turned ON simultaneously. Since the ST is allowed in any of the MLI legs, the switching reliability is significantly improved. During the Non-ST (active state), the MLI is functioning with either one upper switch and two-lower switches/two-upper switches, and one-lower switch. Hence, during the active state, the inverter is operating with eight modes of operation to produce five-level voltages *(*−*Vdc,*−*Vdc*/*2, 0, Vdc*/*2, and Vdc*).

During the regular inverter operating conditions, the boosted voltage is appearing across the inverter and provides pure DC current. For the period of the ST time, the inductor is maintaining its voltage precisely equal to capacitor voltage VC and hence current increases through the inductors leniently and limits the inductor current ripples. The eight modes of operation and their corresponding equivalent circuits of the proposed coupled inductor connected MLI is illustrated in Figure 9.

**Figure 9.** Coupled inductor MLI.

It is a single-phase circuit with two legs associated with coupled circuits. The quasi fed MLI provides *Vpv* + *VS* as input voltage to the coupled inductors (*LM*<sup>1</sup> and *LM*<sup>2</sup>*)*. The mutual inductance (M) of the coupled inductors provides the five-level voltage output with a reduction of the switching devices. The level making of the inverter is done through the *LM*<sup>1</sup> and *LM*<sup>2</sup> with the identical sum. The inductor *LM*<sup>1</sup> = *LM*<sup>2</sup> = *L* is connected between leg v and w. The voltage equation can be expressed as,

$$L\frac{di\_v}{dt} - M\frac{di\_w}{dt} = V\_{in} - V\_{lm} \tag{7}$$

$$L\frac{di\_w}{dt} - M\frac{di\_v}{dt} = V\_{\text{uu}} - V\_{l\text{v}} \tag{8}$$

where, *Vin* = input voltage, *Vbn* = load voltage, and *Vwn* = w leg voltage

Applying current law of Kirchhoff's', the leg current can be written as,

$$i\_u + i\_v + i\_w = 0\tag{9}$$

Hence,

$$V\_{lm} = \frac{V\_{vn} + V\_{vm} + (L - M)\frac{di\_u}{dt}}{2} \tag{10}$$

The inverter leakage inductance *LM*<sup>1</sup> and *LM*<sup>2</sup> are designed approximately equal to the mutual inductance value; hence leakage inductance equals mutual inductance (*L* = *M*). Therefore, the voltage equation on *Vbn* can be written as,

$$V\_{\rm lv} = \frac{V\_{\rm vn} + V\_{\rm vnv}}{2} \tag{11}$$

The voltage output of the inverter can be delivered as,

$$V\_{ab} = V\_{an} - V\_{bn} = V\_{an} - \left(\frac{V\_{\text{vn}} + V\_{\text{uvn}}}{2}\right) \tag{12}$$

$$V\_{ab} = \frac{V\_{ab}}{2} - \frac{\left( + \frac{V\_{ab}}{2} + \frac{V\_{ab}}{2} \right)}{2} = 0\tag{13}$$

The different modes of operation of active inverter switching for level making are explained as follows;

Mode-1: During Mode-1, the inverter switches S1, S4, and S6 are turned ON, and S2, S3, and S5 are turned OFF (see Figure 10). Hence, from Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> *Vab* 2 − <sup>−</sup> *Vab* <sup>2</sup> <sup>−</sup> *Vab* 2 <sup>2</sup> = *Vdc*.

**Figure 10.** During mode 1 the inverter switches S1, S4, and S6 are turned ON.

Mode-2: During Mode-2, the inverter switches S1, S4, and S5 are turned ON, and S2, S3, and S6 are turned OFF (see Figure 11). Hence, the inverter produces half of the *Vdc* (*Vs* = inverter input voltage). <sup>−</sup> *Vab* <sup>2</sup> <sup>+</sup> *Vab* 

From Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> *Vab* 2 − 2 <sup>2</sup> <sup>=</sup> *Vdc* 2 .

Mode-3: During the Mode-3, the inverter switches S1, S3, and S6 are turned ON, and S2, S4, and S5 are turned OFF (see Figure 12). Hence, the inverter produces half of the *Vdc*. From Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> *Vab* 2 − + *Vab* <sup>2</sup> <sup>−</sup> *Vab* 2 <sup>2</sup> <sup>=</sup> *Vdc* 2 .

**Figure 11.** During Mode-2, the inverter switches S1, S4, and S5 are turned ON.

**Figure 12.** During mode 3 the inverter switches S1, S3, and S6 are turned ON.

Mode-4: During Mode-4 the inverter switches S1, S3, and S5 (all upper switch) is turned ON, and S2, S4, and S6 (all lower switch) are turn OFF showing in Figure 13. Hence, the inverter produces zero output voltage. From Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> *Vab* 2 − + *Vab* <sup>2</sup> <sup>+</sup> *Vab* 2 <sup>2</sup> = 0.

**Figure 13.** During Mode-4 the inverter switches S1, S3, and S5 are turned ON.

Mode-5: During Mode-5 the inverter switches S2, S4, and S6 (all lower switch) are turned ON, and S1, S3, and S3 (all upper switch) are turned OFF as shown in Figure 14. Hence, the inverter produces zero output voltage. From Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> <sup>−</sup> *Vab* 2 − <sup>−</sup> *Vab* <sup>2</sup> <sup>−</sup> *Vab* 2 <sup>2</sup> = 0.

**Figure 14.** During mode 5 the inverter switches S2, S4, and S6 are turned ON.

Mode-6: During Mode-6, the inverter switches S2, S4, and S5 are turned ON, and S1, S3, and S6 are turned OFF (see Figure 15). Hence, the inverter produces half of the *Vdc*. From Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> <sup>−</sup> *Vab* 2 − <sup>−</sup> *Vab* <sup>2</sup> <sup>+</sup> *Vab* 2 <sup>2</sup> <sup>=</sup> <sup>−</sup> *Vdc* 2 .

**Figure 15.** During mode-6 the inverter switches S2, S4, and S5 are turned ON.

Mode-7: During Mode-7, the inverter switches S2, S3, and S6 are turned ON, and S1, S4, and S5 are turned OFF (see Figure 16). Hence, the inverter produces half of the *Vdc*. From the Equation.12 the load voltage is derived as, *Vab* <sup>=</sup> <sup>−</sup> *Vab* 2 − + *Vab* <sup>2</sup> <sup>−</sup> *Vab* 2 <sup>2</sup> <sup>=</sup> <sup>−</sup> *Vdc* 2 .

**Figure 16.** During Mode-7 the inverter switches S2, S3, and S6 are turned ON.

Mode-8: During Mode-8, the inverter switches S2, S3, and S5 are turned ON, and S1, S4, and S6 are turned OFF (see Figure 17). Hence, the inverter produces full of the *Vdc* in negative. From Equation (12) the load voltage is derived as, *Vab* <sup>=</sup> <sup>−</sup> *Vab* 2 − + *Vab* <sup>2</sup> <sup>+</sup> *Vab* 2 <sup>2</sup> = −*Vdc*.

**Figure 17.** During Mode-8 the inverter switches S2, S3, and S5 are turned ON.

Table 1 shows the consolidation of the eight modes of operations of the inverter. Of these eight modes, six modes are producing the voltage in different forms between +*Vdc to* −*Vdc*. The Mode-4 and Mode-5 are producing the zero voltages, and hence, any one of the modes can be used for zero voltage. Figure 18 illustrates the all mode operation output voltage structure for proposed MLI.


**Table 1.** Switching table for the proposed topology.

**Figure 18.** Output voltage structure for proposed MLI.

### **5. Modified Space Vector PWM**

The Space Vector PWM is a continuous switching PWM technique, which explicitly selects the active and zero states placed within the carrier period [30]. While designing for the boost converter circuitry, the vector-based algorithm possesses the additional switching states which must be imposed to acquire a higher voltage gain in the traditional impedance source inverters. It may lead to impact the switches in the form of stress or failure of a switch [8]. While looking into the traditional strategy, the upper and lower switch combination must be short as the voltage gain may impose distortion on

voltage. The proposed space vectors consist of normalized state operation, which generates the voltage gain by operating u, v, w legs upper or lower switches, as shown in Figure 10. The condition ST is incorporated with the regular zero vector operation. The projected control algorithm realizes the least number of switching operations to improve the efficiency of an inverter over one switching cycle, as indicated in Figure 18. The operation time for each period and every switching cycle of the dead time for short-zero as well as open-zero states, should be pre-calculated. The six modes (Mode-1 to Mode-6) of switching states are aligned with active vector and Mode-4, and Mode-5 are placed in zero vector.

In a three-phase balanced system, the voltage equation of Space Vector PWM is predefined as,

$$V\_{ref}T\_s = V\_1T\_1 + V\_2T\_2 + V\_0 \frac{T\_0}{2} \tag{14}$$

Here, *Vref* is a reference vector (target vector), From Figure 19b in the sector-1, vector *Vref* can be synthesized as,

$$V\_{ref} = V\_1 \frac{T\_1}{T\_s} + V\_2 \frac{T\_2}{T\_s} + V\_0 \frac{T\_0}{2T\_s} \tag{15}$$

**Figure 19.** (**a**) Dwell time switching states synthesis, (**b**) proposed control strategy *Vref* slope.

The *V*<sup>1</sup> and *V*<sup>2</sup> are the adjustment operating vectors at *T*<sup>1</sup> and *T*2. The *T*<sup>s</sup> is a switching period, and T0 is zero vector time. The pulse period of the active vector is calculated from the below equation when operating in a given switching period *Ts.*

$$T\_1 = \frac{2}{\sqrt{3}} + |V|\sin\left(\frac{2\pi}{3} - \theta\right)T\_s\tag{16}$$

$$T\_2 = \frac{2}{\sqrt{3}}|V|\sin\left(\theta - \frac{\pi}{3}\right)T\_s\tag{17}$$

Hence, the zero-vector time:

$$T\_0 = T\_s - T\_1 - T\_2 = \left(1 - \frac{2}{\sqrt{3}}|V|\sin(\theta)T\_s\right) \tag{18}$$

The proposed Space Vector PWM strategy is selecting the voltage vector switching sequence, according to *Vref*. The *Vref* is the reference vector of output *Vab*. Hence, the output voltage of the inverter is selected by using switch S1. According to Table 1, when S1 is turned ON, the inverter output voltage Vab is either in positive voltage or zero. Hence the relation is framed between S1 and *Vab*, for the smooth implementation.

When S1 is turned ON, the *Vab* ≥ 0 and S1 is low, consequently *Vab* ≤ 0. Nevertheless, the other switching states should be appropriately combined with S1 to make the desired voltage level of the inverter. In order to select the stable switching states, the dwell time (*Td*) of the switch is calculated in every switching frequency *Ts* sampling period. The dwell time concerning inverter DC-link voltage *Vin* is defined as:

$$T\_d = \frac{\left|V\_{ref}\right| - kV\_{in}}{V\_{in}}\tag{19}$$

Here, the *Vref* is related to the sampling period *Ts.* The ST duty ratio for inverter must be predefined for every switching cycle by adding the ST time within the TS. Figure 19a shows the dwell time control of inverter, and it is related to *TS (*= 1/*fS)*, and *Vin*.

To locate the selected switching vector for the *Vref*, a new method of vector identification is proposed. The strategy is to locate the *Vref* value and to find out the different switching states in the space vector diagram (SVD) hexagon (see Figure 20). Hence the control strategy is designed in two steps: (1) locate the real and imaginary equivalent of *Vref*, and (2) find out the control vector within the sector.

**Figure 20.** Space vector diagram and switching table.

Figure 19b represents the proposed control strategy in which, from the *Vref* slope, the real and imaginary equivalent of *Vx* and *Vy* are determined and compared with the targeted switching vector *V*<sup>1</sup> and *V*1*'.* Here, when the condition is *Vy* < *a Vx* + *b*, then *V1* is selected. Else *V*1*'* is selected. Once this targeting vector is selected, the Td is calculated and then active switching time, ST time and zero switching time is calculated according to the inverter output voltage requirement. Figure 20 represents the overall SVD for the proposed control strategy. Here, the entire active targeted vector is placed inside the SVD sector until the hexagonal boundary. The zero vectors [1, 1, 1] and [0, 0, 0] are placed at the origin. The control switching vector is directly related to the inverter modulation index (*ma*), where *Vin* and Vref are related to the inverter output. The maximum inverter control in the linear modulation range is allowed only until <sup>2</sup> √ <sup>3</sup> *Vin* [23]. The switching pulse patent of the proposed PWM is prearranged in Figure 21. Once the active and zero states are done, the ST state patent is included in the switching sampling period. The ST state is calculated based on the VPV value. Figure 22 represents the inverter switching pulse. The zero-state sharing ST state and ST time is calculated directly from the following equations:

$$T\_{sh} = \frac{\left(|V\_{db}| - BV\_{PV}\right)}{V\_{PV}}\tag{20}$$

$$B = \frac{|V\_{ab}|}{V\_{PV}}\tag{21}$$

where *B* is a boosting factor.

**Figure 21.** Space vector PWM algorithm and switching table.

**Figure 22.** Proposed impedance source Space vector PWM and switching table.

### **6. Simulation Result**

The PV powered Q-impedance network connected coupled inductor multilevel inverter and its control switching schemes strategy is designed in MATLAB/Simulink software simulation platform (Figure 23). The inverter is powered by 500 Watts peak power PV. The PV module is arranged to get 100 to 120 V to meet the 330 V DC-link voltage of the inverter. The insulation level of the PV array is 1000 W/m<sup>2</sup> for 10 s, 800 W/m<sup>2</sup> from 10 s to 30 s. The temperature of the PV array is 400◦C for 10 s and 300 ◦C from 10 s onwards. The variation in PV array power input can be overcome by the Perturb and Observe the MPPT algorithm to obtain the constant DC voltage from the PV array. Table 2 shows the simulation parameter for the proposed inverter. The inverter performance is investigated with and without LC filters.

**Figure 23.** Simulation diagram of the proposed photovoltaic (PV) powered modified Q-impedance converter fed coupled inductor MLI.

**Table 2.** Simulation Parameters.

In order to validate the inverter performance simulation is carried out when the PV input power is kept at 500 W and the input PV voltage, *VPV* is maintained at 120 V. The impedance network duty ratio (*TA* and *TST*) is maintained at 20% to 25% to preserve the inverter input (DC-link) voltage 250 to 350 V. The inverter operation is investigated with their modulation index range *ma* = 0 to 0.866. The simulation study is carried out for different impedance network duty ratio *TST* and inverter modulation index range *ma*. Initially, the inverter is operated with a maximum modulation index of 0.886 with the ST switching time *TST* of 25%. Figure 24 shows the PWM pulse of inverter switches S1 and S6. The ST time between switch S1 and S2 is represented in Figure 25, in which the 25% switching time is used for ST event, and hence impedance network can boost input PV voltage nearly 290% and achieved 349 V in the output side of the impedance network (DC-link voltage of inverter). During the operation, the voltage of impedance network capacitors *VC1* and *VC2* shows uniform charging and discharging profile (see Figure 26) along with the uniform inductors current profile ( see Figure 27). Hence, during the ST

period, the impedance network can draw the constant current and provide a regulated boost DC-link voltage to the MLI. Figures 28 and 29 illustrates the captured the inverter input DC-link voltage and multi-level output voltage across the load (*Vab*) respectively. From the results, it can be seen that the 120 V input PV voltage is boosted to 349 V. The inverter load voltage *Vab* is observed as 247.3 V (RMS). The corresponding *Vab* voltage THD spectrum is shown in Figure 30 (without filter). Here the inverter voltage THD is observed as 14.15%, which is higher due to the participation of passive elements in the impedance network. Hence the LC filter is connected across the load, and harmonics spectrum is captured (see Figures 31 and 32). The output voltage THD perceived is very less as 2.81%. The inverter load current waveform and its corresponding current THD spectrum are captured and shown in Figure 33a,b. As expected, the current THD is very less (1.7%).

**Figure 24.** Modified Q- impedance converter fed coupled inductor MLI.

**Figure 25.** ST state representations of S1 and S2.

**Figure 26.** Voltage waveform of impedance network capacitors at TST = 25%; (**a**) *VC1*, (**b**) *VC2*.

**Figure 27.** Current waveform of impedance network inductor at TST = 25%; (**a**) *L1*, (**b**) *L2*.

**Figure 28.** Inverter DC-link voltage at *TST* = 25%.

**Figure 29.** (**a**) Inverter output voltage at *TST* = 25% without filter, (**b**) zoomed view of the inverter output voltage at *TST* = 25% without a filter.

**Figure 30.** THD profile of inverter output voltage when *TST* = 25% without a filter.

**Figure 31.** Inverter output current at *TST* <sup>=</sup> 25% with filter.

**Figure 32.** THD profile of inverter output voltage at *TST* = 25% with filter.

(**b**)

**Figure 33.** (**a**) Inverter output current at *TST* = 25%, (**b**) THD profile of inverter output current at *TST* = 25%.

Next, the simulation study is extended to *TST* = 20% with 0.866 *ma*. In this operating condition, the impedance network has boosted the input PV voltage to nearly 230% and maintaining the inverter DC-link voltage at 280 V. The observed DC-link voltage and impedance network capacitor voltages are shown in Figures 34 and 35. While operating the inverter with a modulation index value of *ma* = 0.866, the inverter has produced the output voltage of 197.23 V, as shown in Figure 36. The inverter output voltage THD is shown in Figure 37. Using LC filter in the inverter output terminal similar to 25% *TST* performance, the voltage THD for *TST* = 20% is maintained lesser value as 2.71%. Correspondingly the current THD is observed as 1.70%. In order to validate the higher ST switching time, the simulation is extended to *TST* = 30% with different modulation indices. During this operating condition, the impedance network passive elements are utilized fully and hence the voltage THD triumphs to a higher value. Figures 38 and 39 illustrates the inverter output voltage and its corresponding voltage THD (without LC filter) for *ma* = 0.6. Though the inverter voltage is preserved as 292V nearly, the voltage THD is poor. Tables 3 and 4 illustrates inverter voltage and its THD performances for *ma* = 0.86 and *ma* = 0.6 through different duty ratio from 10% to 30% without and with an LC filter, respectively.

**Figure 34.** Inverter DC-link voltage at TST = 20%.

**Figure 35.** Voltage waveform of impedance network capacitors at TST = 20%; (**a**) VC1, (**b**) VC2.

**Figure 36.** (**a**) Inverter output voltage at *TST* = 25% without filter, (**b**) zoomed view of inverter output voltage at *TST* = 25% without filter.

**Figure 37.** THD profile of inverter output voltage at *TST* = 25% without a filter.

**Figure 38.** (**a**) Inverter output voltage at *TST* = 30% without filter, (**b**) zoomed view of the inverter output voltage at *TST* = 30% without a filter.

**Figure 39.** THD profile of inverter output voltage at *TST* = 30%.

From the tabulated results, it could be seen that DC-link voltage has a linear variation with *DST*. However, the THD of the inverter voltage increases when increasing the *DST*. For any value less than or equivalent to *DST* 25% in any modulation index, the inverter provides a wide range of voltage variation with better voltage and current THD performance.


**Table 3.** Detailed simulation results for different duty ratio without an LC filter at *ma* = 0.86 and 0.6.

**Table 4.** Detailed simulation results for different duty ratio with an LC filter at *ma* = 0.86 and 0.6.


### **7. Experimental Result**

The proposed PV powered Q-impedance fed coupled inductor multilevel inverter experimental setup was built using six MOSFETs IRF640. The switching signals were associated with the MLI through gate driver TLP250. The switching frequency, *fs* of the inverter is fixed 10 kHz for the 50 Hz inverter output. The 500 W PV module is arranged to get 100 to 120 V to meet 330 V DC-link voltage to the MLI. The RL load (resistance = 10 Ω and inductance = 5 mH) and LC filter (inductance and capacitor values of 2.5 mH, and 50 μF respectively) are used in the inverter output terminal.

Figure 40 shows the experimental setup photograph. The impedance network and other parameters used for the inverter are the same as the simulation model given in Table 2. The control switching scheme strategy is designed in PIC16F778A microcontroller, and the collaborative results are shown in keyset two channels digital signal oscilloscope (DSO).

The experimentation is carried out for the 500W constant PV power for 100 V and 5 amps current. The impedance network duty ratio is maintained at 25% with the aim of inverter constant DC-link voltage 300V. The inverter operation is investigated with its modulation index range *ma* = 0 to 0.866. Initially, the inverter is operated with maximum *ma* = 0.886, and the results are captured. Figure 41 shows the PWM pulse of inverter switches S1 and S2. The ST time between switch S1 and S2 is represented, in which the 25% switching time is used for ST event, and hence impedance network can generate 300% boosting to maintain the DC-link voltage. Figure 42a shows the current waveform of impedance network inductor *L*<sup>1</sup> and *L*2. Figure 42b displays the voltage waveform of impedance network capacitors *C*<sup>1</sup> and *C*2. The voltage profile across the impedance network capacitors *VC*<sup>1</sup> and *VC*<sup>2</sup> are indicating that variation in the *VC*<sup>1</sup> and *VC*<sup>2</sup> are identical. It can be observed that voltages *VC*<sup>1</sup> and *VC*<sup>2</sup> are equally charging the voltage since both are connected in series. Hence the proposed impedance network can provide regulated DC-link voltage to the inverter. Figure 43a,b shows the inverter output voltage (without filters) and input voltage waveform at *ma* = 0.866. The results show the measured five-level inverter voltage with symmetrical set output voltage 0V, ± 125 V, ± 250 V. The THD value of load voltage is captured using power analyzer and is found to be about 17.1% (shown in Figure 44). The same experimentation is investigated further with filter, and the results are captured. Figure 45a,b shows the filtered output load and load current respectively, where the current and voltage are maintaining their THD lesser as 3.1% and 1.4% respectively (Figure 46a,b).

**Figure 40.** Experimental setup; (**a**) overall laboratory-scale 500 W PV powered modified Q-impedance fed coupled inductor MLI, (**b**) modified Q-impedance fed coupled inductor MLI.

**Figure 41.** PWM pulse generation (S1 and S2).

**Figure 42.** Experimental result; (**a**) boost inductor current (*iL1* and *iL2*), (**b**) voltage waveform of impedance network capacitors C1 and C2.

**Figure 43.** Experimental result; (**a**) inverter five-level output voltage, (**b**) quasi Z-source inverter input current waveform.

**Figure 44.** Experimental voltage THD spectrum without a filter.

**Figure 45.** Experimental result; (**a**) inverter output voltage with filter, (**b**) inverter output current waveform with filter.

**Figure 46.** Experimental result; (**a**) voltage THD spectrum with filter, (**b**) current THD spectrum with filter.

To understand the inverter input current control, the duty cycle is varied to 25% and 30%, and results are observed. As expected, the inverter is maintaining the input current regulation at 25% *DST*. However, when *DST* is applied to 30%, the impedance network starts losing its input current regulation. Figure 47 illustrates the output voltage of MLI and impedance input current at 25% and 30% *DST*. From the results, it could be seen that the input PV voltage is boosted via the impedance network to achieve the load voltage of 230 V peak to peak. The DC-link voltage is regulated with a minor ripple of 3%, and hence inverter can maintain its half symmetry and THD of the output voltage is perceived as less. The interesting point to notice at this stage is that the inverter can draw constant current since the impedance network input inductor LS limits the current. The proposed inverter reliability study is conducted for different inverter operating conditions. Table 5 illustrations the switching loss, inverter efficiency, and THD of the proposed inverter for *DST* 10% to 30% and ma = 0.86. From the results, it can seem that the efficiency is higher in all duty cycle. During the 10% *DST*, the inverter efficiency is about 95.68%. However, there is a small dip inefficiency at 20% and 30% duty cycle.

**Figure 47.** Experimental result; (**a**) quasi Z-source coupled MLI output voltage and input current at *DST* = 25%, (**b**) quasi Z-source coupled MLI output voltage and input current at *DST* = 30%.

**Table 5.** Switching loss, inverter efficiency, and THD of the proposed inverter for *ma* = 0.86 and *fs* = 10 kHz concerning *DST* from 10% to 30%.


The proposed inverter topology, in comparison with other reported topologies for the gain accomplishments, are deliberated in Table 6. In terms of passive element usage and maximum achievable voltage gain, the proposed topology is better than topology presented in [45–47]. By comparing the proposed topology with inverter proposed in [36], though the proposed inverter used one extra inductor, the voltage gain is high (3 times). Figure 48 illustrates the passive components rating, cost, boosting, and THD comparisons with other similar topologies [31,39,48]. The proposed inverter topology attains fewer passive elements usage, higher voltage gain conversion and better voltage THD than [31,39,48]. Thus, the proposed inverter topology presents its efficiency and suitability for PV standalone and grid-connected systems.

**Table 6.** Switching loss, inverter efficiency, and THD of the proposed inverter for ma = 0.86 and fs = 10 kHz concerning *DST* from 10% to 30%.


**Figure 48.** Passive components rating, cost, boosting, and THD comparisons; (**a**) Reference [39], (**b**), Reference [41], (**c**) Reference [39], (**d**) proposed QZ Inverter.

### **8. Conclusions**

The proposed Q-source MLI coupled inverter ZSI is a combination of modified Q-source impedance network with six switches coupled inductor connected single-phase five-level MLI. The quasi-Z source coupled inductors MLI tied photovoltaic system with modified space vector PWM produces a maximum voltage gain of 140%. The suggested topology generates the five-level output voltage with the higher voltage gain (maximum voltage gains of 310%) with exceptionally low voltage and current THD. Besides, the proposed MLI reduces the switching stress on the inverter for all the duty cycles in the switching algorithm, when increasing the duty cycle, the boost factor also increases. The proposed quasi Q-ZSI has the merits of operation such as reliability, reduced passive components, voltage boosting capability and reduction in switching stress. The modified space vector PWM is proposed to integrate the boosting and regular inverter switching state within one sampling period.

In comparison with other MLI, it utilizes only half of the power switch, lower modulation index to acquire high voltage gain. The performance of the proposed boost MLI topology and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for stand-alone and grid-connected PV applications.

**Author Contributions:** M.P. and B.C. have developed the proposed research concept, and they both are involved in studying the execution and implementation with statistical software by collecting information from the real environment and developed the simulation model for the same. S.K.V., S.P., L.M.-P., Y.A. shared their expertise and validation examinations to confirm the concept theoretically with the obtained numerical results for its validation of the proposal. All authors are to frame the final version of the manuscript as a full. Moreover, all authors involved in validating and to make the article error-free technical outcome for the set investigation work.

**Funding:** No source of funding for this research activity.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **H**<sup>∞</sup> **Mixed Sensitivity Control for a Three-Port Converter**

### **Jiang You 1, Hongsheng Liu 1, Bin Fu 2,\* and Xingyan Xiong <sup>2</sup>**


Received: 8 May 2019; Accepted: 4 June 2019; Published: 12 June 2019

**Abstract:** The three-port converter (TPC) obtains major attention due to its power density and ability to dispose different electric powers flexibly. Since the control models of the TPC are derived from particular steady state work point through small signal modeling method, the model parameters usually be deviated from their normal values with the change of operation and load conditions. Furthermore, there are couplings and interactions in power delivery between different ports, which have a significant influence in the dynamic control performance of the system. In this paper, the H<sup>∞</sup> mixed sensitivity method is employed to design robust controllers for a TPC control system. Simulation results are given to demonstrate the effectiveness of the proposed scheme, and experimental studies are conducted on a prototype circuit to further validate the developed method. Compared to a traditional PI controller, it shows that a mixed sensitivity based robust controller manifest balanced performance in model parameters changes attenuation and dynamic control performance.

**Keywords:** three-port converter; parameters change; mixed sensitivity; H<sup>∞</sup> control

### **1. Introduction**

Sustainable energy generation, such as photovoltaics, wind and fuel cells, etc. have been widely investigated in the last decade. As shown in Figure 1, various energy sources can be interfaced to a DC microgrid or a common DC bus for direct utilization or further conversion through their separated power converters. These converters are linked together at the DC bus and controlled independently. In some systems, a communication bus might be included to transmit information and instruction for power management between different power conversion subsystems [1]. However, this structure has drawbacks in complexity, cost and power density due to utilization of a number of different power converters (the amount of power converters depends on the size of the whole power conversion system) and communication devices between individual subsystems. With the development of power electronics, the demand for light and compact power converters for renewable generation and industrial applications has been increasing steadily. The configuration of a DC microgrid using a multi-input converter in renewable energy generation system is shown in Figure 2, compared to the conventional structure presented in Figure 1. The power conversions for different energy sources are integrated into a single power converter which is denoted as a multi-port converter. This multi-input topology for combining diverse power sources can be a non-isolated direct connection [2–4] or an isolated magnetic coupling [5–7].

**Figure 1.** Conventional structure of a DC microgrid.

**Figure 2.** Multiport DC/DC converter based structure of a DC microgrid.

An isolated three-port converter is one of the recently developed multi-port power converters which have become attractive due to their compact structure, power density and flexibility in power conversion. Since the three windings of the high frequency transformer (HFT) share a common magnetic core, interaction and coupling of power delivery among the three different ports are unavoidable, and it is necessary to reduce the interactions between different ports through the reasonable control method. The decoupling control method is usually used in three-port converter control, while two single-input single-output (SISO) subsystems can be obtained by introducing appropriate decoupling compensations [8–11], and frequency control theory can be utilized to design controllers for each subsystem, respectively. However, the isolated three-port converter is a multiple-input multiple-output (MIMO) system, several phase-shifting angles and equivalent duty cycles can be used as control variables, and several voltages and currents of different ports can be used as output variables. Therefore, from the view of a MIMO system, a linear quadratic regulator (LQR) based method for three-port converter controller design is proposed in reference [12]. Theoretically, it seems that the LQR method has the capability to achieve a balanced control performance for different ports, however, it has relatively high sensitivity to the accuracy of system parameters (while the small signal models used for control system design are derived at a specific steady state operation point, and the parameters of the models will be varied with the change of operation point), moreover, the parameters design of the time domain based LQR method is relatively complex, and compared to traditional frequency domain design method, LQR method lacks physical meaning.

The topology of a typical full-bridge isolated three-port converter is shown in Figure 3a. For control system design, the linear small signal model can be derived by calculating the partial differential of current in each port, then two independent SISO subsystems can be obtained by feedforward decoupling compensation, and then classical frequency domain control theory can be adopted for control system design [13–15]. However, for those cases without considering the inductor, *L*d1, the double switching frequency component in *i*d1 has a negative impact on the power source (e.g., fuel cell and photovoltaic panel). Therefore, an LC circuit is utilized to suppress the high frequency current ripple. However, this can deteriorate the current control performance and can even cause a stability issue due to the resonant peak introduced by the LC circuit [16]. Although the negative impact of resonant issue can be relieved by decreasing the current control bandwidth, the desirable control performance of the system cannot be guaranteed.

**Figure 3.** Topology, equivalent circuit and modulation scheme of isolated three-port converter (**a**) topology of the isolated three-port converter, (**b**) equivalent Δ-connection circuit, (**c**) modulation scheme.

The H<sup>∞</sup> mixed sensitivity control is employed in this paper to address the aforementioned issues. This controller design method has prominent characteristic to balance control performance (e.g., disturbance rejection) and stability with consideration of model parameter deviations. In this method, the performance requirements and parameter uncertainties can be taken into account by designing appropriate weight functions with particular amplitude-frequency characteristic. Compared to the TPC control system designed by a traditional SISO based frequency method, the advantages of the proposed method mainly lie in two aspects, (1) the corrected TPC control system using H<sup>∞</sup> mixed sensitivity method has stronger abilities in load disturbance rejection with operation point change and model parameters variation. (2) Furthermore, the resonant peak of the corrected current control subsystem of TPC can be attenuated effectively, which is very helpful for improving the stability and dynamic performance of the current control system.

The rest of the paper is organized as follows. In Section 2, the topology, modulation scheme, power delivery relationship, and control-oriented small signal models are presented. H<sup>∞</sup> mixed sensitivity method and design results along with analysis are given in Section 3, a brief illustration of the conventional decoupling control method is also provided in this section for comparison purpose. The simulation and experiment results are presented in Section 4. Finally, the conclusion is drawn in Section 5.

### **2. Modeling of Isolated TPC**

### *2.1. Power Delivery*

The topology of an isolated TPC is shown in Figure 3a. As shown in this figure, the Port 1 is connected to a DC power source, such as a photovoltaic panel or a fuel cell. The load is supplied by Port 2, the batteries connected to Port 3 are used as energy storage (ES). *L*d1 and *C*d1 form an LC circuit to reduce the double switching frequency component in *i*d1. *C*d2 is used to smooth *v*d2 at Port2. The number of turns in the three windings of the high frequency transformer are *N*1, *N*<sup>2</sup> and *N*3, respectively. *L*1, *L*<sup>2</sup> and *L*<sup>3</sup> are the equivalent series inductances (including winding leakage and additional inductances) of the three transformer windings respectively. *v*d1, *v*d2 and *v*d3 are the voltages corresponding to the three ports. S1-S4, K1-K4 and Q1-Q4 are power switches of the full bridge converters in the three different ports. Taking the converter of Port 1 (converter 1) as an example, switches S1 and S3 are complementary to the switches S2 and S4 respectively and their duty cycles are all 50%, the phase shifting between legs a and b is 180◦. The switching patterns of the switching devices in converter 2 (the converter in Port 2) and converter 3 (the converter in Port 3) and the phase shifting between their two legs are identical to those of converter 1.

By transferring the parameters of converter 2 and converter 3 to converter 1, the simplified equivalent Δ-circuit of the TPC can be depicted as Figure 3b. In this figure, *v* <sup>2</sup>, *v* 3, *i* <sup>2</sup> and *i* <sup>3</sup> are the transferred voltages and currents of Port 2 and Port 3 respectively. The expressions of *L*12, *L*<sup>13</sup> and *L*<sup>23</sup> are given in (1).


(2)

in (1)

Taking *v*<sup>1</sup> as reference, the relationships of *v*1, *v* <sup>2</sup> and *v* <sup>3</sup> are shown in Figure 3c. The phases shifting between *v*<sup>1</sup> and *v* <sup>2</sup>, *v*<sup>1</sup> and *v* <sup>3</sup> are φ<sup>12</sup> and φ<sup>13</sup> respectively, and the phase shifting between *v* <sup>2</sup> and *v* <sup>3</sup> is φ23. By regulating φ12, φ<sup>13</sup> and φ23, the direction and values of power transfer between different ports can be controlled.

According to Figure 3b, the powers of Port 1, Port 2 and Port 3 can be expressed as (3).

⎧ ⎪⎪⎪⎪⎪⎪⎪⎨ *L* <sup>2</sup> <sup>=</sup> *<sup>N</sup>*<sup>2</sup> <sup>1</sup>*L*<sup>2</sup> *N*2 2

*L* <sup>3</sup> <sup>=</sup> *<sup>N</sup>*<sup>2</sup> <sup>1</sup>*L*<sup>3</sup> *N*2 3

⎪⎪⎪⎪⎪⎪⎪⎩

$$\begin{cases} P\_1 = P\_{12} + P\_{13} \\ P\_2 = P\_{21} + P\_{23} \\ P\_3 = P\_{31} + P\_{32} \end{cases} \tag{3}$$

In (3), *P*1, *P*<sup>2</sup> and *P*<sup>3</sup> are the powers of Port 1, Port 2 and Port 3, respectively. *P*<sup>12</sup> is the power transferred from Port 1 to Port 2, while *P*<sup>21</sup> is the power transferred from Port 2 to Port 1, and *P*<sup>12</sup> = −*P*<sup>21</sup> is always held. The relationships between *P*<sup>13</sup> and *P*31, *P*<sup>23</sup> and *P*<sup>32</sup> are *P*<sup>13</sup> = −*P*<sup>31</sup> and *P*<sup>23</sup> = −*P*32. The power equation for *P*<sup>12</sup> and *P*<sup>21</sup> can be written as (4). Since the fundamental power is close to the total power in each switching period, the fundamental power is used to formulate the power delivery model of TPC in this paper.

According to Figure 3c and Fourier series expansion, the fundamental phasor of *v*1, *v* <sup>2</sup> and *v* <sup>3</sup> can be formulated as (4).

$$\begin{cases} \dot{v}\_{1\text{f}} = \frac{4V\_1}{\pi\sqrt{2}}\angle 0 = V\_{1\text{f}}\angle 0\\ \dot{v}\_{2\text{f}} = \frac{4N\_1V\_2}{\pi N\_2\sqrt{2}}\angle -q\_{12} = V\_{2\text{f}}'\angle -q\_{12} \\ \dot{v}\_{3\text{f}} = \frac{4N\_1V\_3}{\pi N\_3\sqrt{2}}\angle -q\_{13} = V\_{3\text{f}}'\angle -q\_{13} \end{cases} \tag{4}$$

*V*1, *V*<sup>2</sup> and *V*<sup>2</sup> are the amplitudes of *v*1, *v* <sup>2</sup> and *v* <sup>3</sup> respectively.

Neglecting the influence of Port 3, Port1 and Port2 behave like a dual active bridge (DAB), the equivalent simplified circuit is shown in Figure 4.

**Figure 4.** Equivalent circuit model of a dual active bridge.

The current, *i*<sup>12</sup> can be expressed as (5).

$$i\_{12} = \frac{V\_{2\text{f}}' \sin \varphi\_{12}}{aL\_{12}} - \frac{j(V\_{1\text{f}} - V\_{2\text{f}}' \cos \varphi\_{12})}{aL\_{12}} \tag{5}$$

Combining (5) and considering the power factor angle, α, the fundamental power can be written as (6).

$$P\_{12} = -P\_{21} = V\_{1\text{f}} i\_{12} \cos \alpha = \frac{N\_1 V\_{1\text{f}} V\_{2\text{f}} \sin \varphi\_{12}}{N\_2 \alpha L\_{12}} \tag{6}$$

Similarly, the power transfer equations of Port 2 and Port 3 are given in (7)

$$\begin{cases} P\_{13} = -P\_{31} = \frac{N\_1 V\_{1f} V\_{3f} \sin \varphi\_{13}}{N\_3 \omega L\_{13}}\\ P\_{23} = -P\_{32} = \frac{N\_1^2 V\_{2f} V\_{3f} \sin(\varphi\_{13} - \varphi\_{12})}{N\_2 N\_3 \omega L\_{23}} \end{cases} \tag{7}$$

From (3), the power of Port 3 can be derived as *P*<sup>3</sup> = −(*P*<sup>1</sup> + *P*2), it indicates that the power of ES port is determined by the power of Port 1 and Port 2. Therefore Port 3 can be set as a free port. Combining (3) with (6) and (7), the powers of Port 1 and Port 2 can be represented as (8).

$$\begin{cases} P\_1 = \frac{N\_1 V\_{1\text{f}} V\_{2\text{f}} \sin \varphi\_{12}}{N\_2 \omega L\_{12}} + \frac{N\_1 V\_{1\text{f}} V\_{3\text{f}} \sin \varphi\_{13}}{N\_3 \omega L\_{13}}\\ P\_2 = -\frac{N\_1 V\_{1\text{f}} V\_{2\text{f}} \sin \varphi\_{12}}{N\_2 \omega L\_{12}} + \frac{N\_1^2 V\_{2\text{f}} V\_{3\text{f}} \sin (\varphi\_{13} - \varphi\_{12})}{N\_2 N\_3 \omega L\_{23}} \end{cases} \tag{8}$$

### *2.2. Small Signal Model of TPC*

According to (8), the average values of *i*d1 and *i*d2 are written as (9)

$$\begin{cases} \begin{aligned} \tilde{i}\_{\rm d1} &= \frac{N\_1 V\_{2\rm f} \sin \varphi\_{12}}{N\_2 \omega L\_{12}} + \frac{N\_1 V\_{3\rm f} \sin \varphi\_{13}}{N\_3 \omega L\_{13}} \\ \tilde{i}\_{\rm d2} &= -\frac{N\_1 V\_{1\rm f} \sin \varphi\_{12}}{N\_2 \omega L\_{12}} + \frac{N\_1^2 V\_{2\rm f} \sin (\varphi\_{13} - \varphi\_{12})}{N\_2 N\_3 \omega L\_{23}} \end{aligned} \tag{9}$$

The small signal disturbance of *i*d1 and *i*d2 can be obtained by calculating the partial derivatives of *i*d1 and *i*d2 at a steady state work point A (φ120, φ130) in (9), the result is shown in (10).

$$
\begin{bmatrix} \hat{\mathbf{i}}\_{\mathrm{d}2} \\ \hat{\mathbf{i}}\_{\mathrm{d}1} \end{bmatrix} = \begin{bmatrix} \mathbf{G}\_{11} & \mathbf{G}\_{12} \\ \mathbf{G}\_{21} & \mathbf{G}\_{22} \end{bmatrix} \begin{bmatrix} \boldsymbol{\phi}\_{12} \\ \boldsymbol{\phi}\_{13} \end{bmatrix} = \mathbf{G}\_{\mathbf{A}} \begin{bmatrix} \boldsymbol{\phi}\_{12} \\ \boldsymbol{\phi}\_{13} \end{bmatrix} \tag{10}
$$

where

$$\begin{cases} G\_{11} = -\frac{N\_1 V\_{1f} \cos \varphi\_{120}}{N\_2 \omega L\_{12}} - \frac{N\_1^2 V\_{2f} \cos(\varphi\_{130} - \varphi\_{120})}{N\_2 N\_3 \omega L\_{23}} \\\ G\_{12} = \frac{N\_1^2 V\_{2f} \cos(\varphi\_{130} - \varphi\_{120})}{N\_2 N\_3 \omega L\_{12}} \\\ G\_{21} = \frac{N\_1 V\_{2f} \cos \varphi\_{120}}{N\_2 \omega L\_{12}} \\\ G\_{22} = \frac{N\_1 V\_{2f} \cos \varphi\_{130}}{N\_3 \omega L\_{13}} \end{cases} \tag{11}$$

In (10), it can be seen that there are cross couplings between ˆ*i*d2 and φˆ <sup>13</sup> and also between ˆ*i*d1 and φˆ <sup>12</sup> which are caused by *G*<sup>12</sup> and *G*<sup>21</sup> respectively. Therefore, decoupling is needed to improve dynamic control performance of the three-port converter. The small signal model diagram with decoupling compensations is shown in Figure 5. In this figure, the feedforward decoupling terms *H*<sup>12</sup> and *H*<sup>21</sup> are given in (12).

$$\begin{cases} \begin{aligned} H\_{12} &= -\frac{G\_{12}}{G\_{11}}\\ H\_{21} &= -\frac{G\_{21}}{G\_{22}} \end{aligned} \end{cases} \tag{12}$$

**Figure 5.** Decoupled model.

Therefore, the small signal model for currents ˆ*i*d1 and ˆ*i*d2 with decoupling compensations can be simplified as in (13)

$$\begin{cases} \hat{\mathbf{i}}\_{\rm d2} = \mathbf{G}\_{11} \boldsymbol{\phi}\_{12} \\ \hat{\mathbf{i}}\_{\rm d1} = \mathbf{G}\_{22} \hat{\boldsymbol{\uprho}}\_{13} \end{cases} \tag{13}$$

By utilizing Kirchhoff's circuit laws and (13), the small signal differential equation group that represents the dynamic behavior of Port1 and Port2 can be obtained as (14).

$$\begin{cases} \frac{d\hat{\mathbf{t}}\_{\rm d2}}{dt} = -\frac{1}{R\_{\rm L}\mathbf{C}\_{\rm d2}}\boldsymbol{\mathfrak{v}}\_{\rm d2} & -\frac{G\_{11}}{\mathbf{C}\_{\rm d2}}\boldsymbol{\phi}\_{12} \\\ \frac{d\hat{\mathbf{t}}\_{\rm ds}}{dt} = \frac{1}{L\_{\rm d1}}\boldsymbol{\hat{v}}\_{\rm d1} & -\frac{1}{L\_{\rm d1}}\boldsymbol{v}\_{\rm c1} - \frac{\boldsymbol{r}\_{\rm c}}{L\_{\rm d1}}\boldsymbol{\hat{t}}\_{\rm ds} \\\ \frac{d\hat{\boldsymbol{v}}\_{\rm c1}}{dt} = \frac{1}{C\_{\rm d1}}\boldsymbol{\hat{t}}\_{\rm ds} & -\frac{G\_{22}}{C\_{\rm d1}}\boldsymbol{\phi}\_{13} \end{cases} \tag{14}$$

The corresponding state space model can be written as (15)

$$\begin{cases} \dot{\mathbf{x}} = \mathbf{A}\mathbf{x} + \mathbf{B}u\\ \mathbf{y} = \mathbf{C}\mathbf{x} \end{cases} \tag{15}$$

where *x*, *u* and *y* are state vector, input vector and output vector respectively shown in (16).

$$\begin{cases} \mathbf{x}^{\mathrm{T}} = \begin{bmatrix} \mathfrak{d}\_{\mathrm{d2}} \ \hat{\mathfrak{t}}\_{\mathrm{ds}} \ \mathfrak{d}\_{\mathrm{c1}} \end{bmatrix}^{\mathrm{T}} \\ \mathbf{u}^{\mathrm{T}} = \begin{bmatrix} \mathfrak{d}\_{\mathrm{12}} \ \mathfrak{d}\_{\mathrm{13}} \end{bmatrix}^{\mathrm{T}} \\ \mathbf{y}^{\mathrm{T}} = \begin{bmatrix} \mathfrak{x}\_{1} \ \mathfrak{x}\_{2} \end{bmatrix}^{\mathrm{T}} \end{cases} \tag{16}$$

And the coefficient matrices *A*, *B* and *C* are given in (17).

$$\mathbf{A} = \begin{bmatrix} -\frac{1}{\mathbf{C}\_{\mathrm{d2}}R\_{\mathrm{L}}} & 0 & 0\\ 0 & -\frac{r\_{\mathrm{c}}}{L\_{\mathrm{d1}}} & -\frac{1}{L\_{\mathrm{d1}}}\\ 0 & \frac{1}{\mathbf{C}\_{\mathrm{d1}}} & 0 \end{bmatrix}, \mathbf{B} = \begin{bmatrix} -\frac{\mathbf{G}\_{11}}{\mathbf{C}\_{\mathrm{d2}}} & 0\\ 0 & 0\\ 0 & -\frac{\mathbf{G}\_{22}}{\mathbf{C}\_{\mathrm{d1}}} \end{bmatrix}, \mathbf{C} = \begin{bmatrix} 1 & 0 & 0\\ 0 & 1 & 0 \end{bmatrix}, \mathbf{D} = 0 \tag{17}$$

The objectives of the control system are to obtain the desired current, *i*ds at Port 1 (for example, the output current of a photovoltaic panel with maximum power point tracking), and stabilize the output voltage, *v*d2 of Port 2. The energy storage port, Port 3 works as a free port and the batteries are charged or discharged automatically depending on the power exchange between Port 1 and Port 2. The control block diagram of the three-port converter is shown in Figure 6. In this figure, the phase shifting, φ<sup>12</sup> is used to control the Port 2 voltage, *v*d2, while the phase shifting, φ<sup>13</sup> is used to control the Port 1 current, *i*ds. In dynamic situations (e.g., with load or reference signal change), the transient operating point may deviate greatly from the designed steady-state operating point, which might discount the control performance significantly, therefore, both φ<sup>12</sup> and φ<sup>13</sup> should be limited between 0 and π/2.

**Figure 6.** Control diagram block of the TPC system.

According to this figure and (14), the opened loop transfer functions of the decoupled voltage and current subsystems are shown in (18) and (19) respectively.

$$\mathcal{G}\_{\rm OV} = \frac{G\_{11} R\_{\rm L}}{\mathcal{C}\_{\rm d2} R\_{\rm L} s + 1} \tag{18}$$

$$G\_{\rm oc} = \frac{G\_{22}}{L\_{\rm d1} \mathbb{C}\_{\rm d1} s^2 + r\_{\rm e} \mathbb{C}\_{\rm d1} s + 1} \tag{19}$$

### **3. Controller Design of TPC**

The general design procedure using H<sup>∞</sup> mixed sensitivity method is shown in Figure 7. The control plant modeling of TPC is derived in Section 2. Weight functions selection, which is an important step, will be discussed in this section. This selection has a significant influence on control performance and some instances is used to illustrate the design method. As shown in Figure 7, the step named "Generating an augmented LTI (linear time-invariant) plant" is used to create a state space model of augmented control plant with weight functions which is utilized for an H<sup>∞</sup> controller design (this task can be completed using the "augw" function in Matlab Robust Control Toolbox). The final step shown in Figure 5 is to solve the H<sup>∞</sup> controller using state space method [17]. Since the last two steps are relatively complex and mathematic, the details of the steps will not be discussed further in this section.

**Figure 7.** Design procedure of H<sup>∞</sup> mixed sensitivity based controller.

### *3.1. Fundamental of H*<sup>∞</sup> *Mixed Sensitivity Design*

The standard model for H<sup>∞</sup> mixed sensitivity design is shown in Figure 8 [18]. *W***1**, *W***<sup>2</sup>** and *W***<sup>3</sup>** are weight function matrices, *z*1, *z*<sup>2</sup> and *z*<sup>3</sup> are performance evaluation signal vectors, *d* is disturbance vector. *r*, *e*, *u* and *y* are reference vector, error vector, control signal vector and output vector respectively. *K* is the controller matrix and *G* is the control plant matrix.

**Figure 8.** H<sup>∞</sup> mixed sensitivity standard design model.

The augmented control plant (20) can be obtained according to Figure 8.

$$
\begin{bmatrix} z\_1 \\ z\_2 \\ \overline{z}\_3 \\ \overline{e}\_3 \\ \overline{e}\_3 \end{bmatrix} = \begin{bmatrix} W\_1 e \\ W\_2 u \\ \overline{W\_3} \\ \overline{e}\_3 \end{bmatrix} = \begin{bmatrix} W\_1 & -W\_1 G \\ \mathbf{0} & W\_2 \\ -\mathbf{0} & -\mathbf{W}\_3 G \\ \overline{I} - \overline{I} & -\overline{G} \end{bmatrix} \begin{bmatrix} r \\ u \\ \overline{u} \end{bmatrix} \tag{20}
$$

Weight functions selection is the most important step in H<sup>∞</sup> mixed sensitivity design process, which will determine the control performance, such as disturbance attenuation, robustness and dynamic response ability.

A generalized closed loop transfer function matrix in (21) can be obtained by substituting *u* = *Ke* into (20)

$$P = \begin{bmatrix} \mathcal{W}\_1 \mathcal{S} \\ \mathcal{W}\_2 \mathcal{R} \\ \mathcal{W}\_3 T \end{bmatrix} \tag{21}$$

where *S* = (*I* + *GK*) <sup>−</sup><sup>1</sup> is called sensitivity function matrix, it is the transfer function matrix from *d* to *e*. *T* = *GK*(*I* + *GK*) <sup>−</sup><sup>1</sup> represents transfer function matrix from *u* to *y*. Since *S* + *T* = *I*, *T* is called complimentary sensitivity function matrix, *R* = *K*(*I* + *GK*) <sup>−</sup><sup>1</sup> is the transfer function matrix from *e* to *u*. In (21) *W***1***S* is used to represents control performance requirements for disturbance rejection, and this performance metric can be designed by selecting appropriate *W*1. The strength or the effectiveness of the control signal, *u* is restricted by *W***2**. *W***3***T* represents requirements for robust stability, *W***<sup>3</sup>** reflects the design constraints for multiplicative model uncertainty, it depends on the parameter deviations of control plants. In the frame of H<sup>∞</sup> mixed sensitivity control, the performance requirements for disturbance rejection and robust stability are interactive, however, performance balance (or tradeoff) can be obtained by proper weight functions design. Generally, the following factors should be considered in weight functions selection (scalars are used in following text for ease statement).


frequency unmodeled dynamic of the system. Multiplicative uncertainty, Δ(*s*) can be obtained by solving (22).

$$\Delta(s) = \frac{G\_{\Lambda}(s) - G\_{0}(s)}{G\_{0}(s)} = \frac{G\_{\Lambda}(s)}{G\_{0}(s)} - 1 \tag{22}$$

In (22), *G*<sup>0</sup> and *G*<sup>Δ</sup> are nominal transfer function and practice transfer function, respectively.

In a mixed sensitivity design method, the gain *W*<sup>3</sup> should be designed to guarantee that Δ(*s*) in (22) is properly covered by *W*<sup>3</sup> (as shown in Figures 9 and 10). *W*<sup>3</sup> always has a high pass characteristic to make sure that the corrected control system has a favorable performance to attenuate high frequency disturbance. And the crossover frequency *W*3, *f* w3 should be higher than the desired crossover frequency of the corrected control subsystem. Taking into account the crossover frequency of *W*1, the crossover frequency of the corrected control subsystem will be located between *f* w1 and *f* w3. More systematic and detailed discussions about weight functions selection can be found in references [19,20].

**Figure 9.** Bode plots of W31 and multiplicative uncertainty of *G*ov.

**Figure 10.** Bode plots of W32 and multiplicative uncertainty of *G*oc.

### *3.2. H*<sup>∞</sup> *Controller Design*

For (18) and (19), the values of *G*<sup>11</sup> and *G*<sup>22</sup> will be changed with the variation of steady state operation point, the load change can be represented by different values of *R*L, and there are deviations between the nominal values of *C*d1, *C*d2, *L*d1, *r*<sup>e</sup> and their corresponding actual values. By using (22), the model deviation caused by the mentioned factors can be described through multiplicative uncertainty.

According to the parameters listed in Table 1, assuming *C*d2 has ± 25 % deviation from its nominal value. The equation in (23) can be selected as *W*31.

$$W\_{31} = 2.0250 \times 10^{-4} \text{s} + 0.75$$


**Table 1.** Simulation Parameters.

The possible multiplicative uncertainties of *G*ov (denoted by dashed lines) and the Bode plot (solid line) of W31 are shown in Figure 9. It can be seen that the crossover frequency of W31 is about 520 Hz. Similarly, ±25 % parameter deviation for *C*d1 and *L*d1 are assumed respectively, W32 shown in (24) is selected to cover the multiplicative uncertainty of *G*oc.

$$W\_{32} = 2.34 \times 10^{-6} s^2 + 0.00156s + 0.26\tag{24}$$

The Bode plots of W32 (solid line) and multiplicative uncertainties (dashed lines) with different parameter values are shown in Figure 10. The crossover frequency of W32 in this case is about 90 Hz.

The weight functions, W11 and W12 shown in (25) are designed for the sensitivity functions of current and voltage subsystem respectively, the crossover frequencies of W11 and W12 are 127 Hz and 26 Hz, respectively.

$$\mathbf{W}\_{1} = \begin{bmatrix} W\_{11} & 0\\ 0 & W\_{12} \end{bmatrix} = \begin{bmatrix} \frac{800}{\text{s} + 0.001} & 0\\ 0 & \frac{800}{\text{5s} + 0.001} \end{bmatrix} \tag{25}$$

The weight functions, W21 and W22 given in (26) are used to restrict the control signals.

*W*<sup>2</sup> = *W*<sup>21</sup> 0 <sup>0</sup> *<sup>W</sup>*<sup>22</sup> =  0.1 0 0 0.9 (26)

According to the parameters listed in Table 1, the resulted robust controllers for current and voltage control subsystems are obtained in (27) and (28) respectively (the controller can be solved using "hinfsyn" function in Matlab Robust Control Toolbox).

$$G\_{\rm c} = \frac{4234 \text{s} + 7.057 \times 10^4}{\text{s}^2 + 6043 \text{s} + 6.043} \tag{27}$$

$$\mathbf{G\_{V}} = \frac{5777 \mathbf{s^{2}} + 5.777 \times 10^{5} \mathbf{s} + 4.814 \times 10^{10}}{\mathbf{s^{3}} + 1.367 \times 10^{5} \mathbf{s^{2}} + 1.376 \times 10^{8} \mathbf{s} + 2.751 \times 10^{4}} \tag{28}$$

The Bode plot of the corrected voltage control subsystem is shown in Figure 11, the crossover frequency is about 243 Hz and the phase margin is about 76◦. The Bode plot of the corrected current control subsystem is presented in Figure 12, the crossover frequency of the current control loop is about 59 Hz, the gain margin is about 51 dB and the phase margin is about 70◦. It can be seen from Figure 12 that there is a notch in the Bode plot of the resulted H<sup>∞</sup> controller by which the resonant peak of the uncorrected system can be cancelled accordingly, therefore, a smooth Bode plot of the corrected system is obtained.

As shown in (19), *G*oc will manifest a weak damping characteristic if *r*e is very small and there is a significant resonant peak in the Bode plot of *G*oc. If *G*v and *G*c are designed as a proportional-integral (PI) controller, and the crossover frequency of the corrected current loop by PI controller is expected to be lower than the resonant frequency (about 460 Hz) of *G*oc, in this condition, in order to avoid 0 dB axis intersecting with the corrected current control around the resonant frequency of *G*oc, the crossover frequency should be greatly reduced. As seen in Figure 13, *G*<sup>c</sup> = 0.0144 + 36/s is utilized, the crossover frequency of the corrected current control system is about *f* <sup>c</sup> = 7 Hz, the gain margin is about 9dB and the phase margin is about 89◦. For comparison, if a higher crossover frequency of the corrected current control subsystem is wanted with a PI controller, for example, with about *f* c = 60 Hz (like that in Figure 12 using H<sup>∞</sup> control method) with *G*<sup>c</sup> = 0.17 + 425/*s*, as presented by the dashed line shown in Figure 13, the resulted current control subsystem will be unstable under this condition, because the Bode plot of the corrected current control system crosses 0 dB axis twice around its resonant peak. In contrast, since the resulted current controller, *G*<sup>c</sup> designed by H<sup>∞</sup> mixed sensitivity method in Figure 12 has a natural notch at the resonant frequency of *G*oc, which can cancel the negative impact of *G*oc resonance effectively, the improved current control performance can be obtained accordingly.

**Figure 11.** Bode of voltage control loop with H<sup>∞</sup> robust controller.

**Figure 12.** Bode of current control loop with H<sup>∞</sup> robust controller.

**Figure 13.** Bode of current control loop with a PI controller.

### **4. Simulation and Experimental**

### *4.1. Simulation Results*

A simulation model of the proposed design method is developed in MATLAB/Simulink environment to verify the effectiveness of the proposed method. The parameters used in the simulation model are presented in Table 1. The simulation results for changing the current reference, *i* ∗ ds with different control methods are presented in Figure 14. The simulation results using a PI controller are shown in Figure 14a. In this figure, the current reference value is reduced from 2.1 A to 1 A (at 0.25 s) and then suddenly increased again to 2.1 A (at 0.4 s). It can be seen the actual current, *i*ds can track its reference signal. However, since the current control bandwidth is relatively low in this condition, it takes about 30 ms to reach the reference current value. And the output voltage, *v*d2 is almost kept constant in this process. With the same reference change condition, the simulation results using H<sup>∞</sup> controller are shown in Figure 14b, as it can be concluded from this figure that the dynamic response speed of *i*ds is much faster than that in Figure 14a, the transient state process time is decreased to about 7 ms. And it can be seen in Figure 14 that the battery current *i*d3 is increased from about −0.22 A to

about 0.5 A and then to −0.22 A with the corresponding change of *i* ∗ ds, the dynamic response speed with H<sup>∞</sup> controller in Figure 14b is much faster than that with a PI controller in Figure 14a.

Figure 15 shows the simulation results of a sudden load change test. In Figure 15a, the load resistor value is reduced from 60 Ω to 30 Ω (the load is increased from about 42 W to about 83 W) at 0.25 s and then suddenly increased to 60 Ω at 0.4 s again. In the transient state process, due to the interaction of voltage and current control subsystems, there are fluctuations in *i*ds and *v*d2 simultaneously at the load change moment. With the same load change condition, the simulation results with H<sup>∞</sup> robust controller are given in Figure 15b. Though the fluctuations in *v*d2 and *i*d3 are similar to that in Figure 15a, the amplitudes of fluctuations and the transient recovery time of *i*ds in Figure 15b are significantly reduced compared to that in Figure 15a.

**Figure 14.** Simulation results with current reference change using a (**a**) PI controller, (**b**) H<sup>∞</sup> controller.

**Figure 15.** Simulation results with load change using a (**a**) PI controller, (**b**) H<sup>∞</sup> controller.

### *4.2. Experiment Results*

An experimental hardware shown in Figure 16 is developed to validate the theoretical design and simulation results. The parameter deviations of *C*d1 (about 1130 μF), *L*d1 (about 107 μH) and *C*d2 (about 1046 μF) are limited to 10% of their nominal value (this condition can be easily guaranteed in practice). The other parameters used in the experimental tests are approximately identical to the simulation parameters listed in Table 1. The experiment results are presented in Figures 17–22.

Figure 17 shows the experiment results of *v*d2 and *i*ds using the PI controller. The current reference value is changed from 1 A to 2.1 A and reduced to 1 A again suddenly in Figure 17a,b respectively, and the corresponding transient state process times are about 32 ms and 31 ms. Under the same reference value change condition, the experiment results using H<sup>∞</sup> controller are shown in Figure 18. Since the current control bandwidth using H<sup>∞</sup> controller (59 Hz) is higher than that using a PI controller (7 Hz), the transient state process times shown in Figure 18a,b are 19 ms and 23 ms respectively, which are much shorter than that in Figure 17.

With the same reference value change condition being used in Figure 17, the corresponding experiment results of battery current, *i*d3 using PI and H<sup>∞</sup> controllers are shown in Figures 19 and 20, respectively. It can be seen that the changes of battery current are much faster in Figure 20 than that in Figure 19. Compared to Figure 19a, less time is taken in Figure 20a for the battery current to reach its steady state value due to a higher control bandwidth of the H<sup>∞</sup> controller. A similar result can also be obtained by comparing Figure 19b with Figure 20b.

**Figure 16.** Hardware experiment circuit of three-port converter.

**Figure 17.** *v*d2 and *i*ds using a PI controller with *i* ∗ ds is (**a**) increased, (**b**) decreased.

**Figure 18.** *v*d2 and *i*ds using H<sup>∞</sup> controller with *i* ∗ ds is (**a**) increased, (**b**) decreased.

**Figure 19.** *v*d2 and *i*d3 using a PI controller with *i* ∗ ds is (**a**) increased, (**b**) decreased.

**Figure 20.** *v*d2 and *i*d3 using H<sup>∞</sup> controller with *i* ∗ ds is (**a**) increased, (**b**) decreased.

**Figure 21.** *v*d2, *i*ds and Δ*v*d2 using a PI controller with *R*<sup>L</sup> is (**a**) decreased, (**b**) increased.

**Figure 22.** *v*d2, *i*ds and Δ*v*d2 using H<sup>∞</sup> controller with *R*<sup>L</sup> is (**a**) decreased, (**b**) increased.

The load change experiment results using PI and H<sup>∞</sup> controllers are shown in Figures 21 and 22 respectively. In Figure 21a, the load resistor is changed from 90 Ω to 30 Ω (the load is increased from about 28 W to about 83 W) instantaneously, which causes about a 0.5 V voltage drop in *v*d2 (the peak value of Δ*v*d2) and about a 280 mA current drop in *i*ds. In Figure 22a, the corresponding voltage and current drops are 140 mA and 0.5 V respectively with the same load change. When the load resistor is again increased from 30 Ω to 90 Ω (the load is decreased from about 83 W to 28 W), a 200 mA current increment is produced in *i*ds using a PI controller in Figure 21b, and an 80 mA current increment is caused in *i*ds using an H<sup>∞</sup> controller in Figure 22b. It can be concluded that the interaction between voltage control subsystem and current control subsystem is better attenuated by adopting an H<sup>∞</sup> controller. Furthermore, the voltage fluctuation is reduced from 0.5 V in Figure 21b to about 0.38 V in Figure 22b with the H<sup>∞</sup> controller when the load resistor is increased.

In contrast to the traditional PI controller, the experiment results indicate that the negative impact caused by the couplings between current control subsystem and voltage control subsystem can be effectively suppressed by using the H<sup>∞</sup> controller. And the dynamic response performance of the control system can also be improved with the proposed method.

### **5. Conclusions**

An H<sup>∞</sup> mixed sensitivity method is introduced in this paper for three-port converter control. The H<sup>∞</sup> mixed sensitivity method has an inherent characteristic to balance performance and stability of a control system through the use of an appropriate weight functions selection. The H<sup>∞</sup> current controller manifests a superior characteristic of effectively damping the resonant peak of the current control subsystem that can reduce limitations in the control bandwidth design, and this is beneficial for enhancing the stability of the current control subsystem. The simulation and experiment results show that the resulted optimal H<sup>∞</sup> controller has advantages in dynamic response performance and load disturbance rejection compared to a traditional proportional-integral (PI) controller.

**Author Contributions:** Conceptualization and experiment, J.Y., H.L. and B.F.; All the authors contributed equally to the other parts of work.

**Funding:** This work is sponsored by the fundamental research funds for the central universities of China (No. HEUCFG201822), and the National Natural Science Foundation of China (No.51479042).

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


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