**Three-Port Converter for Integrating Energy Storage and Wireless Power Transfer Systems in Future Residential Applications**

### **Hyeon-Seok Lee <sup>1</sup> and Jae-Jung Yun 2,\***


Received: 15 November 2019; Accepted: 2 January 2020; Published: 5 January 2020

**Abstract:** This paper presents a highly efficient three-port converter to integrate energy storage (ES) and wireless power transfer (WPT) systems. The proposed converter consists of a bidirectional DC-DC converter and an AC-DC converter with a resonant capacitor. By sharing an inductor and four switches in the bidirectional DC-DC converter, the bidirectional DC-DC converter operates as a DC-DC converter for ES systems and simultaneously as a DC-AC converter for WPT systems. Here, four switches are turned on under the zero voltage switching conditions. The AC-DC converter for WPT system achieves high voltage gain by using a resonance between the resonant capacitor and the leakage inductance of a receiving coil. A 100-W prototype was built and tested to verify the effectiveness of the converter; it had a maximum power-conversion efficiency of 95.9% for the battery load and of 93.8% for the wireless charging load.

**Keywords:** energy storage system; wireless power transfer system; DC-DC power conversion; photovoltaic power system

### **1. Introduction**

Photovoltaics (PVs) constitute a promising alternative energy source due to diverse applications and the ubiquity of sunlight [1–4]. Residential PV systems consist of a PV module and a PV inverter, and it converts sunlight into electricity. However, energy output by PV systems is not constant because it is affected by weather conditions and the day/night cycle. Therefore, energy storage (ES) systems are used to efficiently manage the PV energy. They consist of a battery and a bidirectional DC-DC converter that connects to the PV system [5–7]. Besides, in the near future, the wireless power transfer (WPT) systems will be widely used to wirelessly charge laptops as well as cell phones in many households [8–11]. Therefore, future PV energy delivery and management infrastructure for residential applications will consist of PV systems, ES systems, and WPT systems (Figure 1a).

Three-port converters have been used to reduce the cost and size of infrastructure, such as micro-grids and smart grids [12–18]. The infrastructure consists of several systems, so its cost and size increase in proportion to the number of systems. To alleviate this problem, two systems are integrated through on a three-port converter. The three-port converters usually add a port to a typical converter that has two ports, either by using a three-winding transformer instead of a two-winding transformer [13–15] or by using the storage capacitor in the typical converter as a third port [16–18].

Many three-port converters have been introduced to integrate renewable energy sources (e.g., PV, fuel cell, wind turbine) with ES systems, but a three-port converter to integrate ES and WPT systems has not been considered. Therefore, this paper presents a three-port converter that can integrate the ES and WPT systems that will be used in future PV energy delivery and management infrastructure for residential applications (Figure 1b). The proposed three-port converter consists of a bidirectional

DC-DC converter for an ES system and an AC-DC converter with a resonant capacitor. The bidirectional DC-DC converter can also operate as a DC-AC converter of the WPT system because the inductor in the bidirectional DC-DC converter is also used as a transmitting coil for a WPT system. With these few components, the proposed converter can store energy for the ES system and simultaneously transfer the energy by using a WPT system. The proposed converter has a high power-conversion efficiency by achieving zero voltage switching (ZVS) turn-on for switches, and has high voltage gain for WPT by using a resonance between a resonant capacitor and a leakage inductance of a receiving coil.

Section 2 describes the circuit structure and operating principles of the proposed converter. Section 3 presents experimental results, and Section 4 concludes the paper.

**Figure 1.** Future photovoltaic (PV) energy delivery and management infrastructure; (**a**) typical topology, (**b**) proposed topology.

### **2. Proposed Three-Port Converter**

### *2.1. Circuit Structure*

The proposed converter (Figure 2a) combines the structures of a bidirectional DC-DC converter and an AC-DC converter.

The bidirectional DC-DC converter is located between a DC bus and a battery to transfer the energy in both directions (DC bus ↔ battery). This converter consists of four switches (S1, S2, S3, S4), two filter capacitors (bus capacitor, Cbus, with capacitance, Cbus, and battery capacitor, Cbat, with capacitance, Cbat), and an inductor (L1 with inductance L1). In addition, it can transfer the energy of the DC bus (or battery) to the wireless charging load because L1 also acts as a transmitting coil for WPT.

The AC-DC converter is connected to a wireless charging load, such as a cell phone or laptop, and it has a receiving coil (L2 with inductance L2) for WPT, a filter capacitor (WPT capacitor, Cwpt, with capacitance, Cwpt), a resonant capacitor (Cr with capacitance, Cr), and a voltage doubler rectifier that consists of two diodes (D1, D2) and two doubler capacitors (C1 with capacitance, C1, and C2 with capacitance, C2).

L1 and L2 are parts of the two-coil structure; they are coupled magnetically with a coupling coefficient, *k*, to transfer the energy wirelessly. Based on [19,20], the two-coil structure can be represented as a transformer with a leakage inductor (*Llk* with inductance, *Llk*), an effective turn ratio (Ne), and a magnetizing inductor (*Lm* with inductance, *Lm*), where *Llk* = (1 <sup>−</sup> *<sup>k</sup>*2)*L*2, *Ne* = *<sup>k</sup>* √ *L*2/*L*1, and *Lm* = *L*<sup>1</sup> (Figure 2b).

Four switches achieve the ZVS turn-on by using the stored energy in L1. *Llk* resonates with Cr, and high voltage gain between the DC bus and wireless charging load is achieved by setting the switching frequency, *fS*, to the resonant frequency, *fr*, between *Llk* and Cr. The voltage doubler rectifier converts AC voltage to DC voltage for wireless charging load, and clamps the reverse voltages of D1 and D2 to WPT voltage, *Vwpt*.

**Figure 2.** (**a**) Circuit structure of the proposed converter. (**b**) Equivalent circuit of the two-coil structure.

### *2.2. Principle of Operation*

The proposed converter operates at a fixed switching frequency (*fS* = 1/*TS*), where *TS* is a switching period, and it controls the voltage gain between the DC bus voltage, *Vbus*, and battery voltage, *Vbat*, by changing the duty ratios of S1, S2, S3, and S4; the duty ratios of S2 and S3 are defined as *D*, and the duty ratios of S1 and S4 are defined as 1–*D*. In addition, the voltage gain between *Vbus* and *Vwpt* is adjusted by using *Ne*.

The equivalent circuits (Figure 3) and operating waveforms (Figure 4) were obtained under the following assumptions and conditions: (1) All components are lossless, (2) *C*1, *C*2, *Cbus*, *Cbat*, and *Cwpt* are large enough to assume that *VC*1, *VC*2, *Vbus*, *Vbat*, and *Vwpt* are constant voltage sources, (3) *fr* = *fS*, and (4) the converter operates in a steady state. The converter operates in four modes.

Mode 1 (Figure 3a, *t*<sup>0</sup> ≤ *t* ≤ *t*1): This mode starts at *t* = *t*<sup>0</sup> when S2 and S3 are turned on. At this time, S2 and S3 achieve ZVS turn-on because the body diodes, DS2 and DS3, of S2 and S3 are turned on before *t* = *t*0. During this mode, the voltage, *vm*, of Lm becomes *Vbus*, and the current, *im*, of Lm is:

$$
\dot{a}\_m(t) = \dot{a}\_m(t\_0) + (V\_{\text{bus}}/L\_m)(t - t\_0), \tag{1}
$$

where *im*(*t*0) = *Ibus* + *Ibat* − *VbusDTS*/(2*Lm*). Cr has voltage *vCr* = *NeVbus* − *VC*1–*vlk* and current *iCr* = *ilk*, and *iCr*(*t*0) = 0. Therefore:

$$i\_{\rm Cr}(t) = \frac{N\_{\rm c}V\_{\rm bus} - V\_{\rm wpt}/2 - \upsilon\_{\rm Cr}(t\_0)}{\sqrt{\mathcal{L}\_{\rm lk}/\mathcal{C}\_r}} \sin[\omega\_r(t - t\_0)],\tag{2}$$

where *vCr*(*t*0) = <sup>−</sup>0.5*TSIwpt*/*Cr* and <sup>ω</sup>*<sup>r</sup>* <sup>=</sup> 1/ <sup>√</sup> *LlkCr*. The current, *iD*1, of *D*<sup>1</sup> is equal to *iCr* for *t*<sup>0</sup> ≤ *t* ≤ *t*1.

Mode 2 (Figure 3b, *t*<sup>1</sup> ≤ *t* ≤ *t*2): At *t* = *t*1, S2 and S3 are turned off, and S1 and S4 remain in the off-states to prevent a shoot-through problem. This mode is known as dead time. During this mode, the output capacitance, CS1, of S1 discharges from *Vbus* to 0, and the output capacitance, CS2, of S2 charges from 0 to *Vbus*. In addition, the output capacitance, CS4, of S4 discharges from *Vbat* to 0, and the output capacitance, CS3, of S3 charges from 0 to *Vbat*. Shortly after the discharging and charging processes are finished, the body diodes, DS1 and DS4, of S1 and S4 are turned on.

Mode 3 (Figure 3c, *t*<sup>2</sup> ≤ *t* ≤ *t*3): At *t* = *t*2, S1 and S4 are turned on under ZVS conditions because the body diodes, DS1 and DS4, are turned on before *t* = *t*2. During this mode:

$$i\_m(t) = i\_m(t\_2) - (V\_{\rm lut} / L\_m)(t - t\_2),\tag{3}$$

because *vm* = −*Vbat*. *iCr* is obtained using *vCr* = − *NeVbat* + *VC*<sup>2</sup> − *vlk* and *iCr*(*t*2) = 0 as:

$$i\_{\rm Cr}(t) = -\frac{N\_{\rm r}V\_{\rm bat} - V\_{\rm wpt}/2 + v\_{\rm Cr}(t\_2)}{\sqrt{L\_{\rm lk}/\mathbb{C}\_r}}\sin[\omega\_r(t - t\_2)],\tag{4}$$

where *vCr*(*t*2) = 0.5*TSIwpt*/*Cr*. At *t* = *t*2, D2 is turned on, and the current, *iD*2, of D2 is −*iCr*.

Mode 4 (Figure 3d, *t*<sup>3</sup> ≤ *t* ≤ *t*4): S2 and S3 remain in the off-states because this mode is the dead time interval. During this mode, CS2 discharges from *Vbus* to 0, and CS1 charges from 0 to *Vbus*. In addition, CS3 discharges from *Vbat* to 0, and CS4 charges from 0 to *Vbat*. Shortly after the discharging and charging processes are finished, DS2 and DS3 are turned on.

**Figure 3.** *Cont.*

**Figure 3.** (**a**) Circuit diagrams for the operation in Mode 1. (**b**) Circuit diagrams for the operation in Mode 2. (**c**) Circuit diagrams for the operation in Mode 3. (**d**) Circuit diagrams for the operation in Mode 4.

**Figure 4.** Operational waveforms of the proposed converter.

### *2.3. Voltage Gain*

The proposed converter has one input port (DC bus) and two output ports (battery and wireless charging load). Therefore, it has (Equation (1)) a voltage gain, *Gbb*, between the DC bus and battery and (Equation (2)) a voltage gain, *Gwb*, between the DC bus and wireless charging load.

$$(1)\quad G\_{bb} = V\_{bat}/V\_{bus}$$

For one *TS*, the average voltages of Cbus and Cbat are *Vbus* and *Vbat*, respectively. Then, the average voltage at node *N*<sup>1</sup> between *S*<sup>1</sup> and *S*<sup>2</sup> is *DVbus*, and the average voltage at node *N*<sup>2</sup> between S3 and S4 is given by (1-*D*) *Vbat*. The average voltage of L1 is zero due to the volt-second balance law for the inductor, and the average currents of switches are given by <*iS*2>=<*iS*3> = *Ibus* and <*iS*1> = <*iS*4> = −*Ibat* because the average current of the capacitor is zero by the charge balance law. Therefore, the average model of the circuit can be obtained (Figure 5). In this average model, the series resistance, *RS*, is the sum of *RL*<sup>1</sup> and 2*Ron*, where *RL*<sup>1</sup> and *Ron* are a winding resistance of L1 and on-resistance of a switch, respectively.

By applying Kirchhoff's voltage law (KVL) to the closed-loop that contains *DVbus*, *RS*, and (1-*D*) *Vbat*, the voltage gain *Gbb* ( = *Vbat*/*Vbus*) is obtained as:

$$G\_{bb} = -\frac{1}{2} \left| \left[ \frac{(1 - D)R\_{\text{flat}}}{R\_S} + 1 \right] + \sqrt{\left[ \frac{(1 - D)R\_{\text{flat}}}{R\_S} + 1 \right]^2 + \frac{4DR\_{\text{flat}}}{R\_S}} \right| \tag{5}$$

where *Rbat* = *Vbat*/*Ibat*. In most cases, *Rbat* >> *RS*, so:

$$G\_{l\psi} \approx D / (1 - D). \tag{6}$$

**Figure 5.** Average model between node *N*<sup>1</sup> and node *N*2.

### (2) *Gwb* = *Vwpt*/*Vbus*

Based on the four nodes (*N*1, *N*2, *N*3, and *N*4) in Figure 2a, the circuit of the proposed converter can be simplified (Figure 6a). Here, the square voltage, *vac*, between *N*<sup>1</sup> and *N*<sup>2</sup> is *Vbus* − (*Ibus* + *Ibat*)*RS* for *DTS* and − *Vbat* − (*Ibus* + *Ibat*)*RS* for (1-*D*)*TS*. Then, the current *iac* is *iL*<sup>1</sup> − (*Ibus* + *Ibat*), and the square voltage, *vac*2, between *N*<sup>3</sup> and *N*<sup>4</sup> becomes *Vwpt*/2 for 0.5*TS* and −*Vwpt*/2 for the other 0.5*TS*. The current *iac*<sup>2</sup> is given by *iCr*.

By applying fundamental harmonic approximation (FHA) to *vac*, *iac*, *iac*2, and *vac*2, the following root mean square (RMS) values are obtained (Figure 6b); *VL*2,rms is the RMS value of the first harmonic component in the voltage, *vL*2, of L2, and it is given by:

$$V\_{L2,rms} = -\frac{N\_c^{-2}\pi V\_{wpt}R\_S}{\sqrt{2}R\_{wpt}} + \frac{N\_cV\_{bus}}{\sqrt{2}} \left(\frac{2(1+G\_{bb})}{\pi}\sin(D\pi) - \frac{T\_SR\_S}{\pi^2(1-D)L\_m}\right) \tag{7}$$

where:

$$I\_{\text{ac2,rms}} = \pi I\_{\text{upt}} / \sqrt{2},\tag{8}$$

and:

$$V\_{\text{ac2}\,\text{rms}} = \sqrt{2}V\_{\text{upt}}/\pi\,,\tag{9}$$

are RMS values of the first harmonic components in *iac*<sup>2</sup> and *vac*2, respectively. Then, the equivalent resistance, *Rac*2, between *N*<sup>3</sup> and *N*<sup>4</sup> is obtained using Equations (8) and (9) as:

$$R\_{\rm ac2} = V\_{\rm ac2,rms} / I\_{\rm ac2,rms} = 2R\_{\rm upt} / \pi^2,\tag{10}$$

where *Rwpt* = *Vwpt*/*Iwpt*. By applying KVL to the closed-loop in Figure 6b, the relation between *VL*2,rms and *Vac*2,rms is given by:

$$\frac{V\_{L2,rms}}{V\_{ac2,rms}} = \frac{1}{R\_{ac2}} \left[ j \left( \omega\_S L\_{lk} - \frac{1}{\omega\_S \mathbf{C}\_r} \right) + R\_{L2} \right] + 1,\tag{11}$$

where *RL*<sup>2</sup> is a winding resistance of L2. Then, substituting Equations (7) and (9) into Equation (11) yields:

$$\begin{split} G\_{wb} &= \left| \frac{V\_{\text{opt}}}{V\_{bw}} \right| = \frac{N\_{\text{g}}}{2} \Big( 2(1 + G\_{bb}) \sin(D\pi) - \frac{T\_{\text{S}} R\_{\text{S}}}{\pi (1 - D) L\_{\text{m}}} \Big) \\ &\quad / \sqrt{\frac{1}{R\_{\text{w2}} \pi^{2}} \Big( \omega\_{\text{S}} L\_{\text{lk}} - \frac{1}{\omega\_{\text{S}} \mathbf{C}\_{r}} \Big)^{2} + \left( \frac{\pi^{2} R\_{l2}}{2 R\_{\text{wpt}}} + 1 + \frac{N\_{\text{e}} \pi^{2} R\_{\text{S}}}{2 R\_{\text{wpt}}} \right)^{2}} . \end{split} \tag{12}$$

If *fr* = *fS*, maximum *Gwb* is obtained because ω*SLlk* = 1/(ω*SCr*) at *fr* = *fS* (Figure 7), and it is given by:

$$G\_{ub}|\_{f\_r = f\_S} = \frac{N\_c}{2} \Big( 2(1 + G\_{bb}) \sin(D\pi) - \frac{T\_S R\_S}{\pi (1 - D) L\_m} \Big) \Big/ \left(\frac{\pi^2 R\_{L2}}{2R\_{wpt}} + 1 + \frac{N\_c^2 \pi^2 R\_S}{2R\_{wpt}}\right). \tag{13}$$

**Figure 6.** (**a**) Equivalent circuit based on four nodes (*N*1, *N*2, *N*3, and *N*4). (**b**) AC model in the secondary winding side after applying fundamental harmonic approximation (FHA).

**Figure 7.** Voltage gain (*Gwb*) between *Vbus* and *Vwpt* according to *fS*.

Therefore, *Cr* should be chosen to obtain the maximum voltage gain (*Gwb*) between *Vbus* and *Vwpt*. Because <sup>ω</sup>*<sup>r</sup>* <sup>=</sup> 1/ <sup>√</sup> *LlkCr* and *Llk* = (<sup>1</sup> <sup>−</sup> *<sup>k</sup>*2)*L*2, *Cr* can be determined as:

$$C\_r = \frac{1}{4\pi^2 f\_S^2 (1 - k^2) L\_2}.$$

### *2.4. Magnetic Saturation*

The coil structure, which consists of a transmitting coil (L1) and a receiving coil (L2), can use magnetic bars to increase efficiency and reduce magnetic fields that can interfere with nearby electronics [21–23]. Based on [24,25], the magnetic flux density (*BC*) of the coil structure is given by:

$$B\_{\mathbb{C}} = \frac{\mu\_0 \mu\_{\mathfrak{c}} N i\_{m, \text{peak}}}{l\_m},\tag{14}$$

where μ<sup>0</sup> is a vacuum permeability, μ*<sup>e</sup>* = (μ*rlm*)/ 2*lg*μ*<sup>r</sup>* + *lm* is an effective relative permeability, *N* is the number of turns, *im,peak* is a peak value of *im*, *lm* is the mean magnetic path length, μ*<sup>r</sup>* is a relative permeability, and *lg* is thee air-gap length.

Because the proposed converter has a DC bias current (=*Ibus* + *Ibat*) of L1, *im,peak* is given by:

$$i\_{m,peak} = I\_{bus} + I\_{bat} + \frac{V\_{bus}DT\_S}{2L\_m}.\tag{15}$$

Magnetic saturation can be caused by this DC bias current because the DC bias current increases *BC* by increasing *im,peak*. There are two methods to solve the problem of the DC bias current [26,27]. First, decreasing *N* reduces *BC*. Second, increasing *lg* reduces *BC* by decreasing μ*e*. However, *lg* is determined by a distance, *ld*, between L1 and L2. Therefore, the following condition for preventing magnetic saturation can be obtained using *BC* < *Bsat*, (Equations (14) and (15)) as:

$$N < \frac{I\_m B\_{sat}}{\mu\_0 \mu\_c [I\_{bus} + I\_{bat} + V\_{bus} D T\_S / (2L\_m)]} ' \tag{16}$$

where *Bsat* is a saturation flux density of magnetic material.

### **3. Experimental Results**

A prototype (Figure 8) of the proposed converter was fabricated using selected components and circuit parameters (Table 1), then tested to verify the operation of the proposed converter.

**Figure 8.** Photograph of the prototype.



The voltage and current waveforms of S1 and S2 were measured at *Vbus* = 400 V, *Vbat* = 400 V, *fS* = 400 kHz, and *Pwpt* (or *Pbat*) = 20 and 100 W (Figure 9). At both *Pwpt* = 20 W (Figure 9a) and *Pwpt* = 100 W (Figure 9b), the voltage stresses of S1 and S2 were measured as 400 V, which is equal to *Vbus*, and S1 and S2 achieved ZVS turn-on. In addition, S3 and S4 achieved ZVS turn-on at these conditions because *iS*<sup>1</sup> = *iS*<sup>4</sup> and *iS*<sup>2</sup> = *iS*3. Even at both *Pbat* = 20 W (Figure 9c) and *Pbat* = 100 W (Figure 9d), all switches were turned on under the ZVS condition, which improves the power-conversion efficiency, η*e*.

The theoretical *Vwpt* obtained from Equation (13) was compared with the experimental *Vwpt* measured at *Vbus* = 400 V, *Vbat* = 400 V, and *Pwpt* = 20 W~100 W (Figure 10). The theoretical *Vwpt* was higher than experimental *Vwpt* at all *Pwpt*, but the difference was <3%. This result shows that Equation (13) predicts the experimental *Vwpt* with little error. In addition, *Vwpt* was almost constant regardless of *Pwpt*.

**Figure 9.** Voltage and current waveforms of switches (S1, S2) measured at *Pwpt* = (**a**) 20 W and (**b**) 100 W or at *Pbat* = (**c**) 20 and (**d**) 100 W.

**Figure 10.** Comparison between experimental *Vwpt* and theoretical *Vwpt*.

The power-conversion efficiencies (η*e*,wpt for the wireless charging load and η*e*,bat for the battery load) were measured at *Vbus* = 400 V, *Vbat* = 400 V, *fS* = 400 kHz, and *Pwpt* (or *Pbat*) = 20 W~100 W (Figure 11). The proposed converter had the highest η*e*,wpt = 93.8% at *Pwpt* = 100 W (Figure 11a) and had the highest η*e*,bat = 95.9% at *Pbat* = 100 W (Figure 11b). At low *Pwpt* = 20 W, the measured η*e*,wpt was 82.5% (Figure 11a), and the measured η*e*,bat was 83.5% at low *Pbat* = 20 W (Figure 11b). In addition, the measured η*e*,bat was higher than the measured η*e*,wpt because the wireless power loss during transfer between two coils is included in η*e*,wpt. These results show that the proposed converter had high η*e*,wpt > 82% and high η*e*,bat > 83% for all operating ranges due to the ZVS turn-on of all switches.

**Figure 11.** (**a**) Power-conversion efficiency, η*e*,wpt, measured at *Pwpt* =20 W~100W. (**b**) Power-conversion efficiency, η*e*,bat, measured at *Pbat* = 20 W~100 W.

The transient response of *Vwpt* was measured at *Vbus* = 400 V, *Vbat* = 400 V, and *fS* = 400 kHz, while changing the wireless charging load from 20% to 100% and from 100% to 20% (Figure 12). At the load transition, the maximum voltage spike of *Vwpt* was measured as 14 Vp.p, and *Vwpt* returned to the steady-state within 81 ms.

**Figure 12.** Transient responses of *Vwpt* while changing the wireless charging load (**a**) from 20% to 100% and (**b**) from 100% to 20%.

In addition, the transient response of *Vbat* was measured while changing the battery load from 20% to 100% and from 100% to 20% under the same conditions as in Figure 12 (Figure 13). The maximum voltage spike of *Vbat* was measured as 61 Vp.p when the load changed, and *Vbat* returned to the steady state within 125 ms. These experiment results of the transient response show that the proposed converter can operate properly despite sudden load changes.

**Figure 13.** Transient responses of *Vbat* while changing the battery load (**a**) from 20% to 100% and (**b**) from 100% to 20%.

To show that the proposed converter can operate both when charging the battery and when charging wirelessly, *Vwpt* and *Vbat* of the proposed converter were measured under the following four conditions (Figure 14): (1) *Pwpt* = 20 W and *Pbat* = 20 W, (2) *Pwpt* = 20 W and *Pbat* = 100 W, (3) *Pwpt* = 100 W and *Pbat* = 20 W, and (4) *Pwpt* = 100 W and *Pbat* = 100 W. Figure 14 shows that *Vwpt* decreases and *Vbat* increases when the power (*Pwpt*, *Pbat*) increases. However, both *Vwpt* and *Vbat* maintained a near fixed value; *Vwpt* changed from 183.8 to 180.9 V, which is just a 1.58% change, and *Vbat* changed from 399.8 to 401 V, which is just a 0.3% change.

The measured *Vwpt* and *Vbat* are summarized in Table 2, and this experimental result shows that the proposed converter can operate in both charging the battery and charging wirelessly because both *Vwpt* and *Vbat* maintain a near fixed value regardless of *Pwpt* and *Pbat*.

**Figure 14.** The WPT voltage (*Vwpt*) and the battery voltage (*Vbat*) measured at (**a**) *Pwpt* = 20 W and *Pbat* = 20 W, (**b**) *Pwpt* = 20 W and *Pbat* = 100 W, (**c**) *Pwpt* = 100 W and *Pbat* = 20 W, and (**d**) *Pwpt* = 100 W and *Pbat* = 100 W.

**Table 2.** WPT and battery voltages according to the WPT and battery powers.


### **4. Conclusions**

This paper presented a three-port converter to integrate an ES system with a WPT system. If the ES and WPT systems are used separately, many converters are needed. However, these ES and WPT systems can be integrated through only one proposed converter because the proposed converter can use an inductor in the bidirectional DC-DC converter as a transmitting coil for the WPT system. Therefore, the proposed converter consists only of a bidirectional DC-DC converter and an AC-DC converter, and an ES-WPT system that uses the proposed converter can minimize the cost and circuit size. The operation of the proposed converter was verified by theoretical analysis and experimental results, and the proposed converter had high η*e*,wpt > 82% for 20 W ≤ *Pwpt* ≤ 100 W, and η*e*,bat > 83% for 20 W ≤ *Pbat* ≤ 100 W, due to the ZVS turn-on of all switches. These results show that the proposed

converter is suitable for the ES-WPT system that is part of future PV energy delivery and management infrastructure for residential applications.

**Author Contributions:** Both authors contributed equally to this work. H.-S.L. presented the main idea of the three-port converter. H.-S.L. and J.-J.Y. analyzed the proposed converter and performed experiments. J.-J.Y. contributed to the overall composition and writing of the manuscript. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the National Research Foundation of Korea (NRF) grant funded by the government of Korea (MSIP) (NRF-2018R1A1A1A05079496).

**Conflicts of Interest:** The authors have no conflict of interest.

### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **A Hybridization of Cuk and Boost Converter Using Single Switch with Higher Voltage Gain Compatibility**

### **M. Karthikeyan 1,\*, R. Elavarasu 2, P. Ramesh 3, C. Bharatiraja 4, P. Sanjeevikumar 5, Lucian Mihet-Popa 6,\* and Massimo Mitolo <sup>7</sup>**


Received: 31 March 2020; Accepted: 27 April 2020; Published: 6 May 2020

**Abstract:** In the current era, the desire for high boost DC-to-DC converter development has increased. Notably, there has been voltage gain improvement without adding extra power switches, and a large number of passive components have advanced. Magnetically coupled isolated converters are suggested for the higher voltage gain. These converters use large size inductors, and thus the non-isolated traditional boost, Cuk and Sepic converters are modified to increase their gain by adding an extra switch, inductors and capacitors. These converters increase circuit complexity and become bulky. In this paper, we present a hybrid high voltage gain non-isolated single switch converter for photovoltaic applications. The proposed converter connects the standard conventional Cuk and boost converter in parallel for providing continuous current mode operation with the help of a single power switch, which gives less voltage stress on controlled switch and diodes. The proposed hybrid topology uses a single switch with a lower component-count and provides a higher voltage gain than non-isolated traditional converters. The converter circuit mode of operation, operating performance, mathematical derivations and steady-state exploration and circuit parameters design procedures are deliberated in detail. The proposed hybrid converter circuit components, voltage gain and performance, were compared with other topologies in the literature. The MATLAB/Simulink simulation study and microcontroller-based experimental laboratory prototype of 150 W were implemented. The simulation study and experimentation results were confirmed to be a satisfactory agreement with the theoretical analysis. This topology produced non-inverting output in continuous input current mode using a single switch with high voltage gain (≈5.116 gain) with a maximum efficiency of 92.2% under full load.

**Keywords:** DC-to-DC converter; single switch high voltage gain converter; non-isolated DC-to-DC converter; low voltage stress; higher voltage gain

### **1. Introduction**

Due to the increase in energy demand, large amounts of conventional energy have been consumed, which is very dangerous due to their CO2 emissions. For example, all countries are keen on replacing conventional energy sources with non-conventional sources. Researchers are currently exploring power converters and interfacing circuits to meet out-migration. Non-conventional sources such as wind energy [1,2], photovoltaic (PV) [3,4] and hydrogen-powered fuel cells (FC) [5,6] are leading sources for meeting commercial and industrial demands. A PV-powered power system consists of PV modules coupled in a series as well as parallel combinations that are fed to the required DC voltage through the DC-to-DC converter, which is then converted as a DC-to-AC source through the inverter [7]. The controller development of DC-to-DC converters using a fuzzy logic controller and sliding mode control has recently gained attention. Those converters are used in a microgrid that minimizes the instability effects in [8,9]. For optimizing the performance of the converter, an optimization algorithm was used to tune the controller's coefficients [9]. A constant power load in a shipboard DC microgrid was investigated for the finite time by adopting the finite-time disturbance observer method [10]. The estimated load power was then received by the fixed-time terminal sliding mode controller to stabilize the entire marine power grid as well as tracking the reference voltage of the DC bus in a fixed time independent of initial conditions. For a high-efficiency PV system, a dual-power stage micro-inverter (high voltage gain DC-to-DC converter + DC-to-AC inverter) was issued in the market. In many industrial applications such as those found in the automotive, telecommunication and shipping industries, systems need higher voltage gain DC-to-DC converters with large input current [11–13]. These converters typically boost the range from 24–60 V to 100–300 V. For example, automotive headlamps need 48/100/120 V range, but the vehicle battery capacity can only deliver 12/24/48 V. For these situations, high voltage converters are suggested with high voltage gain [14,15]. According to the theoretical calculations, the conventional boost converter can offer a high duty ratio with infinite voltage gain. However, in a practical case, it is limited due to the inductor saturation limits. Besides, any DC-to-DC converter, which needs to provide a high output voltage and high power conversion, draws large input current; hence, the power switches metal-oxide-semiconductor field-effect transistor (MOSFET) and diode) are needed to handle the voltage stress.

Topologies have presented numerous single switch converters in the literature to provide the high step-up voltage conversion [14–20]. These converters have some limitations for their voltage gain, which is mainly because of the inductors, power semiconductor switches and the parasitic elements of those converters. Hence, a researcher has recommended using a step-up transformer with a converter to overcome this issue (flyback converter) [21]. It may be achieved with a high current for high power uses, which is not the most efficient. Other attempts have been made by using a single switch with a forward and tapped inductor connected converters are proposed for high voltage gain [22–24]. Though these converters have a controlled degree of freedom through the transformer turns ratio adjustment, considering the transformer size, the converter is large. The high voltage gain quadratic converters are the next choice in this group [25,26]. However, a quadratic converter has high voltage stress across the first semiconductor, resulting in it being more efficient than the classical converter. The impedance (using two inductors and two capacitors) source-based converter handles the buck-boost voltage conversion with high gain; however, it needs a high voltage-handling power switch to operate shoot-through and not shoot-through operation. A high voltage gain integrated boost and flyback converter is proposed by [27] using the leakage inductor energy recirculation in the switch-off period; however, this method suffered from pulsating input currents.

The converter topology accumulated with a coupled inductor produces a high step-up conversion with high efficiency [28,29]. Here, the voltage gain is dealt with by changing the converter switch turns ratio like isolated type converters. Though this topology obtains a high gain, due to the coupled inductor-leakage inductance, the switch may suffer a high voltage spike. The passive and active clamping approaches have been established [30] by adding a coupled inductor for the high voltage conversion ratio; however, this converter is inefficient in terms of cost and size. The other choice is adapting a switched capacitor in the switching-mode converter for the high voltage gain [28,29]. Due to the pulse shape, the input current of the converter leads to a weak load and line regulation problems. The voltage-doubler concept in converters [30–34] can provide a high voltage gain with the coupled inductor. Here, the switching frequency is less than an inductor magnetizing current frequency, which is not suitable for reliable operation. Recently, using the single switch in DC-to-DC power converters, various research papers have been published to derive high voltage gain without using a higher duty ratio [35–40]. The authors in [33] proposed a 2D/1-D voltage gain single switch buck–boost converter with low input current ripple and appropriate voltage gain. Nevertheless, it has the discontinuous current in the input side. In paper [37], a transformerless high voltage gain buck–boost was proposed with a voltage gain of 3D/1-D; though this converter has a discontinuous input current. A quadratic DC–DC buck–boost converter with single-switch topology is presented in [39] for widespread voltage conversion. The high step-up single switch converter is recommended for PV-based grid applications [30]. However, in this converter, the low-level input voltage habitually roots massive input current and higher current ripples. This large amount of current affects the power switch during the higher duty ratio operation, causing a large conduction loss. Recently, Banaei et al. proposed a converter using a single switch with less switching voltage stress. Even though the converter can maintain the continuous input current for all duty ratios, the primary power switch voltage stress is strictly equal to the converter output voltage, which caused high conduction losses [38]. In [40,41], the single switch Cuk topology uses an extra inductor and capacitor to provide the extra voltage. However, in this topology, when diodes are operating with higher current and voltage, the diode reverse recovery current is predominant, which increases the switching losses. Among all converter topology, the cascade boost converter type is proficient in obtaining a higher gain with minimal duty ratio for the full range of voltage gain [19]. Nevertheless, the main switch has higher voltage stress in this topology.

Based on this discussion, and although several single switch boost converter topologies are proposed in the literature, their major approaches are concerned with the use of less magnetic elements, size, weight, conduction losses and cost-savings for the inductors. These approaches have higher voltage stresses on their switch (nearly the same as their output voltage). Therefore, these converters still have significant challenges, such as high step-up requirements for the larger duty ratio, output diode reverse recovery complication, higher switching voltage stress and satisfactory efficiency. Integrating the classical DC-to-DC converter is a better choice than modifying an existing converter. However, while cascading those classical converters with additional boosting capability, reducing the power switches and passive elements leads to an appropriate converter circuit size as well as cost reductions. With that aim, in this paper, we propose a DC–DC converter topology by integrating the conventional boost and Cuk converters with high voltage gain. Our proposed topology uses only one power switch with higher static voltage gain when compared to other conventional converters. Our proposed converter delivers voltage using two series-connected identical capacitors connected in parallel with the converter circuit. In this paper, we also deal with the maintenance of the capacitor balancing. The detailed converter mode operation, analysis, design, small-signal analysis and analytical switching losses were deliberated. The MATLAB/Simulink simulation and PIC microcontroller-based experimentation results for the integrated converter shows the advantages and practicality of the proposed converter.

The paper is organized as follows: Section 2 describes the proposed hybrid converter design and its mode of operation. Section 3 describes the converter components design and small-signal analysis. Section 4 explains the design procedure and components. The simulation, experimentation and comparison with other similar topologies are discussed in Sections 5 and 6. The conclusion is given at the end of Section 7.

### **2. Topology and Operation of Proposed Hybrid DC–DC Converter**

The proposed integrated hybrid converter combines the conventional boost converter and classical Cuk DC-to-DC converter. The method used for the design of the proposed hybrid converter topology is illustrated in Figure 1. Figure 1a,b shows the typical conventional boost converter and classical Cuk converter, respectively. In both of these converters, the input inductor, power switches and input source are organized in the same way. Hence, there is an opportunity to merge these two converters by keeping the power switch and input inductor commonly on the input side. Except for the input side boost inductor (*L*1) and the power switch T, the rest of the circuit is connected precisely in parallel with each other. Hence, the output side two capacitors (*C*<sup>1</sup> and *C*3) are placed across the load. This hybrid structure increases the voltage gain by complementing the benefits of boost and Cuk converters. The converter provides continuous current mode operation with the help of a single power switch, which provides less voltage stress on the controlled switch and diodes.

**Figure 1.** (**a**) Proposed converter integration; (**b**) proposed single switch hybrid DC–DC converter.

### *Operation of Hybrid DC–DC Converter*

The proposed hybrid DC–DC converter mode operations, their capacitors (*C*1, *C*<sup>2</sup> and *C*3) and inductors (*L*<sup>1</sup> and *L*2) charging and discharging analysis derivations were considered as follows. The two assumptions were taken for this analysis: (1) all the components are ideal; (2) the converter works under continuous conduction. Figure 3a illustrates the continuous conduction operating mode waveforms of the proposed converter. This advanced hybrid DC–DC converter mode operation has three modes of operation.


The proposed hybrid DC-to-DC converter operation mode waveforms are presented in Figure 3. In mode-I, the power switch T is 'ON' and turned 'OFF' in mode-II as well as mode-III. The proposed converter duty ratio versus voltage gain performance was compared to boost and Cuk converters. Figure 3b displays the voltage gain versus duty ratios for boost, Cuk and the proposed hybrid converter. Based on the plot, it can be seen that the proposed hybrid converter has a better voltage gain ratio when compared with the boost and Cuk converter, respectively. In addition to the extended voltage static gain, the proposed topology achieves lower voltage stress across the power switch and diodes, when compared to a boost converter.

The power switch voltage stress is equal to the peak voltage across the capacitor C1. Hence, voltage stress across the power switch T was lower than the total output voltage. The voltage stress of D1 and D2 is equal to the voltage across the power switch T in the OFF state. Hence, the diodes' current rating requirement was lower than power switch T. In the classical boost converters for both Cuk and boost, the power switch and diode need an equal rating. In the higher gain operations, the classical converter needs a higher duty cycle than the proposed converter. Therefore, the voltage stress for switch and diode are higher. Hence, the proposed converter efficiency in the higher gain operation is better than the conventional boost converter.

**Figure 2.** Modes of operation of the proposed hybrid DC-to-DC converter: (**a**) Mode-I [ta–tb]; (**b**) Mode-II [tb–tc]; (**c**) Mode-III [tc–td].

**Figure 3.** (**a**) Mode diagram of the proposed circuit; (**b**) voltage gain versus duty ratio for boost, Cuk and proposed hybrid converter.

In general, for any DC-to-DC converter, the input inductor selection is carried out depending on the converter conduction mode, load current requirement, and it is desirable to confirm the least output current ripple. Hence, the input inductor *L*<sup>1</sup> value was chosen with minimal current ripple ΔiL. The inductor current, iL for the proposed converter is supplied from either a PV or DC source (VPV or Vin). When the converter receives a supply voltage from the input source, the converter power switch T is turned ON, and inductor current iL1 is derived as follows. Applying Kirchhoff's voltage law in mode-I [ta–tb], the capacitors current *iC*<sup>1</sup> and *iC*<sup>2</sup> are derived as

$$\begin{aligned} -VPV + v\_{L1} &= 0 \Rightarrow v\_{L1} = VPV\\ -v\_{C2} + v\_{L2} + v\_{C3} &= 0 \Rightarrow v\_{L2} = -v\_{C3} + v\_{C2} \end{aligned} \tag{1}$$

$$\begin{aligned} -i\mathbf{r} + i\mathbf{i}\_{\perp} - i\mathbf{j}\_{\perp} &= 0\\ i\_O - i\_{\perp 2} - i\_{\mathbb{C}3} &= 0 \end{aligned} \tag{2}$$

$$\begin{aligned} i\_{\rm C2} &= -i\_{\rm L2} \\ i\_{\rm C1} &= -i\_{\rm O} \end{aligned} \tag{3}$$

During mode-II [tb–tc], when the power switch T is in OFF, the coil transfers energy to the capacitors *C*<sup>1</sup> and *C*3. As a result, from loop 1 and loop 2, it can verify that

$$\begin{aligned} \mathbf{v} - V\_{PV} + \mathbf{v}\_{L1} + \mathbf{v}\_{C2} &= \mathbf{0} \Rightarrow \mathbf{v}\_{L1} = -\mathbf{v}\_{C2} + V\_{PV} \\ \mathbf{v}\_{L2} + \mathbf{v}\_{C3} &= \mathbf{0} \Rightarrow \mathbf{v}\_{L2} = -\mathbf{v}\_{C3} \\ \mathbf{v}\_{C2} &= \mathbf{v}\_{C1} \end{aligned} \tag{4}$$

From loop 1 and loop 2 (mode-II Figure 2b), the capacitor current *iC*<sup>1</sup> and *iC*<sup>2</sup> are derived as follows,

$$\begin{aligned} \dot{i}\_{\rm C1} &= \dot{i}\_{\rm D1} - \dot{i}\_{\rm O} \\ \dot{i}\_{\rm C2} &= \dot{i}\_{\rm L1} - \dot{i}\_{\rm D1} = \dot{i}\_{\rm D2} - \dot{i}\_{\rm L2} \end{aligned} \tag{5}$$

$$I\_{\mathbb{C}} = \frac{1}{T} \int\_{0}^{T} i\_{\mathbb{C}} dt = \frac{\mathbb{C}}{T} \int\_{0}^{T} dv\_{\mathbb{C}}(t) = \frac{\mathbb{C}}{T} (v\_{\mathbb{C}}(T) - v\_{\mathbb{C}}(0)) \tag{6}$$

during steady-state condition *VC*(*T*) = *VC*(0). Hence, the average value of the current capacitors is null. Also, the inductor coils average voltage is zero, since *vL*(*t*) <sup>=</sup> *<sup>L</sup>diL*(*t*) *dt* . The currents in the inductors and voltage in the capacitors tend to be approximately constant. The power switch is in the ON state for a percentage of the period (δ*T*) and OFF during the next state (δT-T). Here, T is the total switching time. Therefore, the average value inductor voltage *VL*<sup>1</sup> and capacitor's current *iC*<sup>1</sup> are illustrated in Figure 4 and Figure 7.

$$V\_{L1} = \frac{1}{T} \left[ \int\_{O}^{\delta T} V\_{PV} dt + \int\_{\delta T}^{T} (V\_{PV} - V\_{C1}) dt \right] = 0 \tag{7}$$

**Figure 4.** Inductor voltage *VL*1.

Replacing the voltage on the calculation, we obtain the capacitor voltage *VC*<sup>1</sup>

$$V\_{C1} = \frac{1}{1 - \delta} V\_{PV} \tag{8}$$

The inductor *L*<sup>2</sup> voltage is illustrated in Figure 5, and inductor average voltage value is

**Figure 5.** Inductor voltage *VL*2.

$$V\_{L2} = \frac{1}{T} \left[ \int\_0^{\delta T} (V\_{C1} - V\_{C3}) dt + \int\_{\delta T}^T -V\_{C3} dt \right] = 0\tag{9}$$

The voltage across the capacitor *C*<sup>3</sup> can be written as

$$V\_{C3} = \frac{\delta}{1-\delta} V\_{PV} \tag{10}$$

Hence, the converter output voltage can be calculated as

$$V\_O = \frac{1+\delta}{1-\delta} V\_{PV} \tag{11}$$

By equating the converter input power and output power, the input inductor current is derived as

$$V\_{PV}I\_{L1} = V\_O I\_O \Rightarrow I\_{L1} = \frac{1+\delta}{1-\delta}I\_O \tag{12}$$

When the Kirchhoff's current law is applied in the loop

$$i\_{\rm C3} + i\_{\rm O} - i\_{\rm L2} = 0 \Rightarrow i\_{\rm L2} = i\_{\rm C3} + i\_{\rm O} \tag{13}$$

The capacitor *C*<sup>3</sup> charge and discharge current is shown in Figure 6. Here the capacitor current average value observed is zero, and the average current in the inductor is similar to the average output current, as the inductor tends to retain that average value.

**Figure 6.** Capacitor current *iC*3.

Assuming that *i*<sup>0</sup> = *i*l2

**Figure 7.** Capacitor current *C*1.

The mean value of the capacitor *C*<sup>1</sup> current (*iC*1) is displayed in Figure 7. From the capacitor current interval zero to δ*T* and δ to *T* time, the *iC*<sup>1</sup> is calculated as

$$I\_{C1} = \frac{1}{T} \left[ \int\_0^{\delta T} (-i\_O) dt + \int\_{\delta T}^T (i\_{D1} - i\_O) dt \right] = 0 \tag{14}$$

$$i\_{D1} - i\_O = i\_O \frac{\delta}{1 - \delta} \tag{15}$$

When the power switch T is turned ON, the diode *D*<sup>1</sup> current is calculated as

$$i\_{D1} = \frac{I\_O}{1 - \delta} \tag{16}$$

Similarly, when the power switch T is turned OFF, the diode *D*<sup>2</sup> current is calculated as

$$
\dot{i}\_{L1} - \dot{i}\_{D1} = \dot{i}\_{D2} - \dot{\mathbf{u}}\_{L2} = I\_O \frac{\delta}{1 - \delta} \tag{17}
$$

$$i\_{D2} = \frac{I\_O}{1 - \delta} \tag{18}$$

The current of the power switch T can be written as

$$i\_T = i\_{L1} - i\_{C2} = \frac{2I\_O}{1 - \delta} \tag{19}$$

### **3. Scaling Converter Components Design**

The proposed hybrid converter reactive components, inductors coil (*L*<sup>1</sup> and *L*2) and capacitors (*C*1, *C*<sup>2</sup> and *C*3), are calculated for maximum values as the power switch T should support both the converter voltage and current.

### *3.1. Design of Inductors*

The inductor coil (*L*<sup>1</sup> and *L*2) values calculation and current limitation analysis are observed by precise variation concerning the average value shown in Figure 8. The differential equation of inductor voltage *VL* is shown as

$$w\_L(t) = L \frac{di\_L(t)}{dt} \tag{20}$$

**Figure 8.** Evolution of the inductor current.

By assuming inductor voltage *VL* nearly constant, the current equation inductor is calculated as follows

$$i\_L(t) = \frac{v\_L}{L} \Delta t\_L + i\_L(t0) \tag{21}$$

Thus, *vL*(*t*) <sup>=</sup> *<sup>L</sup>diL*(*t*) *dt* it becomes

$$\frac{\Delta i\_L}{\Delta t\_L} = \frac{v\_L}{L} \tag{22}$$

Using the instantaneous inductor voltage equation, the inductor voltage will be

$$w\_{L1} = \begin{cases} \begin{array}{c} V\_{PV} \\ V\_{PV} - V\_{C1} \end{array} \begin{array}{c} nT < t < nT + \delta T \end{array} \\ \begin{array}{c} nT - V\_{C1} \end{array} \begin{array}{c} nT + \delta T < t < (n+1)T \end{array} \tag{23}$$

During 'ON' state of the power switch, Δ*tL* = δ*T*

$$L\_1 = \frac{V\_{PV} \delta T}{\Delta i\_{L1}}\tag{24}$$

$$v\_{l,2} = \begin{cases} \begin{array}{l} V\_{\subset 1} - V\_{\subset 3}, \\ -V\_{\subset 3}, \end{array} nT < t < nT + \delta T \\ \begin{array}{l} nT + \delta T < t < (n+1)T \end{array} \end{cases} \tag{25}$$

For the 'OFF' state of the power switch, it has Δ*tL* = (1 − δ)*T*

$$L\_2 = \frac{v\_{\rm C3}(1-\delta)T}{\Delta i\_{l\,2}}\tag{26}$$

### *3.2. Design of Capacitors*

The calculation of capacitor values *C*1, *C*<sup>2</sup> and *C*<sup>3</sup> are given below. The changing and discharging variation around the average value is shown in Figure 9.

**Figure 9.** Evolution of the current in the coil.

The differential equation of the capacitor

$$i\_{\mathcal{L}}(t) = \mathbb{C} \frac{dv\_{\mathcal{L}}(t)}{dt} \tag{27}$$

Similar to the calculation of inductors, the capacitor variation is calculated using Equation (27) after linearization of *ic*(*t*) <sup>=</sup> *<sup>C</sup>dvc*(*t*) *dt* becomes,

$$\frac{\Delta v\_{\text{c}}}{\Delta t\_{\text{c}}} = \frac{i\_{\text{C}}}{\text{C}} \tag{28}$$

With the instantaneous value of the capacitor current over a certain period, the value of the capacitor can be calculated. For capacitor *C*1, the current is given by:

$$i\_{\mathbb{C}1} = \begin{cases} -I\_{0\_{\prime}} & nT < t < nT + \delta T \\\ I\_{0} \frac{\delta}{1 - \delta} & nT + \delta T < t < (n+1)T \end{cases} \tag{29}$$

During the first-time interval, for Δ*tc* = δ*T*, *C*<sup>1</sup> is

$$\mathbf{C}\_{1} = \frac{I\_{0}\delta T}{\Delta v\_{C1}}\tag{30}$$

The capacitor current *C*<sup>2</sup> is given by

$$i\_{C2} = \begin{cases} -I\_{0\prime} & nT < t < nT + \delta T \\\ I\_0 \frac{\delta}{1 - \delta} & nT + \delta T < t < (n+1)T \end{cases} \tag{31}$$

During the time interval, when Δ*tc* = δ*T*

$$\mathbf{C}\_{2} = \frac{I\_{0}\delta T}{\Delta v\_{C2}}\tag{32}$$

For capacitor *C*3, the current does not show instantaneous values and is nearly constant during the switching state. The behavior of capacitor *C*<sup>3</sup> is opposite capacitors *C*<sup>1</sup> and *C*2. When controlling the power semiconductor switch for the driving load variation, capacitor charge Δ*Q* is related to the inductor current Δ*iL*2/2 and time is taken T/2.

$$Q = \mathbb{C}v\_{\mathbb{C}} \Rightarrow \mathbb{C} = \frac{Q}{v\_{\mathbb{C}}} \text{ } \mathbb{C} \mathfrak{z} = \frac{\Delta Q}{\Delta v\_{\mathbb{C}3}} \tag{33}$$

$$\text{At load variation, } \Delta Q = \frac{\frac{T}{2} \frac{\Delta i\_2}{2}}{2} = \frac{T \Delta i\_{L2}}{8} \tag{34}$$

$$\text{The capacitor } C\_3 \text{value is calculated as } C\_3 = \frac{T \Delta i\_{l,2}}{8 \Delta v\_{c3}} \tag{35}$$

In the dynamic condition, capacitors *C*<sup>1</sup> and *C*<sup>3</sup> values are deliberate in this section. The calculation is computed by including the sudden change in drive load resistance. Output voltage in the dynamic operating region is determined using the equivalent circuit (Figures 10 and 11), assuming that the current passes zero to its steady-state value, Δ*t*1, the settling time of the current in the inductor *L*1.

$$i\_{\mathbb{C}1} = \mathbb{C}\_1 \frac{dv\_{\mathbb{C}1}}{dt} = -i\_0 \quad \Rightarrow v\_{\mathbb{C}1}(t) = \frac{1}{\mathbb{C}\_1} \int\_0^t (-i\_0)dt + v\_{\mathbb{C}1}(0) \tag{36}$$

$$v\_{\mathbb{C}1}(\Delta t\_1) = \frac{1}{\mathbb{C}\_1} \int\_0^t (-i\_0)dt + v\_{\mathbb{C}1}(0) = -\frac{1}{\mathbb{C}\_1} \frac{P\_0}{V\_0} \Delta t\_1 + v\_{\mathbb{C}1}(0) \tag{37}$$

Thus, capacitor voltage *VC*<sup>1</sup> is calculated using Equation (37)

$$v\_{\mathbb{C}1}(\Delta t\_1) = \frac{1}{\mathbb{C}\_1} \int\_0^t (-i\_0)dt + v\_{\mathbb{C}1}(0) = \frac{1}{\mathbb{C}\_1} \frac{P\_0}{V\_0} \Delta t\_1 \Rightarrow \mathbb{C}\_1 = \frac{1}{\Delta v\_{\mathbb{C}1}} \frac{P\_0}{V\_0} \tag{38}$$

In a dynamic case, while changing the converter duty ratio, the inductor current increases coil rapidly. Hence, the Δ*t*<sup>1</sup> value needs to calculate, in detail, from the response of *iLI*(*s*), which displays the input current of the response when rapid changes occur in output current *io*(*s*). At time Δ*t*2, the current flow through the capacitor *C*<sup>3</sup> is calculated as

$$i\_{\rm C3} = \mathcal{C}\_2 \frac{dv\_{\rm C3}}{dt} = -i\_0 \tag{39}$$

$$\mathcal{L}\_3 = \frac{1}{\Delta v\_{\rm C3}} \frac{P\_0}{V\_0} \Delta t\_{\rm 2} \tag{40}$$

For calculation straightforwardness, it is assumed that the current has equal settling times.

In terms of the energetic properties, the proposal converter is similar to the boost and Cuk converters. The proposed converter input inductor, power switches and input source are organized the same way as the classical boost and Cuk converters. Except for the input side boost inductor (*L*1) and the power switch T, the rest of the proposed converter circuit elements are connected precisely in parallel with each other and on the output side, two capacitors (*C*<sup>1</sup> and *C*3) are placed across the load. Therefore, the proposed converter increases the voltage gain by combining the benefits of boost and Cuk converters.

### *3.3. Small Signal Analysis of Hybrid DC–DC Converter*

The average equivalent circuit model of the proposed hybrid DC–DC converter was derived and is presented in Figure 10. The circuit analysis was derived for the switch in both the ON and OFF period. The initial conditions were an approach to obtain the average value of the coil; the current remained the same.

**Figure 10.** Equivalent circuit of the converter with losses in the mode-1 operation.

**Figure 11.** Equivalent circuit of the converter with losses in mode-2 and mode-3 operation.

By the application of mesh law to the circuit in Figure 10, we can verify that

$$\begin{cases} -V\_{PV} + v\_{L1} + r\_{L1}I\_{L1} + R\_{DSm}i\_T = 0\\ v\_{C2} - v\_{L2} - R\_{DSm}i\tau - v\upsilon \text{3} - r\_{L2}I\_{L2} = 0 \end{cases} \\ \Rightarrow \begin{cases} v\_{L1} = -V\_{PV} - r\_{L1}I\_{L1} - R\_{DSm}i\_T\\ v\_{L2} = v\_{C2} - R\_{DSm}i\tau - v\_{C3} - r\_{L2}I\_{L2} \end{cases} \tag{41}$$

$$\begin{cases} -V\_{PV} + v\_{L1} + r\_{L1}I\_{L1} + v\_{C2} + V\_{D2} + R\_{D2}i\_{D2} = 0\\ v\_{L2} + r\_{L2}I\_{L2} + v\_{C3} + V\_{D2} + R\_{D2}i\_{D2} = 0 \end{cases} \\ \Rightarrow \begin{cases} v\_{L1} = -V\_{PV} - r\_{L1}I\_{L1} - v\_{C2} - V\_{D2} - R\_{D2}i\_{D} \\ v\_{L2} = -r\_{L2}I\_{L2} - v\_{C3} - V\_{D2} - R\_{D2}i\_{D2} \end{cases} \\ \tag{42}$$

$$
\dot{\mathbf{v}} - \mathbf{V}\mathbf{p}\mathbf{v} + \mathbf{v}\mathbf{u}\_1 + \mathbf{r}\mathbf{u}\_1\mathbf{I}\mathbf{u}\_1 + \mathbf{v}\mathbf{c}\mathbf{u}\_1 + \mathbf{r}\mathbf{p}\mathbf{u}\_1 + \mathbf{R}\mathbf{p}\mathbf{u}\_1\mathbf{u}\_1 = \mathbf{0} \tag{43}
$$

$$\upsilon\_{D1} = \upsilon\_{D2}, \ R\_{D1} i\_{D1} = R\_{D2} i\_{D2}, \ \upsilon\_{C2} = \upsilon\_{C1}$$

From the waveform *vL*<sup>1</sup> and *vL*2,

$$V\_{L1A} = V\_{PV} - R\_{D\text{son}}I\_T - r\_{L1}I\_{L1} \tag{44}$$

$$V\_{L1B} = V\_{PV} - r\_{L1}I\_{L1} - V\_{C1} - V\_{D2} - R\_{D2}I\_{D2} \tag{45}$$

$$V\_{L2A} = V\_{C1} - R\_{DSON}I\_{SC} - V\_{C3} - r\_{L2}I\_{L2} \tag{46}$$

$$V\_{L2B} = -r\_{L2}I\_{L2} - V\_{C3} - V\_{D2} - \mathcal{R}\_{D2}I\_{D2} \tag{47}$$

The analysis of converter input to output relation is calculated with losses and approximated with ideal semiconductor devices. The output voltage expressions of the converter were derived and are given below.

$$V\_{L1} = 0 \Rightarrow V\_{C1} = \frac{V\_{PV} - r\_{L1}I\_{L1}}{1 - \delta} \tag{48}$$

$$V\_{\rm L2} = 0 \Rightarrow V\_{\rm C3} = \frac{\delta}{1 - \delta}(V\_{\rm PV} - r\_{\rm L1}I\_{\rm L1}) - r\_{\rm L2}I\_{\rm L2} \tag{49}$$

From the expressions *VC*<sup>1</sup> and *VC*2, the voltage gain converter is calculated as

$$\frac{V\_0}{V\_{PV}} = \frac{1+\delta}{1-\delta + \frac{r\_{L1}}{R\_0}\frac{\left(1+\delta\right)^2}{1-\delta} + \frac{r\_{L2}}{R\_0}(1-\delta)}\tag{50}$$

where *rL*1/*R*<sup>0</sup> = *rL*2/*R*0.

Figure 12 illustrates the voltage output gain versus the duty cycle for the proposed hybrid converter. The Figure indicates the ideal condition (*rL*1/*R*<sup>0</sup> = 0), where losses need to be introduced in the circuit (the gain for unit value goes to zero, as expected) and other operating conditions *rL*1/*R*<sup>0</sup> = *rL*2/*R*<sup>0</sup> = 0.0001 to 0.76, where near 0.76 duty cycle, the converter gain approaches six times boosting (*V*<sup>0</sup> = 6*Vin*).

**Figure 12.** Voltage output gain versus duty cycle.

### *3.4. Analysis of Losses*

The losses of each indictor *L*<sup>1</sup> and *L*<sup>2</sup> are denoted from internal resistors *rL*<sup>1</sup> and *rL*2, respectively. Thus, the losses in *rL*<sup>1</sup>

$$P\_{\rightleftarrows}r\_{L1} = p\_1 \pm P\_{\rightleftarrows} = r\_{L1}I\_{L1rms^2} \Leftrightarrow r\_{L1} = \frac{p\_1 P\_{\overline{i}}}{I\_{L1rms}^2} \tag{51}$$

The sufficient value is given as

$$I\_{L1rms} = \sqrt{I\_{L1}^2 + \left(\frac{\Delta i\_{L1}}{2\sqrt{3}}\right)^2} = \sqrt{I\_{L1}^2 + \left(\frac{0.1I\_{L1}}{2\sqrt{3}}\right)^2} = I\_{L1}\sqrt{1 + \left(\frac{0.1}{2\sqrt{3}}\right)^2} \tag{52}$$

$$\Delta i\_{L2} = 0.1I\_{L2} \tag{53}$$

Since both the inductors are identical, Δ*iL*<sup>1</sup> = 0.1*IL*<sup>1</sup> (53)

Two kinds of losses in the semiconductor are driving and switching.

*3.5. Conduction Losses in the Diodes*

The losses in the diode are given as

$$P\_D = \frac{1}{T} \int\_0^T v\_D(t) i\_D(t) dt = V\_D I\_D + R\_D I\_{D\text{rms}}^2 \tag{54}$$

$$
\dot{v}\_D(t) = V\_D + R\_D i\_D(t) \tag{55}
$$

Specific to the case of the diode, for mode-2 operation:

$$i\_{D1}(\delta T < t < T) = \frac{I\_0}{(1 - \delta)}\tag{56}$$

$$I\_{D1} = \frac{1}{T} \int\_0^T i\_{ak1}(t)dt = I\_0 \tag{57}$$

$$I\_{D1rms} = \sqrt{\frac{1}{T} \int\_0^T t\_{D1}^2(t)dt} = \frac{I\_0}{\sqrt{(1-\delta)}}\tag{58}$$

Thus, resistance is calculated as

$$P\_{D1} = \frac{p\_3}{2} P\_i = V\_{D1} I\_0 + R\_{D1} \left(\frac{I\_0}{\sqrt{(1-\delta)}}\right)^2 \Leftrightarrow R\_{D1} = \left(\frac{p\_3}{2} P\_i - V\_{D1} I\_0\right) \frac{(1-\delta)}{I\_0^2} \tag{59}$$

The same can be applied to *D*2, resulting in the same results for this diode

$$R\_{D2} = \left(\frac{p\_3}{2}P\_i - V\_{D2}I\_0\right)\frac{(1-\delta)}{I\_0^2} \tag{60}$$

### **4. Design Procedure**

The component selections and other design parameters of the proposed converter at the power range of 150 W were calculated and are presented. The input power was considered a DC-fixed source. The general diagram of the converter design flow chart is shown in Figure 13.

**Figure 13.** Design setup of converter parameter selections.

*Energies* **2020**, *13*, 2312

To illustrate the numerical values of converters, capacitor and inductors, the below parameters were fixed for the converter design.


$$\text{1.} \quad \text{Diodes } D\_1 \text{ and } D\_2. \text{ } Vs\_{\text{max}} = 100 \text{ V}\_\prime \text{ } Vs\_{\text{max}} = 95 \text{ V}.$$

The *D*<sup>1</sup> and *D*<sup>2</sup> can ensure a voltage of 100V, which ensures the safety factor of the converter. The converter can support a maximum current of six amps. When using six amps, the current safety factor is reduced to 60%–65%. Hence, the semiconductor must be selected to withstand the converter to provide maximum currents and voltages with a safety factor around 50%. The n-type reinforcing MOSFET is better chosen for providing the safety factor, and the proposed converter design uses the same [35]. The diodes (*D*<sup>1</sup> and *D*2), and MOSFET switching losses and conduction losses were calculated and given in Equations (61)–(73).

Conduction losses of the diode *D*<sup>1</sup> and *D*2:

$$P\_{\rm D} = \int \mathbf{V\_{ak}} \left( \mathbf{t} \right) \mathbf{i}\_{\rm ak} \left( \mathbf{t} \right) dt = \mathbf{V\_{D}} \mathbf{i}\_{\rm ak} + \mathbf{R\_{D}} I\_{\rm alrms}^2 \tag{61}$$

$$\mathbf{R\_{D1}} = \left(\frac{p\Im}{2}\mathbf{p\_i} - \mathbf{V\_{D1}}\mathbf{I\_o}\right)\frac{(1-\delta)}{I\_o^2} \tag{62}$$

$$\mathbf{R\_{D1}} = \left(\frac{p\Im}{2}\mathbf{p\_i} - \mathbf{V\_{D2}}\mathbf{I\_o}\right)\frac{(1-\delta)}{I\_o^2} \tag{63}$$

$$\mathbf{P\_{D1}} = \mathbf{V\_{D1}} \mathbf{i\_{ak1}} + \mathbf{R\_{D1}} I\_{\text{akrms1}}^2 \tag{64}$$

$$\mathbf{P\_{D2}} = \mathbf{V\_{D2}} \mathbf{i\_{ak2+}} \mathbf{R\_{D2}} I\_{\mathbf{akms2}}^2 \tag{65}$$

Switching losses of the Diode *D*<sup>1</sup> and *D*2:

$$P\_{\rm SD1} = \frac{\mathbf{t}\_{\rm rr} - \mathbf{t}\_{\rm s}}{T} \mathbf{V}\_{\rm ak1} \mathbf{i}\_{\rm ak1} \tag{66}$$

$$\mathbf{P\_{SD2}} = \frac{\mathbf{t\_{rr}} - \mathbf{t\_6}}{\mathbf{T}} \mathbf{V\_{ak2}} \mathbf{i\_{ak2}} \tag{67}$$

Conduction losses of the MOSFET:

$$\text{P}\_{\text{MOSFET Conduration Loss}} = \text{R}\_{\text{DS\\_ONMOSFET rms}} \tag{68}$$

$$\mathbf{i}\_{\text{MOSFET}} = \frac{2l\_0}{(1 - \delta)}\tag{69}$$

$$\mathbf{P\_{P\_{MOSFET\ switching loss}}} = \frac{\mathbf{t\_{ON}} + \mathbf{t\_{OFF}}}{\mathbf{T}} (\mathbf{V\_{MOS\ MOS}}) + \frac{1}{2\mathbf{T}} (\mathbf{C\_{MOS}}\mathbf{V\_{MOS}})^2 \tag{70}$$

Total switching losses for the proposed converter is:

$$P\_{\text{total switching losses}} = \frac{\text{t}\_{\text{ON}} + \text{t}\_{\text{OFF}}}{\text{T}} (\text{V}\_{\text{MOS}} \text{i}\_{\text{MOS}}) + \frac{1}{2\text{T}} (\text{C}\_{\text{MOS}} \text{V}\_{\text{MOS}})^2 + 2\frac{\text{t}\_{\text{IT}} \text{t}\_{\text{S}}}{\text{T}} \text{V}\_{\text{ak}} \text{i}\_{\text{ak}} \tag{71}$$

$$\mathbf{t}\_{\rm ON} = \mathbf{t}\_{\rm r}(\mathbf{i}\_{\rm MCS}) + \mathbf{t}\_{\rm f}(\mathbf{V}\_{\rm MOS}) \tag{72}$$

$$\mathbf{t}\_{\rm OFF} = \mathbf{t}\_{\rm f}(\mathbf{i}\_{\rm MOS}) + \mathbf{t}\_{\rm r}(\mathbf{V}\_{\rm MOS}) \tag{73}$$

The efficiency of the proposed converter is found using

$$\eta = \left(\frac{\mathbf{P\_o}}{\mathbf{P\_i}}\right) = \frac{\mathbf{P\_i} - \sum \mathbf{P\_T}}{\mathbf{P\_i}} \tag{74}$$

where Pi = input power and PT = Total losses (P Diode2 Con.Losses + PDiode2 Con.Losses + PMOSFET switching loss + PMOSFET Conduction Loss).

### **5. Simulation Results**

The hybrid DC–DC converter operation and performance estimation were modeled in the MATLAB/Simulink simulation platform and waveforms were presented. The simulation specification and parameter were as follows: The input power = 150 W, input voltage of the converter (Vin) = 24 V, maximum duty cycle δ = 0.8 and switching frequency fs = 10 kHz. The converter input and output inductors were *L*<sup>1</sup> = 1 mH and *L*<sup>2</sup> = 1 mH receptivity. The capacitors were *C*<sup>1</sup> = 100 μF, *C*<sup>2</sup> = 100 μF and *C*<sup>3</sup> = 2 μF. Figures 14–17 show the proposed converter simulation results for 10 kHz switching frequency and 80% duty cycle, and the results confirm the theoretical values. The converter duty cycle was fixed to be equal to or less than 0.8 to minimize the conduction losses. From Figure 14, when the converter duty cycle was fixed at 0.8 with 24V input voltage, the converter delivered an output voltage of 124 V (5.166 times higher than the input voltage). During the continuous conduction mode, the inductance L1 current was limited within the saturation limit in the range of 3 to 4.5 A and maintained the converter input current. Figure 15 displays the input current, as well as voltage across the power switches, and Figure 17 shows *D*<sup>1</sup> and *D*<sup>2</sup> voltages, *VD1* and *VD2,* respectively, during the switching period. From the results, it could be seen that during the time of switching, the switches (MOSFET and diode) were maintained with their maximum allowable voltage as 100 V. It was verified that the voltage across the switches was less than that of the converter. From the *iL*<sup>2</sup> and *VD2* simulation results, it can be seen that the proposed converter maintains a continuous current capability. Figure 16 shows the simulation waveforms for the inductor current iL1 and inductor current *iL*2. From this waveform, it is seen that the inductors were charging uniformly and delivering the current in the continuous conduction. Figure 17 illustrates the voltage across the power diode, *VD1* and *VD2*. When the duty cycle was reduced to 0.6, the converter performance, switching reliability and continuous current capability were linear. Hence, the proposed converter has a wide range of controllability with a controlled degree of freedom to avail wider voltage outputs. The simulation was also performed in transient conditions (changing load and sudden change in the duty cycle). During this transient period, the output voltage and current through iL1 changed with a small transient period and after reaching the continuous conduction and maintaining the constant output voltage.

**Figure 14.** Simulation waveforms for input voltage 24V DC and 0.8 duty cycle; (**a**) input voltage waveform (voltage scale: 1 V/div and t: 20 μs/div) and (**b**) input voltage waveform (voltage scale 50 V/div and t: 20 μs/div).

**Figure 15.** Simulation waveforms for input voltage 24V DC and 0.8 duty cycle; (**a**) input current waveform (current scale: 0.5 A/div and t: 20 μs/div) and (**b**) voltage across the power switch waveform (voltage scale 50 V/div and t: 20 μs/div).

**Figure 16.** Simulation waveforms for input voltage 24 V DC and 0.8 duty cycle; (**a**) inductor current *iL*<sup>1</sup> waveform (current scale: 0.5 A/div and t: 20 μs/div) and (**b**) inductor current iL2 waveform (current scale: 0.5 A V/div and t: 20 μs/div).

**Figure 17.** Simulation waveforms for input voltage 24V DC and 0.8 duty cycle; (**a**) voltage across the power diode, VD1 waveform (voltage scale: 50 V/div and t: 20 μs/div) and (**b**) voltage across the power diode, VD2 waveform (voltage scale: 50 V/div and t: 20 μs/div).

The proposed single switch hybrid DC–DC converter is compared with conventional converters (boost and Cuk) for different duty cycles from the range zero to one. The switching frequency and other circuit components for this evaluation were taken as being the same as the proposed converter values are given in the design (see Table 1). As expected, the proposed converter voltage gain was more than the boost and Cuk converter duty cycle. Figure 18 shows the voltage gain comparison of boost and Cuk with the proposed converter.

**Figure 18.** Voltage gain comparison of boost and Cuk with the proposed converter.

### **6. Experimental Results**

To confirm the experimental performance of the proposed hybrid DC–DC converter, the experimental laboratory setup was developed in collaboration with a Peripheral Interface Controller (PIC) microcontroller, as shown in Figure 19. To verify the theoretical and simulation results, the experimentations were conducted with similar values considered in the simulation studies. The converter was a 150 W circuit with parameters as listed in Table 1.

Similar to the simulation verification, the converter duty cycle was fixed as equal to or less than 0.8 to minimize the conduction losses. While testing the converter, the input DC source was fixed to generate constant input voltage and power as 24 V and 150 W range. As seen in Figure 20, while the converter duty cycle was fixed as 0.8, the corresponding output voltage was observed to be 122 V (closer to the simulation results). Figure 21 shows the converter input current and output voltage.

**Figure 19.** Prototype setup of the proposed converter.


**Table 1.** Parameter of components of the proposed converter.

**Figure 20.** The experimental waveform of the duty cycle and input voltage.

**Figure 21.** The experimental waveform of input voltage and output voltage for input voltage 24 V and 0.8 duty cycle.

During the DC-to-DC conversion period, the converter maintained the continuous conduction with the inductance *L*<sup>1</sup> current saturation limit range of 3 to 4.5 A, as depicted in Figure 22. Hence, the power switch was secured against the high rising current by maintaining the converter input current inductance *L*<sup>1</sup> current saturation limit, which ensures the converter reliability against the input source. Similarly, from Figures 23 and 24, during the time of switching, the MOSFET and diode were maintained with their maximum allowable voltage as 100 V, which was smaller than the converter output voltage (102 V). Here, during the switching period, the voltage across the main power switch was 100 V, and diode *D*<sup>1</sup> and *D*<sup>2</sup> were equal to *VD1* = 100 V and *VD2* = 95 V, respectively. During the entire mode of operation, the inductor current iL1 and iL2 maintained the identical current profile, which maintains the voltage balance between *C*<sup>1</sup> and *C*2. Figure 25 shows the experimental waveform of the input inductor current, *iL*<sup>1</sup> and voltage across *iD2* the power switch for input voltage 24 V and 0.8 duty cycle.

**Figure 22.** The experimental waveform of input current and output voltage for input voltage 24 V and 0.8 duty cycle.

**Figure 23.** The experimental waveform of input current and voltage across the power switch for input voltage 24 V and 0.8 duty cycle.

Next, the converter was operated by changing the duty ratio to observe transient operation behaviour. For the period of transient operation, the converter load was kept constant as the previous value. During the trial, the switching duty-cycle varied from 0.8 to 0.5. During this period, likely the output voltage decreased and stabilized after a few milliseconds. A similar response happened in the inductor current i*L1* and preserved in the converter in continuous conduction.

To validate the comparison of the theoretical and experimental results, the converter continuous conduction mode(CCM) state voltage gain was plotted concerning the variation duty ratio from 0.2 to 0.8 (see Figure 26a). From the results, it can be seen that the experimental values are very close to the theoretical calculations. Finally, the efficiency of the proposed converter was found under full load. The calculated experimental maximum efficiency of the proposed converter at 0.8 duty cycle is 92.2%. The calculated experimental maximum efficiency of the proposed converter is 92.2%. Figure 26b shows experimental power loss distribution operating at the rated condition. During duty ratio δ = 0.8, the semiconductors (*D*1, *D*<sup>2</sup> and MOSFET) switching losses were calculated as 0.4 W, 0.5 W and 1.2 W using equations (61)–(74). Hence, the total switching losses for the converter was 2.1 W. Similarly, the conduction of the power switches and other circuit parameters losses were observed. In the overall power distribution losses, the MOSFET switching loss and conduction loss alone are about 52%. As presented in Figure 26b, the I2R losses in the MOSFET, diode and the snubber circuitry losses were accounted for as significant losses. Nevertheless, the proposed converter voltage stress reduction helps to choose the lower voltage-rating switch, and hence conduction losses are expected to reduce.

**Figure 24.** The experimental waveform of the input inductor current, *iL*<sup>1</sup> and voltage across *iD1* the power switch for input voltage 24 V and 0.8 duty cycle.

**Figure 25.** The experimental waveform of the input inductor current, *iL*<sup>1</sup> and voltage across *iD2* the power switch for input voltage 24 V and 0.8 duty cycle.

**Figure 26.** (**a**) Theoretical and experimental results comparison. (**b**) Experimental power loss distribution operating at rated condition (duty ratio from 0.8).

### *Key Performance Comparison*

For validating the proposed converter performance, Table 2 shows the comparison with other similar converters. According to the table, the proposed converter provides a better voltage gain with a single active switch, and normalized voltages stress of semiconductor devices is less when compared to other converters. Based on the presented analysis and discussions, results and comparisons confirm the functionality and advantages of the proposed converter.


**Table 2.** Performance comparison of similar converter topology.

### **7. Conclusions**

The high voltage gains and highly efficient single switch hybrid non-isolated DC–DC converter is shown in this paper. The proposed topology was derived by integrating conventional boost and Cuk converters. This topology produced a non-inverting output in continuous input current mode with a single switch having high voltage gain (≈5.116 gain). When compared with the classical boost and Cuk converters, the proposed topology facilitates a substantial voltage gain with comparable lower switching stress. The steady-state analysis under the CCM condition and design calculation for the proposed hybrid was discussed in detail.

Finally, the validation test done with the proposed converter privileges, the voltage gain, power switch voltage stress and elements used in the circuit simulation studies were presented. Characterize the proposed topology for its obtained performances, PIC microcontroller based real-time experimental setup was realized under the power rating of 150 W with an efficiency of 92.2%. Experimental results confirmed the practicability in real-time applications needs.

**Author Contributions:** All authors are involved in developing the concept, simulation and experimental validation and in proof-reading the article. All authors have read and agreed to the published version of the manuscript.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **Double Stage Double Output DC–DC Converters for High Voltage Loads in Fuel Cell Vehicles**

### **Mahajan Sagar Bhaskar, Sanjeevikumar Padmanaban \* and Jens Bo Holm-Nielsen**

Center for Bioenergy and Green Engineering, Department of Energy Technology, Aalborg University, 6700 Esbjerg, Denmark; sagar24.mahajan@gmail.com (M.S.B.); jhn@et.aau.dk (J.B.H.-N.)

**\*** Correspondence: san@et.aau.dk

Received: 1 July 2019; Accepted: 19 September 2019; Published: 26 September 2019

**Abstract:** This article aims to enhance the output voltage magnitude of fuel cells (FCs), since the actual generation is low. The traditional technique is too complicated and has a cascaded or parallel connection solution to achieve high voltage for multiple loads in vehicles. In this case, electronic power converters are a viable solution with compact size and cost. Hence, double or multiple output DC–DC converters with high voltage step up are required to feed multiple high voltage loads at the same time. In this article, novel double stage double output (DSDO) DC–DC converters are formulated to feed multiple high voltage loads of FC vehicular system. Four DSDO DC–DC converters called DSDO L–L, DSDO L-2L, DSDO L-2LC, and DSDO L-2LC are developed in this research work and all the converters are derived based on the arrangement of different reactive networks. The primary power circuitry, conceptual operation, and output voltage gain derivation are given in detail with valid proof. The proposed converters are compared with possible parallel combinations of conventional converters and recently available configuration. Comprehensive numerical simulation and experimental prototype results show that our theoretical predictions are valid and that the configuration is applicable for real time application in FC technologies for 'more-electric vehicles'.

**Keywords:** DC–DC; double stage; double output; fuel cell; step-up; vehicular system; X–Y converter family

### **1. Introduction**

In electric grid, hybrid 'more-electric vehicles', automobile high-intensity discharge headlamps, uninterruptible power supply, and luxury loads application multiport and multilevel power converters popular solutions [1–4]. Some advanced predictive control based on the multilevel converter is also proposed for energy storage [5,6]. Fuel cells have many features, including compatibility, size, and modularity [7,8]. However, the amalgamation of series and parallel FCs is not a suitable solution for generating high DC voltage/current. Trade-off loss increases the cost of the system and requires a large space. Furthermore, the major obstacles facing FC technology are durability, low generated voltage, and to fulfill the voltage demand of high voltage loads in FC vehicles. In such cases, power electronic DC–DC converters with high voltage conversion ratios and high efficiency play a pivotal control role [9–12]. Theoretically, a moderate or high output voltage is obtained from a traditional boost converter by operating in an extreme duty cycle. Adverse effects at extreme duty ratio lead to reduced controllability, increased switching losses, high conduction losses, large current ripple, high current and voltage ratings, and reverse diode recovery problems [13–16]. Consequently, traditional DC–DC converters are not suitable candidates for FC electric vehicle applications.

Previous research has achieved high voltage conversion ratio by using a cascaded traditional boost converter configuration. However, cascaded converter configurations have low efficiency and high cost due to the increased number of high voltage/current rating semiconductor devices and reactive elements [17,18]. Further, for implementation, they need complex control logic and increased driver modules to protect and control the semiconductor devices. Quadratic boost converters achieve a high voltage conversion ratio, but high current/voltage rating components/devices and the internal resistance of the inductors limits the output voltage [19]. Multistage diode/capacitor-based DC–DC converters have been proposed to achieve high voltage gain [20–24]. However, multiple discharging/charging loops of the capacitors lead to increased conduction loss, cost, and size, and reduced efficiency due to their parasitic nature. Converters have been proposed to get multiple outputs from a single input source by using push-pull, half-bridge, full-bridge, and fly-back converter topologies [25–27]. In all cases, high voltage is obtained with a high transformer rating on the primary side. Therefore, these converters cannot provide a proper solution for low weight/cost applications.

The parallel configurations of traditional converters such as boost, buck-boost, Cuk, single ended primary inductance converter (SEPIC), and ZETA can be possible solutions to achieve multiple outputs. The power circuitry of possible configurations without common front-end structure are shown in Figure 1a–e. These configurations provide two outputs using two different control switches. However, the voltage gain is not significantly improved, even when using a large number of components and devices. Furthermore, in order to reduce the component or device counts, common front-end structure can be a solution, as shown in Figure 1f–j. These configurations provide dual output using common front-end structures. However, only a few input side components are used, the device count is reduced, and the voltage gain is limited. Moreover, the current rating of the components is increased due to the common structure. In order to reduce the component count, hybrid converters are another possible solution. Moreover, hybrid Cuk, SEPIC, and ZETA converter configurations can achieve multiple outputs. A combination of Cuk and SEPIC converter structure was employed in [28]. Figure 2a shows the SEPIC-Cuk converter circuitry with common front-end design and dual output. A combination of ZETA and buck-boost converter structure was employed in [29].

**Figure 1.** *Cont.*

**Figure 1.** Power circuit of conventional parallel converters: (**a**) boost-boost converter; (**b**) buckboost-buck-boost converter; (**c**) Cuk-Cuk converter; (**d**) single ended primary inductance converter (SEPIC)-SEPIC converter; (**e**) ZETA-ZETA converter; (**f**) boost-boost converter with common front-end structure; (**g**) buck-boost-buck-boost converter with common front end structure; (**h**) Cuk-Cuk converter with common front-end structure; (**i**) SEPIC-SEPIC converter with common front-end structure; (**j**) ZETA-ZETA converter with common front-end structure.

**Figure 2.** Power circuit of (**a**) SEPIC-Cuk converter, (**b**) ZETA–Buck-boost converter, (**c**) boost-Cuk converter; (**d**) Basic block diagram of the X–Y converter family.

Figure 2b shows the circuitry of a ZETA–Buck-boost converter with common front-end structure and two outputs. The combination of Cuk and boost converters is employed in [30]. The circuitry of a boost-Cuk converter with common front-end and two outputs is shown in Figure 2c. The voltage conversion ratio of these topologies is limited. Furthermore, efforts have been made to reduce the switching and to obtain multiple outputs [31–33]. However, these converters have low voltage conversion ratio and are more suitable for low-power applications. The "X–Y converter family" has been proposed for high voltage output and has single switching and a capacitor stack at the output side [34–38]. The block diagram of the X–Y converter family is depicted in Figure 2d. Notable, in XY converters, the X converter is directly connected to the input supply, and the Y converter is fed from the output voltage of the X converter. The output voltage of an X–Y converter is the sum of the output voltages of the X and Y converters. In order to achieve multiple outputs and high voltage conversion ratio, this article contributes the following:


**Figure 3.** Typical structure of fuel cell (FC) vehicle with double stage double output (DSDO) converters.

### **2. Double Stage Double Output Converters**

### *2.1. DSDO L–L Converter*

Figure 4 depicts the power circuit of a DSDO L–L converter. In a DSDO L–L converter, a single switch *S* and input voltage *Vi* are arranged in two stages. Two L–L converters are employed to obtain dual output voltage. The capacitors *C*1, *C*2, inductors *L*1, *L*2, and diodes *D*1, *D*2, *D*<sup>3</sup> are elements of L–L converter-1. The capacitors *C'*1, *C'*2, inductors *L'*1, *L'*2, and diodes *D'*1, *D'*2, *D'*<sup>3</sup> are elements of L–L converter-2. The stage-1 and stage-1 voltages are obtained across capacitors *C*<sup>1</sup> and *C'*1, respectively. The stage-2 and stage-2 voltages are obtained across capacitors *C*<sup>2</sup> and *C'*2, respectively. The load *R*1*<sup>o</sup>* is connected across capacitors *C*1, C2, and load *R*2*<sup>o</sup>* is connected across capacitors *C'*<sup>1</sup> and *C'*<sup>2</sup> to achieve double output voltages, i.e., *V*1*<sup>o</sup>* and *V*2*o*, from a single source input (*Vi*) as shown in Figure 4.

**Figure 4.** Power circuit of a DSDO L–L converter.

The DSDO L–L converter operates in two modes: switch S turn-ON and another when switch S turn-OFF. Figure 5 shows the characteristics of inductor voltage and current obtained for one switching cycle. Time zone A–B describes the ON time of the switch and time zone B–C describes the OFF time. The equivalent circuit for turn-ON mode is shown in Figure 6a. In this mode, inductor *L*<sup>1</sup> is magnetized

through switch *S* and diode *D*<sup>1</sup> from the input power of voltage *Vi*. At the same time, input voltage *Vi* and the voltage across capacitor *C*<sup>1</sup> magnetizes the inductor *L*2. Total energy stored in capacitors *C*<sup>1</sup> and *C*<sup>2</sup> provide load *R*1*o*. Inductor *L'*<sup>1</sup> is magnetized through switch *S* and diode *D'*<sup>1</sup> by the input voltage *Vi*. At the same time, input voltage *Vi* and voltage across capacitor *C'*<sup>1</sup> magnetizes inductor *L'*2. The energy is delivered to load *R*2*<sup>o</sup>* by capacitors *C'*<sup>1</sup> and *C'*2. During turn-ON, capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are discharged, and inductors *L*1, *L'*1, *L*2, and *L'*<sup>2</sup> are magnetized. Throughout this mode, diodes *D*1, *D'*<sup>1</sup> are forward biased and diodes *D*2, *D*3, *D'*2, *D'*<sup>3</sup> are reverse biased.

**Figure 5.** Waveforms of inductor voltages and currents for a DSDO L–L converter.

The voltages across inductors can be obtained as follows,

$$V\_{L1} = V\_{\dot{\nu}} \cdot V\_{L2} = V\_{\subset 1} + V\_{\dot{\nu}} \cdot V\_{L\uparrow 1} = V\_{\dot{\nu}} \cdot V\_{L\uparrow 2} = V\_{\subset 1} + V\_{\dot{\nu}} \tag{1}$$

The equivalent circuit for turn-OFF mode is shown in Figure 6b. In this mode, the capacitor *C*<sup>1</sup> is charged by stored energy in the inductor *L*<sup>1</sup> through diode *D*2. At the same time, capacitor *C*<sup>2</sup> is charged by stored energy in the inductor *L*<sup>2</sup> through diode *D*3. Energy is provided to load *R*1*<sup>o</sup>* by the connection of inductors *L*<sup>1</sup> and *L*2. Capacitor *C'*<sup>1</sup> is charged from stored energy in inductor *L'*<sup>1</sup> through diode *D'*2. At the same time, capacitor *C'*<sup>2</sup> is charged from stored energy in inductor *L'*<sup>2</sup> through diode *D'*3. Energy is provided to load *R*2*<sup>o</sup>* by connection of inductors *L'*<sup>1</sup> and *L'*2. In turn-OFF mode, capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are charged and inductors *L*1, *L'*1, *L*2, and *L'*<sup>2</sup> are demagnetized. In this mode, diodes *D*1, *D'*<sup>1</sup> are reverse biased and diodes *D*2, *D*3, *D'*2, and *D'*<sup>3</sup> are forward biased.

**Figure 6.** Equivalent circuitry of a DSDO L–L converter: (**a**) ON mode; (**b**) OFF mode.

The voltages across inductors can be obtained as follows,

$$V\_{L1} = -V\_{C1}; V\_{L2} = -V\_{C2}; V\_{L1} = -V\_{C1}; V\_{L2} = -V\_{C2} \tag{2}$$

The output voltages *V*1*<sup>o</sup>* and *V*2*<sup>o</sup>* are obtained as follows,

$$\begin{array}{l} \frac{V\_{C1}}{V\_i} = \frac{V\_{C1}}{V\_i} = D(1-D)^{-1}, \frac{V\_{C2}}{V\_i} = \frac{V\_{C2}}{V\_i} = D(1-D)^{-2} \\ V\_{1o} = V\_{2o} = -V\_i \times \left( D(1-D)^{-1} + D(1-D)^{-2} \right) \end{array} \tag{3}$$

### *2.2. DSDO L–2L Converter*

Figure 7 illustrates the power circuit of a DSDO L–2L converter. A single switch *S* and input voltage *Vi* are employed with two-stage L–2L converters to obtain dual output voltage. The capacitors *C*1, *C*<sup>2</sup> inductors *L*1, *L*2, *L*3, and diodes *D*1, *D*2, ... , and *D*<sup>6</sup> are elements of L–2L converter-1. The capacitors *C'*1, *C'*2, inductors *L'*1, *L'*2, *L'*3, and diodes *D'*1, *D'*2, ... , and *D'*<sup>6</sup> are elements of L–2L converter-2. The stage-1 and stage-2 voltages are taken across capacitors *C*<sup>1</sup> and *C*2, respectively. The stage-1 and stage-2 voltages are taken across capacitors *C'*<sup>1</sup> and *C'*2, respectively. The two output voltages are taken across capacitors *C*<sup>1</sup> + *C*<sup>2</sup> and *C'*<sup>1</sup> + *C'*2, respectively. The load *R*1*<sup>o</sup>* is connected across capacitors *C*<sup>1</sup> and *C*2, and load *R*2*<sup>o</sup>* is connected across capacitors *C'*<sup>1</sup> and *C'*2.

The operation of a DSDO L–2L converter is sectioned into two modes: one when switch *S* turn-ON and another when switch S turn-OFF. Figure 8 shows the characteristic waveforms of voltage and current of the inductor for one switching cycle. In the characteristic waveform, time zone A–B describes the turn-ON time and time zone B–C describes the turn-OFF time.

**Figure 7.** Power circuit of a DSDO L–2L converter.

**Figure 8.** Waveforms of inductor voltage and current for a DSDO L–2L converter.

The equivalent circuit for turn-ON mode is shown in Figure 9a. Inductor *L*<sup>1</sup> is magnetized by the input voltage *Vi*. In the same interval, the input voltage *Vi* and voltage across capacitor *C*<sup>1</sup> magnetizes inductors *L*<sup>2</sup> and *L*3. Energy is provided to load *R*1*<sup>o</sup>* by capacitors *C*<sup>1</sup> and *C*2. Inductor *L'*<sup>1</sup> is magnetized by the input voltage *Vi*. In the same interval, the input voltage *Vi* and voltage across capacitor *C'*<sup>1</sup> magnetize inductors *L'*<sup>2</sup> and *L'*3. Energy is provided to load *R*2*<sup>o</sup>* by capacitors *C'*<sup>1</sup> and *C'*2. During turn-ON mode, capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are discharged, and inductors *L*1, *L'*1, *L*2, *L'*2, *L*3, and *L'*<sup>3</sup> are magnetized. In this mode, diodes *D*1, *D'*1, *D*3, *D'*3, *D*5, and *D'*<sup>5</sup> are forward biased and diodes *D*2, *D'*2, *D*4, *D'*4, *D*6, and *D'*<sup>6</sup> are reverse biased.

The voltage across inductors can be obtained as follows,

$$V\_{L1} = V\_{L1} = V\_{i\prime} \; V\_{L2} = V\_{L2} = V\_{L3} = V\_{L3} = V\_{C1} + V\_i \tag{4}$$

The equivalent circuit of the turn-OFF mode of a DSDO L–2L converter is shown in Figure 9b. In this mode, capacitor *C*<sup>1</sup> is charged by the stored energy of inductor *L*1. At same time, capacitor *C*<sup>2</sup> is charged by the series connection of inductors *L*<sup>2</sup> and *L*3. Energy is provided to load *R*1*<sup>o</sup>* by inductors *L*1, *L*2, and *L*3. Capacitor *C'*<sup>1</sup> is charged by the stored energy of inductor *L'*1, whereas the capacitor *C'*<sup>2</sup> is charged by the series connection of inductors *L'*<sup>2</sup> and *L'*3. Energy is provided to load *R*2*<sup>o</sup>* by inductors *L'*1, *L'*2, and *L'*3. In turn-OFF mode, capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are charged and inductors *L*1, *L'*1, *L*2, *L'*2, *L*3, and *L'*<sup>3</sup> are demagnetized. In this mode, diodes *D*1, *D'*1, *D*3, *D'*3, *D*5, and *D'*<sup>5</sup> are reverse biased and *D*2, *D'*2, *D*4, *D'*4, *D*6, and *D'*<sup>6</sup> are forward biased.

**Figure 9.** Equivalent circuitry of a DSDO L–2L converter: (**a**) ON mode; (**b**) OFF mode.

The voltage across inductors can be obtained as follows,

$$V\_{L1} = V\_{L1} = -V\_{C1}; V\_{L2} = V\_{L2} = V\_{L3} = V\_{L3} = -V\_{C2}/2\tag{5}$$

The output voltages *V*1*<sup>o</sup>* and *V*2*<sup>o</sup>* are obtained as follows,

$$\begin{array}{l} \frac{V\_{\text{C1}}}{V\_i} = \frac{V\_{\text{C1}}}{V\_i} = D(1-D)^{-1}, \frac{V\_{\text{C2}}}{V\_i} = \frac{V\_{\text{C2}}}{V\_i} = 2D(1-D)^{-2} \\ V\_{1o} = V\_{2o} = -V\_i \times \left( D(1-D)^{-1} + 2D(1-D)^{-2} \right) \end{array} \tag{6}$$

### *2.3. DSDO L–2LC Converter*

Figure 10 illustrates the power circuit of a DSDO L–2LC converter. A single switch *S* and input voltage *Vi* are employed with two-stage L–2LC converters to obtain dual output voltages. The capacitors C, *C*1, and *C*2, inductors *L*1, *L*2, and *L*3, diodes *D*1, *D*2, ... , and *D*<sup>7</sup> are elements of L–2LC converter-1. The capacitors C', *C'*1, and *C'*2, inductors *L'*1, *L'*2, and *L'*3, diodes *D'*1, *D'*2, ... , and *D'*<sup>7</sup> are elements of L–2LC converter-2. The stage-1 and stage-2 voltages are taken across *C*<sup>1</sup> and *C*2, respectively. The stage-1 and stage-2 voltages are taken across capacitors *C'*<sup>1</sup> and *C'*2, respectively. The load *R*1*<sup>o</sup>* is connected across capacitors *C*<sup>1</sup> and *C*2, and load *R*2*<sup>o</sup>* is connected across capacitors *C'*<sup>1</sup> and *C'*2.

The operation of a DSDO L–2LC converter is sectioned into two modes: one when switch *S* turn-ON and another when switch *S* turn-OFF. Figure 11 shows the characteristic waveforms of voltage and current of the inductor for one switching cycle. Time zone A–B describes the turn-ON time and time zone B–C describes the turn-OFF time of the switch. The equivalent circuit for turn-ON mode is shown in Figure 12a. In this interval, inductor *L*<sup>1</sup> is magnetized by the input voltage *Vi*. The input voltage *Vi* and voltage across capacitor *C*<sup>1</sup> magnetize inductors *L*<sup>2</sup> and *L*3, and charge capacitor *C* in parallel. Energy is provided to load *R*1*<sup>o</sup>* by capacitors *C*<sup>1</sup> and *C*2. The inductor *L'*<sup>1</sup> magnetized by the input voltage *Vi*. The input voltage *Vi* and voltage across capacitor *C'*<sup>1</sup> magnetize inductors *L'*<sup>2</sup> and *L'*<sup>3</sup> and charge the capacitor *C'* in parallel. Energy is provided to load *R*2*<sup>o</sup>* by capacitors *C'*<sup>1</sup> and *C'*2. In turn-ON mode, capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are discharged, capacitors *C* and *C'* are charged, and inductors *L*1, *L'*1, *L*2, *L'*2, *L*3, and *L'*<sup>3</sup> are magnetized. In this mode, diodes *D*1, *D'*1, *D*3, *D'*3, *D*5, *D'*5, *D*6, and *D'*<sup>6</sup> are forward biased and diodes *D*2, *D'*2, *D*4, *D'*4, *D*7, and *D'*<sup>7</sup> are reverse biased.

The voltages across the inductors are obtained as follows,

$$V\_{L1} = V\_{L1} = V\_{i\prime} \; V\_{L2} = V\_{L3} = V\_{L2} = V\_{L3} = V\_{C1} + V\_i \tag{7}$$

**Figure 10.** Power circuit of a DSDO L–2LC converter.

**Figure 11.** Waveforms of inductor voltage and current for a DSDO L–2LC converter.

**Figure 12.** Equivalent circuitry of DSDO L–2LC converter: (**a**) ON mode; (**b**) OFF mode.

The equivalent circuit for turn-OFF mode of a DSDO L–2LC converter is shown in Figure 12b. The capacitor *C*<sup>1</sup> is charged by energy stored in inductor *L*1. The capacitor *C*<sup>2</sup> is charged by the series connection of inductors *L*2, *L*<sup>3</sup> and capacitor *C*. Energy is provided to load *R*1*<sup>o</sup>* by inductors *L*1, *L*2, *L*3, and capacitor *C*. The capacitor *C'*<sup>1</sup> is charged by stored energy of inductor *L'*1. The capacitor *C'*<sup>2</sup> is charged by the series connection of inductors *L'*2, *L'*3, and capacitor *C*'. Energy is provided to load *R*2*<sup>o</sup>* by inductors *L'*1, *L'*2, *L'*3, and capacitor *C'.* Hence, the capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are charged, capacitors C and C' are discharged, and inductors *L*1, *L'*1, *L*2, *L'*2, *L*3, and *L'*<sup>3</sup> are demagnetized. In this mode, diodes *D*1, *D'*1, *D*3, *D'*3, *D*5, *D'*5, *D*6, and *D'*<sup>6</sup> are reverse biased and diodes *D*2, *D'*2, *D*4, *D'*4, *D*7, and *D'*<sup>7</sup> are forward biased.

The voltages across the inductors can be obtained as follows,

$$V\_{L1} = V\_{L1} = -V\_{C1}; \ (V\_{L2} = V\_{L2} = V\_{L3} = V\_{L3}) = \frac{-(V\_{C2} - V\_{C})}{2} = \frac{-(V\_{C2} - V\_{C'})}{2} \tag{8}$$

The output voltages *V*1*<sup>o</sup>* and *V*2*<sup>o</sup>* are obtained as follows,

$$\begin{aligned} \frac{V\_{C1}}{V\_i} &= \frac{V\_{C1}}{V\_i} = D(1-D)^{-1}, \frac{V\_{C2}}{V\_i} = \frac{V\_{C2}}{V\_i} = \frac{(1+D)}{(1-D)^2} \\ V\_{1o} = V\_{2o} &= -V\_i \times \left( D(1-D)^{-1} + (1+D)(1-D)^{-2} \right) \end{aligned} \tag{9}$$

### *2.4. DSDO L–2LCm Converter*

The DSDO L–2LCm converter is a modified version of the DSDO L–2LC converter, obtained by eliminating two diodes. Figure 13 shows the power circuit of the DSDO L–2LCm converter in which a single switch *S* and input voltage *Vi* are employed with two-stage L–2LCm converters to obtain dual

output voltages. The capacitors *C*, *C*1, and *C*2, inductors *L*1, *L*2, and *L*3, diodes *D*1, *D*2, ... , and *D*<sup>5</sup> are elements of L–2LCm converter-1. The capacitors *C'*, *C'*1, and *C'*2, inductors *L'*1, *L'*2, and *L'*3, and diodes *D'*1, *D'*2, ... , and *D'*<sup>5</sup> are elements of L–2LCm converter-2. The stage-1 and stage-2 voltages are taken across capacitors *C*<sup>1</sup> and *C*2, respectively. The stage-1 and stage-2 voltages are taken across capacitors *C'*<sup>1</sup> and *C'*2, respectively. Load *R*1*<sup>o</sup>* is connected across capacitors *C*<sup>1</sup> and *C*<sup>2</sup> and load *R*2*<sup>o</sup>* is connected across capacitors *C'*<sup>1</sup> and *C'*2.

The operation of a DSDO L–2LCm converter is sectioned into two modes: one when switch *S* turn-ON and another when switch *S* turn-OFF. Figure 14 shows the characteristic waveforms of voltage and current for inductors for one switching cycle. The time zone A–B describes the turn-ON time and B–C describes the turn-OFF time. The equivalent circuit for turn-ON mode is shown in Figure 15a. The inductor *L*<sup>1</sup> is magnetized by the input voltage *Vi*. In the same interval, the inductor *Vi* and voltage across capacitor *C*<sup>1</sup> magnetize inductors *L*<sup>2</sup> and *L*<sup>3</sup> and charge capacitor *C* in parallel. The energy is provided to load *R*1*<sup>o</sup>* by capacitors *C*<sup>1</sup> and *C*2. The inductor *L'*<sup>1</sup> magnetized by the input voltage *Vi*. In the same interval, input voltage *Vi* and voltage across capacitor *C'*<sup>1</sup> magnetize inductors *L'*<sup>2</sup> and *L'*<sup>3</sup> and charge capacitor *C'* in parallel. The energy is provided to load *R*2*<sup>o</sup>* by capacitors *C'*<sup>1</sup> and *C'*2. Capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are discharged, capacitors *C* and *C'* charged, and inductors *L*1, *L'*1, *L*2, *L'*2, *L*3, and *L'*<sup>3</sup> are magnetized. In this mode, diodes *D*1, *D'*1, *D*3, *D'*3, *D*4, and *D'*<sup>4</sup> are forward biased and diodes *D*2, *D'*2, *D*5, and *D'*<sup>5</sup> are reverse biased.

**Figure 13.** Power circuit of the DSDO L–2LCm converter.

**Figure 14.** Waveforms of inductor voltage and current for a DSDO L–2LCm converter.

The voltages across inductors can be obtained as follows,

$$V\_{L1} = V\_{L1} = V\_{i\prime} \; V\_{L2} = V\_{L3} = V\_{L2} = V\_{L3} = V\_{C1} + V\_{i} \tag{10}$$

The equivalent circuit for turn-OFF mode is shown in Figure 15b. Capacitor *C*<sup>1</sup> is charged by the energy of inductor *L*1, and capacitor *C*<sup>2</sup> is charged by the series connection of inductors *L*2, *L*<sup>3</sup> and capacitor *C*. Energy is provided to load *R*1*<sup>o</sup>* by inductors *L*1, *L*2, *L*3, and capacitor *C*. Capacitor *C'*<sup>1</sup> is charged by energy of inductor *L'*1. Capacitor *C'*<sup>2</sup> is charged by the series connection of inductors *L'*2, *L'*<sup>3</sup> and capacitor *C*'. Energy is provided to load *R*2*<sup>o</sup>* by inductors *L'*1, *L'*2, *L'*3, and capacitor *C'.* The capacitors *C*1, *C'*1, *C*2, and *C'*<sup>2</sup> are charged, capacitors *C* and *C'* are discharged, and inductors *L*1, *L'*1, *L*2, *L'*2, *L*3, and *L'*<sup>3</sup> are demagnetized. Throughout this mode, diodes *D*1, *D'*1, *D*3, *D'*3, *D*4, and *D'*<sup>4</sup> are reverse biased, and diodes *D*2, *D'*2, *D*5, and *D'*<sup>5</sup> are forward biased.

**Figure 15.** Equivalent circuitry of a DSDO L–2LCm converter: (**a**) ON mode; (**b**) OFF mode.

The voltages across inductors can be obtained as follows,

$$V\_{L1} = V\_{L1} = -V\_{C1}; \left(V\_{L2} = V\_{L2} = V\_{L3} = V\_{L3}\right) = \frac{-\left(V\_{C2} - V\_{C}\right)}{2} = \frac{-\left(V\_{C2} - V\_{C'}\right)}{2} \tag{11}$$

The output voltages *V*1*<sup>o</sup>* and *V*2*<sup>o</sup>* are obtained as follows,

$$\begin{aligned} \frac{V\_{C1}}{V\_i} &= \frac{V\_{C1}}{V\_i} = D(1-D)^{-1}, \frac{V\_{C2}}{V\_i} = \frac{V\_{C2}}{V\_i} = \frac{(1+D)}{(1-D)^2} \\ V\_{1o} = V\_{2o} &= -V\_i \times \left( D(1-D)^{-1} + (1+D)(1-D)^{-2} \right) \end{aligned} \tag{12}$$

### **3. Comparative Study**

In this section, the new DSDO converter configurations are compared with possible parallel combination of conventional converters and recently addressed DC–DC converters. Table 1 tabulates the comparison in terms of number of components and devices, voltage conversion ratio, and ratio of voltage across switch and input voltage. It is observed that one can achieve multiple output voltages by using conventional converters in parallel. However, the voltage conversion ratio is limited and not suitable for feeding high-voltage loads. Hybrid multiple output converters provide two different voltage levels while using common front-end structure. However, the voltage conversion ratio is not significantly improved by using a hybrid structure. The proposed converter provides a higher voltage conversion ratio compared to parallel combination of the conventional converters. In Figure 16a, the voltage conversion ratios of the converters are compared graphically. It is notable that all proposed converters provide inverting high voltage with medium duty cycle. It is observed that the DSDO L–2LC and DSDO L–2LCm converters generate higher voltage conversion ratios compared to the other proposed converters and in comparison to recent DC–DC converters. Figure 16b compares the number of diodes, control switches, inductors, and capacitors. It concludes that the DSDO L–2LCm converter requires fewer diodes than the DSDO L–2LC converter, while both provide the same voltage conversion ratio.


**Table 1.** Comparison of Converters.

**Figure 16.** Comparison of (**a**) voltage conversion ratio versus duty cycle and (**b**) number of diodes (*Nd*), number of capacitors (*NC*), number of Switches (*NS*), and number of inductors (*NL*). A: Boost, B: SEPIC, C: Cuk or Buck-Boost, D: DSDO L–L, E: DSDO L–2L, F: DSDO L–2LC, G: DSDO L–2LCm converters.

### **4. Simulation and Experimental Results**

The principle and performance of the proposed DSDO converter configurations are validated through numerical simulation software. The converters were designed and tested with two loads, each rated to 100 W with a single input voltage of 20 V and with 25 kHz switching frequency. For simulation and prototype hardware implementation, the values of the reactive components were 220 μF for capacitors and 700 μH for inductors.

DSDO L–L converter: Figure 17a shows the voltage across the two different loads *R*1*<sup>o</sup>* and *R*2*o*. Voltage of −105 V was generated across each load with a fixed 60% duty cycle. Figure 17b,c depicts the voltage across capacitors *C*1, *C'*1, *C*2, and *C'*2. The voltage magnitude across capacitors *C*<sup>1</sup> and *C'*<sup>1</sup> are the same, i.e., 30 V. The voltage magnitudes across capacitors *C*<sup>2</sup> and *C'*<sup>2</sup> are both 75 V. Figure 17d shows that the voltage across switch *S* of a DSDO L–L converter is 125 V. DSDO L–2L converter: Figure 18a shows the voltage across the two different loads *R*1*<sup>o</sup>* and *R*2*o*. Voltage of −180 V was generated across each load with a fixed 60% duty cycle. Figure 18b,c depicts the voltage across capacitors *C*1, *C'*1, *C*2, and *C'*2, and shows that the voltage magnitude across capacitors *C*<sup>1</sup> and *C'*<sup>1</sup> is 30 V. The voltage magnitudes across capacitors *C*<sup>2</sup> and *C'*<sup>2</sup> are 150 V. Figure 18d shows that the voltage across switch *S* of the DSDO L–2L converter is 200 V. DSDO L–2LC converter: Figure 19a depicts the voltage across the two different loads *R*1*<sup>o</sup>* and *R*2*o*. Voltage of −230 V is generated across each load with a fixed 60% duty cycle. Figure 19b,c shows the waveforms of the voltage across capacitors *C*1, *C'*1, *C*2, and *C'*2.

**Figure 17.** Simulation results of the DSDO L–L converter configuration: (**a**) Output voltages waveforms; (**b**) Voltage waveforms across stage-1 and stage-2; (**c**) Voltage waveforms across stage-1 and stage-2 ; (**d**) Voltage waveform across switch *S*.

**Figure 18.** Simulation results of the DSDO L–2L converter configuration: (**a**) Output voltages waveforms; (**b**) Voltage waveforms at stage-1 and stage-2; (**c**) Voltage waveforms at stage-1 and stage-2 ; (**d**) Voltage waveform across switch *S*.

**Figure 19.** Simulation results of the DSDO L–2LC converter configuration: (**a**) Output voltages waveforms; (**b**) Voltage waveforms across stage-1 and Stage-2; (**c**) Voltage waveforms across stage-1 and stage-2 ; (**d**) Voltage across switch *S*.

The voltage magnitudes across capacitors *C*<sup>1</sup> and *C'*<sup>1</sup> are 30 V and the voltage across capacitors *C*<sup>2</sup> and *C'*<sup>2</sup> are 200 V. Figure 19d shows the voltage across switch *S* of the DSDO L–2LC converter and its magnitude is 250 V.

DSDO L–2LCm converter: Figure 20a shows the waveforms of the voltage across the two different loads *R*1*<sup>o</sup>* and *R*2*o*. Voltage of −230 V is generated across each load with a fixed 60% duty cycle. Figure 20b,c shows the waveforms of the voltage across capacitors *C*1, *C'*1, *C*2, and *C'*2. The voltage magnitudes across capacitors *C*<sup>1</sup> and *C'*<sup>1</sup> are 30 V, and voltage across capacitors *C*<sup>2</sup> and *C'*<sup>2</sup> are 200 V. Figure 20d shows the voltage across switch *S* of the DSDO L–2LCm converter and its magnitude is 250 V. Figure 21 shows the preliminary implemented hardware of the DSDO L–L converter. The designed hardware is tested with input voltage of 20 V and the output voltages are controlled at −105 V. Digitally controlled pulses are generated with the help of FPGA (Field Programmable Gate Array). Figures 22a and 22b the voltages across *R*1*<sup>o</sup>* and *R*2*<sup>o</sup>* with the voltage of switch *S*, respectively. Using a 20 V input supply, −104.2 V is successfully generated across each load and the voltage across switch *S* is 124.08 V. Figure 22c depicts the voltage and current waveform of inductors *L*<sup>1</sup> and *L*2, respectively. In the ON state, the voltage across inductor *L*<sup>1</sup> is 20 V, which confirms that inductor *L*<sup>1</sup> is magnetized with input voltage. In the OFF state, the voltage across inductor *L*<sup>1</sup> is −30 V, i.e., inductor *L*<sup>1</sup> is demagnetized to charge the capacitor *C*1. In the ON state, the voltage across inductor *L*<sup>2</sup> is 50 V, which confirms that the inductor *L*<sup>2</sup> is magnetized by the input voltage and the voltage across capacitor *C*1. In the OFF state, the voltage across inductor *L*<sup>2</sup> is −75 V, i.e., inductor *L*<sup>2</sup> is demagnetized to charge capacitor *C*2. Figure 22d depicts the voltage and current waveforms of inductor *L'*1, *L'*<sup>2</sup> respectively. In the ON state, the voltage across inductor *L'*<sup>1</sup> is 20 V, which confirms that inductor *L'*<sup>1</sup> is magnetized by the input voltage. In the OFF state, the voltage across inductor *L'*<sup>1</sup> is −30 V, i.e., inductor *L'*<sup>1</sup> is demagnetized to charge capacitor *C'*1. In the ON state, the voltage across inductor *L'*<sup>2</sup> is 50 V, which confirms that inductor *L'*<sup>2</sup> is magnetized by the input voltage and the voltage across capacitor *C'*1. In the OFF state, the voltage across inductor *L'*<sup>2</sup> is −75 V, i.e., inductor *L'*<sup>2</sup> is demagnetized to charge capacitor *C'*2.

**Figure 20.** Simulation results of the DSDO L–2LCm converter configuration: (**a**) Output voltages waveforms; (**b**) Voltage waveforms across stage-1 and Stage-2; (**c**) Voltage waveforms across stage-1 and stage-2 ; (**d**) Voltage across switch *S*.

**Figure 21.** Experimental setup of the DSDO L–L converter configuration.

**Figure 22.** Experimental results of the DSDO L–L converter configuration: (**a**) voltage at load *R*1*<sup>o</sup>* and voltage across switch *S* waveforms; (**b**) voltage at load *R*2*<sup>o</sup>* and voltage across switch *S* waveforms; (**c**) inductor voltages and current of L converter-1; and (**d**) inductor voltages and current of L converter-2.

### **5. Conclusions**

This article developed four DSDO converter configurations for high voltage fuel-cell electric vehicular loads. The proposed converters need a single controlling semiconductor switch and are able to feed two loads with high voltage conversion ratio. The circuitry of the DSDO L–L, DSDO L–2L, DSDO L–2LC, and DSDO L–2LCm converters are developed by merging with two L–L, two L–2L, two L–2LC, and two L–2LCm converters, respectively. The operating principles of the proposed converters are discussed with detailed theoretical analysis and governing equations for the output voltage conversion ratio. Finally, it is concluded that among the proposed converters, the DSDO L–2LC and DSDO L–2LCm converters provide higher output voltage and are effective in comparison with DC–DC converters. Both simulation and experimental results show that the proposed DSDO L–L converters had the expected performance.

**Author Contributions:** All authors contributed equally for the research work, to present the final manuscript as full research article in current version.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **DC Grid for Domestic Electrification**

### **G. Arunkumar 1, D. Elangovan 1,\*, P. Sanjeevikumar 2, Jens Bo Holm Nielsen 2, Zbigniew Leonowicz <sup>3</sup> and Peter K. Joseph <sup>1</sup>**


Received: 26 April 2019; Accepted: 27 May 2019; Published: 5 June 2019

**Abstract:** Various statistics indicate that many of the parts of India, especially rural and island areas have either partial or no access to electricity. The main reason for this scenario is the immense expanse of which the power producing stations and the distribution hubs are located from these rural and distant areas. This emphasizes the significance of subsidiarity of power generation by means of renewable energy resources. Although in current energy production scenario electricity supply is principally by AC current, a large variety of the everyday utility devices like cell phone chargers, computers, laptop chargers etc. all work internally with DC power. The count of intermediate energy transfer steps are significantly abridged by providing DC power to mentioned devices. The paper also states other works that prove the increase in overall system efficiency and thereby cost reduction. With an abundance of solar power at disposal and major modification in the area of power electronic conversion devices, this article suggests a DC grid that can be used for a household in a distant or rural area to power the aforementioned, utilizing Solar PV. A system was designed for a household which is not connected to the main grid and was successfully simulated for several loads totaling to 250 W with the help of an isolated flyback converter at the front end and suitable power electronic conversion devices at each load points. Maximum abstraction of operational energy from renewable sources at a residential and commercial level is intended with the suggested direct current systems.

**Keywords:** DC grid; microgrid; DC-DC converter; renewable energy

### **1. Introduction**

The World Energy Outlook 2015 statuses that nearly 17% of the total inhabitants in the world lacks access to electric power at homes [1]. As per the reports of International Energy Agency, India has over 237 million citizens belonging to this category. According to CEEW (Council for Energy, Environment, and Water), over 50% of houses in the states of West Bengal, Bihar, Madhya Pradesh, Uttar Pradesh, Jharkhand, Orissa has a shortage of electric power in spite of being grid connected. Regardless of the efforts put in over the years to electrify rural stretches, many households in five out of these six states have not more than 8 h of supply or no supply at all and are regularly subjected to blackouts. The states may perhaps slightly better conditions but the same cannot be said for the unfortunate low-income strata of citizens lacking admission to electricity. Most of these homes use kerosene for their lighting purposes which give poor illumination. It also sends out unhealthy fumes, may cause fire perils, ecologically unfavorable and also too exclusive when bought at market tariffs unless subsidized by the Government [2,3].

It may come as surprise to see that not all houses in a village in India maybe be electrified even though the village is said to be grid connected. By the explanation provided by the Government of India, "A village is considered electrified when 10% of the homes in a village are connected to the grid." As on May 2016, 18,452 villages are remaining to be electrified [4]. Nevertheless, during recent past numerous of individuals were able to harvest electricity with the help of fleet-footed economic growth and along with numerous sponsored programs, the country has made significant augmentation in its electrical infrastructure. In the energy production sector, the fossil fuels and conventional methods of power generation are losing it demand rapidly since policymakers around the globe are stressing on the effects of global warming and climate changes. The world is advancing towards green energy to meet the ever increasing power demand, thus requiring a mixing up numerous resources both conventional and non-conventional [5]. The unique energy situation in India is making the country's growth objectives to be revised and modified so that it strive to meet its current demands as well as generating energy which is clean, efficient and environmental friendly [6]. This encourages economy to take up more enterprises and initiatives to extract maximum energy from renewable resources.

The abundance of solar radiation and decreasing prices of Photovoltaic components ease of its maintenance and scalability is making Solar PV generation more popular among renewable energy sources [7]. Even though in most parts of the country the sun shines adequately up to 10 to 12 h a day for the most part of a year, the huge impact of distributed solar power has not been amply exploited. In places receiving sunlight higher than 1400 equivalent peak hours annually, the gap in power shortage can be bridged by using solar energy. The government of India has become conscious of these facts and is enhancing the consumption of renewable power sources, specifically the solar power, in meeting the demand-supply gap nationwide. Thus, pertinent strategic guidelines have been created for endorsing solar power usage across the country. It aims at achieving 100 GW PV (photovoltaic) capacity from current statistics of 20 GW by 2022 with the assistance of the Jawaharlal Nehru National Solar Mission (JNNSM). The JNNSM intends to power rural areas, which was deprived of electricity before. Encouraged by the progress made in 4 years it now aims to achieve 100 GW by 2022 with solar rooftops contributing 40 GW of this. In the light of the launch of JNNSM program few states launched their separate solar policies. The Solar Energy policy of Tamil Nadu initiated in 2012 is targeting 5 GW solar energy by 2023. To encourage solar rooftops the Tamilnadu government provides huge incentives and almost 30% subsidies to buildings incorporating solar rooftops. This movement has encouraged the studies and improvement on Low Voltage DC arrangements, as they are suitable for residence applications as well as can be easily integrated with renewable energy sources and storage systems [8,9]. The rising demand for aggregating renewable energy resources is bringing back DC into the energy distribution frame since it is easy to integrate renewable sources into the grid in such case. Most loads at the utilization terminal these days are DC or non-sinusoidal. As a result, many types of exploration have been going on dc dissemination systems and their prospective uses in residential applications [10]. The DC also enjoys numerous other advantages over the AC system, one of the significant being the reduced number of converters at each power conversion legs and better efficiency in comparison with AC grid. If the solar DC output voltage is fed straight to these device appliances, the conversation stages are reduced from three stage DC-AC-DC to two stage DC-DC when solar PVs and fuel cells are interconnected with DC microgrids [11–15]. Additionally, the lack of reactive power decreases the current required to pass the equal magnitude of energy [16] and also mitigates the issues of skin effect, power factor and harmonics [17].Studies conducted on DC distribution systems in various residences located in various locations and different topologies in the United States showed that energy savings estimation can be up to 5% in case of a non-storage system and up to 14% for a system using storage [18,19]. There are more optimistic researchers that aim to pull of energy savings of 25–30% [20]. Exchanging the prevailing alternating current delivery grids with direct current is impracticable and economically non-viable. This is why DC can become the idyllic pick when it comes to energizing remote areas which are not connected to the main power grid, also known as "island areas". This type of areas can be made self-sustainable by harnessing non-conventional energy resources.

This article proposes one direct current microgrid which uses Solar PV to facilitate a domestically situated appliance in an isolated area to energize itself. Microgrids are entities that can be self-controlled and operated in island or grid connected mode when interconnected with the local distribution systems [21]. They mainly refer to small-scale power network having voltage levels lesser than 20 kV and power rating up to 1 MW. Using this system, unsolicited energy changeover steps and losses accompanying by the same are eliminated. The major advantage of DC Microgrid is its ability to comply easily with DC loads and Distributed Energy Resources (DERs). For example, only a DC-DC conversion stage is required in a DC Microgrid when it is connected to solar PV and a battery storage, thus provides a simple and cost cutting structure with the better control strategy. This boosts the general system efficiency and makes the system less complicated. It also supplements the performance and the life of components [22,23]. The absence of normalization, instruction and improvement of protection devices for DC-DC converters are few of the major problems that DC power systems must solve, before being regarded as an appropriate option that supersedes AC power systems in rural and island areas [17].

Figure 1 illustrates the methodology outline of this research works. The works done and the outcome of this methodology is explained in coming sessions.

**Figure 1.** Methodology outline.

### *Existing Works in DC Microgrids*

An analysis has been performed on a 48 V DC microgrid integrated with PV panels using very effective DC loads utilized in a multi-storied building in India [24,25]. The findings show that the DC microgrid is far efficient in bringing cost savings, thereby dropping the electricity invoices. A practical employment of low power solar system designed to supply the basic power needs of a low-income family in India has been studied [9]. The system supplies a cumulative load of 125 W from PV Panel. This system may not be able to meet up to the power requirement of a fully electrified and digital household but is able to show that when minimizing the system cost is priority a low voltage DC distribution system have no challengers.

Works on larger test beds such as 5 kW with high DC link voltage of 380 V has also been conducted to study the feasibility of DC as distribution system [15]. A solar hybrid system of grid connection along with solar array panel feeding 220 V DC link powering up an entire household is realized in [5]. An effective Maximum Power Point Tracking (MPPT) algorithm to obtain constant DC voltage of 12 V or 24 V using a PI controller is studied in [6]. An Off Grid Home (OGH) which is inverter less system to power lighting loads are deployed in [8].

Green Office and Apartments (GOA) technology is a solution offered to ensure all day power using an integration of grid and batteries charged from solar PV [26]. A DC microgrid consisting of 250 W solar panel and charge controllers to regulate battery charging has been proposed in [27,28]. Suggest a novel reconfigurable inverter topology which can perform DC to DC, DC to AC and grid connection at the same time. An experimental prototype of a power balancing circuit to solve mismatching problems while connecting various renewable to a DC link is proposed in [29,30]. Elaborates the concepts of DC house and Null Net Energy (NNE) buildings which supply DC to residential buildings. Various Multiple Input Multiple Output (MIMOCs) DC-to-DC converters that can be used as front end converter for a DC distribution in future homes is discussed in [31–42].

Apart from the conventional microgrid works, some researches are done in the field of advanced aspects of microgrid implementation. Researches [43–45] discusses about the consumers with distributed storage capacity. In this case, the demand sharing and power quality improvement will be much easier. Refs. [46,47] considers renewable energy sharing mechanism of multiple consumers, rather than the individual renewable energy harvesting topology. Since this research work discusses about the implementation of a DC microgrid in rural domestic area, this advanced techniques are neglected for the initial phase. In addition, since solar energy is weather dependent, to ensure a regulated supply irrespective of the weather or time, storage devices or weather independent renewable energy sources like fuel cells need to be integrated to the microgrid [48,49]. This part also neglected from the simulation, as the outcome will be the same.

### **2. Selection of Bus Voltage**

The DC grid distribution system having several practical challenges in distributing a regulated power supply [32]. The DC microgrid supplying low voltage and higher currents requires high gauge cables, which leads to an increase in overall losses [32,33]. Thus in order to reduce the losses and save the installation cost, the DC microgrid voltage must be sufficiently high enough. As a paradox, if the link voltage is too high, it leads to the occurrence of sparks, arcing and electric shock. Many research works have been done in order to reduce the arcing and spark phenomenon in order to optimize the DC distribution system. However, this paper deals with loads not requiring more than 240 V voltage and 3.42 A current. Hence the DC link voltage is taken as 72 V [34–37].

Since the majority of the domestic electrical appliances internally needs DC voltage for its operation, which is obtained conventionally by stepping down of rectified AC voltage supply [38]. Renewable energy resources can directly produce this low value of DC voltage [39]. Hence the rectification stage can be avoided if the load is powered with DC. A customary magnitude for DC grid voltage is not fixed for a microgrid. The chosen loads for this research has rated voltage varies in the range from 5 V

to 230 V. For ensuring a coherent transition from grid voltage to rated load voltage, an optimum value of grid voltage of 72 V is chosen [40,41].

### **3. Front End Isolated DC to DC Converter**

The input voltage Vdc of the DC microgrid is considered to be a solar panel whose output is expected to be 24 V. A 20 W, 12 V solar panel (54 × 46 cm) is used for implementing the solar array. To make the rated input to the grid, seven parallel connections of two series connected panels are used. The distribution losses in the microgrid can be reduced to a low value by stepping up the input voltage to a DC voltage of 72 V by a Flyback converter. A flyback converter is chosen for the proposed system as the primary side DC-DC converter for the purpose that it can facilitate galvanic seclusion in amongst the input and the DC microgrid. The specifications of the selected flyback converter are input voltage as 24 V, output voltage as 72 V and output power as 250 W. The simplicity of its topology compared to other isolated SMPS topologies is an added advantage. It also has the lesser component count and lowers cost, making it popular. This will function for an extensive difference of the source voltage, as well as, it can facilitate numerous secluded DC voltage outcomes.

L, C and R denotes inductor, capacitor and resistor respectively. Lm denotes the mutual inductance. For an input voltage Vdc of 24 V and grid voltage Vgrd of 72 V, duty cycle ratio of the flyback converter is 0.42. The front end converter is designed to energize a cumulative device power of 250 W. Isolation transformer of turn's ratio 1:4 is chosen for the proposed topology. The magnetizing inductance Lm of the isolation transformer is 85 μH. Switching frequency is selected as 50 KHz, and for a 1% voltage-ripple, capacitor C1 of 50 μF is used. A clamping circuit is also connected to the isolation transformer to absorb the energy stored in the inductor and provide a path for its dissipation to avoid high surge voltage. The capacitance Ccl of 1 μH is used in the clamping circuit. The microgrid voltage is fed to various devices by Point of Load (POL) converters [42]. Depending upon load specifications POL converters can be Buck-boost, Buck or Boost. Table 1 show various loads utilized by the proposed system. Figure 2 shows the proposed topology for the DC microgrid including the front end converter, bus and loads.


**Table 1.** Loads selected for the analysis of work.

**Figure 2.** Proposed Schematic for the proposed circuit topology.

The circuit topology of the complete system including the front end converter, high voltage loads and low voltage loads are as shown in Figure 3. Here M1, M2, M3 and M4 are the controlled switches.

**Figure 3.** Complete circuit topology including front end Flyback converter for 0–240 V loads.

### **4. Loads with 24 V to 240 V Rating**

The voltage essential for these loads is provided by a buck-boost voltage converter. For a home illuminating application, we are considering five 9 W Syska B22 LED bulb with 240 V DC voltage ratings. A buck-boost converter premeditated for a 1% peak voltage ripple and 10% current ripple of the rated voltage and current respectively. The proposed arrangement of the 24–240 V loads are illustrated in Figure 4. The designed values of inductor and capacitor is tabulated in Table 2.

**Figure 4.** Proposed arrangement for 24–240 V Devices.



### **5. Loads with** <**24 V Rating**

Low voltage loads like laptop and DC fan are considered in this section. Figure 5 above illustrates the designed connection diagram for the <24 V devices. These loads essentially need a ripple-free DC output voltage which is usually acquired by using high-efficient DC conversion stages followed by a stepping up PFC (power factor correction) circuit. This setup contributes bulkiness to the system [41]. By replacing the above mentioned circuitry with a steeping down buck converter, the power quality of the grid can be maintained with a minimized space consumption. This will reduces the development cost, dimensions and enhances the lifespan of the device [39]. In rural areas, usually the application side dispersal transformer having a 20% to 25% reduced voltage than the general fixed values. Operation of conventional induction motor based devices like household fans with such voltage variation from the general fixed values may results in higher iron losses, which may leads to the permanent damage of motor [8]. The calculated values of various converter parameters for energizing <24 V devices are tabulated in Table 2. Here VR1, VR2 and VR3 represents the voltage drop across <24 V loads R1, R2 and R3 respectively.

**Figure 5.** Proposed arrangement for <24 V devices.

To mitigate these effects, modern brushless DC motors for DC fans can be used instead of conventional fans having less ripple percentage. In addition the reduction in losses, various advantages like improved power density, enhanced torque, higher life-span, and easy control and reduced maintenance cost.

### **6. Numerical Simulation Results**

The PSIM Professional Version 9.1.1.400 (Vellore, Tamilnadu, India) was used to simulate the proposed system. The equivalent models of real time loads, devices and sources are used for the simulation. The simulated values of each loads are tabulated in Table 3. In this initial phase of research, simulated results are considered for formulating the conclusion. The flyback converter illustrated in Figure 3 is simulated to formulate the parameters. The system in total has four DC-DC converters. 72 V DC bus voltage used for the electrifying DC microgrid is obtained from front end converter as illustrated in Figure 6a. The magnetizing current waveforms from the flyback converter is shown in Figure 6b. Figure 6a illustrates the magnetizing current of the flyback transformer. The current ripple in the inductor magnetizing current is obtained as 9.64%. Figure 6b shows the DC grid voltage waveform. As the grid input is given by flyback converter, the grid voltage is 72 V as per the rating. The voltage ripple is obtained as 0.9%, which is feasible for a domestic power network. Figure 7a illustrates the LED input voltage waveform and Figure 7b shows the LED input current waveform. The voltage ripple and current ripple is obtained as 0.83% and 1.06% respectively. This reduced ripple denotes the high power quality of the microgrid. Figure 8a,b represents the laptop input voltage and current respectively from the grid. The waveforms are of high power quality. The voltage ripple and current ripple are obtained as 0.7% and 0.58% respectively. Similarly Figure 9a,b illustrates the DC fan input voltage and input current respectively. The voltage ripple and current ripple are found as 2.37% and 0.337% accordingly. From the waveforms of these loads, it is clear that the power quality of the proposed microgrid topology is very high compared to other conventional topologies.


**Table 3.** Output voltages and currents of each load.

**Figure 6.** Output of Simulation DC-Grid Voltage. Average Voltage = 71.6 V, voltage ripple = 0.9% and output of Simulation—magnetizing inductor current. Average inductor current 24.39 A, current ripple = 9.64%. (**a**) Magnetizing current of flyback converter; (**b**) DC grid voltage.

**Figure 7.** LED Input Voltage and Current Waveforms. LED Input Voltage Ripple: 0.83% Current Ripple: 1.06%. (**a**) LED input voltage; (**b**) LED input current.

**Figure 8.** Laptop Input Voltage and Current Waveform. Laptop Input Voltage Ripple: 0.7%; Current Ripple: 0.58%. (**a**) Laptop input voltage; (**b**) Laptop input current.

**Figure 9.** DC Fan Load Input Voltage and Current Waveform. DC Fan Input Voltage Ripple: 2.37%; Current Ripple: 0.337%. (**a**) DC fan input voltage; (**b**) DC fan input current.

### **7. Conclusions**

This research proposes to design and simulation of a DC microgrid that facilitates standalone powering of a rural household which uses less than 250 W load from Solar PV array. The DC to DC POL conversion systems were effectively connected to a DC bus of 72 V. This grid is able to highlight the benefits that a DC grid arrangement have above the traditional AC grids, with a supreme advantage of reduced converter count at the device end. DC grid is designed to be 72 V as no fixed standards are available for this topology. The grid voltage on simulation is obtained as 72 V. The conversion circuitry for each device were developed and the prerequisite voltage values were attained from the systems. On observing the simulation results, it can be inferred that the designed DC grid can supply the rated power desirable for each load. By realizing on a higher scale, the scope of this project can be commercialized to power individual homes in an island area thereby achieving the goal of 0% unpowered villages.

**Author Contributions:** All authors contributed equally to the final dissemination of the research investigation as a full article.

**Funding:** This research activity received support from EEEIC International, Poland.

**Acknowledgments:** The authors would like to acknowledge the technical assistance received from the Center for Bioenergy and Green Engineering, Department of Energy Technology, Aalborg University, Denmark.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article*
