*3.3. Active-to-Active Switching Transition in the Matrix Converter*

The transition between two active vectors takes place twice in a switching period. In Figure 2a the transition occurs from *SQ***<sup>1</sup>** to *SQ***<sup>2</sup>** during the first semi cycle; whereas in the second semi cycle, the transition occurs from *SQ***<sup>5</sup>** to *SQ***4**. The transition between adjacent active vectors implies a switching state change in one matrix converter leg. By instance, the state of the second matrix leg, *Sbm* in Figure 2, switches from the off to the on state producing an active-to-active transition. The turn on-to-off sequence of *Q*<sup>3</sup> and *Q*<sup>6</sup> is shown in Figure 9.

**Figure 9.** Switching sequence in the on-to-off transition from active-to-active switching state. (**a**) initial current flow; (**b**) overlap time; (**c**) current flow in the opposite direction; (**d**) bidirectional switch in on state.

In Figure 9a, *Q*6*<sup>a</sup>* and *Q*6*<sup>b</sup>* are firstly turned on and the current flows in the red or blue arrow direction, *iQ*6; then, in Figure 9b *Q*6*<sup>a</sup>* and *Q*3*<sup>a</sup>* are turned off and on respectively to allow the current reversal in the matrix converter leg when the current is flowing in the blue arrow direction; or *Q*6*<sup>b</sup>* and *Q*3*<sup>b</sup>* are turned off and on respectively to allow the current reversal when the current is flowing in the red arrow direction. In this figure, the transistors of *Q*<sup>6</sup> are turned on for a period of time *tD* longer than the turning off time of the semiconductor device, *tr*, to guarantee that the current stops flowing through it. This bidirectional switch configuration comes to an end when the transistor of *Q*<sup>6</sup> is turned off as shown in Figure 9c. Lastly, the sequence finishes by turning on transistors of *Q*3, as shown in Figure 9d, with *iQ*<sup>3</sup> flowing in the opposite direction.

#### **4. Steady-State Analysis and Parameters Selection**

A steady-state analysis of the AC-DC modular converter is derived using the generalized diagram of Figure 10, where *vs* is the three-phase source voltage vector, *L* is the line inductor, *vL* is the line inductor voltage vector, *vcav* is the converter voltage vector, *n*:1 is the transformer turns ratio that links the off-board AC-AC module with the AC-DC module; *Vo* is the DC output voltage and *R* is the output load.

**Figure 10.** Generalized diagram for steady-state analysis

Assuming a vectorial current control to drive the phase and magnitude of the line current *i<sup>L</sup>* and produce high power factor, a phasorial diagram is shown in Figure 11 which describes the behavior of the AC-DC converter of Figure 1. In this diagram, *vs*, *vL* and *vcav* are defined by:

*vs* = *Vspk*Ŀ0◦, (4)

$$
\omega\_L = V\_{Lpk} \sqcup \text{9O}^{\circ}\tag{5}
$$

$$w\_{\rm conv} = V\_{\rm cpk} \mathbb{L}\_{\rm cp} \mathbf{q}^{\odot} \tag{6}$$

In Figure 11 the amplitudes of *vcav* and *vL* are defined by:

$$V\_{cpk} = \frac{V\_{spk}}{\cos \varphi} \tag{7}$$

$$V\_{Lpk} = V\_{cpk} \sin \varphi \tag{8}$$

Whereas the current *i<sup>L</sup>* is obtained with Equation (9):

$$\dot{a}\_L = \frac{\upsilon\_L}{\omega L} \tag{9}$$

Considering the phasorial diagram of Figure 11, *vL* is calculated using Equation (10):

$$
\upsilon\_L = \upsilon\_s - \upsilon\_c \tag{10}
$$

Equations (9) and (10) are used to derive the amplitude of *iL*, *ILpk*, which is defined by:

$$I\_{Lpk} = \frac{V\_{spk}t\mathcal{g}\mathcal{g}}{\omega L} \tag{11}$$

where *ω = 2πf*. Assuming ideal conditions, a power balance is derived:

$$P\_{\rm in} = P\_{\rm out} \tag{12}$$

where *Pin* and *Pout* are the input and output power converter respectively and are equivalent to Equation (13):

$$\frac{3V\_{spk}I\_{Lpk}}{2} = \frac{V\_o^2}{R} \tag{13}$$

Substituting Equation (11) in (13), the power balance becomes:

$$\frac{3V\_{spk}{}^2 t\_{\mathcal{S}} \, q}{2\omega L} = P\_o \tag{14}$$

According to Figure 11, the AC-DC converter can operate under two extreme conditions; a minimum supply voltage, *Vspkmin*, obtaining a maximum phase, *ϕmax*, with a maximum power demand at the output, *Pomax*; and a maximum supply voltage, *Vspkmax* obtaining a minimum phase, *ϕmin*, with a minimum power demand at the output, *Pomin.* Therefore, *ϕmax* and *ϕmin* are obtained using Equations (15) and (16) respectively:

$$
\sigma\_{\max} = t \lg^{-1} \frac{2P\_{\max} \omega L}{\mathfrak{H} V\_{spkmin}^2} \tag{15}
$$

$$\mathfrak{g}\_{\rm min} = \mathfrak{t} \mathfrak{g}^{-1} \frac{2P\_{\rm own} \omega L}{3V\_{\rm spkxxx}^2} \tag{16}$$

Considering *Pomax* = 5 kW, *Pomin* = 500 W, *Vspkmin* = 144 V and *Vspkmax* = 216 V, *ϕmax* and *ϕmin* are obtained for different values of *L*. Figure 12 is used to select the optimal *L* that allows an appropriate range of phase control. *L* was judged to be 3 mH, in such a way that *ϕ* can be ranged from 0.46◦ to 10.3◦.

**Figure 11.** Phasorial diagram for the AC-DC converter operation.

**Figure 12.** *ϕmin* and *ϕmax* obtained for different values of *L*.

*Energies* **2017**, *10*, 1386

The voltage *Vcpk* is expressed in function of the modulation index, *Ma*, when the converter operates with a SVPWM scheme [14], as follows:

$$V\_{cpk} = M\_a n V\_o \frac{\sqrt{3}}{4} \tag{17}$$

The minimum and maximum converter voltages, *Vcpkmin* and *Vcpkmax*, are utilized to obtain the minimum and maximum modulation indexes, *Mamin* and *Mamax* respectively, which are shown in (18) and (19):

$$M\_{\rm amin} = \frac{4V\_{cpkunin}}{\sqrt{3}nV\_o} \tag{18}$$

$$M\_{\text{max}} = \frac{4V\_{cphmax}}{\sqrt{3}nV\_{\theta}}\tag{19}$$

where *Vcpkmin* = 144.004 Volts and *Vcpkmax* = 219.53 Volts were calculated using Equation (7) for *Vspkmin* and *Vspkmax* respectively. An optimal value for *n* was determined by using Equations (18) and (19) and ranging *n* from 2 to 10, such that the results are plotted in Figure 13. *n* was selected to be 5 since *Ma* can be set between 0.66 and 1 to control the amplitude of the converter input voltage. It was judged in this work that n should be 5 to allow the converter an appropriate SVPWM operation and leave a small upper range of *Ma* for the ZVT effects since the maximum value of *Ma* is 1.16 for SVPWM [20].

**Figure 13.** *Mamin* and *Mamax* obtained for different *n*.

Equations (14) and (17) show that there is a compromise between the selection of the parameters *n*, *ϕ* and *L* to reach a wide range of *Ma* within the conventional active rectifier operation range.

#### **5. Numerical Verification**

To verify the principle of operation of the modular AC-DC converter and the SVPWM with ZVT control strategy, a simulation in Saber was performed using ideal components and the parameters listed in Table 4.


**Table 4.** Simulation Parameters.

### *5.1. Verification of the Modified SVPWM*

A Saber simulation was performed synchronizing the operation of the divided rectifier control signals with the fundamental frequency of the supply, using the scheme of Figure 14. *ILpk* is the current reference used to define *θ<sup>c</sup>* and *Ma* for the SVPWM operation of the rectifier and cause high power factor as shown in Figure 11. The converter voltage was phase shifted to align the line currents with the supply using the vectorial control system of Figure 14. A reference current of *ILpk* = 19.54 A was used to obtain a 100 V, 5 kW output with high power factor supply. The component of *Vcav* in the q axis, *Vcavq*, was determined using Equation (7) and the phasorial diagram of Figure 11, *Vcavq* = 22.1 V, such that *Vcavd* = *Vspk* = 180 V, therefore, the phase between *vs* and *vcav* was *ϕ* = 7◦.

**Figure 14.** General scheme used in simulation.

To confirm the correct operation of the scheme shown in Figure 14, Figure 15 shows a Saber result plot of the supply and converter phases, *θ<sup>S</sup>* and *θC*, for current references of 9.4 A and 19.54 A and cause 2.5 kW and 5 kW respectively. In Figure 15a a phase shift of 3◦ is obtained, whereas in Figure 15b the phase shift becomes of 7◦ since the current reference was increased. The effectiveness of the SVPWM rectifier operation of the circuit of Figure 1b was verified analyzing the Saber simulation results of the line currents and input voltages of the converter. Figure 16a shows Saber results of the source voltage *vaN* and the line current *ia*. The resultant line current *ia* is sinusoidal with a 3.3% ripple. Figure 16b shows the five-level converter voltage, *vacN*, to verify the correct operation of the space vector strategy. The current and voltage in the primary side of the transformer, *iprim* and *vprim* are shown in Figure 16c, where *iprim* is the rectified version of the line currents, but, inverted in one quadrant of the switching cycle producing a high-frequency AC square current.

The operation of the H bridge was verified contrasting the conventional SVPWM states with the phase-shifted control signals of the H bridge. Figure 17 plots the Saber results of *Sa, Sb* and *Sc* (Figure 17a–c, respectively) in contrast to *Sx* and *Sy* (Figure 17d,e). The H-bridge input voltages *vxG* and *vyG* are shown in Figure 17f,g, respectively, and its difference *vxy* is shown in Figure 17h. In the latter figure, *vxy* is a ±*Vo* quasi-square waveform, whose zero level is effectively produced by the H-bridge overlap, which can be used to produce the neutral vectors required by the conventional rectifier states in a switching cycle.

**Figure 16.** Simulation results (**a**) Supply voltage *vaN* and line current *ia*; (**b**) converter voltage in phase *a*; and (**c**) High-frequency current and voltage in the primary side of the transformer. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

**Figure 17.** Simulations results: conventional switching states (**a**) *Sa*, (**b**) *Sb* and (**c**) *Sc*; H-bridge switching states (**d**) *Sx* and (**e**) *Sy* and voltages (**f**) *vxG* (**g**) *vyG* and (**h**) *vxy*. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

The SVPWM strategy for the divided AC-DC converter of Figure 1b was verified by contrasting a switching cycle of the states *Sam*, *Sbm* and *Scm* with *Sa*, *Sb* and *Sc*. The upper plot of Figure 18 shows *Sa*, *Sb* and *Sc* together with *Sam*, *Sbm* and *Scm*; whilst the three-phase input converter voltages with respect to the *G* node of the DC link, *vacG*, *vbcG* and *vccG*, are shown in the lower plots of Figure 18 (Figure 18g–i) for straightforward comparison with those plotted in Figure 2. In these plots *vacG* and *vccG* are positive and negative rectified waveforms of *vxy*; furthermore, *vbcG* becomes a fully AC waveform due to the state reversals of the matrix converter leg since this switching cell utilizes the active-to-active switching transition.

**Figure 18.** Simulations results: (**a**) conventional switching states *Sa*; (**b**) *Sb*; and (**c**) and *Sc*; (**d**) matrix converter switching states *Sam*; (**e**) *Sbm*; and (**f**) *Scm*; (**g**) Voltage *vacG*; (**h**) *vbcG*; and (**i**) *vccG*. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

#### *5.2. ZVT Verification*

The effects of the ZVT in the transistors of the matrix converter were initially verified analyzing the quasi-square voltages *vxy* and *vsec* together with the transformer secondary current, *isec* = *iLs*, as shown in Figure 19 for direct comparison with Figure 4. In Figure 19a,b, during the first semi cycle, *vxy* and *vsec* are clamped to *Vo* such that *iLs* (Figure 19c) has a smooth negative slope; however, this slope becomes positive when the H bridge is in its overlap state to produce a neutral voltage vector at the converter AC input. A expanded portion of the first semi cycle of *iLs* is shown in Figure 19d.

**Figure 19.** Simulation results: (**a**) voltage *vxy*; (**b**) *vsec*; (**c**) current *iLs*; (**d**) Expanded portion of the first semicycle; (**e**) expanded portion of *TovL*; and (**f**) expanded portion of the second semicycle. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

At the beginning of the second semicycle, *iLs* is reversed in an overlap period of *TovL = 3* μs, as shown in the expanded portion of Figure 19e, which was confirmed using Equation (3), since *vxy* and *vsec* are now clamped to −*Vo* and zero respectively; whereas the rest of the second semicycle *iLs* becomes a mirrored wave of the first, which is shown in the expanded portion of Figure 19f. *iLs* is an AC trapezoidal waveform that is shaped by the switched operation of the H bridge and the matrix converter, which needs to be controlled to ensure stability and prevent saturation by the aid of a DC blocking capacitor, or a peak current control [21], since a high-frequency transformer is used in the proposed converter.

A zero-voltage switching transition is achieved in the matrix converter legs due to the zero-voltage biasing of its bidirectional switches whilst *iLs* is being reversed. This was verified analyzing the voltage and current waveforms in the first matrix leg switches *Q*<sup>1</sup> and *Q*<sup>4</sup> when an *iLS* reversal occurs. Figure 20 depicts the simulated switching transition result described in Figure 8 to turn on *Q*<sup>4</sup> and turn off *Q*1.Initially in Figure 20, the switches of *Q*1, *Q*1*<sup>a</sup>* and *Q*1*b*, and those of *Q*4, *Q*4*<sup>a</sup>* and *Q*4*b*, are in the on and off states respectively. Later in Figure 20a, *Q*1*<sup>a</sup>* and *Q*4*<sup>a</sup>* have an overlap period that cause to the voltage of *Q*4, *vQ*4*,* decrease to zero, and then *iQ*<sup>4</sup> increases as shown in Figure 20b, achieving a ZVT turn on in *Q*<sup>4</sup> during the current reversal. Whereas *iQ*<sup>4</sup> increases, *iQ*<sup>1</sup> falls to set *Q*<sup>1</sup> to the off state, as shown in Figure 20c, which depicts a hard switch off transition. During the overlap, *vsec* is clamped to zero and then biased to −*Vo* at the end of the overlap, whilst the current reversal in *iLs* occurs (Figure 20d).

**Figure 20.** Simulation results to verify ZVT during the switching transition to turn on *Q*4, (**a**) control signals *Q*1*a*, *Q*1*b*, *Q*4*a*, *Q*4*b*; (**b**) *iQ*<sup>4</sup> and *vQ*4; (**c**) *iQ*<sup>1</sup> and *vQ*1; and (**d**) *vsec* and *iLs*. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

Figure 21a shows the simulated results of the opposite switching transition to turn on *Q*<sup>1</sup> and turn off *Q*4. Mirrored waveforms are obtained for *iQ*1, *iQ*4, *vQ*<sup>1</sup> and *vQ*<sup>4</sup> in contrast to Figure 20. The ZVT is shown in Figure 21b when *iQ*<sup>1</sup> becomes positive during the zero voltage in *Q*1. *vsec* is clamped to *+Vo* whilst *iLs* is reversed.

**Figure 21.** Simulation results to verify ZVT during the switching transition to turn on *Q*1, (**a**) control signals *Q*1*a*, *Q*1*b*, *Q*4*a*, *Q*4*b*; (**b**) *iQ*<sup>1</sup> and *vQ*1; (**c**) *iQ*<sup>4</sup> and *vQ*4; and (**d**) *vsec* and *iLs*. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

#### *5.3. Steady-State Power Balance Verification*

To verify the input-to-output active power balance, the DC output power was calculated by the aid of the H-bridge output current *irect*. The current *iLs* and *irect* are shown in Figure 22a,b, respectively. In these figures *iLs* is seen to be rectified by the H bridge since *irect* may become either ±*iLs*, during the ±*Vo* clamping of *vxy* respectively or zero when the H bridge is in its short-circuit state. The average or *irect*, *Irect*, was calculated using the simulation results shown in Figure 22, and it was found that *Irect* = 50 A and, therefore, the output power is 5 kW, since the Saber simulation was performed assuming a constant DC output voltage of *Vo* = 100 Volts. In this fashion, the output power equalizes the active supply power, demonstrating the principle of operation of the AC-DC divided converter of Figure 1b.

**Figure 22.** Simulations results for (**a**) *iLs*; (**b**) *irect*. Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

To verify the high-quality supply currents the harmonic content in the line current *ia* was calculated, as shown in Figure 23; the measured current THD was 4.43%, being the power rated at 5 kW. Two main current harmonic clusters were found at the harmonic order of *n* = 242 and *n* = 488, corresponding to the frequencies of 14.5 kHz and 29.28 kHz, which were increased in amplitude since four switching transitions take place between space vector combinations during a switching period.

**Figure 23.** Harmonic content for line current *ia*.

The low order harmonic content of the input current was compared with the Standard EN61000-3-2 [22], for the limits of Class A converters. Figure 24 shows that the components are within the standard limits; for example, for *n* = 3, the amplitude is 0.39 A, 2% of the fundamental, that is less than limit, 2.3 A.

**Figure 24.** Low Harmonic content for line current *ia* for comparison with Standard EN 61000-3-2.

#### **6. Comparison of the Proposed Converter with Other AC-DC Topologies**

Table 5 presents a detailed comparison of the proposed topology with four other AC-DC converters of different levels. The first row of this table is referred to the charging power levels for EVs, which are currently three according to the International Electrotechnical Commission standard IEC61851 [23]. Level 1 is for small on-board battery chargers with typical use in home or office; Level 2 is for medium power battery chargers that can be used in private or public outlets, and Level 3 is generally designed for a recharging station for commercial and public transportation. The proposed topology is intended for Level 3 applications, which justifies the use of a three-phase voltage supply.



Table 5 shows that the number of switching devices used in the proposed converter is slightly higher in contrast to the topologies described in [14–16]; however, only four of them are located on-board the vehicle. The use of the bidirectional switches in the matrix converter allows the possibility power flow reversal through the converter, being more suitable to future smart grids. The implementation of the proposed AC-DC modular converter is considering the use of high-frequency, nanocrystal magnetic materials for the transformer core. In this fashion, higher power capability may be obtained with distributed gapped cores, such as the used in [15], increasing the efficiency limit by the actual wireless coupling techniques used in actual AC-DC chargers for wireless electric vehicles [22].

#### **7. Conclusions**

The splitting of a conventional active rectifier into a matrix converter and an H bridge linked through a high-frequency transformer resulted in an AC-DC modular converter topology ideal for high power density applications. The converter portion on board makes the topology particularly attractive for PEV's; nevertheless, the technique is suitable for other applications. A SVPWM technique with ZVT was proposed for the described converter which allows symmetric generation of virtually square current waves that are attractive for high-frequency wireless transmission of high power.

The topology was verified using a numerical prediction performed in Saber which resulted in high-quality supply currents with a current THD of 4.43%. An input-to-output power balance was verified ensuring reliable power transmission. The high-frequency switching of 7.2 kHz allowed ZVT of the semiconductor devices, since a short overlap period was caused by a simple sequential logic circuitry which aids to the reduction of the switching power losses of typical SVPWM schemes; nevertheless, semiconductor current monitoring is required to obtain correct switching behavior of the matrix converter.

Future aims of research of this topology consider its practical development at higher switching frequencies, allowing further reduction of size and weight, possibility of wireless power transmission, which would be particularly attractive for reliable and risk free charging of electric vehicles. Furthermore, the application of the proposed topology could be examined for other power electronic topologies.

**Acknowledgments:** The authors are grateful to the Fronteras de la Ciencia Research Project No. 101 of the Consejo Nacional de Ciencia y Tecnología of Mexico (CONACyT), the Instituto Politécnico Nacional of Mexico (IPN) for their encouragement and kind economic support to realize the research project. In addition, we are grateful to the Fondecyt Regular 1160690 Research Project.

**Author Contributions:** Jazmin Ramirez-Hernandez and Ismael Araujo-Vargas developed the principle of operation of the proposed AC-DC converter. The topology of the AC-DC converter was proposed by Marco Rivera. The numerical simulation results were obtained by Jazmin Ramirez-Hernandez using the Synopsis Saber Software, which was validated by Ismael Araujo-Vargas. Furthermore, the paper writing was done by Jazmin Ramirez-Hernandez and revised by Ismael Araujo-Vargas with a technical revision scope of Marco Rivera. All authors were involved and contributed in each part of the article for its final depiction as a research paper.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Nomenclature**



### **References**


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