*Article* **Direct van der Waals Epitaxy of Crack-Free AlN Thin Film on Epitaxial WS2**

**Yue Yin 1,2,3,†, Fang Ren 1,2,3,†, Yunyu Wang 1,2,3, Zhiqiang Liu 1,2,3,\*, Jinping Ao 4, Meng Liang 1,2,3, Tongbo Wei 1,2,3, Guodong Yuan 1,2,3, Haiyan Ou 5, Jianchang Yan 1,2,3,\*, Xiaoyan Yi 1,2,3,\*, Junxi Wang 1,2,3 and Jinmin Li 1,2,3,\***


Received: 9 November 2018; Accepted: 1 December 2018; Published: 4 December 2018

**Abstract:** Van der Waals epitaxy (vdWE) has drawn continuous attention, as it is unlimited by lattice-mismatch between epitaxial layers and substrates. Previous reports on the vdWE of III-nitride thin film were mAinly based on two-dimensional (2D) mAterials by plasma pretreatment or pre-doping of other hexagonal mAterials. However, it is still a huge challenge for single-crystalline thin film on 2D mAterials without any other extra treatment or interlayer. Here, we grew high-quality single-crystalline AlN thin film on sapphire substrate with an intrinsic WS2 overlayer (WS2/sapphire) by metal-organic chemical vapor deposition, which had surface roughness and defect density similar to that grown on conventional sapphire substrates. Moreover, an AlGaN-based deep ultraviolet light emitting diode structure on WS2/sapphire was demonstrated. The electroluminescence (EL) performance exhibited strong emissions with a single peak at 283 nm. The wavelength of the single peak only showed a faint peak-position shift with increasing current to 80 mA, which further indicated the high quality and low stress of the AlN thin film. This work provides a promising solution for further deep-ultraviolet (DUV) light emitting electrodes (LEDs) development on 2D mAterials, as well as other unconventional substrates.

**Keywords:** AlN thin film; WS2; MOCVD; van der Waals epitaxy

#### **1. Introduction**

Over the past few years, the van der Waals epitaxy (vdWE) of III-nitride devices has attracted a tremendous amount of attention [1–7]. This epitaxial mechanism is based on the weak van der Waals interaction between underlying two-dimensional (2D) mAterials and epitaxial layers, which will help to address the issue of lattice- and thermal-mismatch in the III-nitride heteroepitaxy [8,9]. Furthermore, semiconductors grown on 2D mAterials can be easily transferred to other unconventional substrates, which will create a new era for their potential applications in flexible electronics [10].

Among various 2D mAterials, graphene has been a focus due to the key advantage of its honeycomb crystal lattices, which are structurally compatible with the III-nitride film [7]. However, because of the lack of dangling bonds on 2D mAterials, the growth of high-quality III-nitride film is not an easy task. Several methods have been employed to create artificial defects, which are helpful to increase nucleation density for the subsequent growth of high-quality thin film [11]. Chung et al. conducted the growth of heteroepitaxial nitride thin film on high-density, vertically aligned ZnO nanowalls deposited on a graphene layer treated by O2 plasma [1]. Han et al. utilized graphene oxide microscale patterns based on sapphire substrate to realize the epitaxial lateral overgrowth of GaN [2]. Kim et al. employed the periodic nucleation sites at the step edges of graphene/SiC to realize the direct vdWE of high-quality single-crystalline GaN film [3].

AlN is the fundamental component for AlGaN-based deep-UV LEDs, which are widely applied in the field of water purification, sensing, polymerization solidification, and non-line-of-sight communication [12]. Although some progress has been mAde in the growth of GaN thin films on 2D mAterials, the growth of AlN thin films remains challenging. Our group previously reported a series of studies on the growth of AlN thin films. Qing Zeng et al. released their research into the growth of continuous AlN film on graphene, with the step edges and defects as the nucleation sites [5]. Yang Li et al. experimentally studied the feasibility of solving large mismatch problems with multilayer graphene acting as the interlayer between sapphire and the III-nitride, and further studied the effects of the optical and electrical properties of LEDs on graphene [6]. To mAke the action in strict van der Waals epitaxial growth on 2D mAterials interlayer clear, Yunyu Wang et al. investigated the roles of a graphene buffer layer in AlN nucleation on a sapphire substrate, indicating that graphene caused a decrease of nucleation density and an increase in AlN nuclei growth rate, and significantly weakened the AlN–Al2O3 interaction to release the strain [7].

The studies mentioned above are all based on the graphene buffer layer. Auxiliary methods were needed to assist the deposition of the III-nitride film (e.g., plasma treatment and ZnO nanowalls) [1,3,4]. However, the growth mechanism was changed owing to the introduction of dangling bonds, which means it is not a van der Waals epitaxy in the true sense. To realize the strict van der Waals epitaxy, more 2D mAterials are tested for the growth of III-nitride thin film. WS2 and MoS2 would be perfect candidates because their small lattice mismatches with III-nitrides are only 1.0% and 0.8%, respectively, to the "a" lattice parameter of GaN [13]. In 2016, Gupta et al. proposed exhaustive studies on the growth of strain-free and single-crystal GaN islands by metal-organic chemical vapor deposition (MOCVD) on mechanically-exfoliated WS2 flakes [13]. Chao Zhao et al. reported the growth of InGaN/GaN nanowire LEDs on sulfurized Mo substrates [14]. Nevertheless, the growth of continuous III-nitride thin film on transition metal dichalcogenide (TMDC) buffer layers still lacks relevant research.

Motivated by these considerations, here we present the first experimental investigation of the direct epitaxy of continuous AlN thin film with a WS2 interlayer. Herein, high-quality AlN was obtained by MOCVD on intrinsic WS2/sapphire substrate. The measured root mean square (RMS) roughness was 0.230 nm. Thanks to the atomistic smoothness of the released AlN film, a fully functional 283 nm deep-ultraviolet (DUV) light emitting diodes (LEDs) device was further demonstrated.

#### **2. Materials and Methods**

In our work, high-purity WO3 (at 1000 ◦C) and S (at 200 ◦C) were applied for the synthesis of single-crystalline WS2 film with an area of 1 × 1 cm2 on sapphire substrates directly, with Ar and H2 as carrier gases, respectively, in a three-temperature zone tube furnace. An AlN thin film was deposited by MOCVD on the WS2/sapphire substrate. Trimethylaluminum (TMAl) and NH3 were employed as Al and N precursors, respectively. An AlN nucleation layer was first deposited at 890 ◦C for 4 min with a V/III ratio of about 9640. After low-temperature growth of the AlN nucleation layer, the temperature was increased to 1200 ◦C to grow a 500 nm AlN epilayer for 30 min with a V/III ratio of 578. No additional intermediate layers or substrate treatments were employed for AlN layer growth

on WS2/sapphire layer. H2 was used as carrier gas for all of the growth steps. The MOCVD chamber pressure was kept at 50 torr during the whole growth process.

After the AlN thin film epitaxial growth, AlGaN-based DUV LED structures were further grown on the AlN/WS2/Sapphire template. Trimethylgallium (TMGa) was used as the Ga precursor. A 20-period AlN/Al0.6Ga0.4N superlattice (SL) was first deposited at 1130 ◦C, with periodic flow change of TMAl to adjust the deposition component, while the TMGa flow was kept at 32 sccm. Temperature was reduced to 1002 ◦C. Then, the SiH4 lane was opened with the flow of 20 sccm, and an n-Al0.6Ga0.4N layer was deposited with the thickness of 1.8 μm. Five-period Al0.5Ga0.5N/Al0.6Ga0.4N multiple quantum wells (MQWs) were further grown, with a 12.2 nm quantum barrier and 2.4 nm quantum well in each period. The TMAl was switched from 24 sccm to 14 sccm, while the TMGa was switched from 8 sccm to 7 sccm alternatively each time before the growth of quantum wells. A 60 nm p-Al0.65Ga0.35N electron blocking layer (EBL), a p-AlGaN cladding layer, and a p-GaN contact layer were subsequently extended. The NH3 was 2500 sccm during the whole growth process. After the growth, the sample were annealed at 800 ◦C with N2 flow for 20 min to activate the Mg acceptors.

Furthermore, standard LED processes were mAde to fabricate DUV LED, such as photolithography, ICP etching, etc. A 210 nm Ti/Al/Ti/Au metal stack and a 40 nm Ni/Au stack were respectively vapored as the n- and p-electrodes. In the end, the chips were flip-chip bonded onto ceramic submounts.

#### **3. Results**

The surface morphology of the WS2 on the sapphire substrate was examined using a Hitachi S4800 scanning electron microscopy (SEM, Tokyo, Japan) operated at 3 keV acceleration voltage (Figure 1a) and tapping mode atomic force microscopy (AFM, D3100, Veeco, New York, NY, USA) (Figure 1b), indicating that the substrate could be fully covered with continuous and uniform monolayer WS2 film. Some secondary nuclei were attached to the WS2 film. A JOBIN YVON-HORIBA HR800 Raman spectrometer (Kyoto, Japan) with a semiconductor laser at 532 nm as the excitation source was employed to analyze the chemical properties and detailed compositions of the direct-grown WS2 film. Raman spectra presented similar intensity of 2LA and A1g mode peaks (Figure 1c), which verified the good film uniformity over the area of 1 × 1 cm2 [13].

After the AlN thin film was grown on the WS2/sapphire substrate by MOCVD, a SEM image was obtained to investigate the surface morphology of the as-grown film, as presented in Figure 2a. Mirror-smooth and crack-free AlN thin films were grown with complete coalescence. The AFM image further verifies that the surface topology of as-grown AlN thin film on WS2/sapphire substrates was flat, with the RMS roughness at 0.230 nm over a lateral distance of 5 μm, as seen in Figure 2b, which was comparable with the AlN thin film directly grown on sapphire [15].

The stress of as-grown AlN thin film was further evaluated by Raman spectroscopy. The biaxial strain in the AlN layer was relative to the *E*<sup>2</sup> phonon mode movement of the Raman spectrum. Figure 2c shows the AlN epilayers grown on WS2/sapphire substrate sustained tensile stress, demonstrating a smaller frequency (656 cm<sup>−</sup>1) compared with stress-free AlN (657 cm−1). The stress relaxation of AlN epilayers, prompted by the WS2 interlayer, can be appraised in light of Δ*ω* = *Kσxx*. In this formula, Δ*ω* is the *E*<sup>2</sup> peak movement between the sample and stress-free AlN crystal, while *K* is the biaxial stress conversion factor ≈3.7 cm−1·GPa−<sup>1</sup> [16–18]. The biaxial stress value of AlN epilayers grown on WS2/sapphire substrate was 0.27 GPa. Compared with the Raman spectra of the WS2/sapphire substrate, the presence of WS2 after the film's growth was confirmed by the same peak at 417.6 cm−<sup>1</sup> in Figure 1c.

**Figure 1.** Characterizations of direct growth of WS2 on sapphire substrate. (**a**) Scanning electron microscopy (SEM) image of the WS2 film directly grown on sapphire substrates. (**b**) Atomic force microscopy (AFM) image of the WS2 film with root mean square (RMS) roughness around 0.203 nm. (**c**) Raman spectra of the WS2 film on sapphire substrates.

The crystal quality of AlN was evaluated by means of a Bede X-ray metrology double crystal high-resolution X-ray diffraction rocking curve (XRC) analyses. Figure 2d,e shows the ω-scan profiles (rocking curves) of the AlN (0002) and (10-12) peaks. The full width at half mAximum (FWHM) values of the (0002) and (10-12) rocking curve of AlN are directly related to the densities of screw- and edge-dislocations in epilayers. The FWHM values of AlN thin film were measured to be 546 arcsec and 1469 arcsec, respectively, for (0002) and (10-12) reflections. The estimated densities of screw and edge dislocations were 6.49 × 108 cm−<sup>2</sup> and 2.42 × <sup>10</sup><sup>10</sup> cm−<sup>2</sup> [19]. Although the FWHM value was slightly larger than that of the AlN thin film grown on graphene film with extra plasma treatment. The results of rocking curves suggest the preferable c-axis alignment of the AlN film grown on the WS2 interlayer. To explore the epitaxial relationship between AlN epilayers and c-plane sapphire, we employed XRD-ϕ scan with 2θ = 25.58◦ χ = 57.61◦ (Figure 2f). Six peaks of the AlN curve could be observed. Each one was 60 degrees apart, while three peaks of the sapphire curve could be observed, and each one was 120 degrees apart. Those curves reveal that the AlN (0002) facets were rotated by 30 degrees with sapphire (0006) facets through WS2, describing the epitaxial relationship was [1100] AlN//[11-20] sapphire. The crystalline orientations of as-grown AlN film were also identified by using electron backscatter diffraction (EBSD). The EBSD mApping provided evidence that most of the area of the AlN film displayed almost (0001) single crystallinity, as demonstrated in red by the inverse pole figure color triangle (Figure 2g). These results all strongly suggest that single-crystalline AlN film was grown on WS2 film, and the DUV LEDs could be subsequently deposited on the AlN/WS2/sapphire template.

**Figure 2.** Characterizations of AlN thin film growth on WS2/sapphire substrate without extra treatment. (**a**) SEM image, (**b**) AFM image, (**c**) Raman spectra, (**d**) X-ray rocking curves of (0002), and (**e**) (10-12) of the AlN film grown on sapphire with WS2 interlayers. (**f**) X-ray powder diffraction (XRD) ϕ scan curve with 2θ = 25.58◦ χ = 57.61◦. (**g**) Electron backscatter diffraction (EBSD) mApping of AlN film.

A conventional AlGaN-based DUV LED structure on WS2/sapphire substrate was achieved after the growth of AlN thin film. Its schematic illustration is shown in Figure 3a. In order to characterize the LED heterojunction structure and confirm the existence of WS2 in the AlN/WS2/sapphire interface, cross-sectional scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX) were applied. Microstructural behaviors of the whole heterojunction grown on AlN/WS2/sapphire template were investigated using the cross-sectional STEM at low mAgnification, allowing us to scan the entire DUV LED microstructure. The cross-sectional STEM image in Figure 3b shows that layer-by-layer grown LED structures were formed, consistent with the schematic illustration. Figure 3c indicates the high quality of multiple quantum wells (MQWs) at a higher mAgnification, verifying that the five-period Al0.5Ga0.5N/Al0.6Ga0.4N MQWs were defect-free. Figure 3d proves the existence of WS2 after the growth of the LED structure. The atomically resolved STEM image shows clearly distinguishable line between AlN and sapphire as the signal of WS2 exists. We also investigated the existence of WS2 interlayers by using EDX. The elemental mApping confirmed the existence of WS2 interlayers with distributions of S (Figure 3e) and W (Figure 3f). W element distribution was mAinly localized at the interface, with a relatively clear boundary. However, the wide distribution of S was probably the result of the decomposition of the WS2 layer to some extent. We tend to believe that WS2 layer still existed, although with mAny defects (e.g., S vacancy).

**Figure 3.** Characterizations of conventional AlGaN-based deep ultraviolet (DUV) light emitting diodes (LEDs) grown on WS2/sapphire substrates. (**a**) Schematic illustration of the DUV LED structure. (**b**) Cross-sectional scanning transmission electron microscopy (STEM) image of heterojunction LEDs; (**c**) Al0.5Ga0.5N/Al0.6Ga0.4N MQWs; and (**d**) the AlN/WS2/sapphire interface of the as-grown DUV LED. (**e**) Energy dispersive X-Ray spectroscopy (EDX) mApping of S; and (**f**) W element showing the WS2 gap between AlN and sapphire.

After the electrode deposition and other fabrication processes, the on-wafer electroluminescence (EL) performance of the DUV LED structure on the WS2/sapphire substrates was further investigated. A single-peaked spectrum was observed, with a peak wavelength at 283 nm at a dividing current of 80 mA (Figure 4a). Moreover, the current-voltage curve of the DUV LED with WS2 showed good rectifying behavior with a turn-on voltage of 3.38 V (Figure 4b), and the leakage current measured at −4 V was about 0.04 mA. This confirms that the quality of AlN thin film on WS2/sapphire was sufficiently robust to fabricate DUV LEDs. Figure 4c shows the functional relationship between light-out power (LOP) and injection current of LEDs. LOP increased simultaneously with the injection current, revealing that the EL emission was generated from the carrier injection and radiative recombination at MQW layers. In order to evaluate the reliability, the normalized EL of as-fabricated LED under different injection currents were investigated as shown in Figure 4d. The wavelength of the single peak only showed faint peak-position redshift from 281.8 to 283 nm, with current increasing from 30 to 70 mA, then blueshifted to 282.6 nm under the injection current of 80 mA. The inevitable thermal effect of UV devices and threading dislocation caused the redshift, while screening of the polarization electric field in strained MQW structures caused the blueshift [20,21]. The faint peak-position shift should be attributed to the low-stress property of AlN thin film. The carrier's recombination in p-AlGaN cladding layer likely led to the weak shoulder at 324 nm with low injection

current in the EL spectrum, which signifies that further optimization of the electron blocking layer to enhance the quantum confinement of electrons and suppress the electron overflow is necessary [22,23]. With increasing current, the relative intensity of the weak shoulder got weaker, until the weak shoulder vanished. These results demonstrate that conventional DUV LEDs could be fabricated on the WS2/sapphire substrate.

**Figure 4.** Electroluminescence (EL) of as-fabricated DUV LEDs. (**a**) The single-peaked EL spectrum of the DUV LED structure. (**b**) I-V curve of the fabricated DUV LEDs with WS2 buffer layer. (**c**) Light-out power (LOP) of the fabricated LEDs at various injection currents. (**d**) The normalized EL spectra of fabricated LEDs with currents ranging from 30 to 80 mA.

#### **4. Conclusions**

We demonstrated the experimental realization of crack-free and mirror-like single-crystalline AlN thin film on WS2 buffered sapphire substrate, resulting in RMS surface roughness of 0.230 nm, which is within the range of directly grown AlN film grown on sapphire substrate using MOCVD. The estimated densities of screw and edge dislocations were 6.49 × <sup>10</sup><sup>8</sup> cm−<sup>2</sup> and 2.42 × <sup>10</sup><sup>10</sup> cm−2. Hence, the quality of AlN thin film on WS2/sapphire was robust enough to fabricate DUV LEDs. Fully functional DUV LED was subsequently fabricated on the AlN/WS2/sapphire template. Its clear EL emissions had a peak wavelength of 283 nm at 80 mA. The wavelength of the single peak only showed a faint peak-position shift with increasing current to 80 mA. The cross-sectional TEM and EDS results confirmed our growth model and the presence of the continuous WS2 layer in the AlN/WS2/sapphire hetero-interface, even after the growth of LED. The efficient DUV LEDs fabricated on WS2/sapphire show the potential of WS2 for the epitaxy of the III-nitride on large-size and low-cost metal or amorphous substrates in the future. Our work provides a potential solution for further DUV LED development on unconventional substrates.

**Author Contributions:** Y.Y., F.R., Y.W., Z.L., J.A., M.L., J.Y., and J.L. conceived and designed the experiments. Y.Y. and F.R. conducted the experiments. Y.W., Z.L., T.W., G.Y., M.L., X.Y., H.O., and J.Y. are responsible for technical assistance with LED fabrication and measurement. Y.Y. performed the data analysis and wrote the mAnuscript. All authors contributed to the discussion and analysis of the results regarding the manuscript.

**Funding:** This research was funded by National Key R&D Program of China, grant number 2017YFB0403100, 2017YFB0403103, Beijing Municipal Science and Technology Project, grant number Z161100002116032, Guangzhou Science & Technology Project of Guangdong Province, China, grant number 201704030106 and 2016201604030035 and Innovation Fund Denmark, grant number 4106-00018B.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Article* **Properties of Undoped Few-Layer Graphene-Based Transparent Heaters**

**Yong Zhang 1,2,\*, Hao Liu 1, Longwang Tan 1, Yan Zhang 1, Kjell Jeppson 2, Bin Wei <sup>3</sup> and Johan Liu 1,2,\***


Received: 14 November 2019; Accepted: 17 December 2019; Published: 24 December 2019

**Abstract:** In many applications like sensors, displays, and defoggers, there is a need for transparent and efficient heater elements produced at low cost. For this reason, we evaluated the performance of graphene-based heaters with from one to five layers of graphene on flexible and transparent polyethylene terephthalate (PET) substrates in terms of their electrothermal properties like heating/cooling rates and steady-state temperatures as a function of the input power density. We found that the heating/cooling rates followed an exponential time dependence with a time constant of just below 6 s for monolayer heaters. From the relationship between the steady-state temperatures and the input power density, a convective heat-transfer coefficient of 60 W·m−2· ◦C−<sup>1</sup> was found, indicating a performance much better than that of many other types of heaters like metal thin-film-based heaters and carbon nanotube-based heaters.

**Keywords:** graphene; chemical vapor deposition (CVD); transfer; heater; resistance; heating/cooling rates

#### **1. Introduction**

Transparent resistive heaters were proposed for a variety of applications, such as sensors [1], displays [2], defoggers [3], and defrosters [4]. For certain applications, films of indium tin oxide (ITO) are commonly used materials for transparent heaters; however, poor stretchability and a complicated and costly fabrication process limit their usage [5]. Much effort was devoted to developing replacement materials, with some examples being silver nanowires [6–8], carbon nanotube films [9,10], and hybrid composites [11].

The electrothermal properties of graphene, an atom-thick planar sheet of *sp*2-bonded carbon atoms in a honeycomb pattern [12–14], with superconductivity recently observed in magic-angle graphene superlattices [15], indicate that this two-dimensional (2D) material could be the perfect material for many applications including transparent heater applications. Consequently, graphene-based heaters were recently proposed with graphene obtained by chemical vapor deposition (CVD) [3], from reduced graphene oxide [16–18], and from graphene aerogels [19]. Among these methods, CVD appears to be the most attractive for industrial production of graphene because of its scalability [20]. Graphene-based heaters fabricated by CVD are often doped with AuCl3, Au-CH3NO2, or HNO3 to enhance their electrothermal performance [21]. However, dopants introduced into graphene films might affect the stability of the material by reacting with ambient molecules, thereby causing material properties to degrade over time.

In this article, we present the results of a study of the electrothermal properties of transparent undoped few-layer graphene-based heaters where from one to five layers of graphene grown by CVD were transferred to flexible polyethylene terephthalate (PET) substrates. Our observations of their heating/cooling rates at different power densities are reported in the upcoming sections.

#### **2. Fabrication and Evaluation of Graphene-Based Heater Samples**

For the set of experiments presented in this work, monolayer graphene was grown on copper foils under low partial pressure by CVD following a standard procedure previously described in detail [22]. In short, this process involves a ~15-min temperature ramp-up to 1000 ◦C in ambient argon (1000 sccm)/hydrogen (80 sccm), a 5-min annealing at the growth temperature, a 5-min growth period using a methane precursor (5 sccm), and a ~35-min cool-down to room temperature (RT) again in ambient argon/hydrogen.

After growth, a standard layer-by-layer approach was employed to transfer the graphene from the copper foil onto PET substrates involving spin-coated poly(methyl methacrylate) (PMMA). By repeating the transfer process, a set of samples with between one and five layers of graphene was obtained. Samples were then turned into heaters by deposition of Cr/Au electrodes with a thickness of 10/70 nm at the edges of the graphene on PET samples. Finally, T-type thermocouples were attached to the back side of the PET substrates for in situ monitoring of the heater temperature by using a Keysight 34,970 A data acquisition/data logger switch unit. The accuracy of the thermocouple was estimated to be ±0.5 ◦C. All measurements were performed in a fume cupboard.

After fabrication, the quality of the graphene was investigated. Optical images showing the morphology of the Cu foil after graphene growth are shown in Figure 1a. As seen using an optical microscope, grain boundaries up to several hundred micrometers long became visible on the Cu foil. These grain boundaries were more clearly identified in scanning electron microscope (SEM) photos, such as the one shown in Figure 1b. The wrinkles were due to the mismatch between the coefficients of thermal expansion of graphene and the underlying metal [23]. It should be noted that those wrinkles crossed the Cu grain boundaries, and that no islands were observed, indicating that the as-grown graphene film was continuous [24]. From the Raman spectrum (Raman measurements were carried out with an XploRA (HORIBA, Ltd. Kyoto, Japan) at a 638-nm excitation wavelength and a 100× objective, with an incident power of ~1 mW) in Figure 1c, typical 2D/G peak intensity ratios of ~2.9 were identified indicating monolayer graphene [25]. As no D band was observed, the Raman spectra suggested as-grown graphene of high quality [22]. The transmission electron microscopy (TEM) image in Figure 1d clearly indicates edges of monolayer graphene, consistent with the Raman spectrum.

The flexibility and transparency of a monolayer graphene heater sample with an active heating area of ~1.5 <sup>×</sup> 1.5 cm<sup>2</sup> is shown in Figure 2a. For comparison, a three-layer graphene heater is shown on the same white background, where it can be seen that the transparency changed in the center area. A transmittance of ~97.7% was reported for monolayer graphene [26]. The corresponding transmittances were ~95.4% for bilayer graphene, ~92.7% for three-layer graphene, ~90% for four-layer graphene, and ~87.3% for five-layer graphene. As shown in Figure 2b, the uniform surface temperature distribution, as obtained by infrared imaging, indicated a uniform graphene film well in line with the SEM image in Figure 1b. The resistance of a set of few-layer graphene-based heaters was evaluated using four-point probing. As shown in Figure 3, the monolayer resistance was close to 5 kΩ, while the resistance of the twoto five-layer graphene heaters was in the 1–1.5-kΩ range. The resistances of the four and five-layer graphene-based heaters appeared to be larger than that of the three-layer graphene heater, which could possibly be explained by the uncertainty of the transfer process causing wrinkles or cracks in the graphene film, or from PMMA residues left from the wet transfer process despite a careful rinse process being used.

**Figure 1.** (**a**) Optical image of the morphology of Cu foil after graphene growth. (**b**) SEM image of the morphology of Cu foil after graphene growth. (**c**) Representative Raman spectrum (632 nm) of the graphene grown on Cu foil. (**d**) TEM images of synthesized graphene on Cu foil.

**Figure 2.** (**a**) Optical images of monolayer and three-layer graphene-based heater (top left inset: a monolayer graphene-based heater for illustrating flexibility; top right inset: a monolayer graphene-based heater placed on a Chalmers logo to illustrate transparency). (**b**) Typical infrared image showing the temperature distribution across the surface of a monolayer graphene heater. The infrared camera used was a high-resolution FLIR A655sc featuring a 640 × 480 pixel microbolometer that can detect temperature differences down to less than 30 mK.

**Figure 3.** The resistance of the graphene-based heaters versus the number of graphene layers measured using the four-point probe method.

#### **3. Electrothermal Performance of Graphene-Based Heaters**

The heating mechanism of the graphene heaters was Joule heating. The electrothermal performance of monolayer graphene-based heaters determined using T-type thermocouples is shown in Figure 4, showing the heating and cooling behavior for six different values of applied input power. As shown in the figure, the heating and cooling behavior of the graphene-based heaters showed an exponential time dependence with a thermal time constant of 7 s. This time constant indicated the elapsed time required for the temperature difference of the graphene heater to rise to 63% of its final value during heating or, correspondingly to decay to 37% during cooling. It can also be interpreted as the time it would have taken to reach the final value if the heating/cooling continued at its initial rate. The heating and cooling behavior of the graphene heaters with other numbers of graphene layers showed a similar exponential time dependence, but with different time constants. As an example, the time constant for five-layer graphene heaters was 14 s during cooling and 10 s during heating. This difference between the heating and cooling rates may be attributed to the temperature-dependent electrical conductivity of graphene [27]. The model equation during cooling can be written as follows:

$$T = RT + \Delta T e^{-(t - t\_0) / \tau},\tag{1}$$

where RT is the room temperature, ΔT the temperature difference between room temperature and steady-state temperature, τ is the time constant, and t0 is the time when the cooling starts.

From these experimental plots of the heating/cooling behavior of the graphene heaters, we could also extract the steady-state temperatures versus the input heating power. As shown in Figure 4, a steady-state temperature of 38 ◦C was obtained for an input power of 170 mW, while a steady-state temperature of 80 ◦C was obtained for an input power of 780 mW. The results are shown in Figure 5, where the steady-state temperatures were plotted as a function of the power density obtained by dividing the electrical input power by the 2.25-cm<sup>2</sup> area of the graphene heater. The choice of plotting versus the power density was done to enable a comparison between the performance of our graphene heater and other heaters previously reported in the literature. The plot in Figure 5 shows that graphene-based heaters, for the same input power density, reach much higher temperatures than, for instance, metal-based heaters [8,23]. For low temperatures and limited input power, heaters based on single-walled carbon nanotubes (CNTs) appear comparable, but there are no data available for higher temperatures [28]. Although details of the experimental set-ups may be different, it is

obvious that the electrothermal performance of the graphene heaters in this study is much better than the performance of metal-based heaters and somewhat better than that of CNT-based heaters. The electrothermal performance of a laser-reduced graphene oxide heater [17] was even better than this work. It also seems to be a general trend that nanoscale carbon-based heaters electrothermally outperform heaters based on metallic films. However, the most important feature of the graphene-based heaters, making it worthwhile to investigate their performance for potential use in future applications, is their transparency.

**Figure 4.** Time dependency of the electrothermal performance of a monolayer graphene-based heater for six different applied input voltages. The numbers occurring next to curves denote applied voltage, input power, and steady-state temperature, respectively. The temperature was logged using T-type thermocouples attached to the back side of the polyethylene terephthalate (PET) substrate.

**Figure 5.** Steady-state temperatures vs. dissipated power density for graphene-based heaters with one, two, three, four, and five layers of graphene. Also shown for comparison are the same temperature versus power density relationships for two metallic heaters and one heater based on carbon nanotube films [9,17,28].

From the data in Figure 5, the convective heat-transfer coefficient, *h*, of the graphene heaters could be determined from the trendline slopes of the data for each type of graphene heater, with a calculation method similar to a previous report [4]. Theoretically, the steady-state temperature of a heater is determined by a balance between the electrical input power and the heat loss (mainly due to radiation and convection). For graphene, with its low emissivity, we can neglect the radiation loss and express the convection heat loss by the following equation:

$$
\mathbb{Q}/A = h \,\,\Delta T,\tag{2}
$$

where Q/A is the input power density, and Δ*T* = *T* − *T*<sup>0</sup> is the temperature difference between the steady-state temperature, *T*, and the ambient temperature, *T*0. The resulting heat transfer coefficients are shown in Figure 6. There is no obvious trend for the dependence of the heat-transfer coefficient on the number of graphene layers, except possibly for the five-layer graphene heater that showed a somewhat lower value. For this reason, in Figure 5, only an average trendline is shown for the one- to four-layer graphene-based heaters (*h* <sup>≈</sup> 60 W·m−2· ◦C<sup>−</sup>1). Similarly, the Pt thin-film heater had a heat transfer coefficient of ~150 W·m−2· ◦C<sup>−</sup>1, while the corresponding value for the silver paste heater was ~240 W·m−2· ◦C<sup>−</sup>1.

**Figure 6.** Convective heat-transfer coefficients for graphene-based heaters with from one to five layers of graphene. Also shown are the *R*<sup>2</sup> regression numbers of the trendline approximations.

The heat-transfer coefficients obtained for the graphene-based heaters were higher than the coefficient for natural convection of air (~5–25 W·m−2· ◦C−1), but in the range for that of forced convection of air (~20–200 W·m−2· ◦C<sup>−</sup>1). The higher value obtained here may be due to our experiments being conducted in a fume cupboard. Deviations between graphene samples were not appreciable, thereby validating the reliability of our measurements. The differences in heat-transfer coefficients between carbon-based heaters and metal thin-film heaters may be attributed to differences in the thermal interface conductance between the solid-gas adsorbates.

Finite element models were developed in COMSOL for studying the steady-state properties of graphene-based heaters and their surface temperature distributions. The electrically generated heat was modeled by using the electric currents and layered shell interface aimed at computing currents and potential distributions in thin conducting layers. Simulations using COMSOL for modeling properties of graphene were reported in previous work [29]. In this work, great care was taken to design the geometry of the model so that it would match the experimental behavior. For different electrical input power and the corresponding potential distributions across the heater surface, simulations resulted in an elevated temperature distribution across the surface of the PET substrate. For comparison between simulations and experiments, where the substrate temperatures were measured by a thermocouple, the average temperature of the backside of PET substrate at different input power densities was also calculated. A comparison between simulations and experiments is shown in Figure 7, where the simulation results show good agreement with the experimental results. What is not visible from the graph in Figure 7 is that, for the same power density, only half the applied voltage was needed for the

five-layer graphene-based heater compared to the monolayer heater for the same input power due to the factor of four in their resistance difference. Moreover, the simulated temperature distribution is shown in Figure 8, where it can be seen that the steady-state surface temperature increased with the input voltage. Other graphene heaters had the same trend, whereby the steady-state surface temperature increased with the input voltage, but the values were different.

**Figure 7.** Simulated (open symbols) and experimental (solid symbols) steady-state surface temperatures for monolayer, three-layer, and five-layer graphene-based heaters.

**Figure 8.** Steady-state surface temperature distributions of monolayer graphene-based heaters for six different applied voltages (the applied powers were also calculated).

Finally, an interesting observation made during our experiments was that the resistance of the graphene-based heaters increased after some time of exposure to air. We found that the resistance of the transferred graphene films was significantly increased after a one-year exposure to air, with increases for some samples as much as three to five times, which is much larger than reported in a previous study [30]. Other studies also reported that the resistance of transferred graphene films increased after storage in a humid environment [31,32]. As previously discussed, cracks and residues cannot be completely avoided during the transfer process from the copper foil on which the graphene is grown to the transparent PET substrate. Therefore, there is a risk that water molecules permeate the cracks and traverse the residues, which may weaken the graphene adhesion to the PET substrate and cause an increase in the resistances. It was also found that, when the PET substrates were placed on ice, the resistances of the graphene film increased by 10–20%. However, the resistance returned to the initial values after drying. The increase in resistance indicates that the adhesion between the graphene and the substrate plays a key role in the electrothermal performance of graphene-based heaters in real-world applications.

#### **4. Conclusions**

Based on the assumption that graphene, with its excellent electrothermal properties, could be a perfect material for transparent heaters in many applications, we designed and fabricated a set of graphene-based heaters with from one to five layers of CVD graphene grown on copper and transferred to a PET substrate. The properties of these graphene-based heaters were evaluated both experimentally and theoretically by simulations in terms of steady-state temperatures and in terms of heating/cooling rates versus the applied power density. In conclusion, we find our results promising in terms of quantifiable parameters such as thermal time constants, maximum heating/cooling rates, and convective heat-transfer coefficients when compared to Ag and Pt metal-based thin-film heaters. However, much work remains to refine the fabrication process and to improve the quality of the graphene films. As an example, we found that the quality of the graphene film and its adhesion to the PET substrate play a key role in determining the performance and reliability of graphene-based heaters when it comes to their electrothermal properties. The results presented here in this study strengthen our belief in graphene-based heaters as being promising candidates for the next generation of transparent heaters for various applications, such as anti-fog windows, mirror defoggers, and outdoor displays.

**Author Contributions:** Y.Z. conceptualized and designed the experiments, conducted the experiments together with H.L., and wrote the original draft manuscript. L.T. and Y.Z. conducted the simulations together with Y.Z., who also performed the data analysis together with K.J. The final manuscript was written by K.J. and Y.Z. All authors contributed to the discussion and analysis of the results regarding the final manuscript. All authors have read and agreed to the published version of the manuscript.

**Funding:** The authors acknowledge the financial support by the KeyR&D Development Program from the Ministry of Science and Technology of China with the contract No. 2017YFB0406000, the Science and Technology Commission of Shanghai Municipality Program (19DZ2281000), and the National Natural Science Foundation of China (No. 51872182, No. 11672171, No. 11974236, and No. 61775130). J.L. also acknowledges the financial support from the Swedish Board for Innovation (Vinnova) under the Sioagrafen program, from the Swedish Board for Strategic Research (SSF) with the contract No. SE13-0061 and GMT14-0045, from Formas with the contract No. FR-2017/0009, and from the Swedish National Science Foundation with the contract No. 621-2007-4660, as well as from the Production Area of Advance at Chalmers University of Technology, Sweden.

**Conflicts of Interest:** The authors declare no conflicts of interest.

#### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Review* **Thermal Characterization of Low-Dimensional Materials by Resistance Thermometers**

#### **Yifeng Fu 1,\*, Guofeng Cui <sup>2</sup> and Kjell Jeppson <sup>1</sup>**


Received: 30 April 2019; Accepted: 24 May 2019; Published: 29 May 2019

**Abstract:** The design, fabrication, and use of a hotspot-producing and temperature-sensing resistance thermometer for evaluating the thermal properties of low-dimensional materials are described in this paper. The materials that are characterized include one-dimensional (1D) carbon nanotubes, and two-dimensional (2D) graphene and boron nitride films. The excellent thermal performance of these materials shows great potential for cooling electronic devices and systems such as in three-dimensional (3D) integrated chip-stacks, power amplifiers, and light-emitting diodes. The thermometers are designed to be serpentine-shaped platinum resistors serving both as hotspots and temperature sensors. By using these thermometers, the thermal performance of the abovementioned emerging low-dimensional materials was evaluated with high accuracy.

**Keywords:** thermal characterization; resistance temperature detector; heat spreader; carbon nanotube; graphene; boron nitride

#### **1. Introduction**

The semiconductor industry is pursuing electronic systems with higher integration density, more functions, higher power and frequency, and smaller footprint and volume, with lower cost. When the performance increases, the power density in electronics systems becomes higher and higher; thus, heat dissipation becomes a critical issue. In addition, the increase of hotspots and packaging complexity, such as in three-dimensional (3D) stacking of processor and memory chips, makes thermal management an even more difficult task in microsystems. Various advanced materials and technologies were proposed and demonstrated to improve thermal management in electronics, for instance, nanoparticles and graphene-enhanced thermal interface materials (TIMs) [1], carbon nanotube (CNT)-based TIMs [2], cooling fins [3], etc. Therefore, thermal characterization of such nanomaterials and nanostructures becomes more important than ever to evaluate their performance.

Various methods were developed to characterize the thermal performance of nanomaterials. For instance, the thermal bridge method can be used to measure the in-plane thermal conductivity of extremely small structures down to a single atom layer [4]; the e-beam self-heating method can be used to measure the contact thermal resistance at material interfaces [5]; scanning thermal microscopy is able to map local temperature with nanoscale resolution and thermal conduction in materials [6]; the optothermal Raman spectroscopy technique allows high accuracy measurement of the thermal conductivity of atomic thick nanomaterials [7]; the pulsed photothermal reflectance method can be used to measure both thermal conductivity of materials and contact thermal resistance at interfaces [8]; the 3ω method allows high accuracy measurement of the thermal conductivity of materials [9]; the transient plane source method allows fast measurement of thermal conductivity, thermal diffusivity,

and specific heat capacity of materials [10]; the laser flash method is also an easy-to-implement method for thermal conductivity measurement of materials [11]. It should be noted that the method should be selected depending on the size, geometry, composition, and performance of the materials in order to perform a proper characterization. Among all the thermal characterization methods, the on-chip resistance thermometer is a component allowing high accuracy, high speed, and real-time characterization of nanomaterials and nanostructures. This paper is expanded from a conference paper [12] but elaborates upon and includes the most recent published results to review the previous work on thermal characterization of various one- and two-dimensional (1D and 2D) nanomaterial-based cooling structures using resistance thermometers. First of all, the design, fabrication, and calibration of the resistance thermometer is presented. Secondly, we summarize the thermal characterizations of different low-dimensional materials using the resistance thermometer. This includes CNT-based cooling fins, graphene-based lateral heat spreaders, and boron nitride (BN)-based heat spreaders.

#### **2. Resistance Thermometers**

The principle of a resistance thermometer is to use temperature-sensitive materials to detect temperature by monitoring the change in electrical resistance of the material. Among all the materials, platinum (Pt) is one of the most used due to its highly linear temperature–resistance relationship. Fu et al. fabricated a resistance thermometer using e-beam evaporated Pt thin films on silicon chips [13], as shown in Figure 1. In order to realize the temperature monitoring in an embedded interface, they used through-silicon via (TSV) technology to read out the temperature. The serpentine Pt temperature sensors can also simultaneously act as heating elements to simulate hotspots in chips for the thermal characterization of heat dissipation materials and structures. After the fabrication, the resistance thermometers were calibrated by a standard resistance temperature detector (RTD). After calibration, the resistance thermometers can be used to monitor the temperature distribution on the thermal test chip; therefore, the cooling performance can be easily evaluated by simply measuring the resistance.

**Figure 1.** The thermal test chip with resistance thermometers and heating elements.

The thermal test chip fabricated by Fu et al. [13] shown in Figure 1 consists of a 3 × 3 array of thermometers with a size of 390 <sup>×</sup> 400 <sup>μ</sup>m2. The thickness of the platinum thermometers is 40 nm. Prior to the deposition of the platinum resistors, a 20-nm-thick titanium layer was deposited as an adhesion layer. The thickness of the insulating silicon dioxide (SiO2) layer on the silicon substrate was 300 nm. Balandin et al. used a similar structure to model the heat spreading from metal–oxide–semiconductor (MOS) field-effect transistors on silicon-on-insulator (SOI) substrates with and without graphene heat spreaders [14].

In this paper, the thermal test chip shown in Figure 1 and its slightly modified version (to provide even higher power density) were used to evaluate the cooling performance of various nanomaterials and nanostructures, and the results are presented in Sections 3–5.

#### **3. CNT-Based Micro Heat Sinks**

Owing to the very strong *sp2* hybridized C–C bonding, CNTs exhibit excellent thermal properties. Therefore, they were proposed as a candidate for thermal interface material development and many results were reported [15–19]. On the other hand, since CNTs are mechanically strong [20,21] and can be vertically aligned, they can also be applied as heat sinks. CNT-based micro heat sinks were demonstrated to cool down power transistors by Mo et al. [3]. They grew CNTs on a silicon chip (as shown in Figure 2) and fabricated the cooler separately before attaching it onto the power transistor. It was found that the CNT-based cooler was able to cool down the power transistor to a much lower temperature (108 ◦C vs. 119 ◦C) even at much higher power input (25.7 W vs. 19.6 W). Fu et al. modified the design and fabricated the CNT cooling fins directly on top of the hotspots on silicon chips in order to further decrease the thermal resistance on the heat dissipation path [22], as shown in Figure 3. They firstly grew the CNT structures on a silicon substrate using Fe as a catalyst, and then transferred the CNT cooling fins onto a thermal test chip with high-power-density hotspots. Low-melting-point metal indium was used as the transfer media so that the transfer process would be compatible with complementary metal–oxide–semiconductor (CMOS) processes. The CNT fin structure was electrically insulated from the hotspot resistor by a 300-nm SiO2 insulating layer on the hotspot circuit. More details about the transfer process can be found elsewhere [23,24]. Prior to the fabrication of the CNT cooling fins, multi-scale modeling was performed to optimize the dimension of the CNT structures (i.e., height, width, and pitch of the CNT fins); therefore, optimal pressure decrease (between coolant inlet and outlet) and maximal cooling effect were obtained.

**Figure 2.** As-grown CNT cooling fins used to cool down the power transistor. Reprinted with permission from [3].

**Figure 3.** Transferred CNT cooling fins directly fabricated on top of the hotspot test structure. Reprinted with permission from Reference [22].

After transfer, the on-chip CNT-based micro heat sink was mounted onto a supporting circuit board as shown in Figure 4. To complete the cooling system, inlet and outlet nozzles were fabricated and connected to the CNT cooling fin structures through aluminum chambers at two ends of the test chip. Finally, polydimethylsiloxane (PDMS) was used to encapsulate the whole system to prevent coolant leakage. As a reference for studying the cooling performance of the CNT-based micro heat sink, identical cooling systems without CNT cooling fins were also fabricated and characterized.

**Figure 4.** (**a**) On-chip CNT cooling fin test structure mounted on a supporting circuit board. (**b**) Complete cooling system embedded in polydimethylsiloxane (PDMS) with inlet and outlet nozzles for the coolant.

In order to examine the cooling performance of the CNT-based micro heat sink, air and water were used as coolant, and they were pumped to flow through the micro channels between the CNT fins. Some results of the experiments are shown in Figure 5 where the temperature at the hotspot is plotted vs. heat flux through the resistive hotspot.

As expected, water is a much more effective coolant than air. For a heat flux of 3000 W/cm2, the hotspot temperature decreased by almost 50 ◦C (from 116 to 68 ◦C) upon using water at a flow rate of 0.32 m/s, compared to when air was used as the coolant, even though the air flow rate was ten times larger (3.2 m/s). However, more interesting is the unfortunate fact that the CNT cooling fins seemed to have a minimal influence when air was used as coolant. This is believed to be a combination of the thermal contact resistance to the hotspot being too high due to the interface layers, and that macro-scale cooling may not be directly scalable to a micro-scale environment.

**Figure 5.** Cooling performance of the CNT-based micro heat sink using water as coolant (with air cooling as a reference) plotted as the hotspot temperature vs. heat flux. Experimental data sourced from Reference [22].

The experiments showed that, when the chip was cooled by water at a flow rate of 0.32 m/s, the hotspot temperature on the chip with the CNT cooling fin structure was about 8–10 ◦C lower than on the test chip without the CNT fins. Interestingly enough, beyond a certain flow rate of the water coolant, the cooling effect seems to be more or less independent of the flow rate, as shown in Figure 6. Since the water cooling of the indium adhesive seems to be so effective, the influence of the CNT cooling fins even appears to decrease as the flow rate of the water coolant increases beyond 0.08 m/s.

**Figure 6.** Hotspot temperature decrease vs. flow rate of water coolant for four different heat fluxes through the hotspot resistor. Experimental data sourced from Reference [22].

Finally, Figure 7 shows that the decrease of the hotspot temperature due to water cooling of the CNT fins seems to increase linearly with the flow rate of the water coolant.

**Figure 7.** Hotspot temperature decrease vs. water coolant flow rate (test structure with CNT cooling fins = filled markers; test structure without CNT cooling fins = open markers). Experimental data sourced from Reference [22].

#### **4. Graphene-Based Heat Spreaders**

Similar to CNTs, graphene also possesses excellent thermal and mechanical properties due to its special crystalline structure [25]. In electronic systems, non-uniform distribution of thermal energy dissipates from high-power components, such as high-power transistors and light-emitting diodes (LEDs), leading to the formation of hotspots, together with high average device temperatures, resulting in the degradation of device performance and poor reliability. Therefore, various thermal composites [26–31] and heat spreaders [8,32–38] were developed and demonstrated using liquid-phase exfoliated (LPE) graphene and chemical vapor deposition (CVD)-grown graphene.

Balandin et al. showed that a few-layer graphene-based heat spreader connected to the drain of gallium nitride (GaN) high-power field-effect transistors considerably reduced the device temperature [32]. Using micro-Raman spectroscopy for in situ monitoring, they demonstrated that hotspot temperatures could be lowered by ∼20 ◦C in transistors operating at a power density of ~13 W per mm of channel width, which they claim corresponds to an order-of-magnitude increase in device lifetime. Similarly, Hong et al. showed improved heat dissipation in gallium nitride LEDs by embedding reduced graphene oxide (rGO) patterns into the devices [33]. The infrared images of the LED chip surfaces from their paper shown in Figure 8 indicate a decrease in peak temperature on the chip surface from 58 ◦C for a conventional LED to 53 ◦C for the rGO-embedded LEDs. In addition, the average temperature on the chip surface decreased from 51 to 47 ◦C.

To evaluate the graphene-based heat spreaders, a new version of the resistance thermometer was designed and fabricated. Based on the lessons learnt from the CNT-based micro heat sink, the wires connecting the hotspot resistor and the I/O pads were redesigned to minimize the power dissipation via interconnect circuit. Two examples of such redesigned resistance thermometers are shown in Figure 9.

**Figure 8.** Infrared thermal imaging camera photographs of the chip surfaces showing the temperature distribution on the surface of (**a**) a conventional light-emitting diode (LED) chip, and (**b**) a reduced graphene oxide (rGO)-embedded chip under 100 mA current injections. Sourced from Reference [33]. Reprinted with permission from Nature Communications.

**Figure 9.** Redesigned resistance thermometers with larger area available for the heat spreader (**a**,**c**), and wider terminal wires (**b**,**d**).

These hotspot test structures were used in a series of experiments to investigate the thermal performance of 2D materials with high thermal conductivity, such as monolayer and multilayer graphene, and BN-based heat spreaders. By using such 2D materials as heat spreaders to dissipate the Joule heat generated from the hotspot laterally across the chip surface, both the hotspot temperature and the average temperature across the chip can be lowered. The area of the hotspot resistor used in these experiments was 390 <sup>×</sup> 400 <sup>μ</sup>m2, and its resistance was about 80 <sup>Ω</sup> at room temperature. monolayer graphene grown by chemical vapor deposition (CVD) was placed on the thermal test chip as heat spreader via the transfer method [34,35]. The graphene was isolated from the resistor by a 30 nm SiO2 protective layer. Figure 10 shows the temperature vs. heat flux at the hotspot. It can be seen that the hotspot temperature can be decreased by about 10 ◦C by the graphene-based heat spreader (from 133 ◦C to 123 ◦C) at a heat flux of 460 W/cm2. Thick graphene-based films fabricated from the liquid-phase exfoliation method [8,36,37] were also applied as heat spreaders in the same way as the monolayer graphene as shown in Figure 11. To decrease the thermal contact resistance, the thickness of the SiO2 layer was reduced to one-tenth of the thickness that was used in the CNT

cooling fin experiments. The detailed process of transferring and placing the monolayer and multilayer graphene heat spreader onto the hotspot structure is described elsewhere [34].

**Figure 10.** Temperature monitoring on thermal test chip with and without a monolayer graphene heat spreader. Replotted data sourced from Reference [34].

**Figure 11.** Multilayer transferred graphene film placed on hotspot test structure as a heat spreader across the chip surface.

In another investigation, an infrared camera was used to monitor the temperature on the thermal test chip to evaluate the cooling performance of a graphene-based heat spreader [38]. The thermal images in Figure 12 show the temperature distributions across the surface of the thermal test chip, which indicate that the temperature decreased by 5 ◦C when monolayer graphene was used as lateral heat spreader.

**Figure 12.** Temperature distributions on thermal test chips at a heat flux of 1280 W/cm<sup>2</sup> without (**a**) and with (**b**) a graphene heat spreader. Sourced from Reference [38].

A recent study showed that the cooling performance of a graphene-based heat spreader (fabricated via the vacuum filtration method) can be further improved by interfacial functionalization [36]. In a series of experiments, the graphene films were functionalized by (3-amino-propyl)-triethoxysilane (APTES) molecules to decrease the thermal contact resistance between the graphene-based heat spreader and the hotspot test structure. In this series of experiments, the redesigned resistance thermometer from Figure 9c was used.

The resulting thermal performance of the graphene-based heat spreader before and after functionalization is shown in Figure 13. It can be seen that the hotspot temperature on a bare chip without graphene heat spreader was 146 ◦C under a heat flux of 1500 W/cm2. By placing a graphene film without functionalization on the surface of the test structure and repeating the measurements, the hotspot temperature was found to decrease to 140 ◦C (ΔT = 6 ◦C). The estimated accuracy was ±0.5 ◦C. If, instead, the functionalized graphene-based heat spreader was used, where the thermal contact resistance between the graphene-based film and the test structure was reduced by the addition of a functionalized graphene oxide (FGO) interfacial layer, the hotspot temperature was found to decrease to 134 ◦C (ΔT = 12 ◦C).

**Figure 13.** Cooling performance of functionalized graphene-based heat spreaders. Replotted data sourced from Reference [36].

#### **5. Hexagonal Boron Nitride Heat Spreaders**

In this paper, we also summarize the use of hotspot test structures for the evaluation of the performance of 2D hexagonal boron nitride (hBN) films as heat spreaders. The advantage of BN films over graphene is that they are electrically insulating and yet good thermal conductors [39]. In scenarios where electrical conduction is not allowed, hBN will be a very good complementary material to graphene for heat spreaders.

Bulk hBN has a typical thermal conductivity of 390 W/mK, which is 280 times higher than the thermal conductivity of silicon dioxide (SiO2) insulators. For hBN monolayers, the thermal conductivity value can be even higher [40–42]. Thus, the advantage of hBN films is that they might be integrated to the semiconductor circuitry and be placed directly on top or below the hotspot without any insulating SiO2 layers, which will significantly decrease the total thermal resistance along the heat conduction path and, therefore, greatly improve the cooling performance. For thermal management applications, 2D hBN was used to develop both thermal composites [43–45] and heat spreaders [46–48].

In the experiments to be summarized here, hBN films were transferred from the original growth substrate to the hotspot test structure via a similar method as the graphene films [32]. This transfer process includes spin-coating the hBN film with a supporting layer of polymethyl methacrylate (PMMA). The original growth substrate (Cu) was then etched away in a 30% FeCl3 solution, leaving the PMMA-supported hBN film floating in FeCl3 solution. The monolayer hBN film could then be transferred onto the calibrated hotspot test structure, before the PMMA was dissolved in hot acetone.

It should be noted that it is very challenging to fabricate freestanding pure hBN films since they are too brittle. Recently, Sun et al. successfully developed a process to fabricate flexible and uniform hBN films by adding acetate cellulose to the hBN dispersion [46]. Before thermal characterization on the hotspot test structure, the quality of the hBN material was examined by TEM. Results showed that few-layer hBN flakes were dominant in the film. The hotspot structure with an hBN heat spreader is shown in Figure 14. Thermal characterization was performed to evaluate the cooling performance of the hBN heat spreader using an infrared camera. Results showed that the hBN heat spreader can lower the hotspot temperature by almost 20 ◦C under a power density of 625 W/cm2.

**Figure 14.** The hotspot test structure with the hexagonal boron nitride (hBN) heat spreader film. Reprinted with permission from [46].

In parallel to this study, Bao et al. applied monolayer hBN films as a lateral heat spreader to cool down the hotspot structure, as shown in Figure 9a [47]. Results showed that the performance of the monolayer hBN heat spreader on the hotspot fabricated on silicon substrates was not as good as in the case of the hotspot fabricated on quartz substrates. This is because a big portion of the heat was conducted through the Si substrate due to its higher thermal conductivity than quartz. Figure 15 shows the hotspot temperature under different power densities. It can be seen that, at a heat flux of 625 W/cm2, the hotspot temperature can be reduced by 5 ◦C. When the heat flux was 1000 W/cm2, the hotspot temperature could be reduced by 8 ◦C using the hBN heat spreader.

**Figure 15.** Cooling efficiency of the monolayer hBN heat spreader. Replotted data sourced from Reference [47].

Figure 15 also shows the temperature right below the hotspot (backside of the chip) measured by infrared (IR) camera. An example of such an IR image showing the temperature distribution on the backside of the chip is shown in Figure 16b. This photo again highlights the importance of a proper design of the test structure. The non-negligible resistance of the wires connecting the hotspot resistor with the output pads results in an asymmetrical temperature distribution due to the non-negligible power dissipated in the wires. The temperature distribution can be compared to the one obtained from the improved test structure design used in the previously described experiments. For the IR image captured from the front side of the test chip shown in Figure 16a, which was redesigned with appropriate wire widths and very low power dissipation through the connecting wires, the temperature distribution on the test chip was circular symmetric, which makes it easier to compare with a symmetrical simulation model.

For comparison, a similar study was performed using few-layer hBN films obtained from liquid-phase exfoliation (LPE) [48]. In this study, suspension of 2D hBN flakes was prepared with the assistance of sonication in an aqueous surfactant solution containing ethanol. The LPE process lasted 4 h and was followed by 20 min of centrifugation to get rid of the large BN particles. Afterward, the hBN suspension was drop-coated onto the hotspot test structure and then placed on a 60 ◦C hot plate to evaporate the solvent and obtain the multilayer hBN film as a lateral heat spreader. Details of the fabrication steps can be found in Reference [48]. The results of this study are shown in Figure 17. This graph shows the hotspot temperature vs. power density for three different samples. It can be seen that the temperature decrease at the hotspot was about 3–4 ◦C at a heat flux of 1000 W/cm2—a result somewhat lower than that obtained for monolayer hBN films.

**Figure 16.** Temperature distribution across the hotspot test chip as captured by infrared camera for two different test structure designs: (**a**) new design; (**b**) old design. Reprinted with permission from Reference [46].

**Figure 17.** Bare chip hotspot temperature vs. power density by electrical and infrared measurements, as well as the hotspot temperature decrease due to the hBN heat spreader. Replotted data sourced from Reference [48].

It should be noted that there is larger variation in thermal performance between different hBN films (multilayer hBN films) as compared to variations between different monolayer hBN films. This is explained by the difficulties in maintaining the same properties between samples obtained by drop-coating of LPE hBN solutions. As shown in Reference [46], studies were also performed where the LPE hBN solution was enhanced by the addition of graphene.

#### **6. Summary and Conclusion**

A few emerging low-dimensional materials exhibit excellent thermal properties that could be used for thermal management of high-power electronics. In this paper, we reviewed a number of serpentine hotspot-producing and temperature-sensing test structures that can be used to evaluate the thermal performance of these 1D and 2D materials. The performances of both CNT-based micro heat sinks and two-dimensional films of graphene and hBN-based heat spreaders were summarized. For the CNT-based heat sink, air did not show much cooling effect, while water cooling could lower the

hotspot temperature by 50 ◦C at high heat flux densities. Furthermore, several studies using monolayer graphene and hBN as a heat spreader were summarized. The monolayer graphene heat spreader was shown to be much more efficient in spreading the heat, thereby lowering the hotspot temperature, than the monolayer hBN heat spreader. Concerning few-layer graphene heat spreaders, it was shown that their performance could be improved considerably by functionalization using APTES, which can minimize the thermal contact resistance between the chip and the heat spreader. Few-layer hBN heat spreaders were shown to have similar heat spreading performance to few-layer graphene without functionalization (~5◦C at 1000 W/cm2).

These 1D and 2D materials show great potential as heat dissipation materials in electronics. However, challenges need to be addressed before the low-dimensional materials can be pushed onto the market. For the CNT-based micro heat sink, a CNT transfer process which can be upscaled to industry level and be compatible with the current semiconductor processes needs to be approved. For graphene-based heat spreaders, the thick graphene films are more favorable than the CVD-grown mono- to few-layer graphene films from the processability perspective. Lastly, hBN-based heat spreaders are easier to integrate into electronic systems than graphene-based heat spreaders because hBN films are electrically insulating; however, the mechanical strength of the hBN films needs to be improved.

#### **Author Contributions:** Writing—original draft preparation, Y.F. and K.J.; writing—review and editing, Y.F., G.C., and K.J.

**Funding:** This work was sponsored by the Swedish Foundation for Strategic Research (SSF) under contract Nos. SE13-0061 and GMT14-0045, and from the Nano Area of Advance (Dnr: C 2017-1256) and Production Area of Advance at Chalmers University of Technology, Sweden and EU Horizon 2020 projects Smartherm (690896) and Nanosmart (SEP-210506362). This work was also supported by the National Science Foundation of China under contract No. U1537104, the Shanghai Municipal Science and Technology Commission, and the Shanghai Municipal Education Commission (Shanghai University High Education Peak Discipline Program).

**Conflicts of Interest:** The authors declare no conflicts of interest.

#### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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