*3.2. Electrical Behavior of the Capacitor in a Real Circuit*

Inserting an electronic device in a real circuit is the most appropriate approach to check its operational behavior. In particular, by monitoring the current passing through the capacitor as a function of time, two magnitudes that characterize the device can be known, such as its capacitance (*C*) and leakage current (*I*LK). These two features can be measured at the same time with a given experimental configuration, which is the load curve of the capacitor within a DC RC circuit (see Figure 4a). To extract the appropriate information, Equation (5) has been deduced, which represents the decay of the current (*I*) that the ammeter records as function of time (*t*), from a maximum current value (*I*0). As can be seen in Figure 7, and from Equation (5) also, a resistance in parallel to the capacitor has been included in such a way that this element represents the internal resistance of the capacitor itself to the current flow, which is, the leakage resistance (*R*LK). Note that this resistance is not a real element of the experimental circuit.

**Figure 7.** Theoretical RC charge circuit setup. The ideal model that simulates the electrical behavior of the capacitor (*C*) in the charging mode has been obtained by adding a parallel resistance, or leakage resistance (*R*LK), in the capacitor's branch. The intensity (*I*) flowing through the load resistance (*R*L) would be divided into two, the one that circulates through the capacitor itself (*I*C), and the one circulating through the leak resistance (*I*LK). Note that this figure is a schema because the real circuit used is the one represented in Figure 4a.

Equation (5) shows the intensity flowing through the ammeter as the sum of an intensity that decays due to the capacitance presence (*I*C), plus the capacitor leakage current, which has a constant value and acts as an offset. This magnitude varies according to the DC voltage (*V*) applied by the source and the load resistance (*R*L) of the circuit, as can be seen in Equations (6) and (7). Then, the leakage intensity is a relative property, typical of the circuit or experimental configuration, so this work is also going to account for an intrinsic feature of the capacitor, as it is the leakage resistance. Note also that this model is valid as long as *R*<sup>L</sup> is much greater than the internal resistance (*R*) of the capacitor itself, otherwise R should be taken into account as a series resistor in the capacitor's branch. The real capacitor could be thus modelled as an RC circuit (where the *R* value should be the capacitor's internal resistance and *C* the capacitance) connected to a resistor in parallel, which represents the leakage resistance. As will be demonstrated below, the internal resistance of the capacitor (*R*) has a value three orders of magnitude lower than the load resistance (*R*L), so the presence of the internal capacitor's resistance can be eliminated in the theoretical charge–discharge circuit (as shown in Figure 7).

$$I(t) = \frac{V}{R\_{\rm LK} + R\_{\rm L}} + I\_0 \mathbf{e}^{-\frac{R\_{\rm LK} + R\_{\rm L}}{R\_{\rm LK} R\_{\rm L}} \frac{1}{C} t} \tag{5}$$

$$I\_{\rm LK} = \frac{V}{R\_{\rm LK} + R\_{\rm L}} \tag{6}$$

$$I\_{\mathbb{C}}(t) = I\_0 \mathbf{e}^{-\frac{R\_{\mathbb{L}K} + R\_{\mathbb{L}}}{R\_{\mathbb{L}K}R\_{\mathbb{L}}}} \dot{\xi}^t \tag{7}$$

#### **4. Results and Discussion**

#### *4.1. Dynamic Regime Study*

Next, the analysis performed with the manufactured capacitor working under AC conditions will be explained. The data obtained from the impedance analyzer are the impedance module (|*Z*|) and the capacitor phase as a function of the applied current frequency. As can be seen in Figure 8a,b, both the single layer capacitor as well as the triple layer capacitor show a decay of the impedance module until reaching the resonance frequency, which is located around 2.9 × 107 Hz for the single-layered capacitor, and around 1.7 × <sup>10</sup><sup>7</sup> Hz for the triple-layered capacitor. Being capacitive electronic components, the output signal of this type of devices has a phase shift of −90◦ with respect to the input current. However, once the resonance frequency has been exceeded (in which the imaginary part of the impedance is canceled), this value changes to positive 90◦, becoming in an inductive element. This pattern can be clearly seen in Figure 8a,b.

$$|Z| = \sqrt{R^2 + \left(\frac{1}{2\pi v \mathcal{C}}\right)^2} \tag{8}$$

Despite that the phase of the manufactured devices does not remain constant at −90◦ throughout the frequency range analyzed, it remains close to this value within the low frequency range, confirming that manufactured devices behave as capacitors in this region. In fact, this work places special emphasis on the electrical behavior at a low frequency, as its application for electrostatic energy storage requires the use of low frequency input signals. Following this approach, it is considered that, at low frequency, the capacitor can be analyzed as a pure RC circuit. The data of the impedance module as a function of the frequency (*υ*) have been fitted to Equation (8), in such way that *R* represents the internal resistance of the device and *C* its capacitance. Note that all the fittings shown below have been made by least squares, offering a minimum value for *R*<sup>2</sup> of 0.999, while fitting uncertainties have been calculated with a 95% confidence level. In Figure 8c,d, it is possible to see how, between 40 and 1000 Hz, the electrical behavior of the manufactured capacitors are similar to an RC circuit, because fittings exactly represent the experimental data. *R* and *C* values have been extracted from the fitting for each type of capacitor, as shown in Table 6.

**Figure 8.** Module of impedance (|*Z*|) and phase curves as a function of frequency for the single dielectric layer (**a**) and triple dielectric layer (**b**) capacitors. Below, the impedance module data limited to the low-frequency range (from 40 up to 1000 Hz) and its fittings for the single dielectric layer (**c**) and triple dielectric layer capacitor (**d**), respectively, are represented.

By considering that *R* is the internal resistance of the capacitor and taking into account that it reaches values between 2.3 and 3.9 kΩ, they are of in the order of 1000 smaller than the 2 MΩ for the load resistance. In this way, the condition imposed in the mathematical framework section is fulfilled in order to apply Equation (5) to the charge curves.

**Table 6.** Main features obtained from low frequency impedance fitting curves of the manufactured capacitors.


#### *4.2. Static Regime Study*

After an analysis of the capacitor's properties under an AC input current, another test performed is reported, this time applying an input current DC through the devices. In particular, the charge– discharge cycles have been analyzed on a test circuit (see Figure 4) where the super-ENC prototypes have been placed, obtaining the intensity signal for the capacitor's branch as a function of time. The typical signal of the charge–discharge cycles in circuits including this type of electrostatic capacitors has two main characteristics; namely, the intensity decays are symmetrical with respect to the time axis, and the curves have different signs. The symmetry is due to the fact that *R*<sup>L</sup> and *R*<sup>D</sup> have the same value, and the sign differences are caused by the polarity of the capacitor's branch, which is inverted depending on whether it is in charge mode or in discharge mode. In this work, these conditions are met because *R*<sup>L</sup> and *R*<sup>D</sup> have a value of 2 MΩ, however, as can be seen in Figure 9, the measured signals

have a particularity because the charge cycles appear elevated by a constant value with respect to the 0. This offset is of special interest as it accounts for the leakage current of the capacitor (represented by a red line).

**Figure 9.** Several charge and discharge cycles for the triple dielectric layer capacitor, representing the intensity (*I*) flowing through the ammeter of the circuit as a function of time (*t*). An offset current (red dashed line) can be observed for charge cycles, revealing the leakage current of the capacitor.

By applying Equation (5) to the load cycle, not only *C* can be estimated, but also both *I*LK and *R*LK can be determined. To improve the quality of the fitting as well as the statistics of the experiment, the signal of three consecutive loads is accumulated in order to fit a curve that contains triple the number of points. As can be seen in Figure 10, the proposed model is fitted to the experimental results, which is shown in Table 7. It should be noted that for the single dielectric layer capacitor, it was not possible to detect the presence of leakage current, being, in the existing case, below 50 nA, which is the minimum resolution of the experiment.

**Figure 10.** Intensity (*I*) decays in charge cycle for single dielectric layer (**a**) and triple dielectric layer (**b**) capacitors as a function of time (*t*). Its fittings to Equation (5) are also shown.


**Table 7.** Mean results obtained by applying Equation (5) to the charge cycle intensity decays.

## *4.3. Breakdown Voltage Test*

Finally, the maximum voltage value to which the device can operate was tested. For this, the device is placed in the circuit of Figure 5 and the intensity shown by the ammeter is recorded as a function of the applied voltage. The triple dielectric layer capacitor (SiO2/TiO2/SiO2) exhibited a breakdown voltage of 14 ± 1 V, while the single dielectric layer capacitor (Al2O3) has reached a higher value at 63 ± 1 V. In Figure 11, the voltage ranges at which the capacitors lose their insulating properties and become conductors appear highlighted, as they are indicated by an arrow. It is clear that the multi-layered dielectric SiO2/TiO2/SiO2 is not reaching the insulating features that it was supposed display. On the one hand, it exhibits leakage currents and on the other hand, it has a lower breaking voltage than the Al2O3 capacitor. As no inhomogeneities have been detected in the triple dielectric layer of SiO2/TiO2/SiO2 ALD deposited material, the main causes of this decrease in performance may be other reasons. For example, a higher ALD process temperature for SiO2 causes breaking voltage decreasing [34]. It can also be because of the combination of thin films depositions of different oxides, which may form a new alloyed material that leads to a band-gap reduction with respect to the corresponding ones of SiO2 and TiO2 [35]. In such a way, an a priori insulating material becomes a semiconductor material and, consequently, it could not perform as a dielectric medium.

**Figure 11.** Breakdown current–voltage curves for the single dielectric layer (red) and three-layered (blue) capacitors. Representing the intensity (*I*) recorded by the ammeter (Figure 5) as a function of the applied voltage, it is possible to find the breakdown values, which are indicated by an arrow.

#### **5. Conclusions**

This work has faced the development of electrostatic capacitors and its enhanced possibilities by using nanomaterials, in this way covering the full manufacturing and characterization process of these energy storage devices. An innovative fabrication method has been proposed and achieved, based on the successive combination of an ultrathin layered nanomaterial for the conformation of the dielectric medium of the capacitors. Likewise, an experimental procedure has been followed for the complete characterization of these devices, consisting of three phases, from which the intrinsic magnitudes that completely characterize a capacitor can be measured, such as internal resistance, leakage resistance, capacitance, and breakdown voltage. The test of the manufactured devices in a real circuit, including a model to explain their electrical behavior, which is the main novelty of this study, has obtained experimental results confirming the validity of such a model.

It has been found that the Al2O3 single-dielectric layer capacitors of 9 nm in thickness have been shown to exhibit a better performance than the triple dielectric layer capacitors composed of SiO2/TiO2/SiO2 sheets, each 3 nm in thickness. In particular, single dielectric layer capacitors have less internal resistance (2.3 kΩ), so they are more favorable for storage applications because of a consequent lower power consumption. Al2O3 single-layered capacitors also offer a higher capacitance in dynamic regime (41.6 nF) than those of triple-layered SiO2/TiO2/SiO2. Furthermore, the former display leakage current is lower than 50 nA, so it guarantees that the current losses will be minimal. The main advantage shown by these capacitors is the high value of breakdown voltage (63 V), as a higher working voltage greatly improves the storage capacity of electrical energy of these devices. Only the static regime of capacitance for triple dielectric layer capacitors (93 nF) is higher than that of the single dielectric layer devices (54 nF). However, taking into account all the features in which the Al2O3 capacitors offer better performance, a single property is not enough to affirm that SiO2/TiO2/SiO2 devices have better characteristics.

Nevertheless, the capacitance values derived from our electrostatic supercapacitor prototype are not as high as expected. The values obtained are coherent with the performed analysis, as both the dynamic and the static procedures yield values of the same order of magnitude (nF). However, they are far from the expected capacitance values in the μF range theoretically predicted for these kind of devices, so certain aspects of the manufacture of the supercapacitor devices should be further reconsidered. A feasible explanation on the discrepancies between the expected values of capacities and the experimentally measured ones is that the AZO layer is not properly fulfilling its function as electrode material, for either of two reasons. The first one is that the contact to the AZO layer with silver paint would not be appropriate and thus there is no electron transfer between the AZO layer and the conductive silver paint. The second reason would be that the AZO layer itself is a semiconducting material, and hence it is not able to efficiently conduct the electrical current along the channels of the pores. In addition, the design of the electrical connections of the device becomes critical, because current leakages and short circuits between the electrodes need to be avoided. For example, leakage currents may be decreased in the case of triple layer capacitors, whether or not it can be guaranteed that the electrodes are completely isolated to achieve the most desirable device performance.

There are, therefore, two ways of improving the super-ENCs' capacitance. On the one hand, the substitution of the AZO layer by using a better conductive material that fits the cylindrical morphology of the pores, such as carbon nanotubes, thus taking advantage of the internal surface of the NAAM to increase the capacitance of the devices. On the other hand, the use of more refined techniques to contact the electrodes, such as wire bonding, would allow precise delimitation of the contact zones, avoiding regions in which short circuits could occur, thus reducing the presence of leakage currents. These advances would significantly improve the performance of the manufactured prototypes that, according to the reported results, could become in very promising energy storage devices. In fact, the super-ENCs are suitable complements for the batteries of electrical systems such as vehicles or electricity supply domestic networks. Besides having a high energy density and faster response under a specific power demand, they also present an environmentally sustainable alternative to the current polluting energy supply systems.

**Author Contributions:** Conceptualization, A.S.G. and V.M.d.l.P.; Funding Acquisition: V.M.d.l.P. and V.V.; Investigation, L.J.F.-M., A.S.G., and V.V.; Writing—Original Draft Preparation, L.J.F.-M. and A.S.G.; Writing—Review & Editing, A.S.G., V.M.d.l.P., L.J.F.-M., and V.V.; Supervision, V.M.d.l.P.

**Funding:** This work was funded by the Ministerio de Economía y Competitividad (Spain) under grant MINECO-17-MAT2016-76824-C3-3-R, and IDEPA-ArcelorMittal Proof of Concept grant No RIS3-2015: SV-PA-15-RIS3-2.

**Acknowledgments:** Funding by Spanish MINECO under grant No MAT2016-76824-C3-3-R is gratefully recognized. The scientific support from the SCTs of the University of Oviedo is acknowledged. Helpful assistance within the electrical measurements provided by the group of Sistemas Electrónicos de Alimentación (SEA) led by J. Sebastián Zuñiga from the University of Oviedo is also gratefully recognized. This work is devoted to the memory of our colleague and friend J. Miguel Mesquita Teixeira.

**Conflicts of Interest:** The authors declare no conflict of interest.

## **References**


© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
