*2.2. ALD Performance*

One of the foremost features of thermal ALD is that it is mainly limited to the deposition of oxides, so the deposition of a uniform metallic thin film electrode cannot be easily performed [28]. However, it is possible to achieve a semiconductor oxide material layer performance, capable of constituting the electrode material. Then the use of (1:20) aluminum-doped zinc oxide (AZO) is proposed, because its effectiveness as a semiconductor has already been demonstrated for applications in super-ENCs [29], and its deposition performance by ALD has been widely studied [4,29–31].

The ALD process is carried out in a Savannah 100 thermal ALD reactor equipment from Cambridge Nanotech (Waltham, MA, USA), on exposure mode [11], using an Ar flow of 50 sccm as carrier and purge gas. As previously reported [11], a minimum exposure time of 20 s ensures that the precursor gas diffuses properly throughout the substrate, so that the material can be deposited evenly along the entire length of the pores. The number of ALD cycles for each material has been calculated according to the deposition rates shown in Table 2. For example, in the case of the Al2O3 dielectric layer, 80 ALD cycles were performed in order to obtain a layer thickness of around 9 nm. The successive layers of material are deposited on the NAAMs sequentially, beginning with the bottom electrode (BE), then the dielectric material, and ending with the top electrode (TE). The method composed by 20 cycles of diethyl zinc (DEZ) intercalated with 1 cycle of trimethyl aluminum (TMA) [4], is used to achieve ZnO doped with Al atoms. This pulse sequence results in an Al doping level of around 3%, which is the optimum that minimizes the resistivity of AZO layers [29]. Thus, the resulting material (AZO) has semiconductor properties and is used as the electrode material in the conductor/dielectric/conductor (CDC) structure of the capacitors, both in the BE and in the TE with a thickness of 6 nm (see Table 2). As already mentioned in the introduction, capacitors have been manufactured employing two different

dielectric materials. On the one hand, a single layer of alumina with total thickness of 9 nm, and on the other hand, the multilayered combination of SiO2/TiO2/SiO2, in which each layer provides a thickness of 3 nm (see Table 2), again making a total thickness of 9 nm. During the deposition of each material, at least two kind of precursors have been used, with the first of them corresponding to the compound containing the metal, and the other H2O, which is responsible of the substrate functionalization. For the deposition of SiO2, it is also necessary to use an O3 precursor, in order to improve the functionalization performed by H2O.

**Table 2.** The different deposited materials are listed, indicating the average deposition rate of each material deposited per atomic layer deposition (ALD) cycle, the chamber temperature during the cycles, the precursor used, as well as the estimated layer thickness for each material. The deposition rates for aluminum-doped zinc oxide (AZO) and alumina have been extracted from the work of [4], while those values for TiO2 and SiO2 are obtained from the works of [32,33], respectively. BE—bottom electrode; TE—top electrode.


Each precursor used has its own pulse (*t*1), exposure (*t*2), and purge (*t*3) time, as shown in Table 3. Long exposure (*t*2) and purged (*t*3) times have been employed, in order to assure that the gaseous precursors have enough time to diffuse into the deep pores.

**Table 3.** Timing for ALD processes, with *t*<sup>1</sup> being the precursor pulse time, *t*<sup>2</sup> the exposition time, and *t*<sup>3</sup> the purge lapse. For each material, the exposure times used for each precursor are shown by columns. Note that the precursors and times for Al2O3 are similar, either used for the conformation of AZO or for the Al2O3 dielectric material itself.


In order to ensure the successful deposition of the different layers for the C/D/C capacitor structure, SEM images of the membrane surface have been taken after every deposition step. This characterization allows estimating the thickness of the deposited material attending to the reduction in pores diameter after the placement of each one of the layers that form the capacitor, as can be seen in Figure 2a,c,e. From these images, the homogeneity of the deposited layers can also be appreciated. SEM images have been combined with the EDX technique to study the homogeneity of the materials deposited along the entire pore shape, specifically, for the triple dielectric layer capacitor, as shown in Figure 2b,d,f.

**Figure 2.** Visualization by scanning electron microscope (SEM) image of the reduction in pores diameter as the layers that make up the capacitor are successively deposited, overlapping one above the other. The left column represents the different stages of the conformation for the single layer capacitor, being (**a**) the micrograph made after the deposition of the BE; (**c**) the one taken after the placement of the Al2O3 over the BE; and (**e**) the one that shows the membrane after the deposition of the BE, the Al2O3, and the TE. Likewise, the column on the right shows the three similar steps for the triple layer capacitor, being (**b**) the one corresponding to the BE deposition, (**d**) the one corresponding to the triple layer SiO2/TiO2/SiO2 deposited over the BE, and (**f**) the one showing the whole BE-SiO2/TiO2/SiO2-TE capacitor structure completely deposited. Note the yellow scale bar of 500 nm for all images.

As can be seen in Figure 3, the depth profiles for Al (blue trace), Si (red), and Ti (green) remain stable, indicating that a uniform coating along the whole pores size has been carried out.

**Figure 3.** SEM image of the cross section for the NAAM with the deposited triple dielectric layer capacitor. On the left side, the substrate of Al can be seen, while on the right side, the NAAM surface appears where the pores are opened. EDX analysis has been carried out along the yellow segment, indicating the presence of different elements through it. The blue line corresponds to Al, while the red and green ones correspond to Si and Ti, respectively.

Using ImageJ software (version 1.52a, National Institutes of Health, Bethesda, MD, USA), the reduction in pore diameter has been calculated from the SEM surface images, and the results are shown in Table 4. Taking into account the starting diameter of 65 nm and the thickness values shown in Table 2, the pore diameter is expected to be around of 53 nm after the deposition of the BE, 35 nm after the dielectric material conformation, and 23 nm after deposition of the TE. The experimental data obtained for the reduction in pore diameter are in good agreement with expectations, so that the respective layers forming the capacitor have the appropriate thicknesses.

**Table 4.** Average pore diameters after deposition of the different layers, either BE, dielectric, or TE. Data have been obtained from the analysis of scanning electron microscope (SEM) images with ImageJ software.

