**3. Common Mode Voltage**

The inverter common mode voltage is calculated by averaging the output voltage (*VA*, *VB*, and *VC*) of each leg as follows [38]:

$$V\_{CM} = \frac{V\_A + V\_B + V\_C}{3} \tag{7}$$

For the three-phase two-level inverter, the achievable phase output voltage levels could be *–VDC*/2 or +*VDC*/2 where *VDC* is input voltage. If the voltage at the DC link is zero then only the common mode voltage is zero. For the three-level inverter, the achievable phase output voltage levels could be

positive, negative, and neutral point voltage. Tables 1 and 2 tabulated the output vectors and possible common mode voltages for two-level and three-level inverters, respectively.


**Table 1.** Output vectors and common-mode voltages for two-level inverter.

**Table 2.** Output vectors and common-mode voltages for three-level NPC inverter.


### *3.1. Filtering of Common Mode Voltage*

The appropriate designed filter circuitry is needed to reduce the common mode voltage. The complete three-phase to grid (AC–DC–AC) system with the connection of a passive filter is shown in Figure 4. The DC link with voltage *VD* is created between the AC–DC and DC–AC converter and passive filters are added at the input and output side. The filter consists of damping resistance, Y-connected capacitor and common mode chokes. In the given system, a damping resistor *RCM2* is connected between grid and neutral point capacitor. Additionally, two chokes, *LCM*1 and L*CM*2, and three Y-connected capacitors, *CCM*2, are connected for filter purposes [12–14]. *RCM*1 and *CCM*1 are connected between the grid and negative terminal of the DC link. The range of the resonant frequency for the common mode circuitry is about 1.5 kHz [7] and is calculated as follows:

$$f\_o = 1/\left(2\pi\sqrt{L\_{CM} \times C\_{CM}}\right) \tag{8}$$

where *LCM* and *CCM* are the equivalent inductance and capacitance values. The practical limitation of the real-time application needs to be considered while designing the capacitors. The capacitor size should be small for the designed frequency in order to reduce the bulkiness of the hardware unit.

**Figure 4.** Complete three-phase to grid (AC–DC–AC) system with the connection of a passive filter.

#### *3.2. Comparison of SPWM and Space Vector PWM Techniques for a Two-Level Inverter at a Higher Switching Frequency*

The simple open-loop analysis is carried out for a two-level inverter for current and voltage distortions both with and without a filter. For the analysis, the modulation index is maintained at 0.8 and taken over a range of frequencies between 1 kHz and 150 kHz and the obtained results are tabulated in Table 3. After comparing SPWM and SVPWM results, it is known that SVPWM provides superior results for two-level inverter system. For reduction in CMV, the SVPWM technique provides the best results; however, due to tedious calculations, the requirement of high-end processors and complex hardware implementation, space vector modulation can be replaced with the carrier-based modulation strategy which will give the same results as that of the space vector modulation technique. If the reduction in the CMC can be achieved by using such a modulation strategy, the size of the common mode choke can be reduced.


