**4. Modified PWM Schemes**

Among discussed PWM schemes, SVPWM provides quality results [30]. Nevertheless, due to some inherent disadvantages, the space vector modulation strategy is ruled out from the agenda. Thus. the next challenge was to obtain similar results, which were given by the space vector modulation, in carrier-based modulation as well. The modified carrier phase shift scheme is developed based on the concept of phase disposition PWM scheme. It is given that the input voltage is balanced and the possible two conditions are:


$$V\_A + V\_B + V\_C = 1\tag{9}$$

It is considered that 0 < *VA*, 0 > *VB*, and 0 > *VC* and CMV are caused with the peak value to reach a higher voltage level than 1/6 × V*DC*. The carrier signals and output voltage reference relation for the switching 0–1–1 is as follows:

**Figure 5.** Waveform associated with PWM strategies (**a**) PDPWM method, max amplitude of the addition of the carrier waves is 2, (**b**) modified PWM method, max. amplitude of the addition of the carrier waves is around 1.5.

As phase disposition PWM (PDPWM) is used, at any point of time:

$$\begin{cases} \text{for the state } '0 - 1 - 1' \left\{ \begin{array}{c} V\_{\text{CarrierA}} - V\_{\text{CarrierB}} = 1 \\ 3 \times V\_{\text{CarrierA}} - 2 > 0 \end{array} \right. \end{cases} \tag{10}$$

Hence, to avoid this state,3 × *VCarrierA* − 2 < 0, this condition is to be satisfied. This is done by using three carrier waves, which are 120◦ apart from each other. Figure 5 shows the waveform associated with PWM strategies. Figure 5a depicts the associated waveform of the PDPWM method where the max amplitude of the addition of the carrier waves is 2 (see amplitude in (3) in Figure 5a). Figure 5b depicts the associated waveform of the modified PWM method where the max amplitude of the addition of the carrier waves is around 1.5 (see amplitude in (4) in Figure 5b).

### **5. Simulation and Experimental Results**

The simulation results are presented for the complete AC–DC–AC system. The circuit-level model was developed using the Simulink platform. The closed-loop analysis of both two-level and three-level inverters is carried out. The specifications of the system parameters are given in Appendix A.

### *5.1. Closed-Loop Analysis of the Two-Level Inverter*

The model of the system is done in various stages. Figure 6 shows the complete closed-loop AC–DC–AC system Simulink model with the two-level inverter. The first section includes the diode rectifier model to obtain a constant DC voltage. Then the DC link capacitor was designed so as to provide a constant DC input voltage to the three-phase two-level inverter circuit which is modelled using Insulated Gate Bipolar Transistor (IGBTs) and SVPWM techniques were implemented for firing the inverter circuit.

The analysis of CMV and CMC for the given system is done without filter implementation and the achieved results are depicted in Figure 7a–d. The Fast Fourier Transform(FFT) analysis of the CMV and CMC waveform (150 kHz component) are done without filter, and it is observed that THD of the CMV and CMC is 38.01% and 3152.31%, respectively. The analysis of the common mode voltage and current for the given system are done with a filter implementation and the achieved results are depicted in Figure 7e–h. The FFT analysis of the CMV and CMC waveform (150 kHz component) are done with a filter and it is observed that the THD of the CMV and CMC is 73.39% and 2213.58%, respectively.

**Figure 7.** *Cont.*

**Figure 7.** Simulation results: (**a**) CMV without filter; (**b**) CMC without filter; (**c**) without filter, common mode voltage FFT analysis; (**d**) without filter, common mode current FFT analysis; (**e**) CMV with filter; (**f**) CMC with filter; (**g**) with filter, common mode voltage FFT analysis; (**h**) with filter, common mode current FFT analysis.

From the investigation, the objective of reducing the CMC and CMV of the two-level inverter is achieved. From the analysis made, it can be concluded that when the two-level inverter is operating at a frequency above 10 kHz, the EMI increases drastically. Additionally, the CMV and CMC of the system cannot be reduced effectively by changing the reference, instead the size of the EMI filters have to be larger. Therefore, we need to consider the three-level inverter analysis.

### *5.2. Closed-Loop Analysis of the Three-Level Inverter*

Based on the earlier explanation, the Simulink model of the three-level NPC system is designed in MATLAB. Figure 8 shows the Simulink model of the designed three-level NPC system.
