*4.1. CHIL Platform of Microgrid*

In order to test the effectiveness of the proposed ancillary service on real processor, a CHIL platform is built on the basis of a real-time controller dSPACE [38] and a real-time simulator Typhoon HIL [39]. Figure 11 illustrates the general construction of the micro grid. The complete PV control is implemented by the real embedded system while the rest of the system including the model and other control units are simulated in real-time by the simulator.

**Figure 11.** CHIL simulation structure of the microgrid.

#### 4.1.1. Real-Time Microgrid

To reduce the total computation burden and to make a better usage of the hardware resources, the model is subdivided into two parts considering the PV system in one core and the rest in another using an ideal transformer model (ITM) as the interface algorithm [40]. The ITM is placed in the LCL output filter of the PV inverter (Figure 12). The single-line diagram then is used to clarify the description. A voltage amplified ITM is placed within the PV inverter at the primary side and the grid at the secondary side. The stability of the system is affected by the value of the impedances on

both sides of ITM as shown in [41]. Therefore, more attention needs to be paid while setting the ITM parameters. After circuit partition, the computation burden is greatly reduced from 145 % by one core to 25 % and 3 % respectively by two cores.

**Figure 12.** Equivalent circuit of the partitioned LCL filter used in the Real-time simulation.

The fundamental time step is defined as 1 μs, which is the reference clock to synchronize all parts of the system as well. In the micro grid, the SG is the only source of natural inertia; furthermore, since the proposed approach handles the reactive power flow from the PV plant to mitigate the frequency transients, the system's response has to be faster than the excitation system of the SG. The electrical part of the machine is modeled by a fifth-order state-space model in a synchronously rotating d-q coordinates; the mechanical part is modeled by a second-order state-space model [42]. The execution rate of the simulation of the synchronous generation system is defined as 5 kHz and the parameters are listed in Tables 3–5.

The PV plant is composed of DC side voltage source (PV panels), 3-phase inverter and LCL filter. The state-space variables are calculated at every fundamental step. The inverter gate driving signals are calculated at 1 MHz and therefore, they are generated with an oversampling frequency of 50 MHz, guaranteeing high fidelity of the pulsed signals even under fast switching and narrow duty cycle conditions. The features of the PV plant are listed in Table 6.

The loads and transmission lines are simulated at 1 MHz. The loads consist of a permanent 175.8 kW–6.1 kvar load and an optional 27 kW–1.4 kvar load which creates the frequency transients by connection and disconnection actions. For transmission the equivalent three phase RL modeled overhead lines are used. The related parameters are shown in Table 8. The synchronous generation system, PV system and the loads are joined at the PCC via transmission lines of 100 m, 100 m and 300 m respectively.

#### 4.1.2. Interface and Real-Time Control

As previously mentioned, the PV control algorithm is executed by an embedded system in real-time out of the grid simulator, so an interface is required to join these two devices both physically and logically. The inputs of the control are voltages and currents measured at the PCC and the outputs of the control are the driving signals for the PV inverter. In real implementation, the voltages and currents are firstly measured and transformed by transducers. Before being sent to the controller, these analog signals are normally amplified or attenuated and filtered by conditioning circuits and finally converted into digital signals. On the other hand, the generated gate driving signals are sent to the driving circuit of the inverter where the non-ideal switching of the semiconductors takes place. Aiming at replicating the impact of the sampling devices, a software interface is created inside the real-time simulator, as it is illustrated in Figure 13. The PCC variables are firstly sampled by the maximum rate available in the model, i.e., 1 MHz to avoid aliasing issues. Then the samples go through a set of 1st-order low pass filters (LPFs) and absolute time delays which are executed at 50 kHz, to represent the limited bandwidth, anti-aliasing handling and response time of the measurement system. After the functional part, the physical connection is achieved by the analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and digital inputs/outputs (DI/Os) of the two real-time devices. The conditioned PCC variables are amplified by DACs at 1 MHz. Compared with the receiver ADCs at controller side (10 kHz), the PCC variables are quasi-continuous. The modulation wave generated

by the control algorithm at 10 kHz is then transformed into pulses by a slave dsp whose resolution is 100 ns. And finally the pulses are over-sampled by 50 MHz closely tracking the expected duty cycle.

The control algorithm follows the block diagram shown in Figure 5. The switching frequency is set at 20 kHz. With 100 ns resolution of the carrier signal, the output's duty cycle will have a resolution of 0.2 %. The reading commands of ADCs and the updating of the modulation wave are arranged at the beginning of the code. To a large extent, this fixes the time baseline when the variables are taken and sent within a control period, which avoids the unexpected high frequency harmonics caused by the embedded system, but introduces one-step delay to the actual control at the same time.

**Figure 13.** CHIL interfacing method.
