*2.3. Parallelization of the Model Code*

The HDM and STM can both be well parallelized. In the code of the model, the computation of one time step was implemented as a number of loops. Among these loops, the parallelizable ones were parallelized using loop-based parallelization and the open multiprocessing technique (OpenMP). In this study, a 16-core processor (Intel Xeon E5-2697a v4) and Intel C++ 14.0 formed the hardware and software environment. The runtime speedup, used as an indicator of how much faster the parallel code is than the sequential code, is defined by

$$Sp = T\_1 / T\_{nc} \tag{12}$$

where *Sp* = speedup of a parallel run relative to a sequential run; *T*1 = runtime of a sequential run using one working core; *Tnc* = runtime of a parallel run using *nc* working cores.
