*Article* **The P-Type Module with Virtual DC Links to Increase Levels in Multilevel Inverters**

#### **Emad Samadaei 1,\*, Mohammad Kaviani 2, Mina Iranian <sup>3</sup> and Edris Pouresmaeil 4,\***


Received: 11 October 2019; Accepted: 20 November 2019; Published: 2 December 2019

**Abstract:** There has been an active interest in the evolution of newer multilevel inverter topologies in which the highest operation of DC sources become an important subject. In the paper, a new structure module presented a seventeen levels asymmetrical multilevel inverter by using two unequal DC sources (with the ratio 3:1). The configuration was focused on creating virtual DC links by two chargeable capacitors. The module had a simple inherent charging for capacitors without any additional circuit. The proposed multilevel inverter could produce higher voltage levels by a lower number of components; therefore, it is suitable for a wide range of applications. Also, the cascade connection of the module led to a modular topology with more voltage levels at higher voltages. The capability of the inherent negative voltage was involved. The simulation results obtained in MATLAB/Simulink, as well as the experimental results, verified the proposed topology.

**Keywords:** asymmetric; capacitors; multilevel inverter; power electronics; self-charging; virtual DC links

#### **1. Introduction**

Multilevel inverters (MLIs) have obtained more attention in recent years against two-level inverters because of their abilities in medium to high power applications, such as wind turbine [1], HVDC (High Voltage Direct Current) for transmission line [2,3], photovoltaic systems [4], drives systems [5,6], active power filer [7], power grid [8], and electrical vehicle [9]. MLIs synthesize the desired stepped output waveform from several DC voltage sources by the proper arrangement of the semiconductor switches. One of the important advantages of MLIs is using fewer components to create higher levels of the output voltage. Besides increasing the number of output voltage levels, high resolution on the output voltage and low harmonic components will be expected. Also, scalability, modularity, and lower switches stress are some of the other MLIs outstanding features due to the ability of cascade connection. Various topologies are introduced for MLIs. They can be categorized in three main types: NPC (Neutral Point Clamps) [10], FC (Flying Capacitor) [11], CHB (Cascade H-Bridge) [12]. Some disadvantages in NPC and FC, such as bulky capacitors, unbalanced DC links, and high switch stress, make CHB topologies more interesting. CHB has some comparable aspects: the number of semiconductors and DC sources and levels; total standing voltage (TSV) on switches; the inherent polarity levels, etc. Some conventional and vanguard topologies for the last decade were investigated in [13–16]. In [17], the module generated each level from one DC source by two switches. A series connection of the module can create more levels. The module can only generate positive polarity, and it requires an extra circuit for negative polarity. Full-bridge was added to the series module in [18]

to create both negative and positive levels. By adding full-bridge circuits, negative voltage polarity is generated by the penalty of high switching stress on the semiconductors in the additional circuit and increasing the number of components. The enhancement of multilevel inverters' performances depends on creating higher output voltage levels by using a lower number of switches and DC voltage sources. Recently, asymmetric multilevel inverters with unequal DC sources have been addressed to increase the output levels without any complexity to the power circuit. Modules are designed based on the optimal combination of DC links and semiconductors. On another side, unequal DC links in asymmetric multilevel inverters may influence the stress on switches. The stress on switches is indexed with total standing voltage (TSV), which is the sum of the highest voltage stress on each switch. In [19,20], crossing switches were introduced as a solution to dividing of stress on switches and generating more levels. [21,22] presented extended H-bridge with different amounts of DC links. As the number of voltage levels increases, H-bridge switches tolerate higher stress. So, these topologies need higher rate semiconductors. Another kind of MLIs was proposed in [23] that is well-known as hybrid type topologies, although stress on switches is still obvious. Using full-bridge for negative voltages increases stress on switching and total standing voltages (TSV) on semiconductors. [24,25] introduced modules with inherent negative levels based on the maximum levels of achievement with four DC sources and low semiconductors to overcome these disadvantages. Different energy sources or storage elements, such as capacitors, can be applied instead of some DC sources to form a sinusoidal waveform in various multilevel inverter structures [26]. As a result, output voltage levels are increased with the same number of DC sources. [27–29] redesigned the structure of [11,19] to replace capacitors with some DC sources. In order to decrease the number of sources, [30–33] used a single source. In these configurations, they needed more semiconductors for the charging/discharging of capacitors. Some stair modular configurations with diverse DC sources and capacitors were proposed in [34–36], although full-bridge was applied in the circuits for producing the negative levels.

In the proposed inverter module, a new arrangement of semiconductors was introduced, which used only two DC sources. Two DC sources were unequal with 1xVDC and 3xVDC (one/three times scale of base voltage, respectively). The proposed inverter generated 17 output voltage levels. On the other hand, the proposed asymmetric multilevel module could produce eight positive levels, eight negative levels, and zero level (total 17 levels). Also, it did not need any extra circuit (such as a full-bridge) for negative voltage levels. The cascade connections of the module were described to create more levels for high voltage applications. The proposed multilevel inverter was illustrated in Section 2. Module introduction, switching patterns, charging and discharging of capacitors, cascade connection, and comparison study were included in this section. In Section 3, the nearest level control (NLC) scheme as a switching modulation was described. The voltage ripple on capacitors was investigated in Section 4. Finally, simulation and experimental results were presented in Sections 5 and 6, respectively.

#### **2. Proposed Module**

Figure 1 illustrates a general concept diagram of the proposed multilevel inverter with two DC sources. In order to achieve maximum output levels from sources, capacitors could be added to the configurations. Some extra DC links were created by capacitors to get more levels with the same DC sources. As shown in Figure 1, two DC sources with ratio 3:1 (VDC1 = 3VDC2) could create nine voltage levels; and it could be redesigned with two capacitors and suitable arrangements to create seventeen voltage levels in output. The charging paths of capacitors should be considered as well. The charging paths of capacitors could be provided by a suitable designing of semiconductors arrangement to achieve the output levels paths without using an additional circuit.

**Figure 1.** The general concept diagram of the proposed multilevel inverter (MLI) with capacitors.

#### *2.1. Module Configuration*

Asymmetric multilevel inverters could produce a different number of output voltage levels by using a fewer number of semiconductors in which it caused lower harmonic components as well. This promotion could be achieved by using two DC sources with different amounts as 1xVDC and 3xVDC. It means the amount of one source was three times greater than the other one, and they were rewritten as 1VDC and 3VDC to simplify for the rest of the paper. In order to increase the number of DC links without any change in the number of DC sources, capacitors could be used. This idea gave four DC links involving 2 DC sources and 2 capacitors. Figure 2 shows the proposed module with a new arrangement of the components that contained 18 switches (8 unidirectional switches and 5 bidirectional switches) and 18 diodes in combination with 2 unequal DC sources and 2 capacitors. This configuration produced 17 levels of voltage at the output, including eight positive levels, eight negative levels, and zero level. This means that this module had an inherent negative level ability by connecting each DC link to other ones through different paths from different sides of a DC link. The structure of the proposed topology was figured to polygon, so it is named "P-Type" (Polygon-Type). The proper designing of the proposed module made that DC source with 1VDC to charge the capacitor with 1VDC, and DC source with 3VDC to charge the capacitor with 3VDC without any additional circuit. Figure 3 draws the switching paths of all output voltage levels in the presented structure, and the state of switches in each level is listed in Table 1. The proposed module and their switching paths were designed accurately, as well as the positive terminals of DC links were not connected to the anode of diodes to cause the shortcuts. On the other hand, it was protected from short currents in which Figure 3 shows that the switching paths did not form any closed loop for DC links. Thus, diodes and bidirectional switches guaranteed that short-circuiting would not occur in the module.

**Figure 2.** The proposed module (P-Type, Polygon-Type) for the multilevel inverter.

**Figure 3.** The switching paths of the proposed module.


**Table 1.** Sweating table.

Table 1 shows the on and off states of the switches at each level. It was clear that some pair switches could not be turned on simultaneously, such as (S1, S9); otherwise, the short circuit on DC sources was expectable. Additionally, the number of turning on per one cycle for each switch is shown in Table 1. As can be seen in the last row of Table 1, all switches had low operation frequency. In order to show this fact, S2 and S9 were selected as the switches with the lowest and highest number of turning on in one cycle to calculate the operation frequency. According to Table 1, S2 and S9 would be turning on 2 and 7 times in one cycle, respectively. By considering the fundamental frequency as 50 Hz, the operation frequency of a microprocessor for 32 steps would be calculated 1600 Hz. However, the operation frequency of S2 and S9 in one cycle was 100 Hz and 350 Hz, respectively. It was clear that these switches worked even lower than the overall microprocessor frequency (1600 Hz). It proved that all switches in the proposed module tolerated low-frequency stress.

Schematic output voltage levels associated with different switching states of the proposed module in one cycle are illustrated in Figure 4. Figure 4 also shows the schedule of the DC sources and capacitors, which were used for each level. Consequently, the proposed multilevel inverters, along with two unequal DC sources, could create 17-levels.

**Figure 4.** Switching pattern/schedule of DC links for the proposed inverter in one-cycle.

This module did not require any additional circuit to charge capacitors. According to Figure 4, capacitors were charged at level "zero". The module was designed based on the charging paths consisting of two loops for the charging of DC links that are shown in Figure 5. DC source with 1VDC was charging 1Vc (Figure 5a), and DC source with 3VDC was charging 3Vc (Figure 5b).

**Figure 5.** The charging paths of capacitors in the P-Type module, (**a**) charging for 1Vc; (**b**) charging for 3Vc.

Table 2 shows the equations of the module. The number of the semiconductor, DC sources, capacitors, drivers, and TSV (total standing voltages) based on the number of module units (n) were determined in the middle column and the number of output levels (NL), according to the mentioned variable parameters, were calculated in the last column. The symbol "[]" represents floor function.


**Table 2.** The equations of the proposed module.

According to Figure 3, the maximum magnitude of the blocking voltage was considered for each power switch. The total of all switch blocking voltages was introduced as TSV. The voltage standing on the switches in each level and the circuit study are presented in Figures 6 and 7, respectively. For each level, the voltage standing on each switch was separated by different colors, as shown in Figure 6. Low purple parts in Figure 6 confirms that the voltage stresses on switches were rare, and most of the area had low switch stress in the levels. Figure 7 demonstrates the voltage of switches on the circle graph, showing that the voltage standing in comparison with the total standing voltages was low in S1, S2, S5, S6, S7, S8, S9, S11, S12, and S13.

**Figure 6.** The surface graph of the voltage restrictions on the circuit for each level.

**Figure 7.** The circle graph of the voltage restrictions on each switch.

#### *2.2. Module Extension*

The modularity of the proposed model led to achieving more voltage levels. The cascade configuration was attractive for the medium and high voltage applications with cumulative DC links, such as solar Photovoltaic farms. The cascade connection of the two sequential units is shown in Figure 8. In this configuration, the unit produced 0, ±1VDC, ±2VDC, ±3VDC, ±4VDC, ±5VDC, ±6VDC, ±7VDC, and ±8VDC.

**Figure 8.** The cascade connection of the modular proposed multilevel.

Table 3 demonstrates that the combination of unit 1 and unit 2 created 16 positive levels, 16 negative levels, and zero level (total 33 levels). In Table 3, u1= *VA*<sup>1</sup>*B*<sup>1</sup> *VDC* , u2<sup>=</sup> *VA*<sup>2</sup>*B*<sup>2</sup> *VDC* . The extending of the proposed module as several units in series could make some redundant paths.


**Table 3.** Output levels for two modules to create 33 levels.

#### *2.3. Comparative Study*

Getting maximum voltage levels from the two DC sources is the specialty of the P-Type. It should be mentioned that there are few configurations with the exact two sources to be compared with the proposed multilevel inverter. Table 4 shows some similar new multilevel inverter configurations, as well as the proposed module in case of producing 17 output voltage levels. Some of these configurations could create the same levels with the only use of DC sources without any capacitors [12,18,24,25,35,36], and the presented module in [34] with two DC sources and some capacitors had a close configuration to the P-Type.

**Table 4.** Comparison of some modular multilevel inverter topologies.


<sup>1</sup> Total standing voltages.

As shown in Table 4, to make a suitable comparison, various aspects, such as the number of DC sources, the number of semiconductors, the number of capacitors, the ability to generate negative voltage level, and TSV, were considered in terms of a number of voltage levels (NL). The formula for the other configuration is referred to from [37].

Figure 9 depicts the parameters, as mentioned in Table 4, versus voltage levels in different topologies. It was noticeable that one module generated some ranges of levels with the constant components. If more levels were required, it should be a connected module with the module in cascade connection. This is why Figure 9 was a staircase form. According to Figure 9a,b, it was prominent that the proposed module could attain maximum voltage levels from two DC sources with a lower number of semiconductors. The number of switches versus voltage levels is an important factor for MLIs. As a comparison only in the case of a number of semiconductors, [24,25,36] required a lesser number of switches/diodes, but the number of DC sources should be considered. It was observed that the P-Type had significantly fewer semiconductors than [34] with the same number of DC sources. One of the promising advantages of the P-Type module was using lower DC sources except for the single source configurations (Figure 9c).

**Figure 9.** Comparative studies: The number of switches (**a**); The number of diodes (**b**); The number of sources (**c**); The number of capacitors (**d**); and TSV (**e**) in terms of the number of levels.

It is good to mention that P-Type needed the lowest number of capacitors in comparison with the module that used a capacitor as DC links (see Figure 9d). As shown in Figure 9e, the proposed module had a reasonable range of TSV. It could be referred to as Figure 6, which described the most of switches in the most of levels tolerating low switch stress (at the end of Section 2.1). It is noticeable that the presented topology and [24,25] had an inherent ability to generate negative voltage levels without any additional circuit. [12,18,34–36] could not have produced it without using full-bridge. This ability, along with lower components and switch stress, proved that the presented inverter could perform high in comparison with the other existing ones.

#### **3. Nearest Level Control (NLC) Modulation Method**

The nearest level control method (NLC) was used as a switching technique in the proposed multilevel [38]. This technique was applied in high voltage level converters to simplify and reduce the calculation of the processor. The modulation scheme and the control diagram are shown in Figure 10.

**Figure 10.** Nearest level control: (**a**) Waveform synthesis; (**b**) Control diagram.

According to Figure 10a, the controller sampled a point from the reference voltage (Vref) and then rounded it to the nearest of the voltage level (VaN). Each voltage level had a switching logic according to the switching table to change switches status (Figure 10b). The sampling was repeated for each sample time (Ts).

#### **4. The Analysis of Capacitors Ripple**

The capacitor voltage balancing is necessary to having constant voltage DC links in multilevel converters, which use capacitors as DC links. Since the capacitor voltage is kept constant, feeding the electrical load by MLIs would be guaranteed. Due to this fact, the voltage ripple of capacitors should be considered. To clarify this issue, ripple factor (RF) and figure factor (FF), as the main parameters in the ripple analysis of capacitors, are given by:

$$RF = \frac{V\_{ac}}{V\_{dc}}\tag{1}$$

$$FF = \frac{V\_{rms}}{V\_{dc}}\tag{2}$$

and,

$$V\_{\rm ac} = \sqrt{V\_{rms}^2 - V\_{\rm dc}^2} \tag{3}$$

The ripple waveform is estimated to a sinusoidal waveform eight times bigger than the fundamental period. The maximum ripple is allowed to be less than 5% to obey this condition. Thus, the capacitor's drop voltages are not decreased than 0.95Vmax. The boundaries of the area of the integral are between 77◦ and 103◦.

$$V\_{dc} = \frac{1}{T} \int\_{\text{Start angle of ripple}}^{\text{End angle of ripple}} f(\theta) \, d\theta = \frac{2 \times 1}{2\pi} \int\_{77^{\circ}}^{403^{\circ}} V\_{\text{max}} \sin\frac{\theta}{8} \, d\theta \tag{4}$$

$$V\_{rms} = \sqrt{\frac{1}{T} \int\_{\text{Start angle of ripple}}^{\text{End angle of ripple}} f^2(\theta) \, d\theta} = \sqrt{\frac{2 \times 1}{2\pi} \int\_{77^{\circ}}^{103^{\circ}} V\_{\text{max}}^2 \sin^2 \frac{\theta}{8} \, d\theta} \tag{5}$$

As can be observed from the parallel charging in Figure 5, Vmax for C1 was 10 and for C2 was 30. The following result could be calculated from Equations (1)–(5): Vdc,C1 = 9.65, Vdc,C2 = 28.95, Vrms,C1 = 9.75, Vrms,C2 = 29.2, Vac,C1 = 1.39, Vac,C2 = 4.17, and therefore: FFC1 = 1.01, RFC1 = 0.14 and FFC2 = 1.01, RFC2 = 0.14.

The described analysis showed that the voltages of the capacitors were standard to use in the proposed multilevel inverter.

Taking into account that the amounts of capacitors directly depend on load application, the proper determination of the capacitors resulted in having enough energy to supply the load during each periodic cycle on their levels (see Figure 4). First, the typical AC electrical load was assumed to consume 60 Wh (or 0.333 mW for one cycle = 20 millisecond). Based on Figure 4, the C1 as a DC link supplied levels −5, −8, 2, 5, 7, and 8, meaning 0.062 mW for each one cycle, and levels −8, −7, −6, 2, 5, 6, 7, and 8 were supplied by C2, meaning 0.094 mW for each one cycle.

On the other hand, to keep the DC link voltages at the constant level, the drop voltage of capacitors must be less than 5%. This requires drop voltage to satisfy ΔVC1 < 0.5 and ΔVC2 < 1.5.

The energy stored in capacitors can be calculated by the following equation:

$$E\_{\mathbb{C}} = \frac{1}{2} \mathbb{C} \,\Delta V^2 \,\tag{6}$$

According to the above equation and mentioned conditions, considering C1 ≥ 496 μF and C2 ≥ 84 μF would admit that the capacitor values were sufficient to keep their voltages constant with standard ripple.

It is obvious, the values of the capacitors were selected to limit the voltage ripples. Selecting a higher capacitor as a DC link led to a reduction in the voltage ripples correspondingly.

#### **5. Simulation Results**

The proposed 17 levels of multilevel inverter had been simulated by MATLAB/SIMULINK. The output voltage of P-Type is shown in Figure 11a. The magnitude of each level (VDC) was 10 volts to create a 50 Hz sinusoidal waveform. Figure 11b despises the harmonics spectrums as well. The THD (Total Harmonic Distribution) was calculated as 3.12% by FFT analysis for the waveform of Figure 11a, which was lower than the acceptable amount in the IEEE519 standard (THD% ≤ 8% and each order ≤ 5%).

**Figure 11.** The simulated output voltage waveform of the proposed module: (**a**) Waveform; (**b**) Harmonics spectrums.

In order to indicate the performance of the modular mode, the cascade topology was simulated, and the results are depicted in Figure 12. The illustrated results confirmed the modular ability of proposed topology and its performance for creating 33 levels with THD = 1.54% for the cascade topology. IEEE519 was satisfied, as shown in Figure 12b, showing harmonic spectrums. Simulation results clarified the performance of the proposed module to create maximum output voltage waveforms with low harmonics.

**Figure 12.** The simulated output voltage waveform of the first cascade topology (33 levels): (**a**) Waveform; (**b**) Harmonic spectrums.

#### **6. Experimental Results**

In order to verify the accurate performance of the proposed multilevel inverter and cascade topology connection for generating all output levels, an experimental prototype of the proposed module was built using IGBT12N60A4, Diode RHRP15120. The switching patterns of the different switches were generated by Microcontroller ATMEGA32, which provides on/off pulses for all switches. Based on Tables 1 and 3 and optocoupler-drivers (HCPL3120), the switches (MOSFET23N50E) were driven to create the sinusoidal waveform with a frequency of 50 Hz. Figure 13 depicts the experimental setup in the laboratory.

**Figure 13.** Experimental setup picture in the laboratory.

The experimental test on the setup system was performed, and each step of the voltage was considered 10 volts. Thus, the values of the used DC voltage sources were 10 (V) for 1VDC and 30 (V) for 3VDC in which ±8xVDC and ±16xVDC were generated for one module and cascade connection, respectively. The 17 levels and 33 levels MLI supplied the load with 40 Ω. Figure 14 shows the 50 Hz voltage and current sinusoidal waveforms of the proposed module for 17 levels. It should be mentioned that THD was 3.77% for 17 levels in the experimental test. Figure 15 contains results for 33 levels whose THD was 1.97%. The components were reduced directly affect the manufacturing cost. The new proposed multilevel inverter with a reduced number of DC sources was economical, and the smooth output voltage with low harmonic waveform made P-Type an interesting multilevel.

**Figure 14.** The output voltage of experimental results for 17 levels (case 1).

**Figure 15.** The output voltage of experimental results for 33 levels (case 2).

Finally, the voltages of VC1 and VC2 that were on 10 and 30 volts are demonstrated in Figures 16 and 17, respectively. It was objective that the voltages of the capacitors were constant during the experiment.

**Figure 16.** The voltage of VC1 experimental results.

**Figure 17.** The voltage of VC2 experimental results.

#### **7. Conclusions**

In this paper, a new asymmetrical multilevel inverter module was introduced that is named P-Type. The configuration of P-Type produced 17 voltage levels by using only four DC links, including two DC sources and two capacitors. As a result, the maximum output voltage levels were produced at the output by the reduction of DC sources. By proper designing of the module, capacitors would be charged/discharged without any extra circuit. Modularity with low stress on semiconductors made the proposed module suitable for high power applications. The inherent negative voltage and low THDv were some main advantages of the proposed module. THDv% for one module was obtained as 3.12% and 3.77% in the simulation and experimental results, respectively, satisfying the harmonics standard (IEEE519). THDv% for cascade connection (two modules) was calculated to be 1.54% in simulation and 1.97% in experimental results. The experimental results proved the validity of the proposed module in producing the maximum output levels with a low amount of harmonics. The illustrated features of P-Type made it acceptable in power applications, which use unequal DC sources with ratio 3:1. The proposed module, with its all features, could be used in some applications with DC sources to supply AC loads. For example, it could be used in the solar farms with photovoltaic systems in which the unequal DC sources are accessible by the suitable connection of solar panels. Also, this system could be applied to other DC sources, such as fuel cells, batteries, etc.

**Author Contributions:** All authors contributed equally to this work and all authors have read and approved the final manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **A Multi-Inductor H Bridge Fault Current Limiter**

#### **Amir Heidary 1, Hamid Radmanesh 2, Ali Moghim 1, Kamran Ghorbanyan 1, Kumars Rouzbehi 3, Eduardo M. G. Rodrigues 4,\* and Edris Pouresmaeil 5,\***


Received: 18 May 2019; Accepted: 12 July 2019; Published: 16 July 2019

**Abstract:** Current power systems will suffer from increasing pressure as a result of an upsurge in demand and will experience an ever-growing penetration of distributed power generation, which are factors that will contribute to a higher of incidence fault current levels. Fault current limiters (FCLs) are key power electronic devices. They are able to limit the prospective fault current without completely disconnecting in cases in which a fault occurs, for instance, in a power transmission grid. This paper proposes a new type of FCL capable of fault current limiting in two steps. In this way, the FCLs' power electronic switches experience significantly less stress and their overall performance will significantly increase. The proposed device is essentially a controllable H bridge type fault current limiter (HBFCL) that is comprised of two variable inductances, which operate to reduce current of main switch in the first stage of current limiting. In the next step, the main switch can limit the fault current while it becomes open. Simulation studies are carried out using MATLAB and its prototype setup is built and tested. The comparison of experimental and simulation results indicates that the proposed HBFCL is a promising solution to address protection issues.

**Keywords:** fault current limiter; microgrid protection; power quality; fault current; H bridge

#### **1. Introduction**

The immense global growth in energy demand will require additional power generation as well as an efficient, reliable complex meshed power distribution. The existing power grids will experience, in the near future, a growing burden due to an upsurge in electricity demand and will experience an ever-growing penetration of distributed power generation, which are factors that will contribute to a higher incidence of fault current levels. The massive growth of gird interconnection and integration of distributed generators (DGs) increase the network fault current level [1–4]. The solid-state fault current limiter (FCL) is a fast protection device that includes a DC reactor and solid-state switches [1–4]. The voltage source converters (VSCs) of HVDC systems are sensitive to the fault current. Recently, they have been combined with appropriate FCLs to protect them [5,6]. There are other types of FCLs that have been introduced in the literature. A resistive superconductor FCL based on variable resistance, which is very complex and costly, has been presented in the works of [7,8]. The bridge type FCLs based on DC reactor have been studied in the literature [9–12]. The AC/DC reactor based FCL has been presented in the work of [13]. In this FCL, two-stage operation decreases the voltage stress on the solid-state switches. The other well-known FCL type are the resonance type FCLs, which have high transient voltage, and this is their most important challenge [14,15]. A series two-stage FCL

that behaves by operation of the solid-state switch in the secondary winding is introduced in the works of [16,17]. Saturated core FCL based on DC bias saturation and the series coil is studied in the literature [18–24]. In this type, the electronic switch connects to DC saturation current and does not have any conflict with the line current. Superconductive FCLs have been investigated for limiting the fault current in the microgrid [25,26]. FCLs can preserve microgrid from AC grid fault currents because the AC/DC microgrid should be protected in both the AC and DC sides [27]. Novel types of magnetic based FCLs are analyzed in the works of [28,29] to improve the performance of FCL for a power grid. Flux coupled FCLs and bridge type solid-state FCLs [30,31] are used to design a novel H bridge type fault current limiter (HBFCL).

The rest of this paper is organized as follows. In Section 2, the HBFCL structure is presented. In Section 3, the analytical studies are given and, in the next section, the simulation results of the proposed HBFCL are presented. In Section 5, the experimental test results are presented and, finally, the conclusion is drawn.

#### **2. Proposed HBFCL Configuration**

The proposed HBFCL is connected in series with the line to protect the point of common coupling (PCC) of the microgrid against the fault current. The HBFCL includes four inductors, *L1–L4*, as shown in Figure 1. An antiparallel power electronic IGBTs, that is, *G1* and *G2*, are connected as main switches to the middle branch of the H bridge. *L3* and *L4* are coupled with *L5* and *L6*, respectively. The power electronic switch, *G3* and *G4*, and rectifier diodes, *D1–D4*, are connected to these coupled inductances. After switching of IGBT switches (*G3* and *G4*), *L5* and *L6* are bypassed and two levels for *L3* and *L4* in the different modes are configured.

**Figure 1.** Proposed H bridge type fault current limiter (HBFCL) topology.

The operation of the proposed FCL is divided into three modes, as shown in Figure 2. Figure 2a–c show the HBFCL equivalent circuit during the normal operation mode after fault occurrences and during the fault limiting mode, respectively.

**Figure 2.** HBFCL equivalent circuit. (**a**) Normal operation mode, (**b**) fault operation mode in first state, and (**c**) fault operation mode in second state.

#### *2.1. Normal Operation Mode*

In this mode, as shown in Figure 2a, the secondary sides of *L3* and *L4* are short-circuited via IGBTs and the inductors are modeled by their leakage inductance and a small resistance. Considering *L1* and *L2* values, high inductive current is carried by *L3, L4, G1*, and *G2*. During the normal operation mode, all of the IGBT switches are in ON state and the maximum power flow is passed by the HBFCL.

#### *2.2. Pre-Limiting Mode*

After fault occurrence, the IGBTs *G3* and *G4* become turned-off and the main breaker *SW1*, which includes series antiparallel switches that is shown as *G1*, and *G2* change to turned-off state. In the off state of *G3* and *G4*, the inductance of *L3* and *L4* increases and the current of the main switch, that is, *SW1*, decreases to a low value. Figure 2b shows the equivalent circuit of the pre-limiting mode.

#### *2.3. Fault Current Limiting Mode*

In this mode, the current of the *SW*<sup>1</sup> decreases and it can safely be opened. In this case, the limited fault current is divided between two parallel branches, which include series connection of *L*1, *L*<sup>3</sup> and *L*2, *L*4.

#### **3. Analytical Studies**

#### *3.1. Steady-State Mode*

Analytical studies are presented based on the three operation states of the proposed HBFCL. In the first state, there is no fault in the system. In this case, the microgrid equivalent circuit is shown in Figure 2a and the analytical study is done according to this circuit. In this case, the current and voltage is sinusoidal and we have the following:

$$\dot{q}\_{\rm lim} = \frac{V\_{\rm S}}{Z\_{\rm S} + Z\_{\rm HBFCL} + Z\_{\rm limc} + R\_{\rm finalt}},\tag{1}$$

where

$$Z\_{HBFCL} = (r\_3 + r\_4) + j(X\_{L3} + X\_{L4}),\tag{2}$$

$$V\_{HBFL} = i\_{line}((r\_3 + r\_4) + j(X\_{L3} + X\_{L4})),\tag{3}$$

and

$$V\_{P\overline{C}} = V\_S - i\_{line}((r\_3 + r\_4) + j(X\_{L3} + X\_{L4}) + Z\_S),\tag{4}$$

where *V*s, *V*HBFCL, *V*PCC are source voltage, HBFCL voltage drop, and voltage of point of common coupling, respectively. *i*line is line current. *L*L3, *L*L4, *r*3, and *r*<sup>4</sup> are leakage inductances and resistances of *L*<sup>3</sup> and *L*4, respectively. *Zs*, *Z*HBFCL, and *Zline* are impedances of the source, HBFCL, and line, respectively. *Rfault* is resistance of the fault.

During normal operation, the power loss is calculated with Equation (5).

$$P\_{\rm loss} = P\_{\rm Cu(L\_3)} + P\_{\rm Cu(L\_4)} + P\_{\rm Cu(L\_5)} + P\_{\rm Cu(L\_6)} + P\_{\rm SW1} + P\_{\rm SW2} + P\_{\rm SW3} \tag{5}$$

where

$$P\_{\rm Cu} = i\_{\rm line}{}^2 \times r\_3 + i\_{\rm line}{}^2 \times r\_4 + i\_{\rm 6}{}^2 \times r\_5 + i\_{\rm 6}{}^2 \times r\_{\rm 6} \tag{6}$$

$$P\_{SW} = i\_{line} \times V\_{SW1} + \mathcal{2}(i\_{\&} \times V\_{SW2}).\tag{7}$$

The power loss depends directly on the line current, inductor secondary current, switching voltage, and coil resistance.

According to Equations (5)–(7), the HBFCL power loss is negligible by decreasing coil resistance and using the series power IGBT switch.

#### *3.2. Pre-Fault Limiting Mode*

In fault occurrence, *G*<sup>3</sup> and *G*<sup>4</sup> change the H bridge topology and limit the fault current, and we have the following equation.

$$X\_{\rm L1} \times X\_{\rm L2} = X\_{\rm L3} \times X\_{\rm L4} = \left(2\pi f\right)^2 L\_1 \times L\_2 = \left(2\pi f\right)^2 L\_3 \times L\_4,\tag{8}$$

where *XL1* to *XL4* are reactor impedances while the secondary side is open-circuited and *f* is the network frequency.

#### *3.3. Fault Current Limiting Dynamic Mode*

Considering Figure 2c, we have the following equations:

$$\text{2L}\_1 = \text{L}\_2, \text{ 2L}\_4 = \text{L}\_3, \text{ L} = \text{L}\_1 = \text{L}\_4. \tag{9}$$

$$L\_{HBFCL} = \frac{(L\_1 + L\_3)(L\_2 + L\_4)}{(L\_1 + L\_3) + (L\_2 + L\_4)} = \frac{3}{2}L,\tag{10}$$

and

$$-V\_S(t) + i\_{line}r\_{tq} + (L\_{tq})\frac{di\_{line}}{dt} = 0,\tag{11}$$

and in which

$$i\_{line}(t) = Ae^{-\frac{rq}{T\_{eq}}t} + BVm\sin(\omega t - \theta),\tag{12}$$

where *A* and *B* are determined based on initial condition.

$$r\_{l\eta} = r\_{\mathcal{S}} + r\_{l\text{int}} + r\_{\text{HBFCL}} + \mathcal{R}\_{fault} \tag{13}$$

$$L\_{cq} = L\_S + L\_{line} + \frac{3}{2}L \tag{14}$$

#### **4. Control Strategy**

Figure 3 shows the control system block diagram based on the proposed HBFCL.

**Figure 3.** HBFCL control block diagram.

In this system, represented by the HBFCL control block diagram from Figure 3, the current and voltage signals are monitored via current and voltage transformers are measured and send to a digital (A/D) sampler to make the digital data. In fault cases, the current rate is raised and the *rms* value of the current is compared with the reference value, that is, 1.2 p.u. The voltage signal is sampled by the A/D block and its *rms* value is compared with the reference voltage. A step generator drives IGBT switches. The main switches are driven after a very small delay to meet the HBFCL self-protection and limit the fault current in two steps. After fault current limitation, a timer resets the step generator to turn-on *G*1–*G*<sup>4</sup> for checking the fault clearance.

#### **5. Simulation Results**

In this section, simulation results are carried out considering the system configuration shown in Figure 1. The electrical network parameters are listed in Table 1.


**Table 1.** The values of the H bridge type fault current limiter (HBFCL) parameters.

In order to be able to monitor the fault cases, the line to ground fault is applied to the network and the proposed HBFCL is connected in series in the line. To verify the proposed HBFCL effectiveness, two cases are considered to obtain the simulation results, that is, fault current without HBFCL effect and limited fault current with HBFCL effect, as shown in the following subsections.

#### *5.1. Fault Condition without HBFCL E*ff*ect*

In this section, the proposed electrical system shown in Figure 1 is simulated without the HBFCL effect. Figure 4 shows the line current provided by the main feeder during the normal and fault operation modes. During the normal operation mode, the line current amplitude is 200 A till *t*1. After fault occurrences in *t*1, the fault current is increased and its first peak amplitude reaches 6300 A. Accordingly, if bus bar base current assumes 1000 A fault first peak is 6.1 p.u, which shows studied bus-bar high strength and high possible fault current.

**Figure 4.** System voltage and current without HBFCL effect—the line current during normal and fault conditions.

As shown in Figure 5, the PCC voltage has 20 kV amplitude during the normal operation mode, and after fault occurrences, its amplitude experiences deep voltage sag and decreases to 10 kV.

**Figure 5.** System voltage and current without HBFCL effect—the point of common coupling (PCC) voltage during normal and fault conditions.

#### *5.2. Fault Condition with HBFCL E*ff*ect*

Connecting the proposed HBFCL as a protection device to the line, the fault current is decreased to an acceptable level, as shown in Figure 6.

**Figure 6.** (**a**) Line and SW1 switch currents during normal and fault conditions affected by HBFCL and (**b**) PCC voltage during normal and fault conditions affected by HBFCL.

In order to control the fault current, IGBTs change the HBFCL topology in two steps. In *t*1, 100 ms fault is occurred while between *t*<sup>1</sup> and *t*2, 102 ms HBFCL control system recognizes the fault but HBFCL is not operated. In *t*2, *SW*<sup>2</sup> and *SW*<sup>3</sup> are turned off and current is limited by increasing *L1* and *L2* impedance, as shown in Figure 6a. After a small delay, the main switch *SW*<sup>1</sup> is turned off and current is decreased to nominal current. Considering the HBFCL limiting strategy, the first peak of the fault current is limited to 1 kA. Figure 6b shows the PCC voltage during normal, transient, and fault states. Considering the switching transient recovery voltage (TRV) between *t*<sup>2</sup> and *t*3, the TRV peak has an acceptable rate in the first switching and second switching; it is damped very well for safe switching action.

In Figure 7, it is possible to observe the *SW*<sup>2</sup> and *SW*<sup>3</sup> effect on the PCC transient recovery voltage and the *SW*<sup>1</sup> transient recovery voltage after the 100 ms instant, in which a transition from the normal operating mode to the fault limiting mode can be observed. This effect can also be observed in more detail in the expanded view of Figure 7.

**Figure 7.** The effect of *SW*<sup>2</sup> and *SW*<sup>3</sup> on the PCC transient recovery voltage and the *SW*<sup>1</sup> transient recovery voltage.

Figure 8 shows the limited fault current by HBFCL where the first peak of the fault current is decreased considerably.

**Figure 8.** The line current with and without HBFCL protection.

#### **6. Simulation Results**

In this section, the laboratory test prototype is built and tested to verify the simulation results. The parameters values are listed in Table 2 and the proposed prototype is shown in Figure 9.


**Table 2.** The values of prototype parameters.

**Figure 9.** The proposed experimental setup.

The prototype shown in Figure 9 includes four inductors created by E-I 56 core and 0.5 mm2 wire. Core saturation has occurred in approximately 6 A, which is out of the test range. The IGBTs with part number (STGP10NC60H) as an *SW1* and *SW3* are used in the prototype structure. The control circuit is made by NODE MCU hardware and it has independent current and voltage sensors. This hardware sends the proper pulses to IGBTs via drivers. An autotransformer is used as an electrical source and a variable resistance is used as an electrical load. The line to ground fault is applied by 25 A, 500 V solid-state relay.

The voltage and current signals during the normal and fault operation modes are presented in Figure 10a–c.

In Figure 10a, current waveform is shown during the normal and fault operation where the current amplitude in normal condition is 1 A. In *t*1, fault is applied to the setup and the line current raises and reaches 3 A. This result is in fair agreement with the simulation result shown in Figure 6a. Moreover, the main switch current is measured and considered in three states, that is, normal condition, fault pre-limiting mode, and turning off the main switch. Pre-limiting operation is carried out by *SW*<sup>2</sup> and *SW*<sup>3</sup> operation, which decreases the line current. The main switch is *SW*<sup>1</sup> and its operation causes safe and easy current interruption. Figure 10b shows the PCC voltage profile during the normal and fault conditions. In the normal operation, PCC voltage is 24 V; after fault occurrences, the peak voltage reaches 40 V. By operating the main switch, transient voltage peak value decreases to 32 V and, after HBFCL operation, the PCC voltage is fixed to 23 V. This signal closely agreed with the simulation

result shown in Figure 7. Figure 10c shows the *SW*<sup>1</sup> current in fair agreement with the simulation results shown in Figure 6b.

**Figure 10.** (**a**) Line current during normal and fault condition, (**b**) PCC voltage during normal and fault condition, and (**c**) main switch current during normal and fault condition.

#### **7. Conclusions**

Power systems will suffer a growing pressure as a result of an upsurge in electricity demand and an increasing penetration of distributed power generation, which will cause, in turn, a higher incidence of fault current levels. Therefore, in order to mitigate such potential problems, in this paper, a new type of FCL named H bridge fault current limiter (HBFCL) is proposed. The simulation and experimental results show the appropriate operation of the proposed HBFCL during the normal, transient, and fault conditions. Dissipation of fault energy in the four inductors and fault current limiting by three solid-state switches are a successful method that improves performance of the HBFCL. Experimental tests validate the performed simulations in this paper. They demonstrate that the PCC voltage can be successfully protected against the TRV.

**Author Contributions:** Conceptualization, A.M.; Methodology, K.G.; Software, H.R.; Validation, E.P.; Writing—original draft, A.H.; Writing—review and editing, K.R.; Supervision, E.M.G.R.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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