*4.1. CCM Voltage Gain*

In the CCM, the tapped inductor, *Lcp*, was charged by the input voltage source, *Vin*, only through the primary winding *N*1 or *N*2 during the time of *DTs* (state A or A'). However, the output voltage, *vo* was stressed on all the four windings of the tapped inductor during the time of (1 − *D*)*Ts* (state B or B'). Thus, according to the volt-sec balance, it gives

$$\int\_{0}^{DT\_s} V\_{in} dt + \int\_{DT\_s}^{T\_s} \frac{-v\_o}{2n+2} dt = 0 \tag{1}$$

which led to that the quasi-steady-state voltage gain of the SSBBI to be calculated as

$$M = \frac{v\_o}{V\_{in}} = 2(n+1)\frac{D}{1-D}.\tag{2}$$

It can be recognized from Equation (2) that the SSBBI was a buck-boost type topology and had the function of voltage step-up/down. A higher gain can be achieved by choosing a proper turns ratio, *n*.

#### *4.2. Turns Ratio and Duty Cycle Constraints*

It should be noticed that when the tapped inductor is discharged to the output side (see states B and B'), the voltage across the primary winding must be always less than the DC input voltage, *Vin*. Accordingly,

$$\frac{v\_0}{2(n+1)} < V\_{\text{in}}.\tag{3}$$

In this way, it prevented the discharging current of the tapped inductor to go back to the DC input source through the body diode of the switch at the lower side. Such a condition should be avoided since the output voltage would be clamped and the circulating current will lower the efficiency as well. With this concern, the turns ratio should be designed sufficiently large to make the SSBBI work properly. Thus,

$$n > \frac{V\_{\text{ormax}}}{2V\_{in}} - 1.\tag{4}$$

Moreover, it can be obtained by combining (2) and (3) that

$$\frac{D}{1-D} < 1.\tag{5}$$

Subsequently, the maximum duty ratio, *D*max, should be limited to

$$D\_{\text{max}} < 0.5. \tag{6}$$

## *4.3. Voltage and Current Stress*

## 4.3.1. Voltage Stress of Switches

During state A, the input voltage, *Vin*, was imposed on the primary winding *N*1 of the tapped inductor when the switch *Q*1 was on. Therefore, the voltage stress on the switch *Q*3 was the sum of the input voltage and the induced voltage across the primary winding *N*2, which was twice the input voltage, *Vin as*

$$V\_{Q9\text{max}} = 2V\_{\text{in}}.\tag{7}$$

Meanwhile, since the switch *Q*4 was in on-state, the voltage across the four windings of the tapped inductor as well as the output voltage, *vo*, was stressed on the off-state switch *Q*2. Thus, the maximum stress of the *Q*2 will lead to:

$$V\_{Q2\text{max}} = 2(n+1)V\_{in} + V\_{\text{omax}}.\tag{8}$$

The same results can be obtained for the switches *Q*1 and *Q*4 in state A' because of the symmetrical operation of the SSBBI. The voltage stresses for all the switches are summarized in Table 4.


**Table 4.** SSBBI switch voltage and current stresses.

## 4.3.2. Analysis of Current Stress

It was assumed that the output voltage and current of the SSBBI were ideally in phase without harmonics as

$$\begin{cases} v\_o(t) = V\_m \sin \omega t \\ i\_o(t) = I\_{\text{ff}} \sin \omega t \end{cases} \tag{9}$$

Furthermore, by applying Equations (2) and (9), and replacing the steady-state duty ratio *D* with the time-varying duty ratio *d*(*t*), it can be obtained that

$$\frac{v\_o(t)}{V\_{in}} = 2(n+1)\frac{d(t)}{1-d(t)} = \frac{V\_{in}\sin\omega t}{V\_{in}}\tag{10}$$

from which the duty ratio, *d*(*t*), can be derived as

$$d(t) = \frac{V\_m \sin \omega t}{2(n+1)V\_{in} + V\_m \sin \omega t}. \tag{11}$$

For the proposed SSBBI, the average output current equaled to the average current of the upper switch, *io*(*t*) = *iQ*2(*t*)[1 − *d*(*t*)], as shown in Figure 6. Therefore, assuming that the current ripples are negligible, the current amplitude of the switch *Q*2 can be obtained by combining Equations (9) and (11) as

$$i\_{Q2}(t) = \frac{\langle i\_o(t) \rangle}{1 - d(t)} = I\_m \sin \omega t + \frac{I\_m V\_m \sin^2 \omega t}{2(n+1)V\_{in}}.\tag{12}$$

**Figure 6.** Illustration of the switch current, *iQ*(*t*), and the average output current, <sup>&</sup>lt;*io*(*t*)<sup>&</sup>gt;, throughout the half-line cycle.

Thus, the maximum current of the switch *Q*2 at the peak output voltage can be obtained as

$$I\_{Q2\text{max}} = I\_m + \frac{I\_m V\_m}{2(n+1)V\_{in}}.\tag{13}$$

The squared RMS current of the switch *Q*2 within a switching period is:

$$\mathbf{i}\_{Q2rmsTs}^{2} = \frac{1}{T\_s} \int\_{t}^{t+T\_s} \mathbf{i}\_{Q2}^{2}(t)dt = [1 - d(t)]\mathbf{i}\_{Q2}^{2}(t). \tag{14}$$

Subsequently, the squared value of the switch RMS current is:

$$I\_{Q2rms}^2 = \frac{1}{T/2} \int\_0^{T/2} i\_{Q2rmsTs}^2 dt\tag{15}$$

with *T* being the generated output voltage period. Substituting Equations (11), (12), and (14) into (15) yields

$$I\_{Q2rms}^2 = \frac{1}{T/2} \int\_0^{T/2} I\_m^2 \sin^2 \omega t + \frac{I\_m^2 V\_m \sin^3 \omega t}{2(n+1)V\_{in}} dt = I\_{\text{acms}}^2 \left( 1 + \frac{4}{3\pi} \frac{V\_m}{(n+1)V\_{in}} \right). \tag{16}$$

Thus, the RMS current of the switch Q2 is obtained as

$$I\_{Q2rms} = I\_{acrms} \sqrt{1 + \frac{4}{3\pi} \frac{V\_m}{(n+1)V\_{in}}}.\tag{17}$$

The current amplitude of the lower switch *Q*1 is 2(*n* + 1) times higher than the upper switch current due to the function of the tapped-inductor turns ratio, *n*. Thus,

$$i\_{Q1}(t) = 2(n+1)i\_{Q2}(t) = 2(n+1)I\_{\text{in}}\sin\omega t + \frac{I\_{\text{in}}V\_{\text{in}}\sin^2\omega t}{V\_{\text{in}}}.\tag{18}$$

Therefore, the peak current through the lower switch, Q1, is:

$$i\_{Q1\text{max}} = 2(n+1)I\_m + \frac{I\_m V\_m}{V\_{in}}.\tag{19}$$

The squared value of the lower switch RMS current through the switching period, *Ts*, is:

$$i\_{Q1rmsTs}^2 = \frac{1}{T\_s} \int\_t^{t+T\_s} i\_{Q1}^2(t)dt = d(t)i\_{Q1}^2(t). \tag{20}$$

Since the low switch conducts for half the line period, the squared value of its RMS current on the line period scale can be calculated as:

$$I\_{Q1rms}^2 = \frac{1}{T} \int\_0^T i\_{Q1rmsTs}^2 dt. \tag{21}$$

Substituting Equations (11), (18), and (20) into (21), gives

$$I\_{Q1rms} = I\_{\text{acrms}} \sqrt{\frac{3}{8}} \frac{V\_m^2}{V\_\mathcal{S}^2} + \frac{8}{3\pi} \frac{(n+1)V\_m}{V\_{in}}.\tag{22}$$

With the above analysis, the voltage and current stresses of the SSBBI are summarized in Table 4.

## **5. Simulation Results and Comparison**
