**1. Introduction**

The continuous development of distributed photovoltaic (PV) power generation systems arouses much interest in MIEs/MICs, also known as microinverters. Unlike the string inverters using series-connected PV panels to achieve a high voltage, microinverters are designed to directly connect a single PV panel with a low voltage to the grid while providing an individual MPPT and, in turn, avoiding mismatch losses within the PV array. The "plug-and-play" feature of the microinverter allows the incorporation of PV modules of di fferent types into a single array, also facilitating its future expansion and maintenance. To some extent, the labor cost can also be reduced.

In practice, the low DC voltage produced by the PV module (e.g., 20–30 V) and the relatively high AC voltage of the utility (e.g., 230 V RMS) imply that a high step-up DC-DC stage followed by a regular inverter is required. Such a straightforward scheme is referred to as the two-stage approach and is quite popular due to its ease of implementation and control. Yet, the two-stage solution is costly and the e fficiency is reduced. The single-stage microinverter that combines both the voltage step-up and inversion functions in one power stage can possibly lead to a lower component count and a reduced cost. Thus, the single-stage inverters have been the focus of recent research activities. Numerous single-stage boost-derived topologies have been proposed in the literature due to the inherent voltage step-up capability [1]. The limited voltage gain of the boost-type converter can be improved by means of integrating tapped inductors, as discussed in [2,3].

Additionally, due to the voltage step-up/down capability, the buck-boost derived topologies can also be a viable solution for single-stage inverter applications. Thus, a number of buck-boost type single-stage inverters with low component counts were reported. For instance, single-stage buck-boost inverters with only three switches were proposed in [4,5], as shown in Figure 1a, where a tapped inductor was used as a regular inductor in one half-line cycle and as a fly-back transformer in the subsequent half-line cycle. Unfortunately, this type of inverter cannot attain the required voltage step-up. As shown in Figure 1b, a four-switch, single-stage, buck-boost inverter was then presented in [6], which employed a tapped inductor and the SEPIC converter to increase the voltage gain. However, according to the operational principles, the turns ratio of the tapped inductor has to be equal to unity, and consequently, the voltage gain is still limited. Topologies in [7,8] also have only four switches to realize the single-stage conversion and have the merit of a common terminal between input and output ports. Figure 1c shows the circuit diagram of the converter in [7]. Another single-stage, buck-boost inverter has the advantage of reduced magnetic volume and low leakage currents [9]. The topologies in [10–12] were conceived to also eliminate the leakage currents, but the number of active switches is increased, as observed in Figure 1d. Furthermore, a differential buck-boost inverter with active power decoupling capability was proposed in [13,14], where no extra components are required. It has only four switches; on the contrary, a rather complicated control method is needed. An active buck-boost inverter using an "AC/AC unit" to realize the buck-boost conversion was introduced in [15,16], as presented in Figure 1e. Yet, each unit consisted of four switches, and, thus, in total, eight switches are needed for the microinverter. The authors of [17] expanded this idea to cascaded multilevel buck-boost inverters using H-bridges for each PV panel and a central AC/AC unit. To improve the efficiency and system reliability, a solution for the current shoot-through issue was discussed in [18,19] to eliminate the dead-time effect. Moreover, ref. [18] presented a converter with eight switches and four inductors, while [19] has four switches, four diodes, and six inductors, which make the topologies quite complicated. The topology in [20] has merits of a wide input voltage range, low leakage currents, small grid current ripples, and low common-mode voltages. However, as seen in Figure 1f, it has four high-frequency switches and two bidirectional switches, which are realized by connecting back-to-back MOSFETs in series. Doing so significantly increases the total number of switches (i.e., eight). Although the ideas of [4–20] are very interesting, their attained voltage gain is comparable to the traditional buck-boost converter.

Additional attempts to increase the gain of the buck-boost derived topologies were reported. For example, in [21] a series connection between a buck-boost converter and the PV array was introduced to have a higher gain, but the gain improvement was limited. The topology in [22], see Figure 2a, employed a switched inductor, which can improve the gain by the factor of √2 over that of the traditional buck-boost converter. However, in total, the topology in [22] had four switches, eight diodes, and four inductors. The tapped-inductor buck-boost inverter topologies presented in [23,24], as shown in Figure 2b,c, respectively, can achieve a much higher voltage gain than the traditional ones, but the switch counts were up to eight, whereas [25,26] had five switches, as presented in Figure 2d. The advantage of the topologies in [25,26] is that only one high-frequency switch was used, and thus, the switching losses were lower. For the topologies in Figure 2, the main characteristics are further compared in Table 1. According to Table 1, most of the topologies had a high semiconductor count, from 7 up to 12. The experimental efficiency of more than 96% was reported in [23]. However, the test was with an input of 100–200 V and a 110-V output, which cannot support the performance with a high-voltage step-up. An efficiency of 86% was achieved in [25] with a 60-V input, a 230-V output, and 100-W output power, which is reasonable for a tapped-inductor buck-boost inverter. Yet, the experimental efficiency of the other two proposals was not reported clearly in the literature.


**Table 1.** Comparison of the main topologies of the existing single-stage, buck-boost inverters.

**Figure 1.** Prior-art, single-stage, buck-boost inverters: (**a**) [5], (**b**) [6], (**c**) [7], (**d**) [12], (**e**) [15], and (**f**) [20].

The high switch count of the reviewed converters, the resulting circuit complexity, higher cost, and lower efficiency, counter the main design goal of producing a simple and low-cost single-stage inverter. Therefore, more efforts have been made to develop more single-stage, buck-boost inverter topologies with a high gain and a low switch count. Recently, a family of single-stage, buck-boost rectifiers with high power factor were proposed in [27], analyzed, and verified in [28]. With the same principles, a family of tapped-inductor, buck-boost microinverters can be derived by reversing the power flow. This calls for the application of bidirectional switches. The proposed tapped-inductor, buck-boost type inverter family is illustrated in Figure 3. The basic operation and the preliminary simulation study of the two topologies in the family were reported in [29,30], while the converters have not been experimentally verified, and the design considerations are not fully addressed.

(a) (b)

**Figure 2.** Prior-art, single-stage, buck-boost inverters with high gains: (**a**) [22], (**b**) [23], (**c**) [24], and (**d**) [25].

 Accordingly, in addition to the topologies in [29,30], this paper further introduces two more practical topologies and all four topologies in the family are presented in detail. More importantly, a comparison of the proposed family was done thoroughly in terms of the component count, the voltage conversion ratio, the voltage stress, the peak current stress, and the RMS current stress, which can be used in the design phase. What is more, more detailed simulation studies for all the topologies in the family were presented. A prototype of the SSBBI of the proposed family was built and experimental results are illustrated in this paper. The rest of the paper is organized as follows. Section 2 introduces the proposed family, and the operation principles of the proposed family are demonstrated on a topology (i.e., the SSBBI) in Section 3. Circuit characteristics are discussed in Section 4, including the analysis of the conversion ratio, turns ratio, and duty cycle constraints together with voltage and current stresses, as design considerations. Simulation results are given in Section 5, where the comparison of the family is provided. Experimental tests are presented in Section 6 to validate the discussion. Finally, concluding remarks are provided in Section 7.

**Figure 3.** Proposed family of single-stage, buck-boost inverters: (**a**) Variant 1, (**b**) Variant 2, (**c**) Variant 3, (**d**) Variant 4 (SSBBI).

## **2. Single-Stage, Buck-Boost Inverter Family**

As shown in Figure 3, the proposed inverter family makes use of a tapped inductor to attain a high step-up voltage conversion ratio. This helps to generate a grid-compatible voltage from a low DC voltage source. Two, three, and four winding, tapped-inductor structures are needed. The turns ratio, *n*, of the tapped inductor is defined as follows. For the two-windings inverter topology in Figure 3a, *n* = *N*2/*N*1. The three-windings topology in Figure 3b has an equal number of primary turns, *N*1 = *N*2, and the turns ratio is defined as *n* = *N*3/*N*1 = *N*3/*N*2. The topologies in Figure 3c,d rely on a symmetrical tapped-inductor structure with an equal turns ratio, defined as *n* = *N*3/*N*1 = *N*4/*N*2.

The topology in Figure 3a includes a floating source, a single ground-referenced PWM switch, *Q*1, and a ground-referenced line frequency unfolding bridge, *Q*2–*Q*5. The topology in Figure 3b includes a grounded source, a ground-referenced push-pull pair of PWM switches, *Q*1–*Q*2, and a floating line frequency unfolding totem pole, *Q*3–*Q*4. The topology in Figure 3c includes a floating source, a single ground-referenced PWM switch, *Q*1, and a floating line frequency unfolding totem pole, *Q*2–*Q*3. The topology in Figure 3d includes a grounded source and a ground-referenced full bridge. Here, the lower switches, *Q*1–*Q*3, are PWM devices, whereas the high switch pair can perform either a simple line frequency unfolding function or be operated as synchronous rectifiers. Since the body diodes of the high switches are exploited as rectifiers, the reverse recovery capability should be considered. This can be an issue for silicon-based devices, while the emerging GaN MOSFETs can deliver the required performance.

To summarize, the proposed inverters have the merits of:


The proposed tapped-inductor, buck-boost inverter family in Figure 3 was then studied through simulations. The exploration indicated that the topology in Figure 3d can also help to avoid much of the practical grounding, driving, and controller interface issues. Additionally, considering the lowest semiconductor count (see Table 2), the topology in Figure 3d appears as the most attractive candidate in the family. Hereafter, this topology (i.e., the SSBBI in Figure 3d) is considered in the following detailed analysis to exemplify the converter operation.


**Table 2.** Comparison of the component count of the tapped-inductor, buck-boost inverter family.

#### **3. Operation Principles of the Proposed SSBBI**

As shown in Figure 3d, the power stage of the proposed SSBBI included four switches, *Q*1–*Q*4, in a full-bridge arrangement. A tapped inductor, *Lcp*, with four windings was employed. The output filter capacitor here was *Co* and the load was an equivalent resistance, *RL*, for stand-alone applications. The voltage across them was the AC output, *vo*. As mentioned previously, two symmetrical pairs of windings were used for the tapped inductor. The turns of the primary windings must be the same, i.e., *N*1 = *N*2. Similarly, equal secondary windings were used, i.e., *N*3 = *N*4. The turns ratio of the tapped inductor was then obtained as *n* = *N*3/*N*1 = *N*4/*N*2. The SSBBI can generate a bipolar output voltage

with the help of the symmetrical structure, and thus, it can achieve the DC-AC inversion. The desired output voltage can be obtained using any common control strategy of a constant frequency duty cycle. The operation principle is detailed in the following.

Supposing the converter was operating in the CCM, the SSBBI had two switching states in each half-line cycle, denoted as states A and B in the positive half-line cycle and A' and B' in the negative half-line cycle. The switching states of the four switches are listed in Table 3, and further illustrated in Figure 4.


**Table 3.** Switching states of semiconductor devices.

**Figure 4.** Equivalent circuits (switching states) of the proposed SSBBI: (**a**) State A, (**b**) State B, (**c**) State A', (**d**) State B'.

According to the equivalent circuit of state A shown in Figure 4a, the state started at the beginning of each switching cycle in the positive half-line cycle. Here, the switch *Q*1 was turned on and the state lasted for the duration of *DTs*. In this state, the tapped inductor was charged by the input source, *Vin*, through the primary winding *N*1. The output capacitor, *Co*, can sustain the output voltage on the load. As shown in Figure 4b, state B began when the switch *Q*1 was turned off and lasted for the duration of (1 − *D*)*Ts*. In this state, the energy stored in the tapped inductor was discharged and released to the output side through all the four windings of the tapped inductor. During states A and B, when the output voltage was positive, *Q*1 and *Q*2 were switched, while the switch *Q*3 was maintained o ff and *Q*4 remained on. In comparison, the states A and B were replaced by the states A' and B' during the negative output half-line cycle due to the symmetrical operation principle. The equivalent circuits of state A' and B' are shown in Figure 4c,d, respectively.

The key waveforms of the SSBBI are described in Figure 5, where *SQ*1–*SQ*4 are the gating signals for *Q*1–*Q*4 switches, respectively. Due to the symmetry of the SSBBI, it was su fficient to consider its operation during the positive half cycle. When *Q*1 was turned on and *Q*2 was turned o ff, the primary winding of the tapped inductor was energized. This caused the magnetizing current of the tapped inductor to ramp up. When *Q*1 was turned o ff and *Q*2 was turned on, the tapped inductor was discharged to support the output through all the windings. Thus, the magnetizing current of the tapped inductor ramped down. Notably, in terms of control of the converter, in grid-tied applications, the task of the control circuit is to shape the average output current, *Io*, into a sinusoidal waveform (see *iN4* in Figure 5), while the controller should regulate the output voltage in stand-alone applications.

**Figure 5.** Illustration of key waveforms of the proposed SSBBI.

#### **4. Analysis and Design Considerations of the Proposed SSBBI**
