**3. Overall Control Strategy**

In this work three decoupled control stages are programmed to regulate the current injected into the grid, the power generated by each PV string and the power mismatch between cells. The first one is the MPPT, which set the DC-link voltage reference for both cells and is optionally included to extract the maximum power from the PV panels in case of direct connection to the 3L-TNPC modules. This control stage is complemented with the total DC-link control loop based on the energy interchange between the power cells. The second control stage is the single-phase voltage-oriented control loop, which has an embedded stationary current control loop implemented with Proportional Multi-Resonant (PMR) controllers. The last control loop is in charge of attenuating the DC-link voltage differences to compensate power mismatch issues among each cell of the converter. The overall control scheme is presented in Figure 4, where *vpvk*, *ipvk*, *vdck* and *sok* are the PV voltage, PV current, DC-link voltage measurement and gating pulses of each *k*-th module.

**Figure 4.** Single-phase voltage-oriented control strategy for the proposed 5L-CTNPC converter.

#### *3.1. MPPT and Outer DC-Link Controller*

The well-known Perturb and Observe (P&O) MPPT routine has been implemented for simplicity in this application. As the analyzed power configuration features two separate DC-links or PV string connections, two independent MPPT algorithms are required to obtain its full power operation. The MPPT routines compute the voltage reference for each DC-link *<sup>v</sup>*<sup>∗</sup>*dc*1 and *<sup>v</sup>*<sup>∗</sup>*dc*2, as illustrated in Figure 4. Then, the DC-link control loop is designed to manage the total energy of the system through the difference between the voltage reference and the voltage measured, i.e., *eT* = *e*1 + *e*2. This total energy is governed by using a proportional-integral (PI) controller, which generates the amplitude of the injected grid current ˆ *is*. Note that the DC-link voltage measurements are acquired and processed with a notch filter *Gf* to eliminate the second harmonic ripple 2*ωs* presented in the DC-link capacitors by the rectification of a single-phase grid voltage. In fact, not filtering this harmonic voltage component will generate an undesired third harmonic 3*<sup>ω</sup>s* component in the grid current reference. The MPPT parameters such as voltage step <sup>Δ</sup>*vpv* and time period *Tk* are designed according with conventional commercial values. In experimental results, the voltage step <sup>Δ</sup>*vpv* = 6 V and the time period *Tk* = 2 s, whereas in simulation results, <sup>Δ</sup>*vpv* = 6 V and the time period is ten times smaller than the experimental results. Furthermore, the DC-link compensator has been designed by using a DC-link control bandwidth of 14Hz. Major details about the outer control design can be found in [20].

## *3.2. PMR Current Control Scheme*

The grid current reference is generated by multiplying the amplitude of the injected grid current ˆ *is* with a unitary sinusoidal signal synchronized to the grid voltage. To avoid voltage measurement noise and low frequency harmonic components, a second order generalized integrator (SOGI) with a synchronous reference frame phase lock loop (SRF-PLL) is implemented to set the synchronous angle. Then, the grid current reference *i*∗*s* is compared with the current measured value *is*, giving rise to a current error which is regulated by using a PMR control scheme. The structure of the implemented controller is included in Figure 5 and expressed as following:

$$C\_i(s) = k\_p + \sum\_{h=1,3,5} \frac{2k\_{ih}s}{s^2 + h^2 \omega\_s^2} \tag{3}$$

where *kp* is the proportional gain and *kih* is the resonant gain at each selected *h*-th harmonic. Note that the above resonant controllers have been considered to achieve selective harmonic impedance enhancement at 3st and 5th components. The resonant frequency at *ωs* is equal to the grid frequency, hence the compensator *Ci*(*s*) has infinite gain at *ωs*, providing perfect sinusoidal tracking with zero steady-state error. The PMR compensator in Figure 5 has been designed by a simple pole placement with a crossover frequency of 270 Hz, which corresponds to a rate twenty times faster than the outer control loop. This control scheme is currently adopted for grid-connected PV systems where the grid voltage has important low-frequency harmonics [28].

**Figure 5.** Stationary current control loop implemented with PMR controllers.

The output of the current control loop set the voltage reference across the grid inductor *<sup>v</sup>*<sup>∗</sup>*L*. Neglecting the voltage drop in the resistance *Rs*, the converter voltage is equal to *vc* = *vL* + *vs*. Commonly, the obtained inverter voltage reference *vc* would be directly connected to the modulation block stage to generate the firing pulses in each semiconductor device. Since the current *is* is the same for both series connected 3L-TNPC converters, the voltage references for each power unit must be modified in advance to allow different power inputs. This important control requirement is performed by including an internal DC-link voltage balance stage, which enables the voltage balancing between capacitors in the DC-link and the power unbalance operation between both cells. In fact, the voltage balancing operation is performed by the DC-link voltage references *<sup>v</sup>*<sup>∗</sup>*dc*1 and *<sup>v</sup>*<sup>∗</sup>*dc*2 naturally delivered by the MPPT algorithm.

#### *3.3. Voltage Balancing Control and Power Balance Scheme*

As mentioned, correct power distribution between both cells and a control strategy to avoid voltage unbalancing in the DC-link capacitors is required to provide full operation in the 5L-CTNPC. The compensation block shown in Figure 6 is separated into two parts. The first one is the DC-link balancing control between cells, whose purpose is to regulate the power mismatch by increasing or decreasing the general modulation index amplitude, also referred to as the normalized inverter voltage *vc* delivered from the current controller. In this control loop, the DC voltage error is regulated by using a PI controller and then the voltage compensator Δ*mc* is multiplied by the normalized inverter voltage reference *vc* [29]. Therefore, the cell with higher power will increase its modulation amplitude, as the cell with lower power reduces its modulation amplitude. The second part of the control loop is given by the voltage balancing between the internal capacitors in the DC-link, where the voltage error is controlled using another PI controller. The output signal of this compensator Δ*md* is added to the modulation index provided by the cell voltage control by moving in the vertical axis the modulation index for capacitor balancing purposes. Both PI controllers have been designed by a pole placement strategy, using a bandwidth of 5 Hz. This dynamic has been imposed to avoid fast disturbances into the modulation signal. Note that the proposed balancing control scheme does not need extra measurements, since they are previously accessible from the outer control stage.

&HOOYROWDJHFRQWURO
