**1. Introduction**

In recent years, the increasing exhaustion of traditional fossil energy has resulted in an emerging interest in the development of renewable energies, one of which is solar energy that has already obtained widespread applications. Among all types of commercial solar energy applications, photovoltaic grid-tied system plays an important role, and large-scale photovoltaic power plants have become dominant [1].

In the large-scale photovoltaic power plants, three-phase single-stage central inverters are widely used because of their many advantages, such as cost-effectiveness, simplicity in hardware design and easy maintenance. The two-level, three-level T-type, and three-level neutral point clamp (NPC) voltage source inverters (VSI) are the most widely used topologies among the current commercial central inverters [2]. Furthermore, to increase the transmission efficiency of the overall electrical equipment, the inverters are generally connected to a medium-voltage (MV) grid of a voltage level from 10 kV to 35 kV. Additionally, multi-parallel inverter topology, in which the inverters are connected in parallel through step-up MV transformers, are commonly used in these systems. A typical commercial application example is 1 MW MV turnkey station, which is composed of two 500 kW central inverters and one 1 MVA MV transformer [3]. Since the transformer is essential for the inverters connected to the MV grid, the multi-parallel inverter topology has the possibility to be reconfigured to the dual-inverter fed open-end winding transformer (denominated here as DI-OEWT) topology.

The dual-inverter topology was first proposed for the motor drive application in [4]. Since then, it has already been extended to many applications, such as STATCOM [5], active power filter [6], dynamic voltage restorer [7], photovoltaic grid-tied inverter [8]. It utilizes dual-inverter structure connected to the open-end windings of an induction motor or a three-phase transformer. Through proper modulation strategy, the harmonic cancellation e ffect can be realized among the two inverters, the dual-inverter topology with two N-level inverters can have the same output voltage levels as a (2N-1)-level inverter [9]. Therefore, lower dv/dt and lower harmonics in the output voltage can be obtained, which can reduce the filter requirement. It can also double the DC voltage utilization. A tdual-N-level inverter with half the DC link voltage (compared to a conventional single inverter scheme) is capable of producing the same AC voltage as a single (2N-1) level inverter, which will reduce the voltage capacity of the power switch devices and decrease the switching losses [10]. What is more, the DC sources requirement of the dual-inverter is minimal over other multilevel topologies [11–13]. The two inverters of the dual-inverter can also be supplied by one single DC source for cost saving [14]. Another merit of the dual-inverter topology is the availability of higher redundant switching state combinations compared to the single inverter, which can be used to achieve switching frequency reduction [15], common-mode voltages suppression [16], capacitor voltage balance [17]. Furthermore, it also o ffers the advantage of fault tolerance. In case of a fault in the inverter, the inverter can still work with some adjustment [18–20].

However, the advantages of the dual-inverter topology described above are not all applicable to the topology used in photovoltaic grid-tied applications. Firstly, the DC bus voltage is limited to the photovoltaic array voltage, which is usually 1000 V or 1500 V (open-circuit voltage). It is uneconomic to reduce this voltage because that will increase the system installation costs and narrow the maximum power point tracking (MPPT) voltage operation range [2]. In addition, it will be better for the dual-inverter to be supplied by two separate arrays (two DC sources), which can not only achieve multiple MPPTs, but also suppress the circulating current among the two inverters [21,22]. The fault tolerance capability cannot be a special advantage of the dual-inverter because the multi-parallel inverter topology has the same capability as well. To sum up, compared with the conventional multi-parallel inverter topology, the most attractive advantage of the DI-OEWT topology is the improvement of the harmonic quality in the output voltages, thus can reduce the filter requirement and save the filter costs.

However, there are few papers considering the selection or design of the filters used in DI-OEWT-based grid-tied applications at present. In [23–28], single inductor filter was adopted in these DI-OEWT based grid-tied systems, which is obviously not a good choice. Owing to the weak harmonic suppression capability, it needs a large inductance value to meet the grid standard. To reduce the inductance cost, high order filter is preferred [29]. In [30], two kinds of high order filters for DI-OEWT topology were proposed. One is the "individual capacitor type filter", that the two inverters of the DI-OEWT topology are connected to the open-end windings of the transformer through two individual inductor-capacitor filters. The other one is the "common capacitor type filter", which is also presented in [21,22], that the two inverters are connected to the open-end windings of the transformer through two individual inductors but one common capacitor. However, the authors in [30] were mainly focused on active damping methods of the two di fferent filters, and the authors in [21,22] were mainly focused on the magnetic integration design of the filter inductors, none of these papers analyzed the harmonic suppression capability or the parameter design method of these filters.

In addition, the transformer's leakage inductance is a significant component of the filter, and for the transformer used in the high power MV grid-tied system, the value is usually no less than 6% [31]. This is a relatively big value and should be used properly in the selection and design of the filter, but none of the present literatures has paid attention to this. Another point deserves to be considered is the fault tolerance scheme of the DI-OEWT topology, which is very important for such multi-inverter type topology.

In light of the above, this paper aims to research the filters for the DI-OEWT topology used in photovoltaic grid-tied applications. First, the equivalent circuits of the existing two kinds of high order filters presented in [21,22,30] are derived, and based on this, the harmonic suppression capabilities of these filters are analyzed and compared. According to the analysis results, a new high order filter for DI-OEWT topology is also proposed. Furthermore, a brief parameter design method of the existing and the proposed filters for DI-OEWT is introduced and based on the design examples, the inductance and capacitance requirements of these filters are compared. Besides, these filters are also evaluated in terms of the applicability for fault tolerance.

The rest of the paper is organized as follows: The inductor-capacitor-inductor (LCL) filter used in multi-parallel inverters is presented in Section 2 as the comparison object. The model and harmonic suppression capability analysis of the existing and the proposed filters for DI-OEWT topology are shown in Section 3. The filter design method, together with the design examples, as well as the fault-tolerant scheme, are presented in Section 4. Experimental results are given in Section 5 to validate the filter parameters. Finally, the conclusions are summarized in Section 6.

#### **2. LCL Filter for the Conventional Multi-Parallel Inverters**

The system configuration of the conventional multi-parallel inverters used in photovoltaic applications is illustrated in Figure 1. The two inverters are connected in parallel to the low voltage side of the MV transformer through individual LC filters. The leakage inductance *Lt* of the transformer and the grid inductance *Lg* play the role of the grid-side filter inductor, so the two inverters can also be viewed as connecting in parallel through individual LCL filters.

**Figure 1.** System configuration of the conventional multi-parallel inverters.

It is essential to derive the equivalent circuit of the filter based VSI for the filter design and harmonic suppression capability analysis. Since the LCL filter used in parallel inverters has no difference with that used in single inverters, the single-phase equivalent circuit of the LCL filter can be directly obtained from many existing papers [32,33], as shown in Figure 2. In the figure, the equivalent circuit is drawn referred to the low-voltage side of the transformer, *v*inv1 and *i*inv1 (take inverter 1 as an example) are the inverter output phase voltage and current, respectively. *<sup>v</sup>*g and *i*g are the grid voltage and current, respectively. The inverter-side inductor is represented as *L*1, the combined inductance of the transformer leakage inductance *L*t and the grid inductance *L*g are represented as *L*2, and the filter capacitor is represented as *C*.

**Figure 2.** Single-phase equivalent circuit of the LCL filter.

While the inverter is working, the harmonics in *i*inv1 should be suppressed by the filter to limit the current ripple, and the harmonics in *i*g should be suppressed to meet the grid standard [34]. Assuming that no harmonics exist in the grid voltage, the inverter output voltage *v*inv1 is the only harmonic source of the system, then the transfer functions *v*inv1(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) can be used to reflect the harmonic suppression capability of the LCL filter, as shown in Equations (1) and (2), respectively

$$i\_{\rm g}(s) = \frac{1}{L\_1 L\_2 \rm C s^3 + (L\_1 + L\_2)s} v\_{\rm inv1}(s) \tag{1}$$

$$i\_{\rm inv1}(\mathbf{s}) = \frac{L\_2 \mathbf{C} \mathbf{s}^2 + 1}{L\_1 L\_2 \mathbf{C} \mathbf{s}^3 + (L\_1 + L\_2)\mathbf{s}} v\_{\rm inv1}(\mathbf{s}) \tag{2}$$

where *L*2 = *L*t + *<sup>L</sup>*g. The value of *L*t and *L*g is related to the transformer impedance voltage *V*k and the grid short-circuit ratio (SCR), respectively [35]. Therefore, *L*2 can be calculated as

$$L\_2 = \frac{3v\_\text{g}^2}{2\pi f\_0 P\_{\text{rated}}} V\_\text{k} + \frac{3v\_\text{g}^2}{2\pi f\_0 P\_{\text{rated}} \text{SCR}} = \frac{3v\_\text{g}^2}{2\pi f\_0 P\_{\text{rated}}} \left(V\_\text{k} + \frac{1}{\text{SCR}}\right) \tag{3}$$

where *P*rated is the system rated power, *f* 0 is the fundamental frequency.

#### **3. Existing and Proposed Filters for the DI-OEWT Topology**

#### *3.1. Type-1 Filter for the DI-OEWT Topology*

Direct replacing of the two-winding transformer in the multi-parallel inverter topology (as shown in Figure 1) with the open-end winding (OEW) transformer, can obtain the DI-OEWT topology with the "individual capacitor type filter" (here we call it "Type-1 filter"). The filter was proposed in [30], as illustrated in Figure 3. It is worth noting that the voltage of the low-voltage side of the OEW transformer is twice the voltage of the replaced transformer, since the AC sides of the two inverters are connected in series through the low-voltage side of the transformer [8]. Accordingly, the current level of the inverter remains unchanged, so the multi-parallel inverter topology can be easily reconfigured to the DI-OEWT topology.

**Figure 3.** System configuration of the dual-inverter fed open-end winding transformer (DI-OEWT) topology with the Type-1 filter.

To analyze the Type-1 filter, firstly, the three-phase equivalent circuit of the DI-OEWT topology with the Type-1 filter is derived in Figure 4. The voltage source *V*X1O1 and *V*X2O2 represent the pole voltage of phase *X*1 of inverter 1 and the pole voltage of phase *X*2 of inverter 2, respectively (*X* = *A*, *B*, *C*). In a balanced and symmetrical three-phase system, for inverter 1, a common-mode (CM) voltage exists between the neutral point *O*1 and the capacitor common point *N*c1, this CM voltage is expressed as *V*O1Nc1 = −1/3(*V*A1O1 + *V*B1O1 + *V*C1O1). Similarly, the corresponding CM voltage of inverter 2 is

expressed as *V*O2Nc2 = −1/3(*V*A2O2 + *V*B2O2 + *V*C2O2). According to Kirchhoff's voltage law (KVL), the voltage across the two capacitor common points *N*c1, *N*c2 can be derived as

$$V\_{\rm Nc1Nc2} = \frac{1}{3} \begin{bmatrix} -(V\_{\rm CA1} + V\_{\rm CB1} + V\_{\rm CC1}) + (V\_{\rm CA2} + V\_{\rm CB2} + V\_{\rm CC2}) \\ + (V\_{\rm L\sigma1A} + V\_{\rm L\sigma1B} + V\_{\rm L\sigma1C}) + (V\_{\rm tA1} + V\_{\rm tB1} + V\_{\rm tC1}) \end{bmatrix} \tag{4}$$

**Figure 4.** Three-phase equivalent circuit of the DI-OEWT topology with the Type-1 filter.

The voltage across the neutral point *N*t of the transformer high voltage side and the neutral point *<sup>N</sup>*g of the three-phase grid can be derived as

$$V\_{\rm NtNg} = \frac{1}{3} \begin{bmatrix} (V\_{\rm tA2} + V\_{\rm tB2} + V\_{\rm tC2}) + (V\_{\rm L\sigma2A} + V\_{\rm L\sigma2B} + V\_{\rm L\sigma2C}) \\ + (V\_{\rm LgA} + V\_{\rm LgB} + V\_{\rm LgC}) + (\upsilon\_{gA}' + \upsilon\_{gB}' + \upsilon\_{gC}') \end{bmatrix} \tag{5}$$

In Equations (4) and (5), *V*CX1 and *V*CX2 represent the voltage on the filter capacitor of phase *X*1 and phase *X*2, respectively. *V*Lσ1X and *V*Lσ2X represent the phase *X* voltage on the leakage inductance at low voltage side (*L*σ1) and high voltage side (*L*σ2) of the MV transformer, respectively. *<sup>V</sup>*LgX represents the phase *X* voltage on the grid inductance *L*g. *V*tX1 and *V*tX2 represent the voltage of the low and high voltage side of the MV transformer, respectively. *v*gX is the phase *X* voltage of the MV grid. Considering only the line frequency component and the balanced three-phase system, it is easy to deduce that *V*Nc1Nc2 = 0 and *<sup>V</sup>*NtNg = 0. Thus, *N*c1 can be connected to *N*c2 and *N*t can be connected to *<sup>N</sup>*g. Then, the single-phase equivalent circuit of the DI-OEWT topology with the Type-1 filter can be derived as shown in Figure 5 with further simplification. Where the inverter 1 output phase voltage *v*inv1 = *V*A1O1 + *V*O1Nc1, the inverter 2 output phase voltage *v*inv2 = *V*A2O2 + *V*O2Nc2, *i*inv1 and *i*inv2 represent the output phase current of inverter 1 and inverter 2, respectively.

**Figure 5.** Single-phase equivalent circuit of the DI-OEWT topology with the Type-1 filter.

From Figure 5, the transfer functions *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) can be, respectively, calculated as

$$i\_{\rm g}(s) = \frac{1}{L\_1 L\_2 \text{Cs}^3 + (2L\_1 + L\_2)s} [v\_{\rm inv1}(s) - v\_{\rm inv2}(s)] \tag{6}$$

$$i\_{\rm inv1}(s) = G\_1(s)v\_{\rm inv1}(s) - G\_2(s)v\_{\rm inv2}(s) \tag{7}$$

where

$$i\_{\rm inv1}(s) = G\_1(s)v\_{\rm inv1}(s) - G\_2(s)v\_{\rm inv2}(s)$$

$$G\_2(s) = \frac{1}{L\_1^2 L\_2 C^2 s^5 + \left(2L\_1^2 C + 2L\_1 L\_2 C\right) s^3 + (2L\_1 + L\_2)s}$$

Figure 6a shows Bode plots of the transfer function *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) of both the LCL filter and the Type-1 filter, while the inverter-side inductor *L*1, capacitor *C*, impedance voltage *V*k and SCR are all the same in both filters. Figure 6b presents Bode plots of the transfer function *v*inv1(*s*), *v*inv2(*s*) to *i*inv(*s*) with the aforementioned parameters. According to Figure 6 and Equations (1), (2), (6), (7), the following can be obtained.

**Figure 6.** Bode plots of transfer function *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) in LCL and Type-1 filters (**a**) *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*), (**b**) *v*inv1(*s*), *v*inv2(*s*) to *i*inv1(*s*).

(1) Figure 6a suggests that, for *i*g, Type-1 filter has superior high-frequency harmonic suppression capabilities than the LCL filter. Meanwhile, compare Equation (6) with (1), the harmonic source of *i*g in DI-OEWT topology is *v*inv1 − *v*inv2, while in multi-parallel inverter topology is *v*inv1. Owing to the harmonic cancellation effect in the output voltage of DI-OEWT, *v*inv1 − *v*inv2 has lower harmonics than *v*inv1. Thus, *i*g in DI-OEWT can achieve a much better current quality than the multi-parallel inverter topology. Conversely, Type-1 filter can reduce filter requirement than LCL filter. Since *L*2 is limit by the *V*k and SCR, which cannot be reduced, so *L*1 or *C* may be reduced.

(2) From Equation (7), for the inverter output phase current *i*inv1, *G*1(*s*) and *G*2(*s*) can reflect the suppression capability of the Type-1 filter on *v*inv1 and *v*inv2, respectively. From Figure 6b, in the high-frequency band, the harmonics attenuation rate of *G*2(*s*) is −60 dB/dec, way above the harmonics attenuation rate of *G*1(*s*), which is −20 dB/dec. Therefore, the harmonic source of *i*inv1 in DI-OEWT topology is mainly the *v*inv1, the same as the voltage in multi-parallel inverter topology according to Equation (2). Meanwhile, the harmonics attenuation rate of LCL filter is also −20 dB/dec, thus, *i*inv1 of both the scheme has almost the same current quality. Because the current ripple of *i*inv1, which is mainly suppressed by inverter-side inductor *L*1, is strictly limited by the semiconductor current rating and loss requirement. Therefore, *L*1 of Type-1 filter cannot be reduced.

In summary, compared with the multi-parallel inverter topology, the DI-OEWT topology with Type-1 filter can only reduce the value of filter capacitor *C*, showing that the Type-1 filter maybe not a better solution for the DI-OEWT topology.

Another way to explain why the Type-1 filter has the above characteristics can be shown as follows. Firstly, the reason why the DI-OEWT topology can achieve multilevel output and lower harmonics in output voltages is the harmonic cancellation effect between the two inverters. However, the two individual sets of shunt capacitors of the Type-1 filter break this cancellation loop. Some high-frequency harmonics, which should have been canceled, flow through these capacitors, leading to the increase of filter burden. In other words, Type-1 filter does not make judicious use of the merit of the DI-OEWT topology.

#### *3.2. Type-2 Filter for the DI-OEWT Topology*

The above analysis suggests that the special working characteristic (the harmonic cancellation characteristic) of the DI-OEWT topology should be considered when designing the filter. The "common capacitor type filter" (here we call it "Type-2 filter") for DI-OEWT topology, which is presented in [21,22], seems to be a reasonable one, as illustrated in Figure 7. Two inverters are connected to a common shunt capacitor branch of the filter through the two inverter-side inductors, respectively. Then, the harmonic cancellation of the dual-inverter can be realized through the common capacitor branch. This common capacitor branch can be seen as the series connection of the two individual capacitor branches of the Type-1 filter, and the voltage rating of the former is the twice of the latter, so the actual value of the capacitor in Type-2 filter is half the value in Type-1 filter when the two has the same per unit (p.u.) value. Therefore, the capacitor here is represented as *C*/2.

**Figure 7.** System configuration of the DI-OEWT topology with the Type-2 filter.

Figure 8 shows the three-phase equivalent circuit of the DI-OEWT topology with the Type-2 filter. With the same derivation method as described in Section 3.1, we can ge<sup>t</sup> the corresponding single-phase equivalent circuit as illustrated in Figure 9. From the figure, the transfer functions *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) can be, respectively, calculated as

$$\dot{v}\_{\rm g}(\mathbf{s}) = \frac{1}{L\_1 L\_2 \mathbf{C} \mathbf{s}^3 + (2L\_1 + L\_2)\mathbf{s}} [v\_{\rm inv1}(\mathbf{s}) - v\_{\rm inv2}(\mathbf{s})] \tag{8}$$

$$i\_{\rm inv1}(s) = \frac{(L\_2\mathbb{C}/2)s^2 + 1}{L\_1L\_2\mathbb{C}s^3 + (2L\_1 + L\_2)s} [v\_{\rm inv1}(s) - v\_{\rm inv2}(s)] \tag{9}$$

**Figure 8.** Three-phase equivalent circuit of the DI-OEWT topology with the Type-2 filter.

**Figure 9.** Single-phase equivalent circuit of the DI-OEWT topology with the Type-2 filter.

It can be found from Equations (8) and (9) that the harmonic source of *i*g and *i*inv1 are all *v*inv1 − *v*inv2, proves once again that the Type-2 filter does make judicious use of the merit of the DI-OEWT topology.

Figure 10 shows the bode plots of the transfer functions *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) of both the LCL filter and the Type-2 filter (with the same corresponding parameters), respectively. The figures sugges<sup>t</sup> that, for both *i*g and *i*inv1, Type-2 filter has superior high-frequency harmonic suppression capabilities than the LCL filter. That can lead to a decreasing in the total inductance, capacitance, and volume. Therefore, the Type-2 filter can be an option for the DI-OEWT topology.

**Figure 10.** Bode plots of transfer functions *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) in LCL filter and Type-2 filter. (**a**) *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*), (**b**) *v*inv1(*s*), *v*inv2(*s*) to *i*inv1(*s*).

Furthermore, look again at Figure 9, it shows that the two inverter-side inductors *L*1 of the two inverters are actually connected in series, so these two inductors can merge into one single inductor, further reducing the volume and cost due to the saving of inductor magnetic cores. In this case, the complex magnetic integration method for reducing the inverter-side inductors' magnetic component size, which was proposed in [22], is actually unnecessary.

#### *3.3. The Proposed Type-3 Filter for the DI-OEWT Topology*

According to the above analysis of the existing filters for DI-OEWT topology, only Type-2 filter is suitable because its structure is fit for the working characteristic of the DI-OEWT topology. However, the leakage inductance of the transformer, which is a relatively large value in a high-power MV transformer, has not go<sup>t</sup> special attention and rational utilization.

In Section 3.1, we have mentioned that the voltage of the low-voltage side of the OEW transformer is the twice of the replaced transformer. Then, it can be easy to deduce from Equation (3) that the leakage inductance of OEW transformer is four times as the replaced one (referred to the low-voltage side). Setting such a large inductance as the grid-side inductor may be not a cost-saving solution.

Therefore, in this paper, a new high order filter (here we call it "Type-3 filter") for DI-OEWT topology is proposed, as illustrated in Figure 11. The two inverters are directly connected to the low-voltage side of the OEW transformer, the shunt capacitor *<sup>C</sup>*H and grid-side inductor *<sup>L</sup>*H are set at the high voltage side of the OEW transformer. In this filter, the harmonic cancellation effect of the

DI-OEWT can be realized through the transformer, without any other shunt branch. The transformer leakage inductance *L*t is used as the inverter-side inductor of the filter. If the initial value of *L*t is not enough to suppress the inverter-side current ripple, it can be increased just by increasing the impedance voltage *V*k of the transformer.

**Figure 11.** System configuration of the DI-OEWT topology with the Type-3 filter.

With the similar derivation method described above, here we directly give the single-phase equivalent circuit of the DI-OEWT topology with the Type-3 filter, as shown in Figure 12, where *C*H and *L*H represent the shunt capacitor and grid-side inductor referred to the low-voltage side, respectively.

**Figure 12.** Single-phase equivalent circuit of the DI-OEWT topology with the Type-3 filter.

From Figure 12, the transfer functions *v*inv1(*s*), *v*inv2(*s*) to *<sup>i</sup>*g(*s*) and *i*inv1(*s*) can be, respectively, calculated as

$$i\_{\mathbb{S}}(s) = \frac{1}{(L\_t L\_2 \mathbb{C}\_{\mathbb{H}})s^3 + (L\_t + L\_2)s} [v\_{\text{inv1}}(s) - v\_{\text{inv2}}(s)] \tag{10}$$

$$i\_{\rm inv1}(s) = \frac{L\_2 C\_{\rm H} s^2 + 1}{L\_4 L\_2 C\_{\rm H} s^3 + (L\_1 + L\_2)s} [v\_{\rm inv1}(s) - v\_{\rm inv2}(s)] \tag{11}$$

As can be seen from comparing Figures 9 and 12, the equivalent circuit of the Type-3 and Type-2 filter are actually the same, while the difference between them is the role of the leakage inductance of the OEW transformer. Due to this difference, the extra required capacitance and the inductance value of the two filters may be different. This different value should be compared with specific examples, which will be presented in the following section.

#### **4. Parameter Design and Evaluations of the Filters**

#### *4.1. Parameter Design of the Filters*

The design procedure of the Type-3 filter, together with the Type-1 and Type-2 filters, for the DI-OEWT topology is covered in the following. First, a 30 kW OEW dual-three-level (D3L) inverter, with 5 kHz switching frequency, 460 V~850 V (MPPT lower and upper limit voltage) DC voltage, 380 V line-to-line grid voltage is adopted. The primary side of the transformer is set as the OEW structure, and the secondary side of the transformer is connected in delta. It is worth noting that the primary side line-to-line voltage of the transformer in conventional multi-parallel inverter topology is usually 315 V, so the phase voltage ratio of the OEW transformer used here is 364 V/380 V, where 364 V = 2 × 315 V/1.732. In the following, the filter components calculations are presented on a per-unit basis, and the corresponding base values are listed in Table 1.


**Table 1.** Per-unit base values of the system.

*(1) Inverter-side Inductor:* The inverter-side inductor value is determined by the requirement of the inverter-side current ripple, owing to the semiconductor current rating and efficiency requirement, this current ripple must be limited within a certain range. Besides, the equation for calculating the inductor value is related to the inverter topology as well as the modulation strategy, here the D3L inverter is modulated by the decoupled SVPWM strategy [17].

The decoupled SVPWM strategy has the characteristic that the total reference voltage signal is divided into two opposite parts for the two constituent inverters, and each of the inverter is switched independently of the other with the standard SVPWM strategy. Such characteristic is very appropriate for the two inverters tracking the individual MPPs. The space vector diagram of the individual three-level inverters is shown in Figure 13. In Figure 13, under the decoupled SVPWM strategy, the reference voltage space vector of the two inverters *V***r1** and *V***r2** are synthesized by the nearest three voltage vectors {*V***0**, *V***1**, *V***2**} and {V0, V3, V4}, respectively. The pulse sequence is symmetrical with seven pieces of segments in each switching cycle *T*s and the dwell times for each of the voltage vectors satisfy the following expression.

$$\begin{cases} \mathbf{V\_0}T\_0 + \mathbf{V\_1}T\_1 + \mathbf{V\_2}T\_2 = \mathbf{V\_{r1}}T\_s\\ \mathbf{V'\_0}T'\_0 + \mathbf{V'\_3}T'\_3 + \mathbf{V'\_4}T'\_4 = \mathbf{V\_{r2}}T\_s \end{cases} \tag{12}$$

**Figure 13.** Space vector diagram of the individual three-level inverters. (**a**) Inverter 1, (**b**) inverter 2.

The peak to peak value of the inductor current ripple is defined by volt-seconds applied to the inductor over the switching period [32,35]. For Type-1 filter, as mentioned in Section 3.1, the harmonic source of the inverter-side current is mainly the output phase voltage of one inverter. Take inverter 1 as an instance, the maximum current ripple occurs when the zero vector *V***0** dwell time *T*0 = 0, and the other two vectors *V***1** and *V***2** equally divide the switching period, *T*1 = *T*2 = *T*s/2. In such case, the modulation index M = 1/ √3 and the DC voltage of the inverter is slightly larger than the MPPT upper limit voltage, the reference voltage vector *V***r1** is in the midway between *V***1** and *V***2**. The pulse sequence is degenerated into five pieces of segments and the corresponding inductor voltage and current waveform (take phase A1 as an example and *v*L1 ≈ *v*inv1) are shown in Figure 14.

**Figure 14.** Phase A1 inductor voltage and current waveform.

According to the volt-second balance principle, the following expression can be go<sup>t</sup> as:

$$L\_1 \Delta i\_{\text{max}} = \frac{v\_{\text{dc1}}}{6} \frac{T\_s}{4} \tag{13}$$

where Δ*i*max is the maximum current ripple.

From Equation (13), the minimum inverter-side inductor value of the Type-1 filter can be estimated by

$$L\_{1\text{min}} = \frac{v\_{\text{dc1}}}{24\Delta i\_{\text{max}} f\_{\text{s}}} \tag{14}$$

where *f* s = 1/*T*s is the switching frequency.

For Type-2 and Type-3 filter, the harmonic source of the inverter-side current is the difference between the output phase voltage of the two inverters (*<sup>v</sup>*inv1 – *v*inv2). The maximum current ripple will occur in the case that the reference voltage vector *V***r1** is in the midway between *V***1** and *V***2**, *V***r2** is in the midway between V3 and V4. In this case, *T*0 = *T*0 = 0, *T*1 = *T*2 = *T*3 = *T*4 = *T*s/2. For the convenience of analysis, assuming *v*dc1 = *v*dc2 = *v*dc, then the inverter-side inductor voltage and current waveform of the Type-2 and Type-3 filter can be roughly derived as shown in Figure 15 (take phase A1-A2 as an example and *v*L ≈ *v*inv1 – *v*inv2).

Accordingly, the minimum inverter-side inductor value of the Type-2 and Type-3 filter can be derived based on the volt-second balance across the inductor as

$$L\_{\rm min} = \frac{v\_{\rm dc}}{12 \Delta i\_{\rm max} f\_{\rm s}} \tag{15}$$

where *L* = 2*L*1 for Type-2 filter and *L* = *L*t for Type-3 filter.

For the values *v*dc = 850 V, *f* s = 5000 Hz, and about 15% current ripple, the estimated minimum inverter-side inductor value for each filter can be calculated according to Equations (14) and (15) as follows:

Type-1 filter: two 0.02845 p.u. inductor;

Type-2 filter: one 0.0569 p.u. inductor;

Type-3 filter: transformer leakage inductance, 0.06 p.u..

**Figure 15.** Phase A1-A2 inductor voltage and current waveform.

*(2) Grid-side Inductor and Shunt Capacitor:* The grid-side inductor and shunt capacitor together constitute a shunt network to suppress the grid current harmonics, so as to satisfy the standard. For example, recent published Chinese standard NB/T 32004-2018 [34] requires the harmonics greater than 35th should be less than 0.3% of the 30% of the rated fundamental current. Besides, the capacitor value is limited to the maximum absorbed reactive power at rated load and typically less than 5%. Moreover, the resonant frequency ωres of the filter is often chosen as Equation (16) with the intention of not creating resonance problem in the lower and higher parts of the harmonic spectrum.

$$0.10 \times 2\pi f\_{\rm B} \le \omega\_{\rm res} \le 0.5 \times 2\pi f\_{\rm s} \tag{16}$$

where the value of ωres is (2*L*1 + *<sup>L</sup>*2)/*L*1*L*2*<sup>C</sup>* for Type-1, Type-2 filter and (*<sup>L</sup>*t + *<sup>L</sup>*2)/*L*t*L*2*C*H for Type-3 filter.

For Type-1 and Type-2 filter, the grid-side inductor value is limited by the transformer leakage inductance, and its value is 0.06 p.u. (neglect the grid inductance). The capacitor values of these two filters are computed considering the attenuation of the filter. For instance, the maximum harmonic of the grid current greater than 35th usually occurs around the switching frequency. To limit the maximum current harmonic lower than 0.3%, the capacitor value of these two filters can be computed from Equations (6) or (8) considering the most dominant harmonic *V*(*h*) around the switching frequency in the inverter output voltage spectrum as

$$C \ge \frac{2\pi f\_{\rm B} h (2L\_1 + L\_2) \frac{I\_{\rm B} \times \sqrt{2} \times 30\% \times 0.3\%}{V(h)} + 1}{L\_1 L\_2 (2\pi f\_{\rm B} h)^3 \frac{I\_{\rm B} \times \sqrt{2} \times 30\% \times 0.3\%}{V(h)}}\tag{17}$$

where *h* is the most dominant harmonic order. For D3L inverter with the decoupled SVPWM, if the DC voltage and the power (or the modulation index) of the two inverters are all the same, the harmonic around the switching frequency can be totally cancelled. But when the two inverters are tracking the individual MPPs, the DC voltage and the power (or the modulation index) of the two inverters may be different, this total cancellation cannot be realized. Assuming the worst case that no harmonic

cancellation occurs around the switching frequency harmonics, the most dominant harmonic order *h* = *m*f − 2, the value of the (*<sup>m</sup>*f − 2) order harmonic can be go<sup>t</sup> from simulation on a single three-level inverter as *V*(*<sup>m</sup>*f − 2) ≈ 0.055 p.u. (20.2 V), where *m*f is the modulation frequency index, and the value here is 100 (5000 Hz/50 Hz). Then from Equation (17) a minimum value of *C* can be calculated as 0.0175 p.u. Considering the constraints illustrated in Equation (16) and taking a certain margin, the final capacitor value of Type-1 and Type-2 filter is chosen as 0.0208 p.u.

For Type-3 filter, both the grid-side inductor and the shunt capacitor need to be designed. Usually, we choose a larger capacitor to reduce the requirement of the grid-side inductor for saving cost. Here the capacitor is starting with the value as 0.0416 p.u. With the same methodology as above, to ensure the grid current to satisfy the harmonic requirement, the grid-side inductor value can be computed from Equation (10) as

$$L\_2 \ge \frac{2\pi f\_\text{B} h l L\_t \frac{I\_\text{B} \times \sqrt{2} \times 30 \% \times 0.3 \%}{V(h)} + 1}{2\pi f\_\text{B} h \left[ L\_t \mathbb{C} \left[ 2\pi f\_\text{B} h \right]^2 - 1 \right] \frac{I\_\text{B} \times \sqrt{2} \times 30 \% \times 0.3 \%}{V(h)}}\tag{18}$$

Also, considering the value of the most dominant harmonic order *V*(*<sup>m</sup>*f − 2) ≈ 0.055 p.u., a minimum value of *L*2 can be calculated as 0.0218 p.u.. Considering (16) and taking a certain margin, the final value of *L*2 is selected as 0.0237 p.u.

#### *4.2. Fault-Tolerant Configuration for DI-OEWT Topology*

Like the multi-parallel inverter topology, one of the advantages of the DI-OEWT topology is the availability of fault-tolerant operation. Many papers have investigated the fault-tolerant method for the dual-inverter topology used in motor drives, such as hybrid modulation strategies [18], dual-inverter topology reconfiguring method [19], fault-tolerant direct thrust force control method [20]. However, these methods are not suitable for the DI-OEWT topology used in photovoltaic applications, due to the DC voltages and power of the two inverters in such case are often different for the separate MPPT purpose.

To realize fault-tolerant operation in these systems, a more reasonable way is to cut off the fault inverter while allowing the healthy inverter to continue working. However, only one inverter cannot supply the whole voltage of the transformer due to the DC voltage limit, so the OEW transformer need to be reconfigured. Figure 16 presents a possible configuration to achieve the above purpose. As shown in the figure, a center-tapped (at the low voltage side) OEW transformer is used here, S1 and S2 are the contactors of the respective inverters connecting to the open-end windings of the transformer, S3 is the contactor to short the three-phase center-taps. In case of a fault in one inverter, the corresponding contactor (S1 or S2) of the fault inverter is switched <sup>o</sup>ff, and contactor S3 is switched on, then half of the primary windings are connected in star across the healthy inverter. The healthy inverter only needs to supply half of the original AC voltage, so that it can still work properly without any change.

**Figure 16.** Fault-tolerant configuration of the DI-OEWT topology.

Nevertheless, considering the configurations of the filters described above, not all types of filters are applicable for the presented fault-tolerant scheme. For DI-OEWT topology with the Type-1 and the proposed Type-3 filter, when a fault occurs in one inverter, the healthy inverter can still work through the modified filter. While for DI-OEWT topology with the Type-2 filter, fault-tolerant operation cannot be realized because the shunt capacitor cannot decouple from the faulty inverter.
