**3. General Design Guidelines**

## *3.1. Selection of Passive Components*

The passive element values of the QZS network for both cases were estimated according to the guidelines [6] based on the same approach that includes High-Frequency (HF) and Low-Frequency (LF) ripple analysis. The HF ripple of the input current was taken into account as follows:

$$L\_1 \ge \frac{V\_{OUT}^2 \cdot (1 - 2 \cdot D\_s)}{2 \cdot (1 - D\_s) \cdot K\_{LHI1} \cdot P\_{OUT}} \cdot T\_s \cdot D\_{s\prime} \tag{1}$$

where L1 is the value of QZS network inductance, VOUT is the output voltage, DS is the duration of ST state, TS is the switching period, KLH1 is an assumed HF ripple of input current, and POUT is the output power. The main peculiarities of the calculation and selection process are as follows.

For the 3L NPC QZSI for appropriate inductances L1, L2, L3, L4 chosen according to Equation (1), we assumed the max HF ripple to be limited to 10%, which means KLH1 = 0.1. For the output voltage VOUT = 230 V and max DS = 0.225, the switching period Ts = 1/fs = 1/65 kHz and output power Pout = 900 W. According to Equation (1), it gives us the minimal value of L1 = 0.72 mH.

Since it is a minimal possible value (which provides boundary conduction mode), and assuming possible variation of the inductance under the temperature and other impacts, the value of 0.9 mH was chosen to assure the Continuous Conduction Mode (CCM).

For this value, according to Equation (2), the HF current ripple should be 8%.

$$K\_{LH1} = \frac{\Delta I\_{L1}}{2 \cdot I\_{IN}} \approx \frac{V\_{OUT}^2 \cdot (1 - 2 \cdot D\_S)}{2 \cdot (1 - D\_S) \cdot L\_1 \cdot P\_{OUT}} \cdot T\_S \cdot D\_{S\prime} \tag{2}$$

Since inductances in the 3L NPC QZSI are connected in series, the equivalent inductances for the 2L QZSI could be assumed as L1 = L1+L4, L2 = L2 + L3. Thus, equivalent inductances of 1.8 mH were chosen for the 2L QZSI. For QZS capacitances C1 and C2, we assumed the voltage ripple to be limited to 2% and 1% correspondingly:

$$K\_{\rm CL1} = \frac{\overleftarrow{\upsilon}\_{\rm C1}}{V\_{\rm C1}} = \frac{8 \cdot P\_{\rm OUT} \cdot (1 - D\_{\rm S}) \cdot (4\pi \cdot T \cdot L\_2 + R \cdot T^2)}{3\pi \cdot V\_{\rm OIT}^2 \cdot D\_{\rm S} \cdot \sqrt{16\pi^2 \cdot C\_1^2 \cdot R^2 + (16\pi^2 \cdot C\_1 \cdot L\_2 - T^2)^2}}\tag{3}$$

$$K\_{\rm CL2} = \frac{\stackrel{\leftarrow}{\upsilon}\_{\rm C2}}{V\_{\rm C2}} = \frac{8 \cdot P\_{\rm OUT} \cdot \left(4\pi \cdot T \cdot L\_1 + R \cdot T^2\right)}{3\pi \cdot V\_{\rm OUT}^2 \cdot \sqrt{16\pi^2 \cdot \text{C}\_2^2 \cdot \text{R}^2 + \left(16\pi^2 \cdot \text{C}\_2 \cdot L\_1 - T^2\right)^2}}\tag{4}$$

According to Equations (3) and (4), the minimal values C1 = 1000 μF and C2 = 233 μF were selected. Taking into account the maximal RMS current of the capacitors and decreasing the capacitance under the voltage near to the maximal rated level and the temperature impact, the electrolytic capacitances were chosen as C1 = 2700 μF and C2 = 860 μF.

At the same time, one can assess the LF ripple according to Equation (5), which for the chosen value of 0.9 mH, C2 = 860 μF gives us the level of 25%:

$$K\_{LL1} = \frac{\Delta I\_{L1}}{I\_{IN}} \approx \frac{\Delta I\_{L1} \cdot V\_{IN}}{P\_{OUT}} \approx \frac{8 \cdot (1 - 2 \cdot D\_S) \cdot T^2}{2\pi \cdot (1 - D\_S) \cdot \sqrt{16\pi^2 \cdot C\_2^2 \cdot R^2 + \left(16\pi^2 \cdot C\_2 \cdot L\_1 - T^2\right)^2}},\tag{5}$$

Since the capacitances C1, C4, and C2, C3 in the 3l NPC QZSI are connected in the series under ST, the equivalent capacitance of the asymmetrical QZS network will be twice lower. Thus, taking into account maximal possible voltages, the electrolytic capacitances of C1 = 1200 μF and C2 = 680 μF were chosen for the 2L QZSI topology, which is summed up in Table 3.

It should also be mentioned, that in the 3l NPC QZSI prototype, capacitances C1 and C4 were physically installed as a combination of parallel connection of 1200 μF and 1500 μF, while capacitances C2 and C3 were combined as 390 μF and 470 μF in parallel connection.

For the standalone application (off-grid), the simplest L or LC filter could be used. The application of an LC filter could also provide better efficiency due to the fewer losses. However, since the case study of the PV system is considered for grid-connected applications, we used the LCL filter in both cases. This provides better stability in the grid-connected mode.

The values of the passive components of the output filter were assessed and chosen based on the classical approach, which is reported in Reference [42]. Thus, for both converters the same output LCL filters were chosen with LF1 = 560 μH, CF = 15 μF, and LF2 = 200 μH.

#### *3.2. Selection of Semiconductor Devices and Heatsinks*

The main difference in the proposed solutions was observed during the selection of semiconductor devices. The peak voltage across the QZSI bridge is increasing with the input voltage decreasing. It is explained by the necessity of ST implementation that deteriorates the DC-link voltage utilization. Thus, 1200 V SiC power switches should be used in the 2L QZSI solution for the case study system. To overcome this limitation, the 3l NPC QZSI is considered as an alternative approach. Eight 650 V Si MOSFETs with a fast body diode were used in it. Also, six 650 V SiC diodes (2 in QZS network + 4 as clamping diodes) were used, representing the Si–SiC approach. The SiC diode and four 1200 V SiC

MOSFETs were used in the 2L QZSI representing the full-SiC approach. All semiconductor devices along with chosen passive elements are provided in Table 3.


**Table 3.** Selected elements.

The selected semiconductors are equivalent by means of conduction losses. At the same time, the main differences between the Si and the SiC technology lie in the switching losses and maximum operation temperature. On the one hand, the full-SiC design may provide lower switching losses, on the other hand, the operation temperature can be higher. The practical benefit of the higher semiconductor temperature limit lies in the reduced size of heatsink required. In the heatsink design, our approach was to select the type and volume that can provide the required operation temperature. The heatsink was collected of several items, whereas the thermal resistance of each was equal to 2.8 ◦C/W. Taking into account the higher operation temperature of SiC devices, the volume of heatsink for the 2L solution with the full-SiC approach was twice as small. Thus, for the nominal input voltage, the expected maximal temperature of the heatsink in the 2L solution was about 90 ◦C, while in the case of conventional Si MOSFETs, it was expected up to 70 ◦C.
