*4.3. Performance Verification*

The theoretical and measured conversion gain of the converter as a function in the duty cycle is plotted in Figure 10. The DC voltage gain of the converter equals 12 at *Db* = 0. Small differences between the theoretical and measured DC voltage gain values occurred due to the influence of power losses. Therefore, at the input power of *PIN* = 200 W, deviations between the theoretical and measured DC voltage gain values are more significant because the converter experiences higher losses. Evidently, the input power level affects the duty cycle at the same DC voltage gain, for example, at the gain of *G* = 20: *Db* = 0.22 at *PIN* = 50 W and *Db* = 0.32 at *PIN* = 200 W.

**Figure 10.** Calculated and measured DC voltage gain of the converter versus the duty cycle at two input power levels.

The input voltage regulation range was measured for the proposed and the baseline topologies. As it was predicted, the baseline converter from [18] features limited input voltage and power regulation range, which is more restricted than was predicted theoretically. The area highlighted with yellow color in Figure 11 describes the input voltage and power range, where the proposed converter can operate and thus achieves superiority over the baseline converter from [18]. Experimental study of the baseline converter shows that it cannot regulate the voltage at duty cycles above some critical value, which drops almost linearly from 0.7 at *VIN* = 10 V to 0.46 at *VIN* = 22 V, which corresponds to the limit shown as the green line in Figure 11.

**Figure 11.** Comparison of the experimental limit of the input voltage and power regulation range in relation to the target operating range for the proposed and the baseline SRC topologies.

Next, it is essential to examine the efficiency of the converter with different input voltages and power levels. The efficiency measured across the wide input voltage range is shown in Figure 12a. The maximum efficiency of the proposed converter equaled 96% and 96.5% at *PIN* = 50 W and *PIN* = 200 W, respectively. These values were achieved when the input voltage was at its maximum level (*Db* = 0) and the bidirectional switch was turned <sup>o</sup>ff. The converter is similar to the traditional SRC and the transformer current had the sinusoidal shape. Accordingly, a full soft-switching was achieved in the converter semiconductors. When the input voltage decreased, the converter activated PWM of the bidirectional switch to boost the transformer voltage up to 350 V. With *Db* > 0, the converter lost the full soft-switching feature and the converter efficiency decreased together with the input voltage, causing also higher conduction losses. In addition, the efficiency was affected by the operating power due to the change in the quality factor of the resonant tank. The efficiency was also measured versus the input power for different input voltages, as shown in Figure 12b. The efficiency curves are flat across the wide input power range for the input voltages of over 20 V.

**Figure 12.** Comparison of the measured efficiency of the proposed and the baseline converters versus (**a**) the input voltage at two power levels and (**b**) the input power at different input voltage levels.

Figure 12 also includes several efficiency curves for the baseline converter from [18] to compare it to the proposed converter. It should be noted that the proposed converter features slightly lower efficiencies at higher power, which results from the higher voltage stress of the bidirectional switch in the proposed topology, but higher efficiency at light load, as shown in Figure 12b for the input voltage *VIN* = 25 V. However, this is an acceptable drawback, considering that the proposed converter can operate in the most critical operating points, that is, at low input voltages and high input currents (cf. Figure 11). For example, the converter from [18] cannot achieve the input power of above 200 W at the input voltage below 18 V, as shown in Figure 12a.

An application-specific study was performed to verify the capability of the proposed converter to perform maximum power point tracking (MPPT). A simplified control approach based on the hill-climbing MPPT algorithm with direct perturbations of the duty cycle was used similar to [21]. For the given converter, operation with a PV module resulted in a reduction in the input voltage when the duty cycle *Db* was increased. Hence, the direct MPPT can be implemented, avoiding a PI controller. The test was performed using the solar array simulator (SAS) Agilent E4360A as the input power source and electronic DC load Chroma 63204 in the constant voltage mode. The MPPT routine shown in Figure 13 corresponds to the converter operation with a 48-cell monocrystalline-Si PV module Sharp NQ-R258H. When the converter was first connected to the SAS, the current spike appeared due to the charging of the internal capacitances. When the output voltage reached the reference value of 350 V, the DC load started operation and the converter drew a minimum current from the SAS needed to keep the DC load running. After that, the MPPT started with a delay of 0.6 s. The converter reached the maximum power point of the corresponding PV module in 2.5 s. It should be noted that the resonant capacitor experienced an o ffset of around 200 V caused by start-up transients. Nevertheless, this o ffset disappeared after several seconds of operation. More importantly, it could be seen that the voltage ripple of the resonant capacitor depended tightly on the input power.

**Figure 13.** Experimental MPPT routine.
