**1. Introduction**

Photovoltaic (PV) sources are among the most promising renewable energy sources, providing clean and emission free energy [1,2]. The single-phase transformerless inverter system has popularly been used, as it has high efficiency and low cost compared with the transformer inverter system. However, the leakage current is a key issue [3–5]. The leakage current generated by PV parasitic capacitors must be limited to satisfy the VDC-AR\_N 4015 [6], UL1741 [7], and VDE 0126-1-1 [8] standards. In single-phase, grid-tied inverter systems, half-bridge and full-bridge inverters are typical topologies, as shown in Figure 1.

The Common Mode (CM) current path for grid-tied, transformerless, PV inverter systems is illustrated in Figure 2 [9]. The leakage current path is equivalent to an LC resonant circuit, as shown in Figure 3 [10,11]. *V*AN and *V*BN are the voltage difference between points A and N and points B and N, respectively, and L1 and L2 are the output filter inductors. The equivalent CM voltage *V*ecm is defined as:

$$V\_{\rm occ} = \frac{V\_{\rm AN} + V\_{\rm BN}}{2} + \frac{V\_{\rm AN} - V\_{\rm BN}}{2} \frac{\rm L2 - L1}{L2 + L1} \tag{1}$$

*Energies* **2020**, *13*, 434

For the half-bridge inverter in Figure 1a, only the output filter inductor L1 is employed, so L2 = 0. Thus, (1) can be simplified as follows:

$$V\_{\rm occ} = \frac{V\_{\rm AN} + V\_{\rm BN}}{2} + \frac{V\_{\rm AN} - V\_{\rm BN}}{2} = V\_{\rm BN} \tag{2}$$

**Figure 1.** Topologies of (**a**) half-bridge inverter; and (**b**) full-bridge inverter (named H4).

**Figure 2.** CM current path for transformerless PV inverter.

**Figure 3.** Equivalent circuit for the CM current path.

In Figure 1a, two capacitors, Cdc1 and Cdc2, with equal capacitance values are in series. Capacitor Cdc2 is charged or discharged by the grid current, and voltage *V*BN equals half of the input voltage plus the voltage fluctuation of the line frequency. But the high-frequency fluctuation is so small that it can be ignored. So, *V*BN is approximately constant. However, the DC voltage utilization of half-bridge inverters is only half that of full-bridge topologies, which means that a high-gain boost converter is needed as the first stage. As such, system efficiency and cost will be adversely affected. When two filter inductors are employed (L1 = L2), equation (1) can be simplified as:

$$V\_{\rm ecm} = \frac{V\_{\rm AN} + V\_{\rm BN}}{2} - 0 = \frac{V\_{\rm AN} - V\_{\rm BN}}{2} \tag{3}$$

For the full-bridge topology, the leakage current can be eliminated if the common voltage is kept constant. Some state-of-the-art topologies such as H5 [12], HERIC [13,14], and H6 [10,15–43] have been developed. However, there is still a small leakage current because of the parasitic parameters. Thus, the Neutral Point Clamped (NPC) technique is introduced to achieve zero leakage current [44–48]. The full-bridge topologies are divided into DC decoupling model and AC decoupling model [49].

A few rules have been indirectly reported in the literature, as well as some topology synthetization methods such as those based on the DC- and AC-decoupling model, as well as topology derivation methods from H4, H5, and H6. None of the topology synthetization methods currently being used could answer the question of how many topologies could be derived, as there is no unified model. Part I of this paper focus on the topology derivation methodology to achieve small leakage current [50]. It proposes a unified model to replace the DC- and AC-decoupling models based on four rules, including two which have already been reported in the literature [51,52]. More importantly, a mathematic method called the "MN principle" is proposed to derive all the possible topologies. This only focuses on the number of switches in PC and NC modes. The MN principle also verifies that we only need to focus on M ≤ 4, N ≤ 4, because the remaining topologies can always be simplified into one of them. Thus, the method verifies that all possible topologies can be found. The derivation procedures are introduced to determine all the existing topologies and new topologies under unipolar sinusoidal pulse width modulation (USPWM) and Double-Frequency USPWM (DFUSPWM).

Part I of the paper is organized as follows. Section 2 describes the principles of the unified topology model. Section 3 introduces topology derivation under USPWM. The topology derivation under DFUSPWM is introduced in Section 4. Part I of the paper is concluded in Section 5.

#### **2. Principle of Unified Topology Model and Symmetric Methodology**

Figure 4 shows the full-bridge topology and a simplified schematic diagram.

**Figure 4.** (**a**) Full-bridge topology; (**b**) Simplified schematic diagram of full-bridge topology.

In Figure 4a, point P and point N indicate the positive and negative DC bus terminals, respectively, and point A and point B indicate the first and second arm terminals, respectively. The semiconductor switches are always used to connect or disconnect points P and N to points A and B. Figure 4b shows a simplified schematic diagram of the full-bridge topology. Switches TPA, TNA, TPB, and TNB are the equivalent switches between points P and A, between N and A, between P and B, and between N and B, respectively. It should be noted that each equivalent switch can be a single active switch or several active switches connected in series. *V*PN is the input voltage. The number of switches between points P and A is X1, between points B and N is X2, between points P and B is Y1, and between points N and A is Y2.
