*4.3. Time-Base*

The TB is a crucial part of the system as it has been used to trigger all the calculations. As previously described, the TB relies on an internal high-resolution timer, with a clock frequency as higher as possible to reach the best accuracy possible. High counter frequency implies that the counted number rapidly increases so that a 32-bit timer would be appropriate to implement the TBC. Unfortunately, a 32-bit timer running at system core clock is not a common feature on low cost MCUs; additionally, the adopted MCU has no 32-bit timers at 168 MHz but it has only 16-bit timers and it is not possible to perform a direct hardware cascade connection of two 16-bit timers (to obtain one single 32-bit timer from two 16-bit timers). To face these hardware limitations, a firmware technique to cascade two 16-bit counters for the TBC implementation has been implemented. When the first counter rollover occurs, an ISR manages the working of a second counter until the desired value is reached; particular attention has been paid to insure that the second counter stops before rollover. In the following, for sake of clarity, a numerical example is given for the explanation of the technique. Suppose that the system clock frequency is exactly equal to the nominal value, 168 MHz; in this case, to obtain the 20 ms periodicity for TB, it is needed to count up to 168,000,000/50 = 3,360,000 (reload value for TB), which is a number not representable with 16-bit. For this reason, the firmware lets the 16-bit counter to reach the rollup (so counting up to 216) for a number of times equal to *floor* (3,360,000/216) = 51 and, on the

52-th iteration, the counter must be stopped before rollover; on the last iteration it must count 17,664, so reaching the desired value (51 × 2<sup>16</sup> + 17664 = 3,360,000). Another issue in the implementation of TB comes from the fact that the output of the PID, *uj*, is the current tick number that corresponds to 1 s. This value has to be divided by 50 to obtain the TBC reload value to obtain a periodicity of 20 ms (50 fps). It is apparent that the result of the division is, in general, a decimal number while the TBC reload must be an integer number. A straightforward rounding of this value leads to a loss in resolution that could be relevant for the aimed application. Therefore, to mitigate this effect, the decimal part is properly considered: when, at the PPS event, a new TBC reload is calculated, in the next 50 TB events not always the same value is loaded. In fact, firmware reloads 50 potentially different TB values and the i-th reload value is calculated as:

$$reload\\_valuc\_i = \left\{ \begin{bmatrix} \frac{u\_j}{50} \\ \frac{u\_j - \sum\_{k=0}^{i-1} reload\\_valuc\_k}{50 - i} \end{bmatrix} i = 1, \dots, 49 \right. \tag{4}$$

where square parenthesis means rounding to nearest integer. With this formula, the summation of the 50 TB values will always coincide with *uj*.

#### *4.4. AD Conversion*

Two different ADC are used to acquire voltage and current signals and, to obtain simultaneous sampling, an internal timer has been selected as trigger source for both ADCs. The chosen sampling frequency was 6400 Hz as it corresponds to 128 samples per cycle at 50 Hz and the basic sampling time instants are triggered by a high-resolution timer running at system clock of 168 MHz. The desired sampling periodicity is obtained loading in the timer a proper counting value that nominally can be calculated dividing the rated system clock by the desired sampling frequency. However, the actual counting value has been experimentally evaluated. A square wave, with frequency equal to the desired sampling frequency has been generated. Its frequency has been measured with the frequency counter Agilent 53230A for some hours. The counting value has been chosen in such a way that the measured frequency of the square wave was as close as possible to 6.4 kHz; in particular, a sampling frequency of 6400.2500 Hz has been chosen, with a standard deviation of 100 μHz, which corresponds to about 0.02 μHz/Hz. The ADCs nominal resolution is 12-bit; nevertheless, for the purpose of the developed project, the effect of noise on the analog input or amplitude quantization can remarkably affect the overall accuracy of the results. Thus, ADC characteristics was enhanced through a technique based on over-sampling and averaging [40], thus obtaining improvement both in terms of amplitude resolution and noise rejection. Therefore, when a sampling time instant is triggered, the ADC is configured to acquire 16 samples at a burst sampling frequency much greater than the chosen sampling frequency (588 kHz). It is worthwhile noting that 16 samples are acquired in a really short time of about 27 μs, much lower than the equivalent sampling time interval. Then, the acquired samples are averaged to obtain the final sampling results. To this aim, two direct memory access channels are configured to simultaneously serve the two ADCs. They copy the samples in dedicated queues and an ISR averages the 16 samples of voltage and current, respectively, using the integrated DSP unit. The averaged results are pushed in two different queues, one for voltage and one for current. A final issue is related to the time collocation of the averaged values: they are the result of the averaging of 16 samples over 27 μs. They are considered at the center of the averaging interval and so a systematic phase delay is introduced; however, this phase delay can be compensated with a correction of the measured synchrophasor phase value returned by the estimation algorithm.
