**1. Introduction**

The need for the best estimate of the power system's state is recognized to be a crucial element in improving its performance and its resilience to face catastrophic failures. Thus, one of the most important advancement expected from smart grid technology is the strengthening of the managemen<sup>t</sup> of the power system [1]. Currently, most of the control actions of a power system are performed through an open-loop type centralized control that implements only steady-state security functions. This applies since the Wide Area Measurement Systems (WAMS) typically devoted to this aim have long latency time. This, obviously, places some limits in terms of the level of stability, reliability and safety of the supervised power system. For this reason, in recent years, synchrophasor technologies and the related monitoring devices called Phasor Measurement Units (PMUs) have received a lot of attention [2–5]. A PMU measures the instantaneous voltage, current, frequency and the Rate Of Change Of Frequency (ROCOF) at specific locations in an electric power transmission system; then, it converts the measured parameters into phasor values, typically with a rate of 25 or more, per second. Finally, it also adds a precise time stamp to these phasor values, turning them into synchrophasors. Time stamping allows these phasor values, provided by PMUs in di fferent locations and across di fferent power industry organizations, to be correlated and time-aligned and so properly combined. The resulting information enables transmission grid planners and operators to have a high-resolution "picture" of the conditions throughout the grid in real time [1]. Thus, with a large-scale implementation of WAMS using PMUs and Phasor Data Concentrators (PDCs) in a hierarchical structure, it become possible to perform a closed loop automatic monitoring and control of the power system to steer it away from transient or voltage instability, through corrective actions initiated during a state of emergency [4,5].

The number of installed PMUs worldwide is constantly increasing; nevertheless, the cost of these devices is still a source of concern for widespread installations, [6–8]. Thus, a certain e ffort in research field is devoted in developing methodology to better observe, understand and manage the grid but limiting the number of installed devices, [9–11]. This paper tries to face the same problem but from a di fferent point of view: it proposes a design approach for implementing a PMU only adopting low cost hardware, thus making it possible to use them on a large scale.

In recent years, there have been significant research contributions on the improvement of the PMU performances adopting di fferent algorithms [12–19], or on the PMU-based event detection [20,21]. Few works, to the best of the author's knowledge, focused on the implementation of this kind of instruments. In [22], an example of PMU for distribution grids is presented; however, the implementation details are not disclosed. More details are given in [23] where the described PMU prototype is based on a field programmable gate array with high performance. Despite this, the chosen hardware platform (i.e., a National Instrument Compact RIO) is quite expensive. In [24], a prototype of a PMU, based on a microcontroller, is presented; the synchronization is obtained through a GPS signal received from a Wireless Fidelity (Wi-Fi) module. No details are given on the synchronization, nor device characterization is presented. In [25], the OpenPMU project, an open platform for the development of PMU technology, is presented. No specific details on hardware implementation but just a rough cost, of about 1000 \$, are given; moreover, nothing is said about the instrument performance. In [26], a development of an analog-to-digital converter (ADC) for PMU applications, with GPS synchronization, based on an open hardware development platform, is discussed. It makes use of external devices, such as a GPS receiver, a Phase Locked Loop (PLL) circuit and an ADC, managed by the powerful BeagleBone Black board. Some issues arise: the development board is not an industrial product, so not suitable for harsh environment like substations; moreover, the performance is not accurately evaluated in comparison with a reference instrument. In [27], a technique to lock the sampling frequency of an ADC, managed by a Digital Signal Processor (DSP), is discussed; it does not use a GPS disciplined oscillator, but a simple GPS receiver. It is based on a non-uniform sampling of the signal, since the sampling period is continuously varied between two discrete values. Good synchronization results are shown in the paper; however, the performance is evaluated in a very simple condition, which is a sine wave with constant frequency, amplitude and phase. In fact, the non-uniform sampling may introduce phase noise and worsen the accuracy of synchrophasor phase estimation.

It is worthwhile to emphasize that in all the cited papers, even if the performance is experimentally evaluated, merely rough experiments using signals of a few volt are executed, excluding input transducers. However, it is known that input transducers are typically the major source of uncertainty in measurement chains for power systems [28–37]; this issue, specifically for PMU application, is also demonstrated in [38].

In this paper, a design approach for a low-cost prototype of PMU, with a detailed description of its hardware and firmware implementation, is presented. In addition, a thorough metrological characterization of the realized prototype is shown: it has been performed using a metrological grade reference instrument, the Fluke 6135A/PMUCAL, using voltage and current levels typical of low voltage power systems, which are similar to those which can be found in primary, or secondary, substations, at the output of Voltage and Current Instrument Transformers (VT and CT). The paper is organized as follows. In Section 2 some basic recalls on PMU are given. Section 3 presents the hardware implementation of the proposed system, including the analog input adaption stage. Section 4 describes the firmware implementation, along with the techniques used to obtain the synchronization and to improve the measurement accuracy. Section 5 shows the metrological characterization of the prototype and, finally, Section 6 draws the conclusions.

#### **2. Fundamentals of PMU**

A phasor is a complex number that represents both the magnitude, *A*, and phase angle, ϕ, of the voltage or current sinusoidal waveforms pulsating with an angular frequency ω = <sup>2</sup>π*f* (with *f* equal to 50 Hz or 60 Hz in different power systems) at a specific point in time (shown in Figure 1).

**Figure 1.** Synchrophasor representation.

PMUs measure root mean square (rms) amplitude, phase, frequency and ROCOF of both current and voltage and this collection of grid condition data, which are time-synchronized, is called phasor data. Every PMU measurement obtains a timestamp derived from the GPS universal time. When a phasor measurement is timestamped, it is called a synchrophasor. In this way, PMU measurements performed in different locations can be synchronized and time-aligned and, therefore, combined to provide a detailed view of a wide geographical area. This, moreover, help the system operators to maintain the healthiness of the network.

PMUs sample at speeds of up to 50 observations per second (or 60 in USA system), whereas conventional monitoring technologies (such as Supervisory Control And Data Acquisition, SCADA) measure once every two to four seconds. However, in order to allow the comparison of the electrical quantities of the nodes (amplitude and phase of the voltages and currents), the measurements must be made at common sampling instants. The absolute time reference can be used to synchronize the simultaneous sampling of voltage and current signals. The standards [2,3] define the reference time instants in which the PMU must measure the electrical signals and the levels of accuracy that equipment should meet for the various classes of accuracy. In order to face these requirements several test conditions and performance verifications are prescribed. A crucial role in performance verification is played by the synchronization stage: in fact, as it is stated in [2,3], a synchronization error of 1 μs results itself in a Total Vector Error (TVE) of 1 %. All the recalled requirements reflect on the design of a PMU measurement system. A basic architecture, typically adopted for PMU implementation, is reported in Figure 2.

**Figure 2.** Basic architecture of a Phasor Measurement Unit, which typically include a GPS Disciplined Oscillator.

The core of this architecture is the oscillator disciplined by the Pulse Per Second (PPS) signal coming from GPS receiver, which can give a sampling clock accurately synchronized to the absolute time reference, i.e., the Universal Time Coordinated (UTC). In this way, the synchronization requirements are satisfied as the analog signals are sampled synchronously with the absolute time reference. Nevertheless, the GPS Disciplined Oscillator (GPSDO) is not a cheap component and, to obtain a low-cost implementation, this component should be removed.

In addition, as is demonstrated in [38], the input transducers and the analog signal conditioning stages could be the major source of uncertainty in PMU measurement systems. Therefore, particular attention should be also paid to the design and usage of these components.

#### **3. Hardware Implementation**

#### *3.1. System Architecture*

In order to obtain an adequate level of accuracy and, at the same time, keep low the hardware cost, reference is made to the architecture reported in Figure 3 and only cheap components have been chosen. The input stages are constituted by low cost voltage and current transducers equipped with suitable analog conditioning stages to adapt the signal level to the input range of the ADC. The core of the instrument is a low-cost Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) microcontroller unit (MCU) with integrated ADC (analog-to-digital converter) and Ethernet interface. It is responsible for the absolute time synchronization, data acquisition, signal processing and data communication. A key feature of the design is the lack of a GPSDO. Instead, a simple GPS receiver is used and all the synchronization is derived by the PPS signal. Therefore, a suitable signal processing is adopted to obtain measurements synchronized to the UTC, as it is better explained in Section 4. Voltage and current synchrophasors, frequency and ROCOF are obtained by processing the synchronized signal samples through an Interpolated Discrete Fourier Transform (IpDFT) algorithm [14]. Measurement data are communicated through a Transmission Control Protocol (TCP) socket to a host Personal Computer (PC); for the scope of this work, the standard Institute of Electrical and Electronics Engineers (IEEE) Std C37.118.2-2011 [39] has not been considered.

**Figure 3.** The proposed architecture for a low-cost Phasor Measurement Units (PMU).

#### *3.2. Input Stage*

The used voltage and current transducers are the LEM LV 25-P and the LEM LA 25-NP, respectively. Their conditioning circuits have been designed as simple as possible, using the lowest number of active components as possible, in order to keep, at the same time, the cost low and the signal-to-noise ratio as high as possible. The conditioning circuit for the voltage transducer is shown in Figure 4, where T1 represents the transducer. It converts a rated rms input current of 10 mA in a current of 25 mA, with a maximum rms input voltage of 700 V. The input signal range has been considered limited to a rms value of 300 V so the input resistance *R*1 is chosen equal to 30 kΩ obtaining an output bipolar current of 25 mA. Then, in order to obtain a peak-to-peak unipolar voltage output of about 3.3 V (i.e., the input range of the microcontroller ADC) a resistor *R*2 = 46 Ω is inserted in series and an o ffset voltage of 1.65 V, directly derived from ADC reference voltage, is added as shown in Figure 4. The values of the other components are *R*3 = 10 kΩ (in order to drain a maximum current of about 170 μA from the microcontroller) and *C*1 = 47 nF (in order to cut high frequency noise). The adopted current conditioning circuit is very similar to that previously presented for voltage, the only di fference in the scheme is that current transducer has no need of input resistance.

**Figure 4.** Simplified circuit topology of the voltage channel conditioning stage.
