*4.1. Synchronization*

A PMU shall be capable to receive time synchronization from a reliable and accurate source, such as the GPS, and to perform phasor measurements synchronized to UTC time, with accuracy sufficient to meet the requirements specified in the standards [2,3]. It should perform all the measurements and report the results at a constant reporting rate, expressed in terms of frames per second (fps). The reporting rate is an integer number (i.e., 50/60 fps, 25/30 fps, 10/12 fps, etc.) and it defines the reporting

time instants at which the PMU shall report the measurement results. For a reporting rate N fps, the N reporting times are evenly spaced through each second with first reporting time coincident with the UTC second rollover (e.g., coincident with a 1 PPS provided by GPS, see Figure 5). The typical solution adopted by commercial PMUs is the use of a 10 MHz GPSDO. Starting from this system clock, a sampling clock is derived, so that also sampling instants are referenced to UTC and the constraint of evenly spaced measurements is simply obtained by performing analysis on a constant number of samples (see Figure 6). In this paper, with the aim of cost saving, a di fferent approach, based on a cheap GPS receiver and on a complex firmware technique based on numeric synchronization and resampling, is proposed. In the presented prototype, the internal MCU clock is not disciplined and, thus, it is not aligned to absolute time (see Figure 7). Moreover, it is obtained by multiplying the output frequency of a low cost quartz crystal through the PLL circuit (integrated in the MCU) and so a ffected by frequency jitter and thermal drift; its frequency (168 MHz), however, is much higher than the typical GPSDO frequency. Therefore, the system clock and internal timers are used to build a reference time-base (TB) and a firmware procedure manages the timers to keep their rollover periodicity locked to PPS and thus to UTC absolute time. To this aim, an internal counter (Time-Base Counter, TBC), running at 168 MHz, is used and configured with a counting number that is continuously estimated and corrected to keep its periodicity as close as possible to an integer fraction of 1 s (i.e., 1 s/50 = 20 ms). In fact, at each PPS event coming from the GPS receiver, a specific Interrupt Service Routine (ISR) calculates how many system ticks have been elapsed from the previous PPS event. This number is used to correct the counting number adopted in the next second to produce a counter rollover each 20 ms: the number of ticks, divided by 50, is the fractional number of ticks that corresponds to 20 ms and it defines the reporting time at 50 fps, the maximum reporting rate considered (i.e., related to 50 Hz power frequency). Obviously, since the number of ticks, divided by 50, can be a decimal number, whereas the counter accepts only integer numbers, a specific managemen<sup>t</sup> strategy, explained in Section 4.3, has been used. Other reporting rates can be obtained by decimation. The correction is calculated adopting a discrete Proportional Integrative Derivative (PID) control algorithm, as better explained in Section 4.2. In this way, since the counter rollover is precisely produced every 20 ms (i.e., 50 pulses per second, 50-pps), it can be used to obtain the synchronized reporting time instants. However, in order to have synchronized measurements of the phasor, having a synchronized TB is not enough. In fact, it is necessary to sample the input signals synchronously with the absolute time reference, which is not the case at hand. Therefore, at each TB rollover, MCU takes and stores, in a dedicated queue, the timing information needed to perform a signal resampling, that is the number of ticks elapsed from last sampling time, called control info (CI). In fact, with CI, the actual synchronized sampling instants are estimated and then the acquired data are resampled with linear interpolation, in order to have a signal synchronously sampled. The data acquired between two subsequent TB events is called frame. The subsequent processing stage manipulates the frames and extracts the phasors.

**Figure 5.** A sinusoid with a frequency f, after the Pulse Per Second (PPS), is observed with a reporting time of T0 seconds.

**Figure 6.** Example of a GPS Disciplined Oscillator (GPSDO).

**Figure 7.** Example of an asynchronous high frequency clock.

#### *4.2. PID Control*

As previously mentioned, to keep the internal TB phase locked with the PPS, a specific ISR takes the number of system ticks elapsed from the last PPS event and feeds a PID control algorithm. More in details, at each PPS event, the ISR snapshots the count value of the TBC, it computes the deviation, *ej*, with respect to the values obtained at previous PPS event, and it feeds the PID. The output of the PID, divided by 50, will be the value used to configure the TBC rollover for the next second, as better explained in Section 4.3. In details, the new reload values *uj*, at *j*-th iteration, can be computed as:

$$\mathbf{e}\_{\bar{j}} = \mathbf{y}\_{ref} - \mathbf{y}\_{\bar{j}} \tag{1}$$

$$\mathbf{u}\_{p,j} = \,\,\mathbf{K}\_p \cdot \mathbf{e}\_{j\prime} \colon \mathbf{u}\_{i,j} = \mathbf{u}\_{i,j-1} + \mathbf{K}\_i \cdot \mathbf{e}\_j \colon \mathbf{u}\_{d,j} = \,\,\mathbf{K}\_d \cdot \left(\mathbf{e}\_j - \mathbf{e}\_{j-1}\right) \tag{2}$$

$$u\_j = u\_{p,j} + u\_{i,j} + \
u\_{d,j} \tag{3}$$

where *yre f* is the reference number of ticks, *yj* is the current value of counted ticks and *up*,*j*, *ui*,*j* and *ud*,*j* are, respectively, proportional, integrative and derivative components. Note that *ui*,*j* is computed recursively and *ud*,*j* is approximated as backward finite difference. Since the transfer function of the system is not known, the PID constants (*Kp*, *Ki* and *Kd*) have been determined with the Ziegler-Nichols approach and empirically adjusted. The PID can act only one time per second, because reference time is only available one time per second (each PPS event). Moreover, a little value for *Ki* constant has been chosen in order to obtain a low jitter in steady state conditions. This leads to a quite slow locking to absolute time, many iterations (between 60 and 80, depending on initial phase displacement) are needed to stably converge around the reference; thus, the anti-windup technique and the preload of integrator constant have been implemented to make the system work correctly within a few second after startup. In conclusion, the PID action keeps the TB of 50-pps locked in phase to the 1-PPS signal received by the GPS.

The accuracy of synchronization was experimentally evaluated: the time intervals between the active edges of the PPS signal and obtained time base periodicity have been measured with a 12-bit Lecroy MDA810 digital storage oscilloscope for about some hours. The measured distribution of the time delay is shown in Figure 8. Deviation, at steady state, exhibits almost a normal distribution with a mean systematic delay of 1.25 μs and maximum error of 500 ns. Thus, the system satisfactory reacts to internal clock drift and jitter obtaining good synchronization accuracy.

**Figure 8.** Measured synchronization accuracy.
