**2. Device under Test and Experimental Setup**

The whole analysis was performed on the CREE 4H-SiC vertical double-di ffused MOSFET (VDMOS) denoted as CPMF-1200-S080B, rated 1200 V, 50 A, 80 m Ω, and targeted at solar inverters, high-voltage dc–dc converters, and motor drives. A top-view picture of the device under test (DUT) is given in Figure 1; indicated are the gate pad, the two source pads, and the gate interconnect tracks. The DUT presents a 4.08 × 4.08 mm<sup>2</sup> die area and a 3.46 × 3.46 mm<sup>2</sup> active area (there is a peripheral inactive region), the *e*ff*ective* portion of which contributing to the current capability amounts to about 10 mm2. The pattern is multicellular, with many thousands of body islands located in the N-drift region, within which there are source-body contacts surrounded by the polysilicon gate that lies beneath the source metal. The Ni/Ag drain contact is on the backside.

Isothermal measurements of *I*–*V* transfer and output characteristics of the bare die were performed by means of an *in-house* 250 A-rated curve tracer suited to apply down to 1 μs-wide current pulses, the device baseplate being set to assigned temperatures *TB* through a thermochuck with 1 ◦C resolution. UIS experiments aimed at the evaluation of the breakdown voltage were carried out by a non-destructive custom tester [8]. The switching behavior was investigated by using a half-bridge converter board configured to perform a standard inductive load switching (ILS) test [9].

**Figure 1.** Device under test (bare die).
