**3. Network Model**

As shown in Figure 2, the experimental recorded CPU temperature (Figure 1) can be quite well fitted to the following function:

$$T\_{filt}(t) = 58 + 29\left(1 - \frac{210}{210 - 100}e^{-t/210} + \frac{100}{210 - 100}e^{-t/100}\right) = 58 + 29\left(1 - 1.909\ e^{-t/210} + 0.909\ e^{-t/100}\right) \tag{1}$$

**Figure 2.** Experimental recorded CPU temperature *Texp* (•) compared with an analytical function *Tfitt*.

The moment *t* = 0 in Figure 2 is taken as the starting point of the increased activity of the CPU. It corresponds to the moment around 21.6 min (arrow in Figure 1). Note that the Function (1) satisfies the initial conditions *T* = 58◦ and *dT*/*dt* = 0 at the moment *t* = 0. The temperature of 58◦ is the steady state temperature rise during the long reduced activity period (*t* < 0). For modelling, this constant value will no longer be taken into consideration, because we are mainly interested in the transient behaviour.

A closer look at Figure 1 reveals that the start of the increased activity can be approximately seen as a step function of the power consumption. It is then rather straightforward to establish an equivalent network giving rise to a transient temperature like Equation (1), provided a power step is inputted.

A quick look at Figure 1 shows there is a quite long delay between the start of the increased activity and the temperature rise. This proves that the temperature sensor is not in the middle of the heat source but at a certain distance, e.g., on edge of a heat sink. The heat has to propagate a certain time before any temperature rise can be recorded by the sensor. Figure 3 shows the proposed equivalent network. Δ*P*0 is the power step due to the increased activity. Note that the node *S*, where the temperature is evaluated, is not the input node CPU.

**Figure 3.** Equivalent thermal network. Δ*TCPU* and Δ*TS* are temperature rises above the reference (=58◦).

This is necessary to model the experimentally observed delay. The fact that the two exponential functions in Equation (1) have different signs also proves that we are dealing with transfer impedance. If the temperature would have been calculated at the input node, different signs, like in Equation (1), are physically impossible. Both the CPU and the sensor *S* are connected to the reference temperature through a thermal resistance *R* and a thermal capacitance *C*. We gave them both the same values because there are both within the same package. The coupling resistance *R'* is responsible for the delay between the CPU and sensor's temperature.

The sensor temperature Δ*TS* (Figure 3) is easily found to be given by:

$$
\Delta T\_S(t) = \Delta P\_0 \frac{R^2}{R' + 2R} \left( 1 - \frac{R' + 2R}{2R} e^{-t/\tau\_1} + \frac{R'}{2R} e^{-t/\tau\_2} \right) \tag{2}
$$

where Δ*P0* denotes the power step at the input. The method used to ge<sup>t</sup> Equation (2) is based on the use of symmetrical components as will be outlined in the appendix further on. In Equation (2), the time constants are given by:

$$
\pi\_1 = R \mathcal{C} \,\,\pi\_2 = \frac{RR'}{2R + R'} \mathcal{C} \tag{3}
$$

The comparison between the experimental fitting, Equation (1), and the network solution, Equation (2), is quite straightforward. One may observe immediately that:

$$
\tau\_1 = 210 \text{ s}, \quad \tau\_2 = 100 \text{ s and } R' = 1.818R \tag{4}
$$

Referring to Figure 3, the temperatures Δ*TCPU* and Δ*TS* are in a steady state related by:

$$
\Delta T\_S = \Delta T\_{CPU} \frac{R}{R'+R} = \frac{\Delta T\_{CPU}}{2.81} \tag{5}
$$

Although the CPU temperature is recorded at *S*, the displayed value has been multiplied by 2.81 in order to obtain the correct CPU temperature (at least during the steady state). This explains the values of almost 90◦ in Figure 1 during a high activity period. In order to obtain the correct sensor temperature, the expression (1) should be divided by 2.81.

In steady-state conditions, the total thermal resistance of the CPU to the base plate is the parallel connection of *R* and *R'* + *R*:

$$R\_{CPII} = \frac{R(R' + R)}{R' + 2R} = \frac{3.81}{4.81}R = 0.792R\tag{6}$$

According to the supplier's information, a maximum temperature rise of 90◦ is obtained for a power dissipation between 45 and 50 Watts. Taking the average value 47.5 watts, we get:

$$R\_{CPII} = \frac{90}{47.5} = 1.8947 \frac{K}{W} \tag{7}$$

From Equations (4) and (6), we ge<sup>t</sup> then the values of the resistor of the equivalent network.

$$R = 2.392 \frac{K}{W} \text{ and } R' = 4.349 \frac{K}{W} \tag{8}$$

From the knowledge on the thermal resistance *R* and the time constant τ1, one gets the value of the thermal capacitance *C*:

$$C = \frac{\tau\_1}{R} = \frac{210}{2.392} = 87.79 \frac{\text{J}}{\text{K}} \tag{9}$$

A thermal capacitance is, by definition, known as *C* = *CvV*, where *cv* is the specific heat per unit volume and *V*, the volume. Most solid materials have a volumetric specific heat of around 2 × 10<sup>6</sup> J/m3K. Hence, we roughly get:

$$V = \frac{\mathcal{C}}{c\_v} = \frac{87.79}{210^6} = 43.8 \text{ cm}^3 \tag{10}$$

This seems to be a too high value at first sight. However, one should bear in mind that the chip is connected to the cooling fin through a heat pipe, which is a thermal short circuit. Hence, the volume of 43.8 cm<sup>3</sup> is reasonable if one takes the heat pipe and the cooling fin into account.
