**5. Static and Dynamic Electrothermal Simulations**

The whole pre-processing activity, involving isothermal measurements, optimization of the model parameters, geometry/mesh construction in COMSOL, proper domain discretization, equivalent network extraction with FANTASTIC, calibration of the Kirchho ff's transformation, and macrocircuit generation, can last a few days, after which *any* analysis can be performed in short times on the device of interest.

In particular, the macrocircuit was adopted to perform many PSPICE simulations of the DUT with DBC substrate in both static (dc) and dynamic conditions on a PC with an Intel Core i7-7700 (3.60 GHz) CPU and equipped with a 16 GB RAM. Unfortunately, experimental data for accuracy validation were not available for the examined component. On the other hand, the approach benefits from (i) a careful calibration of the transistor model from experimental data; (ii) a very accurate domain representation in COMSOL aided by the *in-house* routine mentioned in Section 4.2; (iii) an automated (and una ffected by user's errors) extraction of the linear equivalent network through FANTASTIC; (iv) a smart pre-processing calibration of the Kirchho ff's transformation. Hence, the only source of error can be induced by the degree of uncertainty concerning the thermal conductivities of the involved materials, which however a ffects any ET simulation approach.

First, the *ID*–*VDS* output characteristics were determined with a *VDS* step amounting to 0.1 V under isothermal (at *T*0) and ET conditions. Isothermal conditions were obtained by deactivating the thermal feedback block. The CPU time needed to simulate a single ET characteristic was nearly 100 s. Results are reported in Figure 17, which also shows the temperature rise above *T*0 averaged over the e ffective active area ( Δ *Tav*). It can be inferred that the simulation runs were stopped as Δ *Tav* reached 500 K.

**Figure 17.** (**a**) *ID*–*VDS* output characteristics determined with the proposed approach under isothermal (dashed blue lines) and ET (solid red) conditions; (**b**) temperature rise Δ*Tav* = *Tav* – *T*0 corresponding to the ET conditions, *Tav* being the temperature averaged over the e ffective active area.

Afterward, SC tests were simulated. Such tests involve large power dissipation, and are typically used to quantify the device robustness under harsh and abnormal events (see e.g., [7,23,25,44–47], all focused on SiC MOSFETs). In the SC experiment, the DUT is first biased in the OFF state with a given supply voltage applied to the drain, and then turned on with a single gate pulse (a gate resistance RGATE of 50 Ω was considered). The knowledge of the whole temperature distribution over the active area is important, since the value and position of the temperature peak are needed for reliability considerations. The e ffects of many combinations of gate and supply voltages were examined. Simulation runs were very fast: a single test required about 300 s with a fine time discretization. The total drain current *ID* conducted by the DUT vs. time is shown in Figure 18a for all the analyzed cases, while Figure 18b illustrates the corresponding temperature rises Δ *Tav*. The first figure reveals that ID first grows due to the strong positive temperature coe fficient induced by (i) the reduction in threshold voltage and (ii) the mobility increase (for the lowered Coulomb scattering), and then drops since the negative temperature coe fficient triggered by the acoustic-phonon scattering dominates (thermally stable behavior) as all the traps have released electrons [7,25].

The temperature rises Δ *T* over cells #01, #23, #47, #61 (identified in the layout of Figure 10) are reported in Figure 18c for two cases, namely, *VGS* = 10 V/*VDD* = 200 V and *VGS* = 20 V/*VDD* = 200 V. From the inspection of the waveforms, it is found that a pronounced temperature nonuniformity takes place in the first case (the inner cell #47 su ffers from a Δ *T* two times higher than that of the top-corner cell #01), which can be explained as follows. The milder bias conditions ( *VGS* = 10 V) allowed the device to safely undergo the test for a longer period, within which the heat had enough time to significantly spread, thereby favoring a stronger impact of the mutual thermal interactions and the consequent exacerbation of temperature gradients.

The whole temperature field in the domain was determined at chosen time instants from the DCTM generated with FANTASTIC in a post-processing step. More specifically, points A (*t* = 25.5 μs, *VGS* = 20 V/*VDD* = 200 V), B (*t* = 338 μs, *VGS* = 20 V/*VDD* = 50 V), and C (*t* = 14 ms, *VGS* = 10 V/*VDD* = 50 V) identified in Figure 18a,b were selected, which approximately share the same Δ *Tav* value, i.e., 500 K. The computed temperature rise maps are shown in Figure 18d (top view) and Figure 18e (side view). As can be seen, despite the same Δ *Tav*,


Lastly, the macrocircuit was used to simulate two UIS tests, which are commonly adopted to evaluate the maximum amount of avalanche energy sustainable by the device [8,44]. In the UIS experiment, a load inductor L tied to the drain is first ramped up to a desired current by keeping the DUT in linear mode for a time tON; then the DUT is turned o ff and brought into avalanche by the inductor, which preserves the current continuity. The tests will be hereinafter denoted as case #1 and #2, the specifics of which are as follows:


In both cases, a gate voltage equal to 20 V was applied for tON = 200 μs, and then lowered to 0. Again, the time elapsed by PSPICE for a single test was about 300–400 s. Concerning case #1, Figure 19a shows the drain current *ID* and the drain-source voltage *VDS* vs. time in the span 190 to 280 μs, while Figure 19b illustrates the temperature rises of cells #01, #23, #47, #61. An almost uniform temperature distribution was found, as witnessed by the map taken at time instant t\* = 220 μs, where the dynamic temperature averaged over the active area peaks (Figure 19c).

**Figure 18.** Simulated SC test: (**a**) drain current *ID* vs. time for seven *VGS*/*VDD* combinations; (**b**) corresponding temperature rises averaged over the effective active area; (**c**) temperature rises of the individual cells highlighted in Figure 10 for 2 cases; (**d**) top and (**e**) side views of the 3D temperature rise maps determined at points A, B, and C shown in (**a**) and (**b**).

**Figure 19.** Simulated UIS test, case #1: (**a**) drain current *ID* and drain-source voltage *VDS* against time; (**b**) temperature rises of the individual cells identified in Figure 10; (**c**) top and side views of the temperature rise maps calculated at time instant t\* = 220 μs shown in (**a**) and (**b**).

In case #2, despite the lower drain current *ID* ≈ *VDD*·*tON*/*L* before turn-off (10 A instead of 13 A obtained for case #1), the average temperature reaches higher values due the longer discharging transient, in turn dictated by the higher *L*, since

$$\frac{dI\_D}{dt} = -\frac{BV\_{DS}(T) - V\_{DD}}{L} \tag{42}$$

Results are shown in Figure 20. As can be inferred from Figure 20b, which reports the temperature rises of the selected cells, and from Figure 20c, which depicts the post-processing temperature maps at t\* = 240 μs, a slightly more nonuniform temperature field occurs with respect to case #1.

**Figure 20.** Simulated UIS test, case #2: (**a**) drain current *ID* and drain-source voltage *VDS* vs. time; (**b**) temperature rises of the individual cells highlighted in Figure 10; (**c**) top and side views of the temperature rise maps calculated at time instant t\* = 240 μs identified in (**a**) and (**b**).
