**1. Introduction**

Silicon carbide (SiC) power devices are promising candidates for energy distribution, as well as for automotive, aircraft, and spacecraft applications, by virtue of their inherent features like high breakdown voltage, low on-state resistance, and excellent high-temperature capability [1].

Unfortunately, such devices often operate under critical conditions with a large amount of heat generation, which may lead to reliability degradation or even to an irreversible device failure in harsh cases. As a consequence, reliable simulation tools accounting for electrothermal (ET) effects are highly desired to define the thermal dissipation constraints and optimize the design of the transistor layout and/or of the cooling system. Such tools must be suited to describe temperature and current nonuniformities, which are often responsible for the safe operating area shrinking of transistors with a multicellular pattern. However, conceiving and developing a viable simulation strategy are challenging tasks due to multiple reasons. Fully numerical 3D ET analyses with device simulators concurrently solving the semiconductor and heat transfer equations are computationally unfeasible. Commonly-adopted approaches rely (i) on the interaction between a circuit simulation program and a 3D thermal-only numerical solver in a relaxation procedure [2,3], or (ii) on the extension of a finite-volume/-element software package to account for the electrical behavior of the transistor with simplified models [4,5]. However, for the specific case of SiC power devices, results can be trustworthy only by using models that accurately describe the key physical parameters and their *non-intuitive*temperature dependences, which are rather different compared to the traditional silicon (Si) counterparts. In addition, regardless of the technology, the pre-processing geometry/mesh construction within the environment of the thermal solver is onerous and troublesome. Lastly, these approaches are very resource-hungry and prone to convergence failures, especially if dynamic simulations under critical conditions have to be performed.

In this paper, an innovative *circuit-based* ET simulation approach is proposed for multicellular SiC power MOSFETs, with the ambition of optimizing the trade-o ff between computational e fficiency and accuracy. The strategy is articulated as follows: (i) the device is discretized into an assigned number *N* of individual cells (each associated to an independent heat source) described with a simple, ye<sup>t</sup> accurate model accounting for the relevant influence of SiC/SiO2 interface traps; (ii) the cell model is implemented with a SPICE-compatible subcircuit; (iii) an exceptionally accurate 3D finite-element method (FEM) description of the device is e ffortlessly obtained through a commercial solver aided by an *in-house* routine; (iv) the FANTASTIC code [6] is invoked, which *automatically* generates a dynamic compact thermal model (DCTM) of the device from the FEM representation, and thus builds an electrical network emulating the power-temperature feedback; (v) such a network is enriched with suitable voltage sources to account for nonlinear thermal e ffects, and the resulting circuit is referred to as *thermal feedback block*; (vi) a *purely-electrical macrocircuit* describing the whole ET behavior of the power device is constructed by connecting the *N* cell subcircuits to the thermal feedback block; (vii) the macrocircuit can be solved by *any* commercial circuit simulator in very short times and with unlikely occurrence of convergence problems. A multicellular 4H-SiC power MOSFET soldered on a direct bonded copper (DBC) substrate and operated under dc, short-circuit (SC), and unclamped inductive switching (UIS) conditions is considered as a case study.

This work extends the preliminary contribution [7], where a fully circuital representation of the SiC power MOSFET was obtained and solved with a similar approach. However, the generation of the thermal feedback block, based on Foster networks, was carried out in a long pre-processing stage involving *N* 3D FEM transient simulations, as well as a procedure to determine the proper number of RC pairs of each network and identify their values; in addition, the thermal interactions among horizontally-far cells were either coarsely described or even disregarded.

The remainder of the paper is articulated as follows. In Section 2, the device selected to test the approach and the experimental setup are described. Section 3 offers details concerning the transistor model used for the elementary cells. Section 4 probes into the ET simulation approach. Results are reported and discussed in Section 5. Conclusions are then drawn in Section 6.
