**Shin-Ju Chen 1, Sung-Pei Yang 1,2,\*, Chao-Ming Huang <sup>1</sup> and Yu-Hua Chen <sup>1</sup>**


Received: 13 April 2020; Accepted: 14 May 2020; Published: 16 May 2020

**Abstract:** A novel interleaved high step-up DC–DC converter applied for applications in photovoltaic systems is proposed in this paper. The proposed configuration is composed of three-winding coupled inductors, voltage multiplier cells and a clamp circuit. The step-up voltage gain is effectively increased, owing to the voltage-stack and voltage-lift techniques using the voltage multiplier cells. The leakage inductor energy is recycled by the clamp circuit to avoid the voltage surge on a power switch. The low-voltage-rated power switches with low on-state resistances and costs can be used to decrease the conduction losses and increase the conversion efficiency when the voltage stresses of power switches for the converter are considerably lower than the high output voltage. The reverse-recovery problems of diodes are mitigated by the leakage inductances of the coupled inductors. Moreover, both the input current ripple and the current stress on each power switch are reduced, owing to the interleaved operation. The operating principle and steady-state analysis of the proposed converter are thoroughly presented herein. A controller network is designed to diminish the effect of the variations of input voltage and output load on the output voltage. Finally, the experimental results for a 1 kW prototype with 28–380 V voltage conversion are shown to demonstrate its effectiveness and performance.

**Keywords:** interleaved operation; three-winding coupled inductor; high step-up DC–DC converter

### **1. Introduction**

Because of the fast exhaustion of fossil fuels and the global warming problem, much research has been developed to cope with green energy sources, such as the fuel cells, photovoltaic power (PV power) or wind power. Generally, a single-phase 220 Vac grid-connected photovoltaic system requires a DC bus voltage of 380–420 V to provide the requirement for a full-bridge DC–AC inverter. Regrettably, the output voltages of individual PV modules are ordinarily lower than 40 V in household applications [1]. Thus, a high step-up DC–DC converter is necessary to serve as a voltage boosting cell between the PV modules and the AC power generation unit [2–4].

For a traditional boost converter, an extreme duty ratio operation has to be realized to obtain a high voltage gain. However, it will result in large current ripples, high conduction losses, reverse-recovery problems for diodes, and electromagnetic interference problems [5]. In addition, the voltage stresses on the power switches and diodes are equal to the high output voltage. Thus, high-voltage-rated MOSFETs with high on-state resistance and diodes with high forward voltage drop should be used, which leads to lower efficiency due to high conduction losses. To proceed, isolated power converters, such as a conventional flyback DC–DC converter, can derive a high voltage gain by adopting a high transformer turns ratio, which results in a large leakage inductance. A large leakage inductance will cause a much higher voltage spike on the power switch and more power dissipations. Consequently, the aforementioned converters are not proper for use in a high step-up voltage gain application.

To overcome the above problems in high voltage gain applications, many high step-up converters have been presented in the literature. Coupled inductors have been adopted to obtain a high voltage gain in the non-isolated converters, because the turns ratio can be served as a control freedom to enlarge the voltage gain [6–10]. Recently, a three-winding coupled inductor has also been applied to a lot of high step-up DC–DC converters to achieve higher voltage gains [11–13]. In [14–19], the switched-inductor and/or switched-capacitor step-up converters are presented to derive a high voltage gain, owing to their simpler structure and operation. A double-duty technique was applied in the high step-up voltage gain applications with two distinct duty ratios for the power switches in [20,21]. The parallel structure on the input side with interleaved operation can be utilized to increase the power level and reduce the input current ripple. The voltage multiplier cells were also applied to the interleaved high step-up converters in [22–24]. The built-in transformer technique for obtaining a high step-up conversion ratio is presented in [25–27]. The interleaved DC–DC converters with three-winding coupled inductors in [28–30] exhibited a high voltage gain and better current sharing performance simultaneously.

An IA novel interleaved high step-up DC–DC converter is proposed in this paper. It contains three-winding coupled inductors, voltage multiplier cells and a clamp circuit. The voltage-stack and voltage-lift techniques are adopted to extend the voltage gain by means of the voltage multiplier cells. The clamp circuit is utilized to recycle the leakage inductor energy and clamp the voltage stress of power switches. The advantages of the proposed high step-up converter are as follows:


A prototype of 1 kW was implemented in the laboratory to verify the theoretical analysis and the performance of the proposed interleaved high step-up converter. The remainder of this paper is organized as follows. In Section 2, the circuit description is given, and the operating principle is presented in detail simultaneously. Section 3 shows the steady-state analysis. The performance comparison with existing converters is also presented. The closed-loop controller design is provided in Section 4. Section 5 provides the experimental results of a laboratory prototype. Finally, the conclusion of this paper is given in Section 6.

#### **2. Circuit Description and Operating Principle**

Figure 1 shows the circuit topology of the proposed converter. Two three-winding coupled inductors with the same number of turns are included in the proposed converter. The primary, secondary and tertiary windings are denoted by *N*1, *N*<sup>2</sup> and *N*3, respectively. The coupling reference is indicated by and ∗. The primary windings are parallel connected to process the large input current and serve as the filter inductors in the conventional boost converter. The secondary windings are connected in series to constitute the voltage multiplier cell I, which is inserted between the clamp circuit and the output high voltage side to lift the output voltage. The tertiary windings are in series

connection to constitute the voltage multiplier cell II, which is stacked on the output capacitor *C*<sup>1</sup> to enlarge the voltage conversion ratio.

**Figure 1.** Circuit configuration of the proposed converter.

The coupled inductor is modeled as an ideal transformer with a defined turns ratio, which is in parallel with a magnetizing inductor and in series with a leakage inductor.*Lm*<sup>1</sup> and *Lm*<sup>2</sup> represent the magnetizing inductances, while *Lk*<sup>1</sup> and *Lk*<sup>2</sup> represent the leakage inductances. Assuming that the number of turns *N*<sup>3</sup> is equal to *N*2. *n* is defined as the turns ratio with *n* = *N*2/*N*<sup>1</sup> =*N*3/*N*1. The equivalent circuit of the proposed converter is illustrated in Figure 2, where *S*<sup>1</sup> and *S*<sup>2</sup> are the power switches; *Dc*<sup>1</sup> and *Dc*<sup>2</sup> are the clamp diodes; *Cc* is the clamp capacitor; *D*-<sup>1</sup> and *D*-<sup>2</sup> are the lift diodes; *C*-<sup>1</sup> and *C*-<sup>2</sup> are the lift capacitors; *Ds*<sup>1</sup> and *Ds*<sup>2</sup> are the switched diodes; *C*1, *C*<sup>2</sup> and *C*<sup>3</sup> are the output capacitors; *Do* is the output diode; *Vin* is the input voltage; *Vo* is the output voltage; and *R* is the output load.

**Figure 2.** Equivalent circuit of the proposed converter.

The proposed converter operates in continuous conduction mode (CCM). The gate signals of the power switches are interleaved with 180 phase shift, the duty ratios are the same, and they are greater than 0.5. The theoretical waveforms are shown in Figure 3. In CCM operation, the operating mode of the proposed converter can be partitioned into eight stages over one switching period. Figure 4 shows the corresponding circuit models for the eight operating stages.

**Figure 3.** Theoretical waveforms of the proposed converter.

**Stage 1** [*t*<sup>0</sup> ∼ *t*1]: The equivalent circuit of this stage is depicted in Figure 4a. At *t* = *t*0, the power switch *S*<sup>1</sup> starts to turn on with zero-current switching (ZCS) operation, owing to the leakage inductance *Lk*1, and *S*<sup>2</sup> is still in a turn-on state. The diodes *Dc*1, *Dc*2, *D*-1, *D*-<sup>2</sup> and *Ds*<sup>2</sup> are reversed biased, and *Do* as well as *Ds*<sup>1</sup> are still turned on. The current through *Lk*<sup>1</sup> increases rapidly from zero, while the currents through the secondary and tertiary windings of the coupled inductors decrease. The current falling rates through *Do* and *Ds*<sup>1</sup> are controlled by the leakage inductances *Lk*<sup>1</sup> and *Lk*2, such that the diode reverse recovery problem is alleviated. The stored energy in the magnetizing inductor *Lm*<sup>1</sup> is transferred to the output side via the secondary and tertiary windings of the coupled inductors. The following equations are valid:

$$i\_{p2} = -i\_{p1} = n(i\_{\text{Do}} + i\_{\text{Do1}}) \tag{1}$$

$$i\_{Lk1} = i\_{Lm1} + i\_{p1} = i\_{Lm1} - n(i\_{Do} + i\_{Ds1}) \tag{2}$$

As the leakage inductor current *iLk*<sup>1</sup> reaches the magnetizing inductor current *iLm*1, this stage ends. At the same time, the currents through the diodes *Do* and *Ds*<sup>1</sup> fall to zero, and *Do* and *Ds*<sup>1</sup> are turned off with ZCS operation.

**Stage 2** [*t*<sup>1</sup> ∼ *t*2]: The power switches *S*<sup>1</sup> and *S*<sup>2</sup> remain in a turn-on state, and all of the diodes are in a turn-off state. Figure 4b depicts the corresponding operating circuit. The currents through inductors *Lm*1, *Lk*1, *Lm*<sup>2</sup> and *Lk*<sup>2</sup> increase linearly because these inductors are charged from the input DC source. The leakage inductor currents are as follows.

$$i\_{Lk1}(t) = i\_{Lk1}(t\_1) + \frac{V\_{in}}{L\_{m1} + L\_{k1}}(t - t\_1) \tag{3}$$

$$i\_{Lk2}(t) = i\_{Lk2}(t\_1) + \frac{V\_{in}}{L\_{m2} + L\_{k2}}(t - t\_1) \tag{4}$$

This stage ends when *S*<sup>2</sup> is turned off.

**Stage 3** [*t*<sup>2</sup> ∼ *t*3]: In this stage, the switch *S*<sup>2</sup> is in a turn-off state, and *S*<sup>1</sup> keeps conducting. The operating circuit is illustrated in Figure 4c. The clamp capacitor *Cc* is charged by the current *iLk*<sup>2</sup> via the clamp diode *Dc*2. The leakage inductor energy is released to the capacitor *Cc*. The current *iLk*<sup>2</sup> decreases linearly. The voltage across the switch *S*<sup>2</sup> is clamped by the capacitor voltage *VCc*. The energy stored in *Lm*<sup>2</sup> is released to the capacitors *C*-1, *C*-<sup>2</sup> and *C*<sup>2</sup> via the secondary and tertiary windings of the coupled inductors. The lift capacitors *C*-<sup>1</sup> and *C*-<sup>2</sup> are charged by the lift diode currents *iD*-<sup>1</sup> and *iD*-2, respectively. At the same time, the output capacitor *C*<sup>2</sup> is charged by the current *iDs*2. The following equations are valid:

$$i\_{p1} = -i\_{p2} = n i\_{Dd2} + n(i\_{D\ell1} + i\_{D\ell2}) \tag{5}$$

$$i\_{Lk2} = i\_{Lm2} - ni\_{Dk2} - n(i\_{D\ell1} + i\_{D\ell2}) \tag{6}$$

The stage finishes as *iLk*<sup>2</sup> falls to zero at *t* = *t*3, and the clamp diode *Dc*<sup>2</sup> becomes reverse-biased under ZCS operation. Thus, there is no reverse recovery loss for *Dc*2.

**Stage 4** [*t*<sup>3</sup> ∼ *t*4]: At the beginning time, the clamp diode *Dc*<sup>2</sup> is naturally turned off when the leakage inductor energy stored in *Lk*<sup>2</sup> has fully released to the clamp capacitor *Cc*. The operating circuit is illustrated in Figure 4d. Magnetizing inductor *Lm*<sup>2</sup> still transfers its energy to charge *C*-1, *C*-<sup>2</sup> and *C*<sup>2</sup> via the secondary and tertiary windings of the coupled inductors. The current through the power switch *S*<sup>1</sup> is the summation of the currents in the magnetizing inductors *Lm*<sup>1</sup> and *Lm*2. The following equations are held in this stage:

$$i\_{Lm2} = n(i\_{D\ell1} + i\_{D\ell2}) + n i\_{Ds2} \tag{7}$$

$$i\_{S1} = i\_{Lm1} + i\_{Lm2} \tag{8}$$

This stage finishes when the turn-on signal is applied to *S*2.

**Stage 5** [*t*<sup>4</sup> ∼ *t*5]: In this stage, the operating circuit is depicted in Figure 4e. The switch *S*<sup>2</sup> turns on at time *t*<sup>4</sup> under ZCS condition, owing to the leakage inductance *Lk*2, and *S*<sup>1</sup> is still conducting. The current *iLk*<sup>2</sup> increases rapidly from zero, and the currents in the secondary and tertiary windings of the coupled inductors decrease. The current falling rates through *D*-1, *D*-<sup>2</sup> and *Ds*<sup>2</sup> are dominated by *Lk*<sup>1</sup> and *Lk*2, such that the diode reverse recovery problem is mitigated. As the leakage inductor current *iLk*<sup>2</sup> reaches *iLm*2, this stage ends at *t* = *t*5. At the same time, the currents through *D*-1, *D*-<sup>2</sup> and *Ds*<sup>2</sup> fall to zero, and these diodes are naturally turned off with ZCS operation.

**Stage 6** [*t*<sup>5</sup> ∼ *t*6]: The switches *S*<sup>1</sup> and *S*<sup>2</sup> are conducting in this interval. All of the diodes are in a turn-off state. The operating circuit is depicted in Figure 4f. The operating modes of stages 1 and 6 are similar. At the end of this stage the switch *S*<sup>1</sup> is turned off.

**Stage 7** [*t*<sup>6</sup> ∼ *t*7]: The switch *S*<sup>1</sup> is turned off at time *t*6. The operating circuit is illustrated in Figure 4g. One part of the leakage inductor energy stored in *Lk*<sup>1</sup> is released to the clamped capacitor *Cc*, and another part of the leakage inductor energy is recycled to the output side. The leakage inductor current *iLk*<sup>1</sup> is falling. The input voltage *Vin*, *C*-<sup>2</sup> and *C*-<sup>1</sup> are in series connection to transfer energy to the output capacitor *C*<sup>1</sup> via diodes *Dc*<sup>1</sup> and *Do*, as well as the primary and secondary windings of the coupled inductors, thus extending the voltage on the output capacitor *C*1. The stored energy in *Lm*<sup>1</sup> is delivered to the secondary and tertiary windings of the coupled inductors, such that output capacitor *C*<sup>3</sup> is charged by the diode current *iDs*1, and *C*<sup>1</sup> is charged by the diode current *iDo*. As the leakage

inductor current *iLk*<sup>1</sup> drops to zero, the diode *Dc*<sup>1</sup> becomes reverse-biased and turns off at time *t*<sup>7</sup> under ZCS condition. Thus, there is no reverse recovery loss for *Dc*1. At this moment, this stage ends.

**Stage 8** [*t*<sup>7</sup> ∼ *t*8]: Figure 4h illustrates the operating circuit. At the beginning time, the leakage inductor energy stored in *Lk*<sup>1</sup> has completely released. Magnetizing inductor *Lm*<sup>1</sup> still transfers energy to the capacitors *C*<sup>1</sup> and *C*<sup>3</sup> via the secondary and tertiary windings of the coupled inductors. The capacitors *Cc*, *C*-1, *C*-<sup>2</sup> and the secondary windings are connected in series to transfer their energy to the output capacitor *C*1. The current in the switch *S*<sup>2</sup> is the summation of the currents *iLm*<sup>1</sup> and *iLm*2. The switch *S*<sup>1</sup> is turned on at the end of this stage. Then, a new switching period begins to start.

**Figure 4.** Operating stages of the proposed converter. (**a**) Stage 1, (**b**) Stage 2, (**c**) Stage 3, (**d**) Stage 4, (**e**) Stage 5, (**f**) Stage 6, (**g**) Stage 7, (**h**) Stage 8.

#### **3. Steady-State Analysis**

*3.1. Voltage Gain Derivation*

To briefly describe the voltage gain derivation, the following assumptions are used:


All of the capacitors are large enough. As a result, the voltages across them are considered constant during one switching period. Based on the volt-second balance principle of the magnetizing inductance *Lm*1, the voltage on the clamp capacitor *Cc* can be derived as

$$V\_{\mathbb{C}\varepsilon} = \frac{1}{1 - D} V\_{in} \tag{9}$$

where *D* is the operating duty ratio. The result in Equation (9) is identical to the output voltage of a conventional boost converter.

Let the voltages across the secondary and tertiary windings of the coupled inductors be denoted by *V*<sup>I</sup> *<sup>N</sup>*<sup>2</sup> and *<sup>V</sup>*<sup>I</sup> *<sup>N</sup>*3, *<sup>V</sup>*II *<sup>N</sup>*<sup>2</sup> and *<sup>V</sup>*II *<sup>N</sup>*3, respectively. According to Kirchhoff's Voltage Low (KVL), the voltages across the lift capacitors *C*-<sup>1</sup> and *C*-<sup>2</sup> can be calculated from stage 3 as

$$V\_{\mathbb{C}\ell1} = V\_{\mathbb{C}\ell2} = V\_{N2}^{\mathbb{I}} - V\_{N2}^{\mathbb{II}} = nV\_{\text{in}} - n(V\_{\text{in}} - V\_{\mathbb{C}\varepsilon}) = nV\_{\mathbb{C}\varepsilon} \tag{10}$$

Moreover, it also yields

$$\mathbf{V\_{C2}} = V\_{N3}^{\mathrm{I}} - V\_{N3}^{\mathrm{II}} = nV\_{\mathrm{in}} - n(V\_{\mathrm{in}} - V\_{\mathrm{Cc}}) = nV\_{\mathrm{Cc}} \tag{11}$$

Substituting Equation (9) into Equations (10) and (11), the capacitor voltages are rewritten as

$$V\_{C\ell1} = V\_{C\ell2} = \frac{n}{1 - D} V\_{in} \tag{12}$$

$$V\_{C2} = \frac{n}{1 - D} V\_{\dot{m}} \tag{13}$$

By applying KVL in stage 7, the voltage *VC*<sup>3</sup> across the output capacitor *C*<sup>3</sup> can be derived as

$$V\_{\mathbb{C}3} = V\_{N3}^{\text{II}} - V\_{N3}^{\text{I}} = nV\_{\mathbb{C}\varepsilon} = \frac{n}{1 - D}V\_{\text{in}} \tag{14}$$

Moreover, the voltage across the output capacitor *C*<sup>1</sup> is derived as

$$V\_{\rm C1} = V\_{\rm N2}^{\rm II} - V\_{\rm N2}^{\rm I} + V\_{\rm C2} + V\_{\rm C1} + V\_{\rm C2} = \frac{3n+1}{1-D} V\_{\rm in} \tag{15}$$

According to (13)–(15), the output voltage can be obtained as follows:

$$V\_o = V\_{C1} + V\_{C2} + V\_{C3} = \frac{5n+1}{1-D} V\_{in} \tag{16}$$

Hence, we have the ideal voltage gain *M* of the proposed converter as

$$M = \frac{V\_o}{V\_{in}} = \frac{5n+1}{1-D} \tag{17}$$

The plot of voltage gain *M* versus turns ratio *n* and duty ratio *D* is drawn in Figure 5. It shows that the turns ratio has a significant impact on the step-up voltage gain. In addition, the high voltage gain can be achieved without any extreme duty ratio or high turns ratio in the proposed converter. When the duty ratio is merely 0.6 and turns ratio *n* = 1, the voltage gain is calculated as 15.

**Figure 5.** Voltage gain curve versus duty ratio with different turns ratio.

#### *3.2. Voltage Stresses on Semiconductor Devices*

The steady-state analysis reveals that the voltage on the power switches and the clamp diodes during their off-state are all equal to the voltage on the clamp capacitor. From Equations (9) and (17), the voltage stresses are given by

$$V\_{S1} = V\_{S2} = V\_{Dc1} = V\_{Dc2} = V\_{Cc} = \frac{1}{1 - D} V\_{in} = \frac{1}{5n + 1} V\_o \tag{18}$$

Moreover, the voltage stress on the switching diode *Ds*<sup>1</sup> can be derived as

$$V\_{D\approx 1} = V\_{C2} + V\_{C3} = \frac{2n}{1 - D}V\_{in} = \frac{2n}{5n + 1}V\_o \tag{19}$$

The voltage stress on the output diode *Do* is given by

$$V\_{Do} = V\_{C1} - V\_{C1} - V\_{Cc} = \frac{2n}{1 - D}V\_{in} = \frac{2n}{5n + 1}V\_o \tag{20}$$

Similarly, the voltage stresses on the diodes *Ds*2, *D*-<sup>1</sup> and *D*-<sup>2</sup> can be derived as

$$V\_{D32} = V\_{D\ell1} = V\_{D\ell2} = \frac{2n}{1-D}V\_{in} = \frac{2n}{5n+1}V\_o \tag{21}$$

From Equations (18)–(21), the relationship between the normalized voltage stresses on semiconductor devices and the turns ratio of the coupled inductors is shown in Figure 6.

**Figure 6.** Normalized voltage stresses on semiconductor devices.

As the turns ratio increases, the voltage stresses on *S*1, *S*2, *Dc*<sup>1</sup> and *Dc*<sup>2</sup> decrease, and the voltage stresses on the other diodes become large. It is worth noting that the voltage stresses are lower than the output voltage. As a result, power MOSFETs with low *Rds*(ON) and diodes with low forward voltage drop can be employed to reduce the on-state losses and improve the conversion efficiency.

#### *3.3. Design Considerations*

#### 3.3.1. Design of Coupled Inductors

The turns ratio of the coupled inductors is designed from Equation (17). Once the duty ratio has been selected, the turns ratio *n* can be properly designed by

$$m = \frac{N\_3}{N\_1} = \frac{N\_2}{N\_1} = \frac{(1 - D)V\_o}{5V\_{in}} - \frac{1}{5} \tag{22}$$

Once the turns ratio of the coupled inductor is obtained, the magnetizing inductance can be determined from the CCM operation mode and an acceptable current ripple. The current ripple on the magnetizing inductor is identical, and given by

$$
\Delta \dot{\iota}\_{L\text{\tiny\tiny\text{\tiny\tiny\text{\tiny\phantom{\text{\tiny}}}}} = \frac{V\_{\text{\tiny\tiny\text{in}}}D}{L\_{\text{\tiny\text{m}}}f\_{\text{\tiny\text{s}}}} \tag{23}
$$

where *fs* is the switching frequency. The average magnetizing current can be derived as

$$I\_{L\text{in}} = \frac{P\_o}{2V\_{\text{in}}} = \frac{V\_o^2}{2V\_{\text{in}}R} \tag{24}$$

where *P*o is the output power. For CCM operation, the following condition holds:

$$I\_{L,m} - \frac{1}{2} \Delta i\_{L,m} > 0\tag{25}$$

Substituting Equations (23) and (24) into (25), the condition of magnetizing inductance for CCM operation is expressed as

$$L\_{\rm m} > \frac{V\_{\rm in}^2 D}{P\_o f\_s} = \frac{D(1-D)^2 V\_o^2}{\left(5n+1\right)^2 P\_o f\_s} = \frac{D(1-D)^2 R}{\left(5n+1\right)^2 f\_s} \tag{26}$$

#### 3.3.2. Design of Capacitors

The capacitors are determined to limit their voltage ripples to within an acceptable range. The output capacitor *C*<sup>1</sup> is discharged by the average load current *Io* from Stage 2 to Stage 6. Thus, its voltage ripple can be derived as

$$
\Delta V\_{\rm C1} = \frac{D l\_{\rm o}}{\mathcal{C}\_1 f\_s} \tag{27}
$$

Substituting Equations (15) and (17) into (27), the required capacitance is calculated as

$$\mathbb{C}\_{1} = \frac{(5n+1)D}{(3n+1)R f\_{\mathbb{S}}(\Delta V\_{\mathbb{C}1}/V\_{\mathbb{C}1})} \tag{28}$$

which is expressed by the specified voltage ripple on the output capacitor *C*1. Similarly, one can obtain the design of the following capacitors in terms of their own specified voltage ripples:

$$\mathcal{C}\_2 = \mathcal{C}\_3 = \frac{(5\,\text{n} + 1)D}{nRf\_s(\Delta V\_{\text{Ci}}/V\_{\text{Ci}})}, \; i = 2, 3\tag{29}$$

$$\mathbb{C}\_{\mathfrak{c}} = \frac{5n+1}{R f\_{\mathfrak{s}}(\Delta V\_{\mathbb{C}\mathfrak{c}}/V\_{\mathbb{C}\mathfrak{c}})} \tag{30}$$

#### *3.4. Performance Comparison*

Table 1 shows the performance comparison between the proposed converter and some interleaved high step-up converters published in [28–30], including voltage gain, voltage stress on switches, maximum diode voltage stress and the quantities of the devices. In these comparative converters, three-winding coupled inductors are employed to achieve high step-up voltage gain. Figure 7 shows the voltage gain comparison with turns ratio *n* = 1. As can be seen, the proposed converter has the highest voltage gain. In addition, it also has the lowest voltage stresses on the switches and diodes. The voltage stresses on the semiconductor devices are lower than the high output voltage, which results in the use of switches with low on-resistance and diodes with low forward voltage drop to reduce the conduction losses and improve the conversion efficiency. As a result, it is clear that the proposed converter is very suitable for applications requiring high efficiency and a high step-up voltage conversion ratio.

$$\mathcal{C}\_{\ell 1} = \mathcal{C}\_{\ell 2} = \frac{5n + 1}{n \mathcal{R} f\_{\mathfrak{s}} (\Delta V\_{\mathcal{C}\ell j} / V\_{\mathcal{C}\ell j})}, j = 1, 2 \tag{31}$$


**Table 1.** Performance comparison of characteristics.

**Figure 7.** Voltage gain comparison with turns ratio *n* = 1.

#### **4. Controller Design**

For the purposes of the output voltage regulation, regardless of the variations of input voltage and output load, the voltage-mode feedback control system was built as shown in Figure 8. Blocks *C*(*s*) and PWM represent the controller and pulse-width modulator, respectively. Block *P*(*s*) denotes the converter power stage. Block *K* denotes the sensor gain.

**Figure 8.** Control system block diagram.

A small-signal model was investigated through the frequency response with experimental measurements for the prototype converter. The electrical specifications and component parameters of the prototype converter are shown in Table 2. The experimental frequency response at the operating point of half load was measured by an NF FRA5012 frequency response analyzer. The Bode plot of the measured transfer function from control to scaled output voltage (*vc* to *<sup>K</sup>vo*) is shown in Figure 9 with red curves. The corresponding transfer function can be obtained by the curve-fitting method, and it is given by

$$G(s) = \frac{\overline{Kv}\_0(s)}{\overline{v}\_c(s)} = \frac{138.3(s - 45000)}{(s + 700)(s + 7000)}\tag{32}$$


**Table 2.** Electrical specifications and parameters of the prototype converter.

**Figure 9.** Comparison between measured (red) and curve-fitting (blue).

The Bode plot of the curve-fitting transfer function in Equation (32), together with the measured results, is shown in Figure 9. Comparing the magnitude and phase curves, it can be seen that the curves agree well with each other. Thus, the curve-fitting transfer function expressed in Equation (32) can be used for the controller design.

Based on the *K*-factor method [31], a type III controller [32] with three-pole and two-zero was designed for the closed-loop control system. One of the poles of the controller was located at the origin to achieve the zero steady-state error, while the other two poles were positioned below the desired crossover frequency to attenuate the switching noises in the feedback loop. In addition, the zeros and gain of the controller were adjusted to achieve the desired phase margin at the crossover frequency. The controller transfer function was designed as

$$C(s) = 3.3 \times 10^6 \frac{(s + 2659)(s + 2673)}{s(s + 1.49 \times 10^4)} \tag{33}$$

*Energies* **2020**, *13*, 2537

The controller was implemented by the operational amplifier circuit, as shown in Figure 10, and its transfer function is given by

*vc*(*s*) *Kvo*(*s*) <sup>=</sup> <sup>−</sup>*R*<sup>1</sup> <sup>+</sup> *<sup>R</sup>*<sup>3</sup> *R*1*R*3*C*<sup>2</sup> *s* + <sup>1</sup> *R*2*C*<sup>1</sup> *s* + <sup>1</sup> (*R*1+*R*3)*C*<sup>3</sup> *s s* + <sup>1</sup> *R*2*C*1*C*2/(*C*1+*C*2) *s* + <sup>1</sup> *R*3*C*3 (34) *. <sup>R</sup> Y 5 5 & & &* 

*F Y*

**Figure 10.** Controller circuit.

*9UHI*

*5*

The Bode plots of the plant *G*(*s*), the controller *C*(*s*) and the loop gain Tol(*s*) = *G*(*s*)*C*(*s*) are shown in Figure 11. As a result, a crossover frequency of 1 kHz and a phase margin of 45◦ were achieved for the output voltage controlled system.

**Figure 11.** Bode plots of plant, controller and loop gain.

#### **5. Experimental Verification**

An experimental prototype with maximal output power 1 kW was implemented and tested to verify the performance of the proposed converter. Table 2 shows the components and parameters of the prototype converter [33]. Figures 12–16 show the simulated results using IsSpice software and the experimental results under full load 1 kW condition, as described below.

**Figure 12.** Waveforms of *vgs*1, *vgs*2, *Vin* and *Vo*. (**a**) Simulated results. (**b**) Experimental results.

**Figure 13.** Waveforms of *vgs*1, *vgs*2, *vds*<sup>1</sup> and *vds*2. (**a**) Simulated results. (**b**) Experimental results.

**Figure 14.** Waveforms of *iin*, *iLk*<sup>1</sup> and *iLk*2. (**a**) Simulated results. (**b**) Experimental results.

**Figure 15.** Waveforms of *iDc*1, *vDc*1, *iDc*<sup>2</sup> and *vDc*2. (**a**) Simulated results. (**b**) Experimental results.

**Figure 16.** Waveforms of the ZCS turn-on for switches *S*<sup>1</sup> and *S*2. (**a**) and (**b**) simulated results. (**c**) and (**d**) experimental results.

Figure 12 shows the waveforms of *Vin*, *Vo*, and the gate signals *vgs*<sup>1</sup> and *vgs*2, for the switches *S*<sup>1</sup> and *S*<sup>2</sup> with interleaved operation. It can be seen that the high voltage gain was over 13 times; however, the duty ratios of the switches were not extremely large.

Figure 13 illustrates the gate signals and the drain-source voltage waveforms *vds*<sup>1</sup> and *vds*<sup>2</sup> for the switches *S*<sup>1</sup> and *S*2. It was observed that the voltage stress on *S*<sup>1</sup> and *S*<sup>2</sup> was only about 63 V, which is *Vo*/6. The switch voltage stress was much lower than the output voltage. This result meets with that of the steady-state analysis in Equation (18). Therefore, the power switch with a low voltage rating and low on-resistance can be chosen to reduce the conduction losses.

Figure 14 represents the input current *iin* and the leakage inductor currents *iLk*<sup>1</sup> and *iLk*2. Since the input current *iin* is equal to *iLk*<sup>1</sup> plus *iLk*2, one can see that the interleaved operation helps the ripple current cancellation. Consequently, the input current ripple is really small. The ripple current reduction is helpful for the lifetime of green energy sources. Moreover, a good input current sharing capability can be observed by the leakage inductor currents for the two phases of the proposed converter.

Figure 15 exhibits the currents and voltage waveforms on the clamped diodes *Dc*<sup>1</sup> and *Dc*2. One can see that the voltage stress on the diodes is about 63 V, which is only one-sixth of the output voltage. The experimental results show good agreement with the theoretical result in (18). In addition, as can be seen, the currents *iDc*<sup>1</sup> and *iDc*<sup>2</sup> fell to zero, and then the considered diodes turned off with the ZCS operation, which is consistent with the operating analysis in stages 3 and 7. Thus, there are no reverse-recovery losses for the clamped diodes *Dc*<sup>1</sup> and *Dc*2.

In Figure 16, the simulated and experimental waveforms of the voltages and the currents on the switches *S*<sup>1</sup> and *S*<sup>2</sup> are illustrated. It can be seen that the power switches can achieve ZCS turn-on operation. The switching losses are reduced accordingly for high efficiency.

Figure 17 shows the dynamic response of the output voltage under the load variation between 200W and 1000W using a dc electronic load. The dynamic response of the output voltage under the input voltage varying from 28 V to 32 V, and vice versa, is shown in Figure 18. As shown in the figures, the output voltage is insensitive to the load change and input voltage variation. It means that the

well dynamic performance of the output voltage regulation can be provided with the closed-loop controller design.

**Figure 17.** Dynamic response of output voltage under step load variation.

**Figure 18.** Dynamic response of output voltage under input voltage variation.

Figure 19 represents the conversion efficiency of the prototype converter under various output powers. A high precision power analyzer (HIOKI 3390) was employed to measure the power conversion efficiency, which is the ratio of the measured output power over the measured input power, Pout/Pin. The measured maximum conversion efficiency was up to 98%, which was obtained at the output power of 100 W. Moreover, the conversion efficiency was 91.08% at the full-load condition. At higher output power, the on-state conduction losses of switching devices are high. Then, the efficiency decreases. The photograph of the laboratory prototype is illustrated in Figure 20.

**Figure 19.** Power conversion efficiency.

**Figure 20.** Photograph of the laboratory prototype.

#### **6. Conclusions**

The three-winding coupled inductors and voltage multiplier cells, and the voltage-lift and voltage-stack techniques were utilized to create a novel high step-up DC–DC converter configuration, which is suitable for applications in PV generation systems. The proposed high step-up converter gets high voltage gain conversion with proper duty ratio operation and low voltage stresses on the switches and diodes. Switches with smaller on-resistance and diodes with lower forward voltage drop can thereby be used to reduce the conduction losses. The interleaved operation reduces the input current ripple. Moreover, the diode reverse-recovery loss is alleviated due to the leakage inductances of the coupled inductors. The leakage inductor energy is absorbed and recycled to improve efficiency. This paper presented the operating principle and steady-state analysis of the proposed converter. The closed-loop controller is also well designed for the output voltage regulation, regardless of the variations in the input voltage or output load. Finally, a 1 kW laboratory prototype was tested to verify the performance and the presented analysis. The experimental results showed that the proposed converter is suitable for high efficiency and high voltage gain in DC–DC conversion.

**Author Contributions:** S.-J.C. and S.-P.Y.: analysis and design. Y.-H.C.: experiment. C.-M.H.: supervision and inspection. S.-J.C. and S.-P.Y.: writing and editing. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was financially supported by the Green Energy Technology Research Center from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE) in Taiwan, and the Ministry of Science and Technology, Taiwan, under grant numbers MOST 108-2221-E-168-004.

**Conflicts of Interest:** The authors declare that there is no conflict of interest.

#### **References**


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