2.2.2. Energy Efficiency

The energy efficiency of NTC circuits is highly dependent on design, process variation, and runtime parameters. Scaling down the supply voltage changes the ratio of dynamic and leakage power consumption significantly, causing a paradigm shift in design and optimization. Figure 2 presents the power consumption of an IA32 processor. The contribution of logic dynamic power decreases from 81% in the super-threshold region to 4% in the sub-threshold region, whereas the contribution of logic leakage power increases from 11% to 33% [26]. Therefore, leakage power reduction techniques at architecture-level (e.g., by power-gating schemes) down to device-level (e.g., by incorporating advanced technologies such as FinFET) are more rewarding in the NTV region compared to the super-threshold region, in which leakage power has a smaller contribution.

**Figure 2.** Power breakdown of the IA32 processor presented in [26] highlights a significant increase in the relative contribution of the leakage power of logic components to the total power consumption, when supply voltage is reduced towards near-threshold and sub-threshold regimes. The rest of the power consumption is due to the memory (8%, 20%, and 63% in the super-threshold, near-threshold, and sub-threshold region, respectively.)

The methods used for addressing the variation-induced reliability challenges affect the energy efficiency as well. Some of the methods commonly used in the super-threshold region for controlling the impact of variations are too expensive in the NTV region. As an example, adding a timing margin to compensate for variation-induced timing fluctuation is energy inefficient in the NTV region due to the extent of variations. Therefore, it is necessary to design the circuits to be more resilient against timing variation, for example, by variation-aware circuit synthesis.

The MEP of a circuit points to a specific supply voltage *VMEP dd* and the maximum speed *f MEP* (inversely proportional to clock period *TMEP clk* = 1/*f MEP*) at that supply voltage. A number of factors impact the MEP of a circuit including technology, internal activity, workload, and process and runtime variations. FinFET technology offers close to 60 mV/dec sub-threshold slope leading to better Ion/Ioff ratio, which is very useful in reducing the MEP and improving the energy efficiency. It has been shown that the MEP may move from a sub-threshold voltage region to super-threshold voltage region depending on the circuit structure and circuit internal switching activity [32]. For example, the contribution of leakage power to the total power, i.e., *Pleak*/*Ptotal*, is typically larger in SRAM arrays compared to the core logic. Therefore, the MEP of SRAM arrays is higher than core logic [32]. This also means that workloads that cause higher internal switching activity (high dynamic power), will reduce the MEP of a circuit. Process and runtime variations significantly contribute to MEP fluctuation. Therefore, design optimization and runtime tuning are also necessary to achieve high energy efficiency in the NTV region.

The average impact of process variation on *VMEP dd* of the benchmark circuits is displayed in Figure 3a. The shift in *VMEP dd* due to process variation is on average 66 mV for the benchmark circuits. This shift in *VMEP dd*may lead to significant performance variation and energy overheads. Moreover, the speed (*TMEP clk*)

of some circuits is also highly affected by process variation. Figure 3b demonstrates that *TMEP clk* of a circuit may change by about one order of magnitude when it is under different process variation impacts.

The impact of temperature variation is shown in Figure 4, where the MEP is plotted for different temperatures ranging from −25 to 100 °C. The clock period corresponding to the MEP (*TMEP clk* ) is also greatly affected by the change in the circuit temperature, with an exponential dependency. Comparing Figures 3 and 4 reveals that the impact of temperature could be much stronger than the impact of the process variation. This is also in line with the reported process and temperature variation sensitivities as in [27,28,33,47].

**Figure 3.** Process variation impact on the MEP of some ISCAS'85 benchmark circuits [71]. (**a**) Process variation can change *VMEP dd* on average by 66 mV. (**b**) Process variation can change *TMEP Clk* by up to an order of magnitude over different process corners.

**Figure 4.** Temperature variation impact on the MEP of some ISCAS'85 benchmark circuits [71]. (**a**) Up to 80 mV variation in *VMEP dd* is observed over 125 °C temperature change. (**b**) More than 2 orders of magnitude variation in *TMEP clk*is observed over 125 °C temperature change.

Figure 5 shows the change in *VMEP dd* for circuit c499 of ISCAS'85 benchmark due to a change in the internal switching activity. The x-axis of the figure represents the ratio of the dynamic energy to the leakage energy of the circuit (Dynamic/Leakage), when the circuit is operating at the nominal supply voltage (*VNOM dd* ). The Dynamic/Leakage value has an inverse relation with *VMEP dd* as demonstrated in Figure 5. According to this figure, if the input switching activity *α* changes from 0.01 to 0.1, the *VMEP dd* can vary from 0.49 V down to 0.35 V as Dynamic/Leakage increases. In a pure combinational circuit such as c499, the impact of workload variation could be very high as the dynamic power consumption *Pdyn* is dependent on the input switching activity *α*. However, in sequential circuits, a large portion of dynamic power consumption is related to the clock network. In such cases, *Pdyn* variation due to *α* fluctuation is typically less than in combinational circuits. Therefore, workload variation can also have a significant impact on energy efficiency, depending on the circuit architecture.

**Figure 5.** Workload variation impact on the MEP. The change in the *VMEP dd* versus the ratio of dynamic to leakage energy at nominal *Vdd*. The realistic change in the input switching activity *α* is displayed by the light blue box (0.062 ≤ *α* ≤ 0.108) [71].

In summary, the energy efficiency of NTC circuits is highly affected by PVT. Design optimization methods can effectively improve energy efficiency by reducing the leakage power. Runtime tuning methods can adapt the circuit to operate at the MEP, which fluctuates at runtime due to temperature and workload fluctuation.
