**2. Near-Threshold Computing**

Various methodologies at different abstraction-levels have been proposed and employed [18–22,34–36] to improve the energy efficiency and overcome the power wall challenge caused by the end of Dennard's scaling [9–12]. Aggressive supply voltage scaling down to the sub-threshold region [12,18,23–25] is also presented as an effective way to reduce the power consumption by several orders of magnitude; however, the speed of digital circuits at that supply voltage range is poor. In the following, we present a promising approach towards supply voltage scaling, called NTC, which also retains enough performance for many applications.

Near-Threshold Computing is a paradigm in which the supply voltage is reduced close to the threshold voltage of transistors to gain large energy efficiency while retaining enough performance for many applications. However, there are various challenges towards NTC mainly in the area of reliability and energy efficiency, which can nullify the benefits of NTC if not addressed correctly. This paper focuses on the NTC and its challenges.

From a circuit-level point of view, the total power consumption of a circuit can be calculated as in Equation (1):

$$P\_{\text{total}} = P\_{\text{dyn},sw} + P\_{\text{dyn},sc} + P\_{\text{leak}} \tag{1}$$

where *Pdyn*,*sw*, *Pdyn*,*sc*, and *Pleak* are dynamic switching power, dynamic short-circuit power, and leakage power, respectively.

In the nominal supply voltage, the *Pdyn*,*sw* is the dominant power consumption, which is quadratically dependent on the supply voltage, as shown in Figure 1a. Therefore, reducing the supply voltage can quadratically reduce the overall power consumption. In the same supply voltage regime, the speed of a circuit is linearly dependent on the supply voltage.

The energy consumption is calculated according to Equation (2):

$$E\_{total} = P\_{total} \times T\_{clk} = E\_{dyn,sw} + E\_{dyn,sc} + E\_{leak} \tag{2}$$

Therefore, by slightly reducing the supply voltage from the nominal voltage, it is possible to reduce the energy consumption, linearly. As shown in Figure 1b, this energy improvement holds as long as the rate of total power consumption reduction is higher than the rate of speed degradation. When *Vdd* goes below *Vth*, the speed degradation becomes exponential because the current has an exponential relation with supply voltage. Therefore, energy consumption starts to increase due to higher rate of speed degradation. As a result, the supply voltage leading to minimum energy consumption is somewhere close to the threshold voltage of transistors. Such operating condition leading to the best energy efficiency, i.e., the lowest energy consumption, is commonly known as the Minimum Energy Point (MEP) and is shown in Figure 1b for c499 circuit from ISCAS'85 benchmark circuits [37,38].

**Figure 1.** MEP exploration for circuit c499 from ISCAS'85 benchmark [37,38]. (**a**) Circuit power and clock period versus supply voltage ( *Vdd*); (**b**) Minimum Energy Point (MEP). Minimum Energy Per operation is achieved where *Vdd* is close to *Vth*.

## *2.1. MOSFET Model in the Near-Threshold Voltage region*

The conventional three-region long-channel MOSFET model as well as the alpha-power model [39] are piece-wise models with a discontinuity at the threshold voltage of transistors, which makes them inappropriate for NTC circuit analysis. However, it is possible to explain the characteristics of MOSFET based on continuous models such as EKV [40–42]. Accordingly, a simplified trans-regional model for digital NTC CMOS circuits is proposed in [43], which facilitates analytical analysis. Based on this model, the MOSFET on-current can be obtained based on the overdrive voltage *Vov* as follows:

$$I\_{ds,NTC} = I\_{\rm x} k\_0 e^{k\_1 \frac{V\_{\rm avr}}{nV\_T} + k\_2 \left(\frac{V\_{\rm avr}}{nV\_T}\right)^2}, \qquad V\_{\rm av} = V\_{\rm \%} - V\_{th\prime} \tag{3}$$

where *Ix* depends on process parameters and transistor dimensions (*W*, *L*), whereas *k*0, *k*1, and *k*2 are process independent fitting parameters [43]. In the above equation, it is assumed that *Vds* - *VT*; therefore, the term depending on *Vds* is eliminated. However, it is possible to consider the threshold voltage dependency on *Vds* and body-biasing. Based on this model, the propagation delay of a gate in the Near-Threshold Voltage (NTV) region is obtained as:

$$t\_{p,NTC} = \frac{k\_f C\_L V\_{dd}}{I\_x k\_0} \varepsilon^{-k\_1 \frac{V\_{dd}}{\pi V\_T} - k\_2 \left(\frac{V\_{dd}}{\pi V\_T}\right)^2}, \qquad V\_{dt} = V\_{dd} - V\_{th}.\tag{4}$$

Similarly, energy and power consumption of digital circuits can be calculated in the NTV region [43].

Process, Voltage, and Temperature Variation in NTC

The impacts of process, supply voltage, and temperature variations (PVT) are more pronounced in the NTV region [27,33,44]. Authors of [45] showed that the sensitivity of the drain-source current of a transistor (*Ids*) to changes in *Vth* and *Vdd* increases by about 10× when the supply voltage is reduced from the super-threshold region to the sub-threshold region. Equation (4) also demonstrates that propagation delay in the NTV region is exponentially dependent on supply and threshold voltages. Intel [33] reported that while the process and temperature variations cause 18% and 5% performance variation in the super-threshold region, their impacts aggravate to 2× performance variation in the NTV region.

The power consumption of NTC circuits is orders of magnitude smaller than the super-threshold region. As a result, runtime supply voltage fluctuation caused by power consumption also decreases by the same scale, which makes it insignificant in NTC circuits, even considering the large sensitivity to fluctuations. Moreover, the temperature of NTC circuits is solely determined by the ambient temperature since the power dissipation is very small and has a negligible impact on circuit temperature fluctuation [46].
