**1. Introduction**

Wide-bandgap GaN-based high electron mobility transistors (HEMTs) are promising candidates in the applications of high-frequency and high-power electronics owing to their superior material properties such as large bandgap, high critical breakdown field, and high-density carriers in the form of two-dimensional electron gas (2DEG) with high mobility over 2000 cm<sup>2</sup>/V·<sup>s</sup> [1–5]. Nowadays, much progress has been achieved in GaN-based HEMTs with the development of the material quality and the innovation of the device structure [6,7]. However, there are still several important issues unaddressed, among which, the normally-o ff operation with a large threshold voltage (Vth) is a big concern when the chip products are pushed toward the market [8–10]. Several device architectures, such as p-GaN cap, barrier layer-recessed, fluorinated-gate, and cascode-connected metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs), have been reported to shift the threshold voltage to be positive [11–16]. Indeed, the device performances have been improved significantly in the past ten years. However, these normally-o ff HEMTs still su ffer from either large on-resistance (Ron) or low Vth which increases the risk of device switching failure. Basically, the enhancement of Vth comes at the expense of increasing the Ron of the devices. A trade-o ff, hence, has to be made between them [17]. In recent years, several novel normally-o ff schemes such as tri-gate, Fin-gate, and trench etching in the SiO2 buried layer have also been proposed and developed [18–20]. However, a truly effective device structure to gain both high Vth and low Ron simultaneously should be developed to resolve the mentioned issues effectively.

In this work, a novel scheme featuring a vertical short gate channel is proposed and demonstrated in AlGaN/GaN MIS-HEMTs to realize the normally-off operation. The source electrode is located at the trenched GaN bulk region with gate dielectric layer covering the side wall. The proposed vertical gate HEMT (VG-HEMT) is able to ge<sup>t</sup> a higher Vth (>3 V) and at the same time a lower Ron due to the short vertical channel (200–500 nm in this work). To verify this design, a conventional HEMT was fabricated and its output characteristics were utilized to extract the physical parameters for the subsequent TCAD simulations for the VG-HEMT design which finally exhibits a much higher output current and transconductance (gm) while displaying a better off-state electric field profile. The quantitative dependences of saturated current density and Ron on scattering factors in the trenched vertical gate channel were also investigated in detail in the work.

#### **2. The Proposed Device and Physical Principle**

Figure 1 shows the cross-sectional schematics of GaN-based HEMTs, where the same LGD (distance between gate and drain) and gate length (including the gate overlap) have been employed. In the conventional lateral gate-recessed HEMTs (LG-HEMTs), as shown in Figure 1a, the length of the recessed gate is usually designed to be 1–3 μm, which is limited by the influence of the UV light diffraction in the lithography process. It is hard to ge<sup>t</sup> very high pattern resolution just using the common mask aligner. If the pattern resolution below 1 μm is required, a more precise and expensive lithography apparatus such as stepper has to be used. The technology processes, such as gate channel etching and metal lift-off, with resolution below 1 μm are more rigorous and challenging, and hence increase the cost. It is not easy to control the precision around few nanometers for fully etching just the thin AlGaN barrier (~20 nm), and the resulting over-etch leads to a severe degradation of 2DEG channel mobility. Therefore, an unstable Vth and large Ron are still the typical issues unaddressed till now.

**Figure 1.** Cross-sectional schematics of (**a**) the lateral gate-recessed-high electron mobility transistors (LG-HEMT) and (**b**) the vertical gate HEMT (VG-HEMT).

In contrast to this, the conductive 2DEG channel is removed completely by fine etching in the VG-HEMTs and the source electrode is placed at the wafer body, as shown in Figure 1b. A decent source contact can be formed by Si ion implantation beneath the source region and post-annealing treatment [21]. To address the mismatch issue, the self-aligned technology will be employed in the future to precisely adjust the source metal edge to the edge of the recessed region. To make a better isolation between gate and source, a multiple dielectric stack or a relative thick dielectric film (e.g., 30 nm) will be employed. The vertical gate on the sidewall can modulate the electric field in the vertical channel for electron accumulation and hence control the device on/off switching. Considering the large G-to-S capacitance, the VG-HEMT devices will not be used in high-frequency or microwave applications. But, for the conventional switching applications at the frequency less than 1.0 MHz, they should be able to handle. Moreover, more schemes such as increasing the dielectric thickness between the gate and source and reducing the overlap dimension of the gate electrode will be employed to reduce the capacitance. To improve the gate breakdown endurance, the bi-layer dielectric and slanted gate schemes are considered and the gate overdrive circuit will also be designed to protect the device. Compared with the long recessed-gate channel in the LG-HEMTs, the main benefits in the VG-HEMTs include a shorter gate channel originated from the low-mobility trenched region based on a simple lithography technique and greater tolerance on etching depth error. Therefore, the device is able to achieve both high Vth and low Ron.

#### **3. Fabrication Work and Parameter Calibration for TCAD simulation**

The heterostructure comprising 25 nm Al0.2Ga0.8N barrier layer and 4 μm undoped GaN channel and bu ffer layers was grown on a 6-inch p-Si (111) substrate by metal-organic chemical vapor deposition (MOCVD) technique. The conventional GaN-based HEMTs were fabricated and characterized. The fabrication work started with the device isolation by employing Cl--based plasma etching. Source and drain contacts were formed by depositing Ti/Al/Ni/Au stack using E-beam evaporation system followed by a rapid thermal annealing (RTA) at 875 ◦C for 30 s in N2 atmosphere. The gate electrode was deposited by evaporating Ni/Au alloy. Then, 300 nm SiO2 layer was deposited on the device surface at 300 ◦C by plasma enhanced chemical vapor deposition (PECVD) system for passivation purpose. Figure 2a indicates the structural schematic of the GaN HEMT. Figure 2b shows the microscopy image of the fabricated device and the I–V characteristics measured using Agilent B1505A system and benchmarked by the simulation data.

**Figure 2.** (**a**) Schematic and (**b**) microscopy image of the fabricated normally-on AlGaN/GaN HEMTs, and (**c**) comparisons of output I–V characteristics of the devices for physical parameter calibration.

In TCAD simulations, Auger recombination, Shockley–Read–Hall (SRH) recombination, and Van Overstraeten–De Man models were used to simulate the device behaviors. To investigate the dry etching e ffects on the carrier mobility of gate channel in the normally-o ff devices, several mobility models were selected. The Arora model was employed to determine the doping-dependent mobility in the low-field case, and the transferred electron model was used to describe the e ffect of a transfer of electrons into an energetically higher side valley with a much larger e ffective mass in the high-field case [22]. The mobility degradations caused by high field and interface scattering are given by Meinerzhagen–Engl model and Lombardi model, respectively [23,24]. The comparison of simulated output I–V characteristics with the measurement data is shown in Figure 2c. The displayed I–V curves match well and the average mismatch for the current density is within 5%. This confirms the validity of the parameters used in the simulations. The physical parameters used in simulation are listed in Table 1 [3]. Especially, in the VG-HEMT, it is also of grea<sup>t</sup> importance to know the the mobility degradation at the etched sidewall. Thus, the effects of the etched roughness at the gate region on the device performances were investigated in detail in the next section.

**Table 1.** Physical parameters used in technology computer-aided design (TCAD) simulations after calibration [3].


#### **4. Results and Discussions**

The output I–V characteristics of the normally-off LG-HEMT and VG-HEMT are illustrated in Figure 3. The Vth values are defined by extrapolating the linear section of the ID–VG curve to the voltage axis. The normally-off operation with a positive Vth is realized in both devices. The VG-HEMT exhibits a Vth of 3.1 V and a high peak gm of 213 mS/mm compared with 3.6 V and 114 mS/mm in the LG-HEMT, respectively. The similar Vth values in both devices are found when the influence of the polar plane is ignored considering the fact that usually the gate surface polarization might be damaged severely after a long-time plasma etching in the gate recess process and the polarization charges at the lateral surface are generally compensated by the high-density surface states, such as donor-like traps.

**Figure 3.** Comparisons of (**a**) transfer characteristics, (**b**) output ID–VD curves, and (**c**) off-state breakdown characteristics between the LG-HEMT and VG-HEMT devices, and (**d**) performance comparisons among the reported normally-off HEMTs including the VG-HEMT in this work (the red star).

Theoretically, the Vth model for the MIS-HEMT can be expressed in Equation (1) [25]:

$$V\_{\rm th} = \frac{q\_{\rm b}}{q} - \frac{\Delta E\_{\rm c}}{q} - \frac{q\_f}{q} - \frac{q \cdot \Delta Q\_{\rm it} t\_{\rm ox}}{\varepsilon\_{\rm ox}} \tag{1}$$

where ϕb is the barrier height for gate metal on the dielectric (3.2 eV for Ni on Si3N4), Δ Ec the conduction band o ffset between Si3N4 and GaN (1.5 eV), ϕ*f* the conduction band distance from the Fermi-level in GaN (0.2 eV), tox the dielectric thickness (20 nm), εox the permittivity of dielectric (6.6 × 10−<sup>13</sup> F/cm), and Δ *Qit* the net charge density at the interface (~3.4 × 10<sup>12</sup> cm<sup>−</sup><sup>2</sup> in this work which is reasonable and reported widely for the III–V group GaN-based materials) [26,27]. The calculated Vth of the VG-HEMT is found to be 3.2 V, which is roughly consistent with the simulation data at 3.1 V. Furthermore, the slight di fference of the Vth value between the two devices is mainly caused by the increased drain current and transconductance values in the VG-HEMT considering that the effective vertical gate length is much less than that in the LG-HEMT. The maximum current density and Ron are found to be 793 mA/mm and 0.53 m Ω·cm<sup>2</sup> at VG = 7 V in the VG-HEMT, while 381 mA/mm and 0.92 m Ω·cm<sup>2</sup> in LG-HEMT, respectively. The VG-HEMT shows a higher drain current mainly owing to the saving of the LGS length by placing the source electrode under the gate and a shorter gate channel originated from the low-mobility trenched region. The shorter total channel length and narrower trenched-gate originated from the structural feature of the proposed VG-HEMT result in the increase of the drain current. Furthermore, a similar o ff-state breakdown voltage level (606 V vs. 615 V at ID,off = 1 μA/mm) is revealed between the VG-HEMT and LG-HEMT, as shown in Figure 3c. The proposed VG-HEMT exhibits even a lower drain leakage current owing to a more uniform electric field distribution. Figure 3d gives the performance comparisons with other reported normally-o ff HEMTs, which clearly indicates the advantage of the proposed scheme by employing a vertical short gate structure [27–34].

To further investigate the electrical behaviors of the VG-HEMT, its energy band and electron density distributions at di fferent biases are calculated and compared, as shown in Figure 4a,b. The conduction band of vertical channel is pulled down to the Fermi level with the increasing gate and drain bias and an electron density peak is formed in the conduction channel. The surface potential of the semiconductor can be a ffected by the di fferent dielectric deposition processes due to the influence of the high-density dielectric/GaN interface traps (1012–1013 cm<sup>−</sup>2) and the short distance to the conduction channel. As a result, the conduction band bending occurs at the interface, as shown in Figure 4a. The concentration of the accumulated electrons is given by Equation (2) [35]:

$$m\_{\varepsilon} = \frac{\mathbb{C}\_{\text{crr}}}{q} \cdot (V\_{\text{g}} - \frac{q\rho\_{b} - q\rho\_{t} - q\rho\_{f} - \Delta E\_{\text{c}}}{q}) \tag{2}$$

where Cox is the capacitance of the gate dielectric (3.32 × 10−<sup>7</sup> <sup>F</sup>/cm<sup>−</sup>2), Vg the applied gate voltage, and ϕ*it* the impact on the surface potential caused by the interface electrons. Using the Δ *Qit* value of 3.4 × 10<sup>12</sup> cm<sup>−</sup>2, the calculated peak *ne* at Vg = 7 V is 7.8 × 10<sup>12</sup> cm<sup>−</sup>2, which is approximately consistent with the data of 7.2 × 10<sup>12</sup> cm<sup>−</sup><sup>3</sup> for the blue line after integral calculation in Figure 4b.

Furthermore, the physical mechanisms of output current conduction in the VG-HEMT were analyzed. The ID–VD characteristics of these two devices are compared because they have similar electrode distance LGD and gate length LG. A decent source contact technology will make it easier to obtain a low source resistance and minimize the e ffect on the on-resistance. In this case, the surface roughness at the etched gate region becomes the major factor that influences the on-resistance of the device. The mobility degradation in the etched vertical channel is strongly dependent on several scattering factors. The sidewall channel mobility μ is modeled by the following expression based on Lombardi model [36]:

$$\frac{1}{\mu} = \frac{1}{\mu\_{\rm ac}} + \frac{1}{\mu\_{\rm b}} + \frac{1}{\mu\_{\rm sr}} \tag{3}$$

where μac is the mobility contribution by acoustic phonon scattering, μb the carrier mobility in bulk, and μsr the mobility contribution by surface roughness scattering. In the simulations, μac was determined to be 818 cm<sup>2</sup>/(V·s) using the equation μac = (BT/*E*eff + C/*E*eff (1/3))·(1/T) [24], where *E*eff is the effective field controlled by the channel charge, T (= 300 K) is the temperature, and B (= 9 × 10<sup>7</sup> cm/s) and C (= 5.8 × 10<sup>2</sup> cm5/3·V–2/3·<sup>s</sup>–1) are the fitting parameters, respectively [37].The μb value of 803 cm<sup>2</sup>/(V·s) is extracted from the calibration data. Considering that μac and μb are almost constant for a technically mature GaN wafer at a certain temperature, μ in the vertical channel is mainly modulated by μsr, which can be expressed as [33]:

$$
\mu\_{\rm sr} = \frac{\delta}{E\_{\rm eff}^{\alpha}} \tag{4}
$$

where α is determined by the experimental fitting. And δ is inversely proportional to the root mean square (RMS) value of the surface roughness, and is the main factor resulting in mobility degradation at the etched surface. The μsr value was then determined to be 1114 cm<sup>2</sup>/(V·s) by employing the parameters extracted from the simulation. Therefore, the mobility value of 297 cm<sup>2</sup>/(V·s) was achieved for the sidewall channel in VG-HEMT. The quantitative effects of δ values on the drain current density and Ron are shown in Figure 4c,d, taking into account the effect from the roughness scattering [37].The VG-HEMT exhibits much better current characteristics owing to the less scattering amount in the shorter gate channel, as shown in Figure 4c. Moreover, to further investigate the effect of etching damage on the output characteristic, as well as distinguish the specific damage between the sidewall and surface, more experiments will be carried out in future work.

**Figure 4.** (**a**) Energy band and (**b**) electron concentration diagrams along the horizontal direction across the gate channel ("*y*-cut" marked in the inset). (**c**) ID–VD curves affected by different δ values using Lombardi model in the VG-HEMT. (**d**) Dependences of saturated current density and Ron on δ values.

Figure 5 shows the 2-D equipotential lines and electric field distributions near the gate region in the same dimension range of the devices at VD = 400 V and VG = 0 V. With comparison, the VG-HEMT exhibits more uniform electrostatic potential and electric field distribution at the gate corner toward the drain side where usually the electrical breakdown occurs due to the high field crowding. Without an additional field plate design which requires more lithography and metal deposition steps, the VG-HEMT can ge<sup>t</sup> a reduced electric field at the gate corner owing to the presence of a "natural field plate", forming by the overlap of gate metal at the etched edge. The depletion region in the vertical gate structure is expanded to a wider range to sustain a higher voltage and hence reduce the device leakage current. Figure 5c,d show the detailed data plots of the electrostatic potential and electric field extracted in the 2DEG channel of both devices. The electrostatic potential increases more smoothly at the gate corner of the VG-HEMT, while a large field crowding happens in the LG-HEMT. The peak of electric field in the VG-HEMT is reduced to 26% compared with the LG-HEMT case, which indicates a better stability and reliability in the VG-HEMT. Furthermore, an improved breakdown voltage can be hopefully achieved when the length of the "natural field plate" is further optimized. To avoid a punch-through breakdown in the VG-HEMT due to the o ff-state conducting path formed in GaN bulk, carbon doping in GaN bulk to reduce the background carrier density and design of drain-side field plate will be considered and demonstrated in future work.

**Figure 5.** Comparisons of (**a**) electrostatic potential and (**b**) electric field distribution profiles between the LG-HEMT and VG-HEMT devices. The data plots in (**c**) and (**d**) are derived along the two-dimensional electron gas (2DEG) channel within 5 nm near the gate toward the drain side.
