**1. Introduction**

In recent years, the rapid increase in the penetration level of renewable energy (RE)-based distributed power generation (DPG) has resulted in noticeable degradation in the voltage stability and power quality (PQ) of existing power systems. The intrinsic features of DPG systems include (1) intermittent power flow caused by the utilization of maximum power point tracking (MPPT) control functions and (2) harmonic current injections caused by various power converters using switching type control techniques. Moreover, modern technologies such as automatic manufacturing systems (AMS), Internet of Things (IoT), and Industry 4.0 require a large number of power converters based on high-switching frequency power electronic devices. It can be imagined that the combination of a variety of different harmonics in load currents and unbalanced active and reactive powers can negatively affect the PQ of power networks. In practice, there are a number of compensating schemes and devices commonly used for PQ improvement applications, such as capacitor banks, passive filters, series active power filters, shunt active power filters and their combinations. Of the reported methods, the active power filter (APF) is a very widely adopted solution because, with appropriate control strategy, it is capable of providing simultaneous compensation for voltage sag, harmonic current, imbalance, and active and reactive powers. Moreover, with an external energy source and/or energy storage devices, it can also be used as an uninterruptable power supply (UPS). The main unit of an APF system is a power converter that performs the desired PQ control functions though proper switching control of power electronic devices. An APF is usually connected to the point of common coupling (PCC) in parallel or series to perform its designed functions; however, shunt APFs are more commonly used because they provide more flexible compensation functions though current-injecting control and require less auxiliary equipment. When a series APF and a shunt APF are connected with a common direct current (DC) link, they can be used simultaneously, known as a unified power quality conditioner (UPQC) [1–4].

In open literature, there are a lot of papers investigating the application of APF to the mitigation of PQ issues, such as the improvement of PCC voltage stability [5,6], compensation of harmonic currents [5–7] and unbalance load currents [7,8], injection of active power [8,9], regulation of reactive power [6,9], etc. In order to develop high-performance APFs, it is crucial to improve the switching performance of power converters. In other words, it is very desirable to achieve higher e fficiency, shorter response time, and higher power density of power converters used in APFs. To realize the aforementioned objective, wide-bandgap (WBG)-based power switching devices o ffer a promising solution. Gallium nitride (GaN) is a widely discussed WBG semiconductor material that benefits power-switching device technology with higher voltage, higher switching frequency, higher power, and better high-temperature capability in power switches compared with conventional silicon (Si)-based technologies. It has been expected that GaN high electron-mobility transistors (HEMTs) can greatly enhance the performance of power converters with less than 1-kV power switching requirement [10–12]. However, in open literature, the published papers on GaN HEMTs mostly address the manufacturing, device characteristics, driving, and switching performances [13]. Only two papers regarding GaN-based single-phase APFs were found in the Institute of Electrical and Electronics Engineers (IEEE)/Institution of Engineering and Technology (IET) Electronic Library (IEL) and ScienceDirect OnSite (SDOS) databases [14,15]. In [14], a GaN-based single-phase APF with a modified sigma-delta modulator technique was proposed and verified with simulation studies. In [15], a 5kW single-phase hybrid APF with a new control system was proposed to improve the system performance. There are currently few papers addressing the design issues and reporting performances of GaN-based three-phase inverters in practical application cases. As a result, this paper presents the key design procedure and demonstrates for the first time the performance of a 2-kVA GaN-based three-phase shunt APF system.

Following the introduction in this section, the next section will briefly describe the features of GaN HEMTs and its driving requirements. The third section addresses the mathematical modeling and control strategy of the proposed GaN-based three-phase APF based on synchronous reference frame (SRF) theory. In the fourth section, the proposed APF and control system are simulated using a comprehensive PQ control scenario. Hardware implementation and a test of a 2 kVA prototype are carried out in the fifth section. The sixth section provides some discussions on key technical issues related to the proposed GaN based three-phase APF. Finally, this paper is concluded in the last section.

#### **2. Gallium Nitride (GaN) High Electron-Mobility Transistor (HEMT) and Its Driving Requirements**

GaN HEMTs are believed to be the most promising solution for low- to medium-power applications because of their advantages such as higher breakdown voltage, lower on-resistance, and higher switching speed compared with conventional Si-based switching devices; these advantages can increase system e fficiency and power density significantly and thus lead to new opportunities for achieving power converters with improved performance. Commercially available GaN HEMTs now achieve up to 650 V/50 A and 900 V/15 A [13].

There are normally on and normally o ff GaN HEMTs. Normally on GaN HEMTs, also known as depletion mode (D mode) GaN HEMTs, are not popular because normally o ff switching devices are a common requirement for power converter applications. On the other hand, normally o ff GaN HEMTs such as enhancement mode (E mode) GaN HEMTs and cascode GaN HEMTs can be turned on with positive *VGS* and turned o ff with zero or negative *VGS*. Generally, the turn-on threshold and highest allowed driving voltages of a GaN HEMT are much smaller than those of conventional Si-based

switches. As a result, the careful design of driving circuit is necessary in order to avoid fault turn-on and high overshoot. Common suggestions include providing separate turn-on and turn-o ff driving paths, achieving minimized overlapping between driving and power loops, using Miller clamp and negative voltage sources to ensure reliable turn-o ffs, etc. [13].

#### **3. Mathematical Modeling and Control Algorithms of GaN-Based Active Power Filter (APF)**

#### *3.1. GaN-Based Three-Phase Active Power Filter*

The main power electronic circuit in a three-phase shunt APF system is a three-phase inverter. The main control functions in an APF are to adjust the DC link voltage of the three-phase inverter to the rated value and to compensate reactive power, unbalanced current and harmonic components of the load as required. The circuit architecture of the proposed three-phase inverter is shown in Figure 1. The DC link voltage control adopts dual-loop control schemes, where the inner loop controls inductor currents, and the outer loop controls DC link voltage. By controlling the inductor currents, the goals of regulating DC link voltage and compensating harmonics, unbalanced and reactive components of load currents can be achieved.

**Figure 1.** Shunt three-phase inverter.

The circuit specifications of the proposed three-phase inverter developed in this paper are the following: the three-phase line to line voltage of the grid = 110 Vrms, grid frequency = 60 Hz, rated power = 2 kVA, DC link voltage = 200 V, switching frequency = 50–100 kHz, DC voltage sensing factor = 0.012, AC current sensing factor = 0.05, AC voltage sensing factor = 0.0062, and DC voltage variation limit = 1%.

#### *3.2. Design of Direct Current (DC) Capacitor and Filter Inductors*

The main function of the DC link capacitor is to stabilize DC link voltage. If the DC link capacitance is too large, the dynamic response of the DC link voltage will be slow, and the cost of the APF hardware system will be increased; if the DC capacitor is too small, it will be di fficult to suppress the disturbance caused by external power flow. In order to design the appropriate size of the capacitor, we first define instantaneous power of the DC link:

$$P\_{dc} = V\_{dc}I\_{dc} = (\overline{V}\_{dc} + \overline{V}\_{dc})(\overline{I}\_{dc} + \overline{I}\_{dc})\_\prime \tag{1}$$

where *Vdc* and *Idc* represent DC voltage and current, respectively, which can both be separated into their respective DC components ( *Vdc* and *Idc*) and AC components ( *<sup>V</sup>dc* and *Idc*). In order to simplify the analysis, we make three assumptions: the conversion e fficiency of the three-phase inverter is 100%, *V dc* is considered zero, and *Idc* is considered zero because *Idc* is generally far larger than *Idc*. As a result, we obtain the following:

$$P\_{dc} \cong \overline{V}\_{dc} \overline{I}\_{dc}(t) = \overline{V}\_{dc} \mathbb{C}\_{dc} \frac{d\overline{V}\_{dc}(t)}{dt} \,. \tag{2}$$

where *Cdc* represents DC link capacitance. Then, we obtain the voltage variation of the DC link capacitor:

$$
\overline{V}\_{dc}(t) = \frac{1}{\mathbb{C}\_{dc}\overline{V}\_{dc}} \int\_0^t P\_{dc}(t)dt,\tag{3}
$$

where *t*0 *Pdc*(*t*)*dt* represents the capacity of the three-phase inverter. Then, we obtain DC link capacitance:

$$
\Delta V\_{dc} = \frac{S}{f\_{sw}\mathbb{C}\_{dc}\overline{V}\_{dc}} \Rightarrow \mathbb{C}\_{dc} = \frac{S}{f\_{sw}\Delta V\_{dc}\overline{V}\_{dc}}\,'\tag{4}
$$

where *fsw* represents the switching frequency. It should be noted that if an electrolytic capacitor were used for this APF design case, a higher capacitor specification will be required.

The function of the filter inductors is to filter out current ripples caused by the switching of the shunt three-phase inverter. Large inductances suppress the ripples of inductor currents but reduce the response speed of current controllers. On the other hand, although small inductances improve the response speed of the current controller, they cause large current ripples. Therefore, the inductances can be adjusted according to the actual situation. In order to design the filter inductances, we first need the following inductor voltage equation:

$$w(t) = L\_{\rm slt} \frac{di\_{\rm slt}(t)}{dt},\tag{5}$$

where *Lsh* represents inductance value, and *ish* represents inductor current. According to the relationship between voltage and current on an inductor, (5) can be expressed as follows.

$$
\Delta I\_{\rm slt} = \frac{\frac{D}{Z} \times T\_{\rm sw} \times (V\_{\rm dc} - V\_{\rm grid})}{L\_{\rm slt}},
\tag{6}
$$

where Δ*Ish* represents shunt inductor current ripple, *D* represents duty cycle, *Tsw* represents switching period, and *Vgrid* represents grid voltage. The duty cycle can be expressed the following:

$$D(\omega t) = m\_0 \sin(\omega t),\tag{7}$$

where *ma* represents modulation factor and equals modulation signal divided by triangular wave amplitude (*vcon*/*vtri*). Then, we ge<sup>t</sup> output AC voltage:

$$V\_{sl}(\omega t) = V\_{dc}m\_a \sin(\omega t). \tag{8}$$

Substituting (7) and (8) into (6) yields the following:

$$
\Delta I\_{\rm sh} = \frac{V\_{\rm dc} \times T\_{\rm sw}}{2L\_{\rm sh}} m\_d \sin(\omega t) [1 - m\_d \sin(\omega t)]. \tag{9}
$$

Then, we differentiate (9) and let the result be zero in order to obtain the maximum value of inductor current ripple:

$$\frac{d\Delta I\_{\rm sh}(\omega t)}{d\omega t} = \frac{V\_{\rm d\xi} T\_{\rm sw}}{2L\_{\rm s\rm l}} m\_{\rm a} [\cos(\omega t) - 2m\_{\rm a} \sin(\omega t) \cos(\omega t)] = 0. \tag{10}$$

As a result,

$$
\sin(\alpha t) = \frac{1}{2m\_a}.\tag{11}
$$

Lastly, substituting (11) into (9) yields the following equation:

$$L\_{\rm sh} = \frac{V\_{\rm dc}}{8f\_{\rm sw}\Delta I\_{\rm sl}}.\tag{12}$$

According to the circuit specifications of the three-phase inverter and commonly assumed inductor current ripple, 10% of output current, it is calculated that the required inductance should be at least larger than 500 μH.

#### *3.3. Mathematical Modeling and Controller's Design for GaN-Based Shunt APF*

#### 3.3.1. Mathematical Modeling

The mathematical model of the shunt-connected three-phase inverter can be derived according to Figure 1. First, the following equations are obtained with Kirchhoff's voltage law:

$$L\_{sl}\frac{di\_{sl\\_a}}{dt} = \upsilon\_{AN} - \upsilon\_{\text{grid\\_a}} - \upsilon\_{nN\nu} \tag{13}$$

$$L\_{\rm sl} \frac{di\_{\rm sl\\_b}}{dt} = \upsilon\_{\rm BN} - \upsilon\_{\rm grid\\_b} - \upsilon\_{\rm nN\nu} \tag{14}$$

$$L\_{\rm sl} \frac{di\_{\rm sl\\_c}}{dt} = \upsilon\_{\rm CN} - \upsilon\_{\rm grid\\_c} - \upsilon\_{\rm nN\\_e} \tag{15}$$

where *ish\_a*, *ish\_b*, and *ish\_c* represent three-phase inductor currents, *vAN*, *vBN*, and *vCN* represent switching point voltages, *Vgrid\_a*, *Vgrid\_b*, and *Vgrid\_c* represent three-phase grid voltages, and *vnN* represents the voltage between the grid ground and the inverter ground. Also, the three-phase three-wire system satisfies the following condition:

$$i\_{sl\\_a} + i\_{sl\\_b} + i\_{sl\\_c} = 0.\tag{16}$$

As a result, *vnN* can be expressed as the following:

$$v\_{nN} = \frac{(v\_{AN} + v\_{BN} + v\_{CN}) - (v\_{grid\\_a} + v\_{grid\\_b} + v\_{grid\\_c})}{3}.\tag{17}$$

Substituting Equation (17) into Equations (13)–(15) yields the following:

$$
\begin{bmatrix} L\_{sh} \frac{di\_{sh,a}}{dt} \\ L\_{sh} \frac{di\_{sh,b}}{dt} \\ L\_{sh} \frac{di\_{sh,\mathcal{L}}}{dt} \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 \frac{-1}{2} \frac{-1}{2} \\ \frac{-1}{2} 1 \frac{-1}{2} \\ \frac{-1}{2} \frac{-1}{2} 1 \end{bmatrix} \begin{bmatrix} v\_{AN} \\ v\_{BN} \\ v\_{CN} \end{bmatrix} - \begin{bmatrix} v\_{grid\\_d} \\ v\_{grid\\_b} \\ v\_{grid\\_c} \end{bmatrix} \tag{18}
$$

In this study, pulse width modulation (PWM) is used in the control, where the three-phase modulation signals *vcona*, *vconb*, and *vconc* are compared with *vtri* respectively to trigger the switches of all three switching legs. The output voltages of the switching legs can be expressed as follows:

$$v\_{\rm avN} = \left(\frac{1}{2} + \frac{v\_{\rm com}}{2v\_{\rm tri}}\right) V\_{\rm dc};\tag{19}$$

$$
\omega\_{bN} = (\frac{1}{2} + \frac{v\_{comb}}{2v\_{tri}}) V\_{dc};\tag{20}
$$

$$v\_{\rm tN} = (\frac{1}{2} + \frac{v\_{\rm conc}}{2v\_{\rm tri}})V\_{\rm dc}.\tag{21}$$

Substituting Equations (19)–(21) into Equation (18) and letting *Vdc*/2*Vtri* = *Kpwm* yield the following:

$$
\begin{bmatrix} L\_{\text{sl}} \frac{d\bar{l}\_{\text{sl},a}}{dt} \\ L\_{\text{sl}} \frac{d\bar{l}\_{\text{sl}}}{dt} \\ L\_{\text{sl}} \frac{d\bar{l}\_{\text{sl}}}{dt} \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 \frac{-1}{2} \frac{-1}{2} \\ \frac{-1}{2} 1 \frac{-1}{2} \\ \frac{-1}{2} \frac{-1}{2} 1 \end{bmatrix} (K\_{\text{punu}} \begin{bmatrix} \upsilon\_{\text{couz}} \\ \upsilon\_{\text{cunb}} \\ \upsilon\_{\text{couz}} \end{bmatrix} - \begin{bmatrix} \upsilon\_{\text{grid\\_a}} \\ \upsilon\_{\text{grid\\_b}} \\ \upsilon\_{\text{grid\\_c}} \end{bmatrix}). \tag{22}
$$

Using SRF theory, Equation (22) can be converted into the following:

$$
\begin{bmatrix} L\_{\text{sl}} \frac{d\mathbb{I}\_{\text{fd}}}{dt} \\ L\_{\text{sl}} \frac{d\mathbb{I}\_{\text{fd}}}{dt} \\ L\_{\text{sl}} \frac{d\mathbb{I}\_{\text{fd}}}{dt} \end{bmatrix} = K\_{\text{gauss}} \begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 0 & 1 \end{bmatrix} \begin{bmatrix} \upsilon\_{\text{cou}} \\ \upsilon\_{\text{cou}} \\ \upsilon\_{\text{ion}} \end{bmatrix} - \begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 0 & 1 \end{bmatrix} \begin{bmatrix} V\_{\text{gvd},d} \\ V\_{\text{gvd},q} \\ V\_{\text{gvd},\text{l}} \end{bmatrix} - \begin{bmatrix} 0 & \omega L\_{\text{sl}} & 0 \\ -\omega L\_{\text{sl}} & 0 & 0 \\ 0 & 0 & 0 \end{bmatrix} \begin{bmatrix} I\_{\text{sh},d} \\ I\_{\text{sh},q} \\ I\_{\text{sh},\text{l}} \end{bmatrix} \tag{23}
$$

#### 3.3.2. Design of Current Controllers

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

According to Equation (23), we can obtain block diagrams of direct-quadrature axis (d-q axis) current loops with type-II controllers as shown in Figures 2 and 3, where *ks* and *kv* represent AC current and voltage-sensing factors, respectively. Under ideal feed-forward conditions, the transfer function of current loop (d-axis or q-axis) is as follows:

$$H\_l(\mathbf{s}) = \frac{k\_s \mathcal{K}\_{\text{puv}}}{\text{s} \mathcal{L}\_{\text{sl}}}.\tag{24}$$

The transfer function of the adopted type II controller, which consists of a proportional-integral (PI) controller and a low pass filter (LPF), is as follows:

$$G\_{\bar{l}}(s) = \frac{k(s+z)}{s(s+p)}.\tag{25}$$

The loop gain can be expressed as follows:

$$L\_i(s) = G\_i(s)H\_i(s) = \frac{k(s+z)}{s(s+p)} \frac{k\_s K\_{pww}}{sL\_{\text{sl}}}.\tag{26}$$

**Figure 2.** Block diagram of d-axis current controller.

**Figure 3.** Block diagram of q-axis current controller.

In this application case, the crossover frequency of a Type II controller is designed within the range of 1/4 to 1/10 of the switching frequency. This paper chooses the controller crossover frequency to be 1/10 of the switching frequency, the zero is designed at 1/4 of the crossover frequency, and the cut-o ff frequency of the LPF is designed to be 15 kHz:

$$
\omega\_{\bar{i}} = 0.1 \times 50k \times 2\pi = 31416 rad/s. \tag{27}
$$

$$z = \omega\_{i}/4 = 7854 \text{rad/s}.\tag{28}$$

$$p = 2\pi \times 15k = 94248 rad/s.\tag{29}$$

It follows that the gain of the plant at crossover frequency (GainHi) is as follows:

$$\begin{array}{l}\text{Gain}\_{\text{Hi}} = \frac{k\_o K\_{\text{pww}}}{sL\_{\text{sh}}} = \frac{2000}{\mu\nu} = 0 - j0.0637\\ \Rightarrow |\text{Gain}\_{\text{Hi}}| = 0.0637 \end{array} \tag{30}$$

The gain of the controller at crossover frequency (GainGi1) is as follows:

$$\begin{split} \text{Gain}\_{\text{Gi1}} &= \frac{(s+z)}{s(s+p)} = \frac{j\omega\_l + 7854}{j\omega\_l(j\omega\_l + 94248)} = 8.7535 \times 10^{-6} - j5.5704 \times 10^{-6} \\ &\Rightarrow |\text{Gain}\_{\text{Gi1}}| = 1.0376 \times 10^{-5} \end{split} \tag{31}$$

Then, the required gain for compensation at crossover frequency can be calculated:

$$k = \frac{1}{|\text{Gain}\_{\text{Hi}}| \times |\text{Gain}\_{\text{Ci}1}|} = 1.5139 \times 10^6. \tag{32}$$

Finally, the transfer function is obtained as follows:

$$G\_i(s) = \frac{1.5139 \times 10^b (s + 7854)}{s(s + 94248)}.\tag{33}$$

The designed *kP* and *kI* are 16.0633 and 2.5232956, respectively. Figure 4 shows the Bode plot of the controller and plant, where the designed phase margin is 58 degrees.

**Figure 4.** Bode plot of shunt active power filter (APF) inductor current control loop.

#### 3.3.3. Design of DC Link Voltage Controller

The DC link voltage control loop regulates the real power balancing between the alternating current (AC) and DC terminals of the three-phase inverter. By ignoring steady-state operating point, we can obtain equivalent small signal model of the voltage loop as shown in Figure 5.

**Figure 5.** Equivalent circuits of the voltage control loop: (**a**) equivalent circuit under synchronous reference frame; (**b**) equivalent circuit on direct current (DC) side.

The instantaneous AC power at the AC side can be defined as follows:

$$P\_{\rm ac} = V\_m \sin \theta \ast I\_m \sin \theta + V\_m \cos \theta \ast I\_m \cos \theta,\tag{34}$$

where *Vm* and *Im* represent the maximum voltage and current under dq axes, respectively. According to trigonometric functions, Equation (34) can be simplified as follows:

$$P\_{\rm ac} = V\_{\rm m} I\_{\rm m}.\tag{35}$$

Mapping the AC side signals onto the DC side and assuming that the inverter is lossless, we obtain the following:

$$P\_{\text{ac}} = P\_{\text{dc}}\text{\textdegree} \tag{36}$$

$$V\_m I\_m = V\_{dc} I\_{dc}.\tag{37}$$

Then, we can obtain the relationship between the DC side current and the AC side current:

$$I\_{dc} = \frac{V\_m}{V\_{dc}} I\_m = k\_{dc} I\_m;\tag{38}$$

$$C\_{dc}\frac{dV\_{dc}}{dt} = I\_{dc} \Rightarrow V\_{dc} = I\_{dc}\frac{1}{sC\_{dc}}\tag{39}$$

where *kdc* represents the conversion factor from AC side to DC side. According to Equations (38) and (39), we can obtain the transfer function of DC side voltage:

$$\frac{V\_{dc}}{I\_m} = \frac{k\_{dc}}{s\mathbb{C}\_{dc}}, k\_{dc} = \frac{V\_m}{V\_{dc}}.\tag{40}$$

According to the above derivations, we can obtain the block diagram of a DC link voltage control loop with a type-II controller as shown in Figure 6, where *kvd* and *ks* represent the sensing factors of DC voltage and AC current, respectively. Therefore, the transfer function of the DC voltage loop is as follows:

$$H\_{dc}(\mathbf{s}) = \frac{k\_{\rm rd}k\_{\rm dc}}{k\_{\rm s}\mathbb{C}\_{\rm dc}\mathbf{s}}.\tag{41}$$

The transfer function of the Type II controller is defined as follows:

$$\mathcal{G}\_{\mathcal{V}}(\mathbf{s}) = \frac{k(\mathbf{s} + \mathbf{z})}{\mathbf{s}(\mathbf{s} + \mathbf{p})}. \tag{42}$$

It follows that the loop gain can be expressed as follows:

$$L\_v(s) = G\_v(s)H\_{dc}(s) = \frac{k(s+z)}{s(s+p)} \frac{k\_{vd}k\_{dc}}{k\_sC\_{dc}s}.\tag{43}$$

**Figure 6.** Block diagram of DC voltage loop type II controller.

The main purpose of the Type II controller is to use an LPF to reduce possible interference a ffecting the DC link when the APF system compensates for PQ problems such as imbalance and harmonics in three-phase load currents. The crossover frequency is set at 1/500 of that of the current loop, the cut-o ff frequency of the LPF is set at 49 Hz, and the zero is designed at 1/5 of the crossover frequency of the DC loop:

$$
\omega\_{\upsilon} = \omega\_{\text{l}} \times 0.002 = 62.832 \,\text{rad/s}; \tag{44}
$$

$$p = 2\pi \times 49 = 307.8768 \text{rad/s};\tag{45}$$

$$z = a\nu\_{\rm v}/5 = 12.5664 rad/s.\tag{46}$$

The gain of the plant at crossover frequency (GainHdc) can be calculated as follows:

$$\begin{array}{l} \text{Gainı}\_{\text{Hdc}} = \frac{k\_{\text{ml}} k\_{\text{dc}}}{k\_{\text{e}} \text{C}\_{\text{d}} s} = \frac{118.9}{j\omega\_{\text{v}}}\\ l = 0 - j1.8917 \Rightarrow |\text{Gainı}\_{\text{Hdc}}| = 1.8917 \end{array} \tag{47}$$

The gain of the controller at the crossover frequency (GainGv1) is as follows:

$$\begin{array}{l} \text{Gain}\_{\text{Gv1}} = \frac{(s+z)}{s(s+p)} = \frac{j\omega\_v + 12.57}{j\omega\_v(j\omega\_v + 307.88)} \\ = 0.003 - j0.0013 \\ \Rightarrow |\text{Gain}\_{\text{Gv1}}| = 0.0032 \end{array} \tag{48}$$

Then, the required gain compensation at the designed crossover frequency can be calculated by:

$$k = \frac{1}{|\text{Gain}\_{\text{Hdc}}| \times |\text{Gain}\_{\text{Gv1}}|} = 165.1953. \tag{49}$$

Finally, the transfer function of the voltage controller is obtained:

$$G\_{\rm{\upsilon}}(\mathbf{s}) = \frac{165.1953(\mathbf{s} + 12.5664)}{\mathbf{s}(\mathbf{s} + 307.8768)}. \tag{50}$$

The designed *kP* and *kI* are 0.5286 and 0.0001329397, respectively. Figure 7 shows the Bode plot of the controller and plant, where phase margin is 67 degrees.

**Figure 7.** Bode plot of shunt APF inductor DC link voltage control loop.

#### 3.3.4. Load Current Compensation Signals of APF

Using the SRF conversion technique, distorted and unbalanced three-phase load currents can be expressed as follows:

$$
\begin{bmatrix}
\dot{i}\_{Ld} \\
\dot{i}\_{Lq}
\end{bmatrix} = \begin{bmatrix}
\dot{i}\_{Ld} \\
\dot{i}\_{Lq}
\end{bmatrix} + \begin{bmatrix}
\overleftarrow{i}\_{Ld} \\
\dot{i}\_{Lq}
\end{bmatrix} \tag{51}
$$

where *iLd* and *iLq* represent dq-axis load currents, *iLd* and *iLq* represent dq-axis load currents with the fundamental frequency, and *iLd* and *iLq* represent the dq-axis components that require compensation. In order to obtain the compensation signals of the active current (q axis) *iLq*\*, *iLq* is firstly filtered with an LPF and then subtracted from q-axis current feedback signal (*iLq*), while the compensation signals of the reactive current (d axis) *iLd*\* equals the whole d-axis current feedback signal (*iLd*), as shown in Figure 8.

**Figure 8.** The direct-quadrature axis currents compensation signals of the APF.

#### *3.4. Complete System of GaN-Based Shunt APF*

According to Figure 8, DC link voltage controller, and inductor current controllers, we can obtain the circuit configuration of the proposed GaN based three-phase APF system with the block diagram of complete control architecture, as shown in Figure 9.

**Figure 9.** The circuit configuration of gallium nitride (GaN)-based shunt APF system and the block diagram of the control scheme.

#### **4. Simulation Study and Results**

With the design presented in the previous section, the proposed Gan-based shunt-type APF is tested for an integrated compensation of multiple power quality problems, including current harmonics, load current imbalance, and reactive currents. Powersim (PSIM) software is used to perform the simulation case of the abovementioned comparison tasks. The PSIM simulation model is shown in Figure 10.

**Figure 10.** Powersim (PSIM) simulation model of the proposed APF system.

#### *4.1. Simulation Scenario*

To demonstrate the performance of the proposed controllers, the integrated compensation for multiple load current quality problems with APF is simulated. In this case, the three-phase load bank consists of a balanced reactive load, an unbalance resistive load, and a non-linear load, as shown in Figure 11. Table 1 shows the detailed values of the loads used. At first (t0–t1), the shunt APF, connected to a three-phase power grid with the line to line voltage of 110 V, 60 Hz, adjusts the DC link voltage to 200 V and the compensation function is not activated; at t1, compensation is activated to achieve a set of balanced grid currents, zero distortion, and unit power factor (PF), as shown in Figure 12. Figures 13–17 show the corresponding simulation results, and Table 2 shows root-mean-square (RMS) currents and total harmonic distortion (THD) data before and after compensation.

**Figure 11.** Load condition in simulated scenario.


**Table 1.** Load parameters for simulation scenario.

**Figure 12.** Schematic diagram of simulated scenario.

**Figure 13.** The grid-side phase-a voltage and three-phase currents/DC link voltage/shunt APF three-phase currents (t0–t2).

**Figure 14.** Before t1: the grid phase-a voltage and three-phase currents/the fast Fourier transform (FFT) waveform of the grid phase-a current.

**Figure 15.** After t1: the grid phase-a voltage and three-phase currents/FFT waveform of the grid phase-a current.

**Figure 16.** Shunt APF DC link voltage command and feedback signals (t0–t2).

**Figure 17.** Shunt APF dq-axis current commands and feedbacks (t0–t2).


**Table 2.** Root-mean-square (RMS) currents and total harmonic distortion (THD).

#### **5. Hardware Implementation and Test Results**

To verify the performance of the proposed GaN-based APF, this section presents the implementation of APF hardware prototype for verification and analysis based on the scenario arranged in the simulation case stated in the previous section. The photograph of the constructed GaN-based APF prototype is shown in Figure 18, where the numbered devices are listed in Table 3. A programmable three-phase AC power supply is adopted to emulate the grid voltage. The Texas Instruments (TI) microcontroller, TMS320F28335 (Texas Instruments, Dallas, TX, USA), is used to provide efficiency and flexibility in controller design. The system parameters and conditions of the experimental tests and measurement scenarios are the same as that used in the previous simulation case presented in Section 4.1. Figures 19–24 show a set of test results; Figure 19 shows the waveforms of measured phase-a voltage and three-phase currents of the grid from t0 to t2. Figure 20 shows the DC link voltage and the output three-phase currents of the shunt APF from t0 to t2. The related waveforms of grid phase-a voltage and three-phase currents and the fast Fourier transform (FFT) of the grid phase-a current before the before and after the APF is activated are shown in Figures 21 and 22, respectively. As can be seen in Figure 22, after the APF is activated the unbalanced and distorted currents have been well compensated and the current is in phase with the grid voltage achieving the control objective of unity power factor. To demonstrate the performance of the designed controllers, Figure 23 shows the command and feedback signals of DC link voltage and the PI controller output signals. The dq-axis current commands and feedback signals are shown in Figure 24. To provide a set of quantitative results, Table 4 shows the measured RMS currents and calculated THD data before and after compensation. In the stage of hardware construction and tests, the system efficiencies at different switching frequencies are also explored. The arrangemen<sup>t</sup> of the test scenario and the detailed results are presented in the next section.

**Figure 18.** (**a**) Photo of GaN-based three-phase APF hardware; (**b**) schematic of the hardware test and system.

**Table 3.** Devices in Figure 18a.


**Figure19.**Gridphase-avoltage andthree-phasecurrents(t0–t2).

**Figure 20.** DC link voltage and the

 shunt

 APF three-phase  currents (t0–t2).

> grid

**Figure 21.** Before t1: the grid phase-a voltage and three-phase currents and the fast Fourier transform (FFT) waveform of the grid phase-a current.

**Figure 22.** After t1: the grid phase-a voltage and three-phase currents and FFT waveform of the

**Figure 23.** The command and feedback signals of DC link voltage and the proportional-integral (PI)controller output signal (t0–t2).

**Figure 24.** The shunt APF dq-axis current commands and feedbacks (t0–t2).


**Table 4.** RMS currents and THD.
