**1. Introduction**

A fully controlled bidirectional semiconductor switch is an element of the Conventional Matrix Converter (CMC) which offers a direct AC–AC voltages conversion with additional input power factor control functionality. This type of converter, in comparison with the more established Voltage Source Inverter (VSI), has certain individual features that determine the innovation of such a solution [1–3]. It does not contain a bulk dc-link capacitor, thus is far more promising in terms of power density with the inherent four-quadrant operation [4,5]. Compared to traditional variable speed drives with CMC, the multi-phase electric motor drive gives some fundamental advantages. These configurations have grater system redundancy because it can operate during some fault conditions, is characterized by the lower torque ripple and lower per-leg converter rating [6]. Furthermore, the operation of multiphase motors is quieter, allowing for the independent control of two or more series/parallel connected motors [7]. Multiphase

electric machines can be fed also by the conventional matrix converter with three inputs [8–11]. The matrix topology is also presented as a unit, which control the power flow between the power generator and the electrical grid [12–16]. Multiphase generators have also been used in systems generating electricity such as offshore installations and wind farms [17,18]. Another application of the multiphase matrix converter in straight forward energy conversion is described in [19], where the 6 × 6 CMC and multi-winding transformer have been used to supply variable reactive power flow to the power system. A modulation approach based on the model of the 5 × 5 matrix converter with fictitious DC-link was shown in conference paper [20].

Multi-phase electric machines, including three-phase and five-phase variants, can be designed as a machine with open stator winding. Such a solution, especially in combination with a CMC, offers some important features. First, the possibility of direct power supply to both ends of the stator phase winding increases the maximum voltage amplitude within the linear range of the PWM modulator [21]. It should be noted here that the output voltage of the CMC cannot exceed the input voltages envelope. A quite frequency discussed problem in drives controlled by power converters, is the common voltage, which can be understood as a voltage measured between the ground potential and a virtually created star point connected with the stator terminals. The common-mode voltage in terminals of AC drives resulting in bearing currents harmful for the motor drive. The use of certain voltage modulation techniques in a matrix converter allows eliminating this problem [5,22–24]. As indicated in the brief introduction multi-phase drives with CMCs are rather niche applications. However, PWM algorithms are the subject of numerous studies, and almost all of the presented algorithms assume ideal sinusoidal input voltage and are designed for machines with the symmetric construction. The application of these methods without consideration of an input voltage asymmetry or the source harmonics in the calculation results in inaccurate load voltage generation. The approach to voltage synthesis proposed in the article takes this aspect into account and allows for the generation of the appropriate load voltage.

Due to a large number of input and output phases, the complexity of PWM algorithms based on the space-vector approach increases significantly. For a single matrix converter with three inputs and three outputs, the number of switch states is 33 (27). In the case of five input, five output converter, it gives 55 (3125) and analogically in drive with the open-end stator winding, the number of states is equal to 510. Therefore, the graphical presentation of voltage vectors corresponding to all switch states, at a given moment of time, becomes very unreadable, which makes it problematic to design and elaborate the dedicated PWM algorithms. The works [3,25] show that the synthesis of output voltages in multi-phase systems can be successfully simplified. These methods can be classified to the direct method of modulation. Compared to the transformation proposed by Clarke, the use of the Hilbert transform leads to the reduction of the number of required vectors. Therefore, for the CMC 5 × 5 the PWM algorithm can be developed using only 10 vectors. Apart from the modulation methods based on the space-vector approach, a group of methods of direct modulation can be indicated, such as the Venturini solution [1,26,27], while the general Venturini formulas for PWM duty cycles for several multi-phase converters, including square-type matrix converters are presented in [28]. The work in [25] proposes Wachspress formulas, which can be theoretically applied for any number of inputs. The use of either the Venturini solution or the Wachspress functions forces the commutation all switches of the given output cell (shown in the drawing later in the article). This can be explained by the fact that the switch modulating function is continuous, thus results in higher switching losses. All the PWM modulation methods discussed in the article are characterized by a lower number of switching cycles of at most 6 during the modulation period.

The paper is organized as follows. Definitions and principles of the proposed an output voltage synthesis using the DSM-CMC converter are presented in Section 2. This section also presents the method of generating quadrature signals using the Discrete Second-Order Generalized Integrator (DSOGI) structure. Then, the next three sections demonstrate variants of the proposed modulation. Abilities of the

input displacement angle control have been also discussed. Results are summarized and discussed in the conclusion section. Due to a huge number of switching elements, the realization of the experimental setup is very expensive. Therefore, the conclusions presented in the article are the result of circuit simulation in PSIM11 software and analytical research only. However, the proposed solution has been verified partially by an experiment and published in [3,25,29].

#### **2. The Principle of an Output Voltage Synthesis in DSM-CMC Converter**

The DSM-CMC converter consists of two square-type matrix converters, CMCP and CMCN, connected to load terminals as shown in Figure 1, where the simplified diagram of the circuit is depicted. If the number of load phases is equal to *n*, the total number of bidirectional power electronic switches is equal to 2*n*2. Both converter are connected with the *n*-phase AC voltage source *v*i1, *v*i2, ..., and *v*in. The voltage of the phase x of the load

$$
\upsilon\_{\rm ox}(t) = \upsilon\_{\rm Pr}(t) - \upsilon\_{\rm N\chi}(t) \tag{1}
$$

measured at the load terminals, are synthesized by these converters by using the switch group *h*11, *h*21, ..., *h*n1.

**Figure 1.** Simplified diagram of the square-type double conventional matrix converter.

As can be seen in Figure 2, switches on both sides of one phase of the load make the single commutation cell with two voltage multiplexers, *s*<sup>P</sup> and *s*N, respectively.

**Figure 2.** The single commutation cell for DSM-CMC 5 × 5.

### *2.1. Case of 5 Phases*

The number of multiplexer switches is equal to the number of input voltages, and in this case, takes 5. For a better understanding of the proposal, let the further consideration will be focused on 5 × 5 topology. According to the proposed concept of the voltage synthesis described in [3], all input voltages with pulsation *ω*<sup>i</sup> can be represented as a collection of five rotating vectors:

$$\mathbf{v}\_{\mathsf{I}} = \begin{bmatrix} \upsilon\_{\mathsf{I}1\mathsf{x}} & \upsilon\_{\mathsf{I}1\mathsf{y}} \\ & \upsilon\_{\mathsf{I}2\mathsf{x}} & \upsilon\_{\mathsf{I}2\mathsf{y}} \\ & \upsilon\_{\mathsf{I}3\mathsf{x}} & \upsilon\_{\mathsf{I}3\mathsf{y}} \\ & \upsilon\_{\mathsf{I}4\mathsf{x}} & \upsilon\_{\mathsf{I}4\mathsf{y}} \\ & \upsilon\_{\mathsf{I}5\mathsf{x}} & \upsilon\_{\mathsf{I}5\mathsf{y}} \end{bmatrix} \tag{2}$$

with the real

$$\begin{aligned} v\_{\text{l1x}} &= V\_{\text{l1}} \cdot \cos\left(\omega\_{\text{l}}t\right) \\ v\_{\text{l2x}} &= V\_{\text{l2}} \cdot \cos\left(\omega\_{\text{l}}t - 2\pi/5\right) \\ v\_{\text{l3x}} &= V\_{\text{l3}} \cdot \cos\left(\omega\_{\text{l}}t - 4\pi/5\right) \\ v\_{\text{l4x}} &= V\_{\text{l4}} \cdot \cos\left(\omega\_{\text{l}}t - 6\pi/5\right) \\ v\_{\text{l5x}} &= V\_{\text{l5}} \cdot \cos\left(\omega\_{\text{l}}t - 8\pi/5\right) \end{aligned} \tag{3}$$

and the imaginary parts of coordinates

$$\begin{aligned} v\_{\text{i1y}} &= V\_{\text{i1}} \cdot \sin\left(\omega\_{\text{i}} t\right) \\ v\_{\text{i2y}} &= V\_{\text{i2}} \cdot \sin\left(\omega\_{\text{i}} t - 2\pi/5\right) \\ v\_{\text{i3y}} &= V\_{\text{i3}} \cdot \sin\left(\omega\_{\text{i}} t - 4\pi/5\right) \\ v\_{\text{i4y}} &= V\_{\text{i4}} \cdot \sin\left(\omega\_{\text{i}} t - 6\pi/5\right) \\ v\_{\text{i5y}} &= V\_{\text{i5}} \cdot \sin\left(\omega\_{\text{i}} t - 8\pi/5\right) \end{aligned} \tag{4}$$

where *V*i1, ..., *V*i5 are the amplitudes of these voltages. Due to the analytic signal concept based on the Hilbert transform, for the pure sinusoidal input waveforms, the imaginary coordinates are just quadrature

components and an input voltage vectors collection can be presented as shown in Figure 3 as the symmetric system.

**Figure 3.** The collection of five the rotating input vectors.

These coordinates can be determined using the Hilbert filter or obtained through FFT/DFT based operation [30–32]. However, the Hilbert filter and algorithms based on DFT, although are quite accurate, are not the simple solution from code developing point of view. Moreover, error signals in the form of DC offsets, glitches, and momentary voltage sags may occur in measurements. Therefore, the input vector coordinates can be calculated in a different manner. A compromise solution, between accuracy and not complicated solution, maybe the use of the Double Second-Order Generalized Integrator with loop feedback extension functioned as Orthogonal Signal Generator (DSOGI-OSG), which in the OSG part prevents unexpected resonance and variables overflow. DSOGI-OSG structure in continuous time-domain is presented in Figure 4.

**Figure 4.** Double Second-Order Generalized Integrator with loop feedback extension functioned as Orthogonal Signal Generator (DSOGI-OSG) structure in continuous time-domain [33–35]: *V*i—the input sinusoidal signal, *V*ix—in-phase component of the input signal, *V*iy—the quadrature component of the input signal, *E*<sup>i</sup> the error signal, *k*—the gain block, *ω*i—reference pulsation of the input signal, and is an integrator block.

The transfer function takes the form of (5) for in-phase output and (6) for orthogonal output, while (7) represents the notch filter equation

$$\frac{V\_{\text{lx}}\left(s\right)}{V\_{\text{l}}\left(s\right)} = \frac{k \cdot \omega\_{\text{l}} \cdot s}{s^2 + k \cdot \omega\_{\text{l}} \cdot s + \omega\_{\text{l}}^2} \tag{5}$$

$$\frac{V\_{\rm ly}\left(s\right)}{V\_{\rm l}\left(s\right)} = \frac{k \cdot \omega\_{\rm l}^2}{s^2 + k \cdot \omega\_{\rm l} \cdot s + \omega\_{\rm l}^2} \tag{6}$$

$$\frac{E\_{\rm l}(s)}{V\_{\rm l}(s)} = \frac{s^2 + \omega\_{\rm l}^2}{s^2 + k \cdot \omega\_{\rm l} \cdot s + \omega\_{\rm l}^2} \tag{7}$$

where the parameter *k* is a value less than unity (*k* is taken the value of 1/ <sup>√</sup><sup>2</sup> here), *<sup>E</sup>*i(*s*) is the error signal, while *ω*<sup>i</sup> is an input voltage nominal pulsation. If processed signal frequency does not have an exact value, another extension of SOGI structure, called Frequency-Locked Loop (FLL), may be applied [36–38].

The load voltage *v*<sup>o</sup> produced by the single commutation cell, shown in Figure 2, can be analogous represented by two rotating vectors, *v*<sup>P</sup> and *v*N, as is depicted in Figure 5. Only the geometrical distance of real (indicated by subscript x) coordinates of these vectors produce the load voltage. While the imaginary coordinate (indicated by subscript y) can generate the reactive power flow at the converter input. In general, there exists some degree of freedom for selecting the instantaneous value of this component because it does not influence on the load currents. The article is focused on the cases, which locus of each output vector is straight a circle. This means that a rotating output voltage vector moves along a circular trajectory and this movement can be clockwise or counterclockwise. Four variants of the PWM modulation scheme are shown in Figure 5.

A vector arrangement in Figure 6a, for the given commutation cell, can be presented as the rotating polygon as illustrated in Figure 6b. The polygon surface is named here as the output voltage synthesis field. All the points, which represent output voltage vectors, have to be located inside the synthesis field. Such a geometric arrangement allows for direct application the Wachspress function for the PWM duty cycles calculation [25,28]. However, the number of switching within the modulation period should be minimal, and for this reason, Venturini and Wachpress solution is not suitable. Decreasing the number of switching can be realized by applying the Nearest Three Vectors (NTV) modulation technique, which relays on the selection of a proper triangle in the synthesis field. Figure 6c shows two selected triangles for the voltages generated by CMCP and CMCN converters. Note that both points, representing these voltages, are located in their triangular local synthesis fields. This is the required condition of output voltage synthesizability. The selection of the optimal triangle may consist in finding the appropriate vertex of the synthesis field, which clearly indicates the input vector closest to the output vector. In the case of using NTV technique, this solution is sufficient, because the other two required vectors are adjacent to the selected one. As can be seen, vector *v*<sup>P</sup> is closest to the vertex number 2, while vector *v*<sup>N</sup> is closest to vertex 4. All six required PWM duty cycles can be calculated using the smooth interpolation technique, which is, in the discussed case, nothing more than an appropriate triangle area relation for the NTV modulation [3]. An area of the triangle can be computed using the second-order matrix determinant. Thus, an application of that solution only needs coordinates of the triangle vertices. As mentioned earlier, these coordinates can be computed using the DSOGI-OSG block shown in Figure 4.

**Figure 5.** Four variants of output vectors rotation: (**a**) CCV-CCV, (**b**) CV-CV, (**c**) CCV-CV, and (**d**) CV-CCV.

**Figure 6.** The principle of operation: (**a**) vectors arrangement, (**b**) synthesis field, and (**c**) selected triangles.

#### *2.2. Case of 12 Phases*

In the case of more input voltages, for example, when the number of inputs is equal to 12, the choice of the optimal triangle is not so obvious. Now, let us consider the graphical vector arrangements for 12 × 12 topology expressed as regular polygon shown in Figure 7a.

**Figure 7.** Synthesis field of the 12 × 12 matrix topology (**a**), the input voltage vectors, and an example reference output voltage *v*o1 (**b**).

One of 12 presented input vectors is referred here as the base vector. It means that the distance—defined as *r*<sup>1</sup> ···*r*<sup>12</sup> and shown in Figure 7b—between this vector and the reference vector *v*o1 is the smallest. There are three triangles with a common upper vertex with coordinates {*v*i1x, *v*i1y}: Δ[2,1,12], Δ[3,1,11], and Δ[4,1,10]. A vector *v*i1 is the base vector in this case. The given triangle Δ[p,q,r] satisfies the modulation conditions when the sum

where

$$
\Sigma\_{\left[\mathbf{p},\mathbf{q},\mathbf{r}\right]} = d\_{\mathbf{p}} + d\_{\mathbf{q}} + d\_{\mathbf{r}} \tag{8}
$$

$$\begin{bmatrix} d\_{\rm p} \\ d\_{\rm q} \\ d\_{\rm r} \end{bmatrix} = \boldsymbol{\xi} \left[ \begin{bmatrix} \text{det}\begin{bmatrix} \boldsymbol{\upsilon}\_{\rm qx} - \boldsymbol{\upsilon}\_{\rm o1x} & \boldsymbol{\upsilon}\_{\rm qy} - \boldsymbol{\upsilon}\_{\rm o1y} \\ \boldsymbol{\upsilon}\_{\rm rx} - \boldsymbol{\upsilon}\_{\rm o1x} & \boldsymbol{\upsilon}\_{\rm ry} - \boldsymbol{\upsilon}\_{\rm o1y} \end{bmatrix} \\\\ \mathbf{det}\begin{bmatrix} \boldsymbol{\upsilon}\_{\rm px} - \boldsymbol{\upsilon}\_{\rm o1x} & \boldsymbol{\upsilon}\_{\rm py} - \boldsymbol{\upsilon}\_{\rm o1y} \\ \boldsymbol{\upsilon}\_{\rm rx} - \boldsymbol{\upsilon}\_{\rm o1x} & \boldsymbol{\upsilon}\_{\rm ry} - \boldsymbol{\upsilon}\_{\rm o1y} \\ \boldsymbol{\upsilon}\_{\rm qx} - \boldsymbol{\upsilon}\_{\rm o1x} & \boldsymbol{\upsilon}\_{\rm qy} - \boldsymbol{\upsilon}\_{\rm o1y} \\ \boldsymbol{\upsilon}\_{\rm px} - \boldsymbol{\upsilon}\_{\rm o1x} & \boldsymbol{\upsilon}\_{\rm py} - \boldsymbol{\upsilon}\_{\rm o1y} \end{bmatrix} \right] \tag{9}$$

and

$$\zeta = \left| \det \begin{bmatrix} \upsilon\_{\text{P}\text{x}} - \upsilon\_{\text{q}\text{x}} & \upsilon\_{\text{P}\text{y}} - \upsilon\_{\text{Q}\text{y}} \\ \upsilon\_{\text{rx}} - \upsilon\_{\text{q}\text{x}} & \upsilon\_{\text{ry}} - \upsilon\_{\text{q}\text{y}} \end{bmatrix} \right|^{-1} \tag{10}$$

of PWM duty cycles *d*p, *d*q, and *d*r takes the smallest value, ideally equal unity. When two or more triangles meet this condition, the triangle with the smallest area should be selected for further consideration. In practice, this operation can be performed by using optimized DSP functions like qsort (sorting in required order), vecmin (finding the minimum value within the set), or standard conditional operators.

When the value of transfer voltage ratio *q* = *V*o/*V*<sup>i</sup> of the 12 × 12 topology, e.g., for CMCP or CMCN, is in the range

$$\frac{\cos\left(\frac{\pi}{6}\right)}{\cos\left(\frac{\pi}{12}\right)} \le q \le \cos\left(\frac{\pi}{12}\right) \tag{11}$$

a large number of output phases allows generating the output voltage with lower THD, therefore the cost of passive elements can be decreasing. Corresponding simulation results are presented in the further part of the text. PWM duty cycles calculation for CMCP and CMCN are explained in two separate subsections. While the two concepts of gating signals generation have been presented in the third subsection.
