*3.3. Selection of LSC and CCk Values*

Firstly, the required peak current of the *L*SC should be determined. According to Figure 5e, the total charge *Q*ossT that must be provided by the *L*SC inductor during the dead time equals the sum of the *Q*oss(*U*s) determined for every transistor. The charge must be transferred during the dead time interval *t*DT, thus the required peak current of *L*SC is given as:

$$I\_{\rm LSCpk} = \frac{1}{t\_{\rm DT}} \sum\_{m=1}^{2n} Q\_{\rm loss(m)}(\ell L\_{\rm S}),\tag{14}$$

where *Q*oss(m)(*U*S)—charge determined based on Equation (6) for the *m*-th transistor for voltage *U*S. The required inductance *L*SC could be approximated as:

$$L\_{\rm SC} = \frac{\mathcal{U}\_{\rm S}}{8f\_{\rm s}I\_{\rm LSCpk}}.\tag{15}$$

The values of the *C*Ck capacitors should be large enough so that the voltage across does not change significantly in the dead time interval, when the *I*LSC flows through them, charging the *C*oss of the transistors. The values of the *C*Ck capacitors are given by:

$$\mathcal{C}\_{\rm CK} = \frac{1}{\Delta U\_{\rm CC}(k)} \sum\_{m=2k+1}^{2n} Q\_{\rm cos(m)}(\mathcal{U}\_{\rm S}) \,. \tag{16}$$

where Δ*UCC*(*k*)—change of voltage across *k*-th capacitor in the dead time interval.

The selection of the values of the capacitor according to Equation (16) is therefore dependent on the permitted change of the voltage across in the dead time interval Δ*U*CCk and *C*oss of the used transistors. Too high Δ*U*CCk values (too low capacitance of *C*Ck capacitors) cause inefficient charging and discharging of *C*oss of higher-level transistors and stimulation of resonance branches by voltage glitches during the dead time intervals. Too low Δ*U*CCk values (too high capacitances) are unfavorable not only in terms of size and cost but also due to the increased participation of these capacitors in energy transport between level voltages, which cause unwanted inrush currents. From the conducted experimental research, it follows that the values of Δ*U*CCk in the range of few volts (for SiC-based devices between 10 and 100 nF) bring suspected favorable effects. From Equation (16), it follows that the higher the index of the capacitor, the lower the capacitance demanded. To dampen very fast oscillation caused by hard switching of *C*Ck and parasitic inductances, resistors *R*Ck should be added in series with CCk. Typically, values in the range 0.1–1 Ω are optimal.

#### **4. Experimental Results**

#### *4.1. The laboraTory Setup and Operation of MRSCC*

The laboratory setup was designed for performing tests and measurements of a 2 kV four-level MRSCC converter in a comparative manner. To mitigate the problem of high-voltage measurements, the special laboratory setup was designed. Because the topology is bidirectional, twin converters can be connected back-to-back, creating a cascade with the common high-voltage link. The input and output voltage value of the cascade was 500 V, and this allowed for utilization of the low-voltage laboratory equipment.

Figure 7 presents the schematic of the experimental setup. Tables 1 and 2 contain the crucial parameters of the experimental system. Figure 8a presents the picture of the experimental system. The setup consists of two identical converters designed as a PCB module, which contains all the power and auxiliary components. Every voltage level was equipped with two channel gate driver ICs (UCC21520, Texas Instruments, Dallas, USA). The driver incorporates DT logic and a timer, thus only one control signal was sufficient for each voltage level. The fiber wires were used for signal delivery because of the great isolation that they provide. The controller was designed with an FPGA device and provided control for both converters, with eight control signals in total. The control algorithm included simple pattern generation in open loop mode. The resonant branches were designed to achieve a unified voltage ripple across all the resonant capacitors (about 100 Vpk-pk), and the same resonant frequency. The resonant branches were composed of the inductors based on ferrite gapped toroid- and FKP1 (WIMA, Mannheim, Germany)-type capacitors.

Figure 6 presents the waveforms of the resonant branch current and the output voltages of every single HB (which in fact are the voltages of the switches with an odd index). The waveforms in Figure 6a were obtained in MRSCC in the base configuration while the waveforms in Figure 6b were measured in the modified MRSCC.

**Figure 7.** Schematic of the MRSCC laboratory back-to-back setup with modification applied (*L*SC + *C*Ck*R*Ck).

**Figure 8.** (**a**) Picture of the MRSCC laboratory back-to-back setup (**b**) IR (Infrared) picture under full load (5 kW)—both SiC design.

#### *4.2. E*ffi*ciency Measurement Results and Discussion*

Figure 9 presents the experimental results related to the efficiency of the MRSCC converter. The measurements presented in Figure 9a,b are related to the single converter but those in Figure 9c are related to the whole cascade. The measurement was performed for different configurations of the converter. The power efficiency of the converter for the base configuration was relatively low (Figure 9c-curves no. 4). The influence of the high idle power losses was significant because a typical peak of the efficiency in the chart efficiency versus power was not observed. Despite this, the efficiency increased with the power load. In the first modification, the *C*Ck*R*Ck branches were added but with no inductor *L*SC (Figure 9c-curves no. 1). The power efficiency was even worse for the low load because the frequency (285 kHz) was higher due to the lack of oscillation breaks in DT intervals. Therefore, the *C*oss losses were proportionally higher in this case. However, the distortions in dead time intervals were eliminated, which improved of the voltage efficiency. After the application of the commutation supporting inductor *L*SC, outstanding results were obtained (Figure 9c-curves no. 2). Figure 9a,b presents the detailed results related to the improvement of the efficiency of the converter by a reduction of the *C*oss losses. As described in Section 3, it was achieved by the application of the supporting inductor (*L*SC) and operation at the appropriate peak current of *L*SC during commutations. Figure 9a presents the waveforms of the rising slope of the low side transistor in a half bridge for a different peak value of the *L*SC current, and Figure 9b presents the respective idle power measurements for the SiC-based design. The results were performed on the experimental setup with SiC switches operating with 285 kHz. The current of *L*SC should be low but sufficient to effectively perform the transition. A current of *L*SC that is too high causes hard switching and increases of the losses (Figure 9c). It is remarkable that the idle mode power losses were reduced from approximately 100W in the case when *I*LSCpk = 0A to nearly 3 W for *I*LSCpk = 6A.

**Figure 9.** Experimental results: (**a**) waveforms of voltage rising slope HB1. (**b**) idle power losses of the single MRSCC converter-SiC design 285 kHz, (**c**) Power and voltage efficiency characteristics vs. output power for different configurations of the cascaded setup. Yokogawa WT1800 Precision Power Analyzer.

For further references, the power and voltage efficiency curves are presented in Figure 9c-curves no. 3. The parameters of the Si design were insignificantly worse only when compared to outstanding SiC. Higher *R*DSon losses for Si MOSFETs (Table 1) limited the voltage efficiency and maximum load of the converter. The Si-based design was not able to operate with 285 kHz without the *L*SC supporting inductor due to huge commutation losses (in theory, 270 W per single converter based on Table 2 and simple calculation). This extreme case shows how effective the proposed modification is. In Table 2, the power consumed by a single non-loaded HB is listed (for different transistors, given frequency, and common DC link voltage). As can be noticed, the power losses are significant, especially for Si devices, even when the types with definitely higher *R*DSon are compared. The results of the case of the Si-based design *L*SC inductor and *f* <sup>s</sup> = 285 kHz are presented in Figure 9c-curve no. 3.

A thermography picture presented in Figure 8b shows that the heating of both the converters was nearly the same. It means that the efficiency of a single converter can be properly estimated on the basis of the efficiency results presented in Figure 9c taking into account half of the total losses in the system. Therefore, the peak efficiency of the SiC-based MRSCC with the *L*SC inductor was approximately equal to 98.5%.

#### **5. Conclusions**

In this paper, the research results under the operation of a modified SiC and Si-based MRSCC converters were presented. The MRSCC converter is a relatively novel topology and its improvement was proposed in this paper. The solution assumes the application of a commutation supporting inductor to reduce the switching losses associated with Coss in a converter made up of any number of levels.

The majority of research was performed in the 5 kW laboratory setup, which demonstrates the feasibility of boost and buck operation of the MRSCC. The conversion between the levels of 500 and 2 kV at a switching frequency 285 kHz, with the use of switches with VDS = 900 and VDS = 650 V, was demonstrated. Both the converters were tested simultaneously in the system with a common high voltage DC link. The input and output of the system remained on a low voltage level, which made it possible to perform high-precision efficiency measurements. Furthermore, it is a good example of a low-cost laboratory test setup for high voltage ratio converters.

The major goal of the research focused on a verification of the topology improvement in a four-level bi-directional MRSCC with a 0.5/2 kV voltage conversion ratio with the use of SiC and Si switches. It was accomplished with very promising results and the following conclusions:


The efficiency versus power characteristic showed an insignificant decline when the power increased, which is also beneficial. The voltage drop versus power was not significant in the demonstrated design cases of MRSCC. The best solution of 2.5% of the voltage decrease in the 5 kW range was observed. The results of the heat distribution in the converter showed that it can be regular. Overheating of particular cells was not observed.

**Author Contributions:** Conceptualization, A.K.; methodology, A.K.; software, A.K.; validation, A.K. and R.S.; formal analysis, A.K.; investigation, A.K.; resources, A.K. and R.S.; data curation, A.K.; writing—original draft preparation, A.K. and R.S.; writing—review and editing, A.K., and R.S.; visualization, A.K.; supervision, R.S.; project administration, A.K.; funding acquisition, A.K. and R.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by Polish National Science Center, grant number 2016/21/N/ST7/02355.

**Conflicts of Interest:** The authors declare no conflict of interest.
