*2.1. FPGA Hardware*

In the manuscript, we consider National Instruments PXIe-8135 controller as the primary development environment. The PXIe-8135 is an Intel Core i7 embedded controller with the design tool—LabVIEW. The development environment also includes the FPGA R-Series Multifunction RIO - PXI-7854R card (illustration in Figure 1) with VIRTEX-5 LX110 [11].

**Figure 1.** Field-Programmable Gate Array (FPGA) PXI-7854R illustration [11].

The PXI-7854R FPGA-based card has a few dozen Input/Output (I/O) resources, which include analog/digital converters (ADCs), digital/analog converters (DACs) and digital I/O lines. The design tool LabVIEW accesses the FPGA PXI-7854R device through the bus interfaces (PXI Triggers and PXI BUS). This connection makes possible timing, triggering, processing and custom I/O measurements, based on FPGA target programming, and most of it is available for demanded functions. Those required functions may use varied amounts of logic, besides using I/O resources. We assume that all control techniques require the same I/O resources, such as signals controlling transistors, or input faults. Therefore, the number of FPGA resources, used for logical and arithmetic operations, indicates the algorithmic complexity and it will be considered as one essential parameter to evaluate the control techniques implemented in FPGA.

#### *2.2. PWM Modulator Algorithm*

To control the converter switches the PWM modulator is used. Figure 2 shows the main flowchart of the PWM modulator. For better visualization, we divide all operations into three (III) parts. In part I, the user may set the main control parameters: the average switching frequency *fsw* and duty cycle of the PWM signal *D*. Then, the program calculates the required number of clock ticks for the period (*N*) and the duration of high state (*Nd*) according to the Equations (1) and (2).

$$N = f\_{\text{FPGA}} / (f\_{\text{sw}} \cdot \text{SC}\_{TL}) \tag{1}$$

$$N\_d = D \cdot N \tag{2}$$

where:

*fFPGA*—onboard available clock frequency, *fsw*—switching frequency and *SCTL*—single cycle timed loop (in clock ticks).

**Figure 2.** The main flowchart of the PWM modulator, providing parameters (I), counter ramp (II), and generation of output signal (III).

The index *m* (in Figure 2) means that the *Ndm* and *Nm* value is taken and recalculated for the m'th PWM period. The presented modulator can, therefore, cooperate with an external voltage controller and dynamically change the factor D. The duration of the period, represented by *Nm*, may be constant for deterministic modulation (DetM) or may be changed randomly for RanM case. Part II illustrated the carrier function counter ramp represented by the variable *i*. Parameters *N* and *Nd* are compared with the variable *i* to determine the value of output signal Y and control the loop I execution. Part III presents the generation of control (output) signal and the interaction with a *CS* function. In the presence of hardware signals of fault (*F*) or the stop button (*S*), the function *CS* returns 1, and the PWM operation is interrupted. The fault signal is typically generated by converter hardware in any emergency, while the stop signal is from the user. Figure 3 shows the operation of the modulator.

**Figure 3.** The principle of the PWM operation.

### *2.3. Random Number Generator*

The main advantage of RanM instead DetM is highlighted in the literature [8,10,12–15] as the EMI noise reduction related to the *fsw* and its harmonics. The random number generator is crucial to the operation of RanM control algorithms. Since we consider FPGA features connected with the fixed-point operation, we propose to generate the random stream by a linear congruential generator (LCG). The LCG is a modular arithmetic algorithm, which provides a stream of pseudo-randomized numbers calculated with a Equation (3).

$$RN\_m = (\mathfrak{a} \cdot RN\_{m-1} + \mathfrak{c}) \bmod n \tag{3}$$

where:

*RNm*—the m'th random number provided by LCG, *α*, *c*, *n*—LCG coefficients.

The values of coefficients configured for the FPGA implementation were *α* = 17 and *RN*<sup>0</sup> = 17, *c* = 0 and *n* = 232. The modulo operation is made automatically due to the use of long integer variables with 32 bits of storage. For RanM, the generation of a random stream is done in a loop to get a new pseudo-random number for each PWM signal period. The presented LCG generates pseudo-random numbers with a period of 2<sup>31</sup> and a normal distribution. To show the property of a random stream, Figure 4 shows the 10,000 numbers *RNm* generated by LCG and their histogram/distribution.

**Figure 4.** *RNm* distribution (**a**), and histogram (**b**).

#### *2.4. FPGA Implementation*

This section presents the practical implementation of DetM and RandM in FPGA systems utilizing LabVIEW software. Additionaly, for RanM probability density function PDF analysis in MATLAB software will be shown.

Traditionally, during LabVIEW programming, we use modules with palettes of structures and functions. The number of such functions in LabVIEW FPGA Module is much smaller than for typical control devices with a microprocessor. Further, available functions can only operate on integer variables. Despite these drawbacks, the LabVIEW program Implementation in FPGA systems allows full control of program execution and high speed calculation. For instance, the LabVIEW FPGA Module has access to Single-Cycle Timed Loops (SCTL). The SCTL is a unique loop structure that executes all functions inside within one fixed time period (*SCTL*) [11]. The *SCTL* may be defined by the user as a time period or in ticks of the FPGA clock. In the control board used, the maximum clock frequency is 40 MHz.

To realize the algorithm from Figure 2 in LabVIEW for FPGA, the While Loop structure with a sub-system For Loop was chosen. The For Loop corresponds to the loop II in Figure 2 and is executed N times. The While Loop corresponds to the loop I in Figure 2. The While Loop is performed until the *CS* function is activated. For DetM we consider the *SCTL* = 1 tick, and the number *N* = *Nm* is constant.

#### 2.4.1. Single Randomization

For RandM the number *Nm* is randomly changed for each PWM period using a random stream from the LCG (described in previous section). However, due to the use of fixed-point operations in FPGA, the resulting random number must be scaled (reduction of bit precision) to make it suitable for *Nm* calculation. Figure 5 illustrates in the part I how to scale the *RNm* using the Reshaped Array Function (*RAF*) which is available in the LabVIEW environment.

**Figure 5.** The scheme of the *RNm* scaling process, led to lower bit precision (**I**), and for calculating the random stream of *Nm* (**II**) and *Ndm* (**III**).

Figure 5 shows in part I the parameter *bi*, which is responsible for providing the length of the output array and must be numeric. Before resizing, the number *RNm* is converted to a Boolean Array by the *N*2*BA* function. After resizing, the Boolean Array is converted to a number again by the *BA*2*N* function. As a result, a random number, *<sup>β</sup>m*, from 0 to 2*bi* − 1 is obtained. The next task is to calculate *Nm* and *Ndm* (from Figure 2), to change randomly according to the random *β<sup>m</sup>* number for each PWM period. The changes of the *Nm* and *Ndm* should also take place within the assumed range from the *N* maximum and minimum values. These operations should be performed with the appropriate precision in fixed-point arithmetic. However, LabVIEW software for FPGA does not allow direct actions of the mathematical division. The solution to the stated problem for *Nm* calculation is shown in part II of the Figure 5. The *δN* describes the maximum assumed changes in the PWM period and may be calculated as:

$$
\delta N = N\_{\text{max}} - N\_{\text{min}} + 1. \tag{4}
$$

The *δN* can be also represented relative to the average value of *N*, e.g., *δN* = 50% · *NAV* + 1. Thus, for the first interaction illustrated in Figure 5, part II, consider the multiplication of the *β<sup>m</sup>* by *δN*. Since a divide operation is not available, the Delete from Array Function (*DAF*) is applied to provide *δNR*, a random stream that corresponds to the range between the 0 and the value of *δN* − 1. In this step, the *Nm* value is calculated using Equation (5). The final formula for calculating *Nm* according to the concept from Figure 5, part II, is presented in Equation (6).

$$
\delta N\_R = \left( \left( \left( RN\_m \gg \left( 32 - b\_i \right) \right) \cdot \delta N \right) \gg b\_i \right) \tag{5}
$$

$$N\_m = \delta N\_R + N\_{\rm min} \tag{6}$$

Although Equation (6) accurately describes random changes in the *N* value (which corresponds to the PWM period—*TPWM*), it does not provide information on the average value. Therefore, later in the article, discussing RanM properties, we will give the average value of *N* − *NAV*, and *δN*, so the variation range of *N* is equal to *NAV* ± *δN*/2. Choosing the right *δN* is not apparent and should be the subject of a broader analysis. Despite, this topic will not be fully discussed in this article. However, we will show the basic challenges that face when choosing parameters for RanM.

We can take *δN* value based on expected frequency randomization. For instance, if we assume that *fsw* = 80 kHz and this frequency may change ±50%, we will obtain *max*(*fsw*) = 80 kHz + 50% = 120 kHz, *min*(*fsw*) = 80 kHz − 50% = 40 kHz. The *Nmin* value will be related to 120 kHz and *Nmax* to 40 kHz (based on Equation (1)), so *δN* = 1000 − 333 + 1=668. However, the value of *NAV* = 667 which does not correspond to a frequency of 80 kHz. Figure 6 shows the histogram of randomized *Nm* values and the histogram of randomized frequencies *fsw* related to *Nm*, for *NAV* = 667 with *δN* = 668. Figure 6b shows that switching frequency *fsw* varies within the assumed range from 40 to 120 kHz. Despite this, the frequency distribution is not uniform and the average frequency is not equal to 80 kHz. Adopting the *δN* in such a way is therefore not particularly useful. Another possible approach to selecting *δN* value may be made based on a relative change in time. Figure 7 shows the histogram of *Nm* values and histogram of *fsw*, for *NAV* = 500 (value related to *fsw* = 80 kHz) with *δN* = 334 so *N* ∈< *NAV* ± 30% >. In such a case, the average value of the frequency is closer to that intended, but the frequency distribution is still strongly non-linear.

**Figure 6.** Histogram of *Nm* ticks distribution (**a**), and histogram of frequency distribution (**b**), for *NAV* = 667 and *δN* = 668.

**Figure 7.** Histogram of *Nm* ticks distribution (**a**) and histogram of frequency distribution (**b**), for *NAV* = 500 and *δN* = 333.

Figure 5 shows in part III the *DAF* function with consideration of the set up of length and index of array, to provide calculation of *Ndm*. We assumed that the coefficient *d*, represented as an 8 bit integer will be proportional to duty cycle factor D. The FPGA implementation considers the index value (*wi*) equal to 8, and the *bi* equal to 23. Thus, the final value of *Ndm* is configurable, maintaining the proportionality with *Nm*, within a range defined by *d*, as follows in Equation (7).

$$N\_{dm} = D \cdot N\_m = \left( (d \cdot N\_m) > > w\_i \right) = \frac{d \cdot N\_m}{2^{w\_i}} \tag{7}$$

To calculate the period of PWM signal and its Duty cycle for RanM we use Equations (6) and (7), respectively. These equations are computed in the fixed time of a one loop execution—*SCTL*. We may consider the situation, in which the time *SCTL* is also changed randomly (*RSCTL*).

### 2.4.2. RanM with *RSCTL*—Additional Randomization

When we randomly change both the number of periods of the For Loop (*Nm*) and the duration of this loop, we can talk about an additional randomization (RanM with *RSCTL*). Basically, for *RSCTL* generation, we assume the same principle, as illustrated in Figure 5, part I and part II, however instead of *SCTL* = 1 tick we generate random value from 7 to 13. The m'th PWM period *TPWMm* is equal to (*Nm* · *SCTLm*)/ *fFPGA*. Figure 8 shows the histogram of the *TPWMm* and histogram of related *fsw*, for *N* = 50, *δN* = 34 and *RSCTL* ∈< 7 : 13 >. Figure 8 shows that when we consider *Nm* and *RSCTL*, the density distribution in both cases, (a) and (b), is changed. This approach of *Nm* and *RSCTL* randomization gives us the possibility of shaping the density distribution. The frequency distribution is closer to the Gaussian distribution, which should be more favourable in terms of the average frequency and converter losses.

**Figure 8.** Histogram of *TPWMm* distribution (**a**) and histogram of related *fsw* distribution (**b**), for *NAV* = 50 with *δN* = 34, and *RSCTL* ∈< 7 : 13 >.

#### 2.4.3. RanM2—Split Distribution of Variable

The other method to shape the *TPWMm* and *fsw* distributions is to split the *Nm* distribution to a few sub-ranges in the entire *Nm* range. For the presented FPGA implementation, we propose to use two predefined random sequence ranges. Then we consider the use of one random bit, digital 1 and 0 levels to choose the range of *Nm*. The FPGA implementation is executed with a particular function (*SF*), which is available in the LabVIEW environment. The parameter *S* determines whether the *SF* returns the value wired to T or F. Thus, for each parameter, F or T, we assign one of the two predefined random sequence ranges, both provided by *Nm*. Figure 9 illustrating the proposed FPGA implementation. We will denote random modulation with such a distribution as RanM2.

**Figure 9.** Illustration of *Nm* generation in proposed RanM2.

Figure 10 shows the histograms of *Nm* values and their corresponding *fsw* values, for *NAV*<sup>1</sup> = 750 with *δN*<sup>1</sup> = 500 and *NAV*<sup>2</sup> = 416 with *δN*<sup>2</sup> = 167.

**Figure 10.** Histogram of *Nm* ticks distribution (**a**) and histogram of frequency distribution (**b**), for RanM2 with parameters: *NAV*<sup>1</sup> = 750 with *δN*<sup>1</sup> = 500 and *NAV*<sup>2</sup> = 416 with *δN*<sup>2</sup> = 167.

As one can see, the use of two probability distributions for a PWM period (which is proportional to *Nm*) produces a more equal alignment of the frequency distribution. Therefore, in such a manner there is a possibility to create, with obvious limitations, the distribution of frequency.

### 2.4.4. RanM2 with *RSCTL*

The presented concept of two distributions of *Nm* (RanM2) may be linked with the concept of additional randomization *RSCTL*. Figure 11 considers such a case with *RSCTL* ∈< 7 : 13 > and for *NAV*<sup>1</sup> = 75 with *δN*<sup>1</sup> = 50 and *NAV*<sup>2</sup> = 42 with *δN*<sup>2</sup> = 17. The obtained histograms are more smooth than histograms in Figure 10, which can be an advantage. However, the use of *RSCTL* increases the frequency spread.

**Figure 11.** Histogram of *Nm* ticks distribution (**a**) and frequency distribution (**b**), for RanM2 with *RSCTL* with parameters: *RSCTL* ∈< 7 : 13 >, *NAV*<sup>1</sup> = 75, *δN*<sup>1</sup> = 50, *NAV*<sup>2</sup> = 42 and *δN*<sup>2</sup> = 17.

Figure 12 shows the LabVIEW general program implemented in FPGA. In Figure 12, the parts corresponding to (I) and (II) refer to the basic modulator configuration (Figure 2). Therefore, it is applicable to both DetM and RanM. Part (III) presents the random number generator with a number scaling block, corresponding to part I of (Figure 5) and is used only for RanM, for both approaches of randomization discussed in Section 2.4 Parts (IV) and (V) correspond to part II and part III of (Figure 5), respectively. Since the FPGA needs to execute predefined random sequence ranges (the concept of additional randomization), the *DAF* function proportionally increases.

**Figure 12.** LabVIEW general program implemented in FPGA, for loop (counter ramp) and output signal generation (I), conditions for stopping the program II), random number generator (III), *Nm* and *SCTL* calculation (IV), and *Ndm* calculation (V).
