*5.6. Controller Hardware*

For implementing the proposed control strategy a DSP-based MASTER controller board and ten ARM processor-based SLAVE controller boards have been designed as shown in Figure 18 with the features of advanced functionalities and fast execution time. As shown in the Figure 18a, the MASTER controller board consists of a digital signal processor (ADSP-21363) control card, including a FPGA (FPGA-CYCLONE II EP2C8F256) and additional ARM Cortex-M4 32b processor (STM32F407IGT6) control card. The ADSP-21363 floating-point signal processor (3 Mb SRAM, 333 MHz, 2GFLOPS) implements the traction motor torque and excitation control, and the traction line current and voltage control, while the STM32F407IGT6 processor (MCU + FPU, 210DMIPS, 1MB Flash/192 + 4KB RAM, USB OTG HS/FS, Ethernet) realizes human-machine interfacing (HMI) and the communication with other STM32F407IGT6 ARM Cortex-M4 32b processors of nine power electronic cells.

**Figure 18.** MASTER controller board consisting of main ADSP-21363 based control card and the auxiliary STM32F407IGT6 Arm Cortex based control card (**a**); one of nine STM32F407IGT6 Arm Cortex based SLAVE controller boards controlling nine 4QC-DAB-DC/AC power electronic cells (**b**).

The DSP-based MASTER controller board receives the measurements from 4QC-DAB-DC/AC power electronic cells and implements the traction motor control and traction line voltage and current control algorithms. The FPGA receives the input DC voltage and three-phase output voltage commands from the DSP and implements the PWM algorithm and outputs nine command signals to ARM-based SLAVE controller boards, shown in Figure 18b, via optical fibers. The individual ARM-based SLAVE controller boards receive a command from the MASTER controller board and implement PWM times and outputs gate signals to the transistors. Ten SLAVE controller boards output gate signals to 72 SiC MOSFET dual power modules. To ensure complete isolation between the input stage and the output stage of the DC PETT, one SLAVE controller controls the SiC MOSFET H-bridges of the input sides of the two 4QC-DAB-DC/AC power electronic cells, while the other SLAVE controller controls the transistor bridges of the output sides of these two 4QC-DAB-DC/AC power electronic cells. Both SLAVE controllers communicate with each other using fiber optics.

The MASTER controller board and all SLAVE controller boards contain signal conditioning circuits designed to receive individual voltage and current sensors signals and send them to the DSP or ARM processors respectively. The isolated communication interfaces are realized by a serial Controller Area Network (CAN) interface port.

The overall MASTER control commands of the DSP can be received in two modes: from the driver's console in the train driver's cab (train running mode) and from the operator's PC through the DSP CAN port (service mode). The execution period of one cycle of the control scheme in the main DSP is 150 μs, while the FPGA on the MASTER control card works with a three times shorter execution period of the PWM algorithm. Individual FPGAs on SLAVE controller boards operate with the execution period equal to 33.33 μs. The accuracy of the PWM time counting on the SLAVE controller board results from the used 150 MHz clock.

The control relay outputs on the main-board shown in Figure 18a are used to control the train's individual switching devices, such as the circuit breaker circuit or the contactor circuits in the on-board high-voltage switchgear.
