*2.4. PWM Duty Cycles Calculation for CMCN and Topology 5* × *5*

Referred to the triangle Δ[3,4,5] in Figure 6, the reference output voltage *v*<sup>N</sup> is synthesized by 3 switches: *h*31, *h*41, and *h*51. The corresponded duty cycles can be calculate using the following formulas,

$$d\_{\rm 3N} = \zeta\_{\rm N} \cdot \left| \det \begin{bmatrix} \upsilon\_{\rm 4x} - \upsilon\_{\rm Nx} & \upsilon\_{\rm 4y} - \upsilon\_{\rm Ny} \\ \upsilon\_{\rm 5y} - \upsilon\_{\rm Nx} & \upsilon\_{\rm 5y} - \upsilon\_{\rm Ny} \end{bmatrix} \right| = \frac{\Delta\_{\rm [4, N, 5]}}{\Delta\_{\rm [3, 4, 5]}} \tag{17}$$

$$d\_{\mathsf{iN}} = \zeta\_{\mathsf{N}} \cdot \left| \det \begin{bmatrix} \upsilon\_{\mathsf{i}\mathsf{F}\mathsf{x}} - \upsilon\_{\mathsf{N}\mathsf{x}} & \upsilon\_{\mathsf{i}\mathsf{F}\mathsf{y}} - \upsilon\_{\mathsf{N}\mathsf{y}} \\ \upsilon\_{\mathsf{i}\mathsf{N}} - \upsilon\_{\mathsf{N}\mathsf{x}} & \upsilon\_{\mathsf{i}\mathsf{N}} - \upsilon\_{\mathsf{N}\mathsf{y}} \end{bmatrix} \right| = \frac{\Delta\_{\mathsf{[5,N,3]}}}{\Delta\_{\mathsf{[3,4,5]}}} \tag{18}$$

$$d\_{\rm SN} = 1 - d\_{\rm 3N} - d\_{\rm 4N} = \frac{\Delta\_{[3, \rm N, 4]}}{\Delta\_{[3, 4, \rm 5]}} \tag{19}$$

where

$$\mathbf{x}\_{\rm N}^{\rm x} = \left| \det \begin{bmatrix} \upsilon\_{\rm l4\chi} - \upsilon\_{\rm l3\chi} & \upsilon\_{\rm l4\chi} - \upsilon\_{\rm l3\chi} \\ \upsilon\_{\rm l5\chi} - \upsilon\_{\rm l3\chi} & \upsilon\_{\rm l5\chi} - \upsilon\_{\rm l3\chi} \end{bmatrix} \right|^{-1} \tag{20}$$

is the scaling factor, which is equal to the triangle Δ[3,4,5] surface. The average value of the CMCN output voltage can be expressed by the following formula

$$
\overline{\boldsymbol{\upsilon}}\_{\text{N}} = d\_{\text{3N}} \cdot \boldsymbol{\upsilon}\_{\text{l}3} + d\_{\text{4N}} \cdot \boldsymbol{\upsilon}\_{\text{l}4} + d\_{\text{5N}} \cdot \boldsymbol{\upsilon}\_{\text{l}5} \tag{21}
$$

### *2.5. The Concept of Gating Signals Generation*

The gate signals can be controlled according to different strategies. Apap et al. [39] compared and presented several PWM signal gating methods. Among them, the cyclic Venturini and Min-Mid-Max (MMM) schemes of modulation are proposed. Two approaches have been applied to the gates signal generation: basic and mentioned MMM scheme.

In the case of the basic solution, the sequences of the switch states always depend on the selected triangle in which the synthesis of the output voltage is realized. Therefore, these sequences can be placed in a lookup table. An overview of the basic sequences is shown in Figure 8, where the value of *ϕ* 1.618, which is so-called the golden ratio exists in the pentagon.

(**a**) sequences type I for *<sup>q</sup>* ∈ 1/(<sup>1</sup> + *<sup>ϕ</sup>*), cos(*π*/5) 

(**b**) sequences type II for *<sup>q</sup>* ∈ (0, 1/(<sup>1</sup> + *<sup>ϕ</sup>*))

**Figure 8.** The switch state sequences in the basic solution of the gating signals for both converter cells *CMCP* and *CMCN*.

The MMM method is used to improve the quality of the voltage generated by the converter in terms of THD. The switch states sequences for the CMCP and CMCN converters are characterized in Figure 9. Note that these sequences correspond to the case illustrated in Figure 6b.


(**a**) for CMCP converter

(**b**) for CMCN converter

**Figure 9.** The MMM type of sequences of the gating signals for both converter cells *CMC*<sup>P</sup> and *CMC*<sup>N</sup> for the case depicted in Figure 6c.

#### **3. The PWM Variant 1—An Output Voltage Synthesis with Zero Value of the Common-Mode Voltage**

The common-mode voltage, defined as

$$v\_{\rm cm}(t) = \left(v\_{01}(t) + v\_{02}(t) + v\_{03}(t) + v\_{04}(t) + v\_{05}(t)\right)/5,\tag{22}$$

can lead to the degradation of rolling bearings in electric machines powered by PWM inverters. As indicated in the introduction an open-end windings stator fed by the double matrix converter allows for the PWM modulation without the common-mode voltage generation. The proposed approach to the load voltage synthesis with conjunction with the basic solution of the gating signals control (shown in Figure 8) give the same desired result. Elimination of the common-mode voltage can be performed by all four PWM modulation schemes: CV-CV, CCV-CCV, CV-CCV, and CCV-CV. The use of the first two cases allows obtaining an input displacement angle, which is dependent on the load parameters like in the Venturini methods [1,26].

The referenced *k*-output voltage vectors of the CCV-CCV modulation scheme can be expressed by following equations.

$$
\upsilon\_{\rm Pxk} = q \cdot \cos(\omega\_o \cdot t - ((k-1) \cdot 2\pi/5))\tag{23}
$$

$$
\omega\_{\rm Pyk} = -\eta \cdot \sin(\omega\_0 \cdot t - ((k-1) \cdot 2\pi/5))\tag{24}
$$

$$
\omega\_{\rm Nuk} = -q \cdot \cos(\omega\_o \cdot t - ((k-1) \cdot 2\pi/5))\tag{25}
$$

$$
\sigma\_{\text{Nyk}} = q \cdot \sin(\omega\_0 \cdot t - ((k-1) \cdot 2\pi/5))\tag{26}
$$

Above equation are proposed for the first commutation cell. Equations for the rest of the rotating vectors pairs can be represented by analogous elaboration. The referenced output voltages in CV-CV scheme can be represented by following equations.

$$
\omega\_{\rm Pxk} = q \cdot \cos(\omega\_0 \cdot t - ((k-1) \cdot 2\pi/5))\tag{27}
$$

$$v\_{\rm Pyk} = q \cdot \sin(\omega\_0 \cdot t - ((k-1) \cdot 2\pi/5))\tag{28}$$

$$
\omega\_{\rm Nuk} = -q \cdot \cos(\omega\_o \cdot t - ((k-1) \cdot 2\pi/5))\tag{29}
$$

$$
\upsilon\_{\rm Nyk} = -q \cdot \sin(\omega\_0 \cdot t - ((k-1) \cdot 2\pi/5))\tag{30}
$$

The possibility to change the rotation of the given output vector by changing the sign of the imaginary component allows realizing the PWM modulation, in which the resultant imaginary component of the *v*oy takes the zero value. If vectors *v*<sup>P</sup> and *v*<sup>N</sup> rotate in opposite directions, as is typical for last two presented schemes of modulation CV-CCV and CCV-CV, the passive input current component is not generated. Simulation results of the PWM variant 1 for DSM-CMC 5 × 5 and four modulation schemes are shown in Figure 10. Simulation parameters are listed in Table A1, which can be found in an appendix.

**Figure 10.** Simulation of the PWM variant 1 for DSM-CMC 5 × 5 and four modulation schemes—RL load case.

Analogous simulation tests have been realized for the proposed converter connected to a 12-phase symmetrical power supply. Figure 11 shows the load voltage generated by DSM-CMC 12 × 12 for an output frequency equal to 10 Hz, while results obtained for 300 Hz are presented in Figure 12.

Simulation parameters for this case are available in Table A2 in Appendix A. The selection of different sets of simulation parameters did not subserve a specific purpose. The simulation tests were carried out with the use of two independent simulation files. However, in the case of the DSM-CMC 12 × 12 simulation, a small calculation step was chosen due to the high modulation frequency. It was set to 100 kHz to get a good PWM resolution at 300 Hz of the fundamental frequency.

**Figure 11.** The load voltage *v*<sup>o</sup> for DSM-CMC 12 × 12 converter for the three selected modulation schemes: *f*<sup>o</sup> = 10 Hz, *q* = 2 × 0.95.

**Figure 12.** The load voltage *v*<sup>o</sup> for DSM-CMC 12 × 12 converter for the three selected modulation schemes: *f*<sup>o</sup> = 300 Hz, *q* = 2 × 0.95.

Properties of this type of matrix converter, compared with counterpart 5 × 5, remains the same. In particular, the common-mode voltage is also eliminated by using the basic type of switches state sequences. The voltages shown in these figures are characterized by a low THD, which is about 12%. Comparing to the 5 × 5 topology, the resulted voltage gain for DSM-CMC is higher and takes optimally the value of 1.93.

#### **4. The PWM Variant 2—An Output Voltage Synthesis with Less Harmonic Distortion**

The basic solution of the switch states sequence has been applied in the PWM modulation with eliminating the common-mode voltage. If a lower THD of the load voltage waveform is desired, a more advanced gating signal generation mechanism can be proposed, such as MMM scheme shown in Figure 9. With regard to variant 1, this is the only change. However, the MMM method is more complicated because the input voltage vector collection should be arranged in a specific order {*min* − *mid* − *max* − *mid* − *min*} within the selected triangular synthesis field. Simulation results are presented in Figure 13. A lower THD of the load voltage *v*<sup>o</sup> is obtained but the common-mode voltage *v*cm is also generated, as marked in the presented drawings.

**Figure 13.** Simulation of the PWM variant 2 for DSM-CMC 5 × 5 and four modulation schemes: *f*<sup>o</sup> = 250 Hz, *q* = 2 × 0.8.

#### **5. The PWM Variant 3—An Output Voltage Synthesis with Maximum Voltage Transfer Ratio and Minimum Number of Switching**

A synthesis field for multi-phase and symmetrical AC voltage sources can be represented by a regular polygon as shown in Figures 6b and 7a. A radius of a circle inscribed of this polygon limits an output voltage amplitude in the linear range of modulation. The maximum voltage transfer ratio for CMCN

and CMCP, related to the input voltage amplitude and number of inputs equal to *n*, can be expressed as follows,

$$q\_{P\max} = q\_{\text{N\,max}} = \cos(\pi/n) \tag{31}$$

Therefore, the maximum load voltage for DSM-CMC 5 × 5 in *p*.*u*. is equal to

$$v\_{\text{o max}} = 2 \cdot \cos(\pi/5) = 1.618 \tag{32}$$

The value (32) can be increased by modifying the position of the *v*<sup>P</sup> and *v*<sup>N</sup> vectors. In contrast to the methods described in the previous sections, trajectories of these vectors are not a circle. The locus of each vector is not changing smoothly and contains discontinuities. This type of modulation belongs to the discontinuous group of PWM modulations. Both reference vectors *v*<sup>P</sup> and *v*<sup>N</sup> take exactly five positions, in which they lie on one of five input vectors. An algorithm flowchart for DSM-CMC 5 × 5 is presented in Figure 14.

**Figure 14.** An algorithm flowchart of the variant 3 PWM modulation: (**a**) Step 1: generation of synthesis field and reference voltage vectors *v*<sup>P</sup> and *v*N. (**b**) Step 2: calculation of the set of distances between the N point and vertices of the synthesis field. (**c**) Step 3: calculation of the set of distances between the P point and vertices of the synthesis field. (**d**) Step 4: shortest distance selection, setting the origin vertex, and the vector's offset {*v*sx, *v*sy} calculation. (**e**) Step 5: the reference vector *v*<sup>o</sup> shift resulting in the new coordinates of *P* and *N* points. (**f**) Step 6: calculation of four areas of the triangle and PWM duty cycles.

The output voltage synthesis field is generated using the DSOGI blocks at the first step of the proposed algorithm. The reference output voltage vectors coordinates, {*v*Nx, *v*Ny} and {*v*Px, *v*Py}, are also calculated

at this step. The vectors can rotate clockwise (CV-CV scheme) or counterclockwise (CCV-CCV scheme), as shown in Figure 15.

**Figure 15.** An example rotation of the reference output vector.

Based on the analysis of the vector arrangement in Figure 15, it can be written that the maximum length of the voltage vector, in a linear range of modulation, is equal to the following expression.

$$v\_{\text{o max} \,(\text{variant3})} = 1 + \cos(\pi/5) = 1.809 \tag{33}$$

However, a vector of this length has to be accordingly shifted inside the synthesis field as shown in Figure 14d,e. Therefore, new coordinates of the reference output vector for the given commutation cell can be calculated as follows.

$$
\upsilon\_{\rm O\\$} = \upsilon\_{\rm OX} + \upsilon\_{\rm Si} \tag{34}
$$

$$
\boldsymbol{\upsilon}\_{\rm{oxy}} = \boldsymbol{\upsilon}\_{\rm{oy}} + \boldsymbol{\upsilon}\_{\rm{sy}} \tag{35}
$$

Distances between N-point and all the synthesis field vertices are calculated in Step 2. The same procedure is applied for the point P in Step 3. Next, the shortest calculated distance in a N-collection {*r*N1,*r*N2,*r*N3,*r*N4,*r*N5} is compared with the shortest calculated distance in a P-collection {*r*P1,*r*P2,*r*P3,*r*P4,*r*P5}. Finally, the less value is selected, which correctly indicates the optimal vertex of the synthesis field. The shift coordinates are calculated in Step 4. As can be seen in Figure 14d, vertex number 4 has been chosen. Thus, the PWM duty cycles, for the case illustrated in Figure 14f can be calculated using the following formulas.

$$d\_{\rm 1Ps} = \Delta\_{[2, \rm Ps, 4]} / \Delta\_{[1, 2, 4]} \tag{36}$$

$$d\_{2\text{Ps}} = \Delta\_{[4,\text{Ps},1]} / \Delta\_{[1,2,4]} \tag{37}$$

$$d\_{4Ps} = \Delta\_{[1, \text{Ps}, 2]} / \Delta\_{[1, 2, 4]} \tag{38}$$

and

$$d\_{4\text{N}\sharp} \equiv 1\tag{39}$$

Formula (39) refers to the case where the end of the *v*<sup>N</sup> vector coincides with the *v*i4 vector. It means the permanent connection of the input voltage *v*i4 with one side of the load phase during the PWM

modulation period. Figure 15 shows a case, which in the one side of the load is permanently connected to an input voltage *v*i1 during PWM modulation. Sequences of the switch states shown in Figure 16 correspond to the case, which in the *s*<sup>N</sup> switch is connected permanently to the input phase 4. The zero load voltage is generated by using the same switch in both CMCP and CMCN matrix converters. Simulation results for maximal voltage transfer ratio (33) are shown in Figure 17. The common-mode voltage *v*cm is eliminated. An application of the CV-CV and CCV-CCV scheme of modulation resulting in the non-zero input displacement angle.

**Figure 16.** Sequences of the switch states in one commutation cell for the case presented in Figure 14.

**Figure 17.** Simulation of the PWM variant 3 for DSM-CMC 5 × 5 and two modulation schemes: *f*<sup>o</sup> = 250 Hz, *q* = 1.8.

Having half the number of switching operations during the PWM modulation period is an advantage of variant 3. In order to obtain the unity power factor at the system input, the sequence types have to be toggled continuously in the order CV-CV, CCV-CCV,..., etc. However, this mode of operation may require to redesign of an input filter. Example simulation results of the PWM variant 3 with toggling mode for DSM-CMC 5 × 5 have been presented in Figure 18.

**Figure 18.** Simulation of the PWM variant 3 with toggling mode for DSM-CMC5 × 5.

#### **6. Summary and Conclusions**

This paper presents a new approach to the PWM modulation for the multi-phase matrix converters supplying loads with open-end winding. The proposed approach is an alternative for the methods based on the space-vector modulation. Three variants of PWM modulation were presented. Animations for the first two of them (Figures S1 and S2) are available in Supplementary Materials. The first variant allows for eliminating the common-mode voltage, which is a desired feature from a practical point of view. The second variant based on a specific rearranging switches state sequences can offer quasimultilevel waveforms with low THD. However, a common-mode voltage level can be unaccepted due to influence on the bearings lifetime. Variant 3 of the PWM modulation described in a paper offer over 12% greater voltage transfer gain. Comparison of an input angle value for the proposed variants of PWM modulation is presented in Table 1.


**Table 1.** Comparison of an input angle value for the proposed variants of PWM modulation.

The multi-phase matrix converters, with an equal number of input and outputs, belong to the niche solution. Recently, we can observe an increasing interest in multi-phase systems. Furthermore, the complexity of the modulation algorithms grows up. The described proposal is a research result of analytic signal and an application of the smooth interpolation method in PWM duty cycle computing. Some selected features and properties have been compared with the space-vector method. Table 2 presents such a comparison. The PWM duty cycle computation represented by equations, from (12) to (14), is performed using only a second-order determinant of the voltages coordinate matrix without trigonometry usage. Therefore, the proposed method also naturally extends the applicability of the formulas to unbalanced and distorted AC voltage sources. Moreover, all computation can be realized in the FPGA structure using the simple multipliers and adders. The important contribution of the presented article is a presentation of the novel algorithm, which is much easier than algorithms based on the space-vector approach. This property is essential in multi-phase systems because the number of vectors is very high. The proposed solution uses only vectors that represent the Hilbert analytic signal pair calculated for the input and the reference

vectors. The number of vectors needed to realize the output voltage synthesis is equal to only the sum of input and output phases.


**Table 2.** The comparison of the proposed modulation with the space-vector approach.

**Supplementary Materials:** The following are available at http://www.mdpi.com/1996-1073/14/2/466/s1, Supplementary data: Matlab script m-file: energies\_1056291\_Supplementary\_Materials.m, Figure S1: A New Approach to the PWM Modulation for the Multiphase Matrix Converters Supplying Loads with Open-End Winding: two rotating the reference vectors, Figure S2: A New Approach to the PWM Modulation for the Multiphase Matrix Converters Supplying Loads with Open-EndWinding: the input and the output waveforms obtained, and the PWM duty cycles.

**Author Contributions:** The concept, algorithmization, simulation studies, P.S.; simulation results verification and presubmission editing, E.R.-C. and N.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the LINTE∧2 Laboratory, Gdansk University of Technology.

**Conflicts of Interest:** All authors declare no conflict of interest.

#### **Appendix A. Simulation Parameters**




**Table A2.** Simulation parameters for DSM-CMC 12 × 12.

Simulation research has been performed for symmetric and balanced source and load. Obtained currents and voltages have been presented as *p*.*u*. values referred to the base voltage *V*base = *V*<sup>i</sup> and the base current equal to *I*base = *V*i/*Z*o, where *Z*<sup>o</sup> was a load impedance.

#### **References**




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