**5. Experimental Results**

In this section, experiments are carried out under several distorted grid conditions. Different from a traditional grid, when a grid is dominated by renewable energy sources, called a "weak grid", phase jump is inevitable during the process of grid faults, sudden large load tripping and other transient behavior. Wind power fluctuation is an important issue with the increasing penetration of wind power plants, which usually cause grid frequency deviation. Thus, the proposed method is also evaluated under frequency step change and frequency ramp change conditions. Owing to the existence of a large amount of power electronics elements, harmonic disturbances are injected by power converter-based equipment such as HVDC, MMC, etc. Sub/super-synchronous oscillations arising from inappropriate system configuration can also pollute grid voltages. Hence, the proposed PLL is also examined under unbalanced and harmonic distorted voltage conditions.

In this section, experiments are implemented on a real-time experimental platform to examine the performance of the proposed PLL. Three phase voltage signals are generated by a personal computer with a data acquisition board. Through the Digital-Analogy output ports, the voltages signals are exported. PLL is implemented on a digital signal processor (DSP TMS320F28335) board. After receiving voltage signals, the estimated phase and frequency are exported through DA ports on a DSP board. Oscilloscope is used to capture all waveforms.

The grid nominal frequency is 50 Hz. The sampling frequency of a digital system is 10 kHz. The zero-order hold method is used for discretization. Besides this, the proposed PLL, EGDSC-PLL [37] is also implemented as a traditional DSC-based PLL for comparative study. QT1-PLL [36] and MAF-PLL [38] are also compared to assess the performance. Figure 18 shows the setup of the experimental platform.

**Figure 18.** The experimental setup.

### *5.1. Test Case 1: Phase Jump*

The performance is evaluated when phase jump occurs in grid voltages. Figure 19 shows the waveform of three phase voltages. A +40◦ phase jump came up during the experiments. Figure 20 shows the transient behavior after a phase jump. It is observed that the proposed PLL provides the fastest transient response. The settling times of phase-error and estimated frequency are around one grid period. The dynamic behavior of QT1-PLL takes over 30 ms to converge. The dynamic performance of EGDSC-PLL and MAF-PLL are even more unacceptable, owing to their more than two grid period settling time. According to the requirement of a transient response in some grid codes [21,22], an accurate estimation of grid voltage information should be extracted after undesired injection of disturbance within 25 ms. EGDSC-PLL and MAF-PLL can definitely not fulfill this requirement.

**Figure 19.** Grid voltages under +40◦ phase jump condition.

**Figure 20.** The experimental results of test case 1. (**a**) Estimated frequency and (**b**) phase error.

### *5.2. Test Case 2: Frequency Step Change*

Test case 2 is carried out when grid voltages are under +5 Hz frequency step change. Figure 21 depicts the waveform of three phase voltages. The waveform of estimated frequency and phase error are shown in Figure 22. It is observed that the proposed PLL can accurately estimate grid frequency in less than one period. The phase error of the proposed PLL can converge to zero within only 15 ms. The settling time of QT1-PLL is around one period in both estimated frequency and phase error, which is acceptable for most practical application. While EGDSC-PLL can track grid frequency as fast as QT1-PLL, the phase error takes over 30 ms to converge.

**Figure 21.** Grid voltages under +5 Hz frequency step change condition.

**Figure 22.** The experimental results of test case 2. (**a**) Estimated frequency and (**b**) phase error.

### *5.3. Test Case 3: Frequency Ramp Change*

In practical conditions, grid frequency can hardly have a step change. Most of time, grid frequency varies bit by bit continuously. Consequently, a ramp change is implemented to the grid frequency to examine PLLs' performance. The grid frequency rises from 50 Hz to 55 Hz with a +100 Hz/s ramp rising rate. The whole behavior last for 50 ms. Figure 23 shows the waveform of grid voltages during this rising procedure. Figure 24 shows the transient behavior of four advanced PLLs. It can be seen that the proposed PLL provides 0.5◦ phase error during the frequency rising procedure. The phase error of QT1-PLL is less than 2◦, which is also acceptable. By contrast, the phase errors of EGDSC-PLL and MAF-PLL are too big, which means PLL cannot provide acceptable phase information during the frequency changing procedure.

**Figure 23.** Grid voltages under +5 Hz frequency step change conditions.

**Figure 24.** The experimental results of test case 3. (**a**) Estimated frequency and (**b**) phase error.

### *5.4. Test Case 4: Unbalanced and Distorted Grid Voltages*

To examine the filtering capability, the proposed PLL is evaluated under unbalanced and distorted grid voltages condition. A frequency step change occurs during the experimental procedure. The parameters of voltage components in the polluted grid voltages are listed in Table 2. To achieve a satisfactory performance, the delay and MAF units in the proposed PLL, QT1-PLL and MAF-PLL are frequency adaptive. The corresponding implementation of a frequency adaptive structure can be found in [36] and [38]. While EGDSC-PLL can also improve its performance by making DSCs adaptive, too many DSCs used in its filtering stage increases its computational burden dramatically. Hence, EGDSC-PLL with non-adaptive DSCs is more practical for the comparison.


**Table 2.** Parameters of grid voltages.

The polluted grid voltages are depicted in Figure 25. The transient responses of four PLLs are depicted in Figure 26. It can be observed that all PLLs can eliminate disturbances completely when grid frequency is at its nominal value. When grid frequency jumps from 50 Hz to 55 Hz, transient behavior occurs for every PLL. Thanks to frequency adaptive implementation, the proposed PLL, QT1-PLL and MAF-PLL can still provide a satisfactory filtering capability after frequency change. However, oscillation of phase error occurs in the transient behavior of EGDSC-PLLs for its non-adaptive DSCs. While this problem can be solved by applying adaptive DSCs, a huge computational burden is still a big problem for designers to solve.

**Figure 25.** Grid voltages under +5 Hz frequency step change conditions.

**Figure 26.** The experimental results of test case 3. (**a**) Estimated frequency and (**b**) phase error.
