**5. Simulation Results**

Simulations using the PSIM software tool were conducted to validate the proposed method. The system configuration was similar to that shown in Figure 1. The DC link voltage (*Vdc*) was 300 V, and was distributed equally between the top capacitance voltage (*Vtop*) and the bottom capacitance voltage (*Vbottom*). The total DC link capacitance was 2200 μF and the switching frequency was 10 kHz. The value of |*Elimit*| was set empirically at 2.6 V. The simulation parameters are given in Table 2. After synthesizing the reference voltage vectors with the minimized cost function using the deadbeat DSVM-MPC system, the reference voltage vector was applied to the grid-connected 3L T-type VSI.


**Table 2.** System parameters.

Figure 7 shows the simulation results for the optimal voltage vectors in the *d–q* frame for the deadbeat DSVM-MPC, which followed the reference current using only four candidate voltage vectors [20]. Figure 8 shows the simulation results for the deadbeat DSVM-MPC using the balancing method in Reference [20] and using the proposed DPWM method. It can be seen that the current waveforms became highly distorted before implementation of the neutral-point balancing of capacitance voltage, owing to large voltage deviations. Obviously, the total harmonic distortion (THD was is significantly reduced using either one of the balancing methods. Nevertheless, the proposed balancing method performed better in terms of THD, as shown in Figure 8b.

**Figure 7.** Simulation results of the optimal voltage vectors for the deadbeat FS-MPC with DSVM.

**Figure 8.** *Cont*.

**Figure 8.** Simulation results of capacitance voltage balancing for deadbeat DSVM-MPC. (**a**) Conventional balancing method [20]. (**b**) Proposed balancing method.

Figure 9 shows the simulation results for dynamic response for the deadbeat DSVM-MPC system, using the two balancing methods. As can be seen, both methods exhibited a fast dynamic current response, because the MPC method was used. On the other hand, the proposed method exhibited smaller THD compared with the method in Reference [20].

**Figure 9.** *Cont*.

 **Figure 9.** Simulation results of current dynamic response for deadbeat DSVM-MPC with (**a**) conventional balancing method [20] and (**b**) proposed balancing method.

The robustness of the proposed method was shown by varying the impedances of the grid connected system including the inductance (L) and resistance (R) (Figure 10). The values of resistance and inductance were increased (at t = 0.1 s) by 100% and 50% of the nominal values, respectively. It can be obviously seen that there was a negligible increase in the THD. Therefore, it was confirmed that the proposed balancing method in FS-MPC with DSVM and DBC is robust to the variations of impedances.

Figure 11a,b depicts the frequency spectrum of the phase voltage for the conventional method and proposed method, respectively. Apparently, the first harmonic component (i.e., switching frequency (*fsw*)) was greatly reduced with the proposed algorithm, compared to the conventional method. This indicates the proposed method has less switching frequency owing to the use of the DPWM modulator, as mentioned previously.

**Figure 10.** Simulation results of grid impedance variation for the proposed method.

**Figure 11.** Simulation results of frequency spectrum for the phase voltage with (**a**) conventional balancing method [20] and (**b**) proposed balancing method.
