**2. System Modeling**

Essentially, there are three switching states for three-level topologies such as neutral-point clamped (NPC) and T-type inverters. Figure 1 shows the topology of a grid-connected, three-level T-type voltage source inverter. The output poles of the T-type inverter can be connected to three di fferent levels of the source voltage, namely the positive bus bar "*P,*" the negative bus bar "*N,*" and the neutral point *Energies* **2019**, *12*, 3111

"*0*" [21]. With three-phase to two-phase transformation, the model of the inverter in the stationary *d–q* frame is given by:

$$
\mu = R \cdot \stackrel{\rightarrow}{i} + L \cdot \frac{di}{dt} + \text{e.} \tag{1}
$$

In Equation (1), *R, L, u, i*, and *e,* are the load resistance, filter inductance, inverter voltage vector, output current vector, and grid voltage vector, respectively. Because the top capacitance voltage (*Vtop*) and the bottom capacitance voltage (*Vbottom*) can become unequal in the three-level voltage source inverter (VSI) (and hence will produce poor-quality output current and distorted output voltage), the capacitor voltages should be observed and taken into account at every time step, to ensure that they become balanced. The dynamic equations of the two capacitor voltages are given by:

$$V^{top} = V^{top} + I\_{NP^\*}(T\_s/\mathbb{C}) \tag{2}$$

$$V^{bottom} = V^{bottom} + I\_{NP^\*}(T\_s/\mathbb{C}) \tag{3}$$

where *C* is the capacitance of each capacitor, *Ts* is the sampling time, and *INP* is the neutral-point current.

**Figure 1.** Circuit diagram of three-level T-type inverter.

### **3. FS-MPC Based DSVM with Deadbeat Control**
