*3.3. Deadbeat Control Strategy*

As mentioned earlier, considering all virtual voltage vectors significantly increases the computational burden on the prediction process. Therefore, a control method, namely deadbeat control (DBC), for alleviating the computational burden on the digital signal processor (DSP) is required. In addition, all of the voltage vector values in the stationary *d–q* frame should be predefined in a lookup table [16]. As a result, more complex lookup tables are required with increasing voltage vectors [16]. Thus, the deadbeat control method is utilized for reducing the computational burden associated with instantaneous computation of candidate voltage vectors.

The virtual voltage vectors in the stationary *d–q* frame are defined as [20]:

$$\mathbf{u}\_d(\mathbf{x}, \mathbf{y}) = (V\_{d\varepsilon} / \boldsymbol{\theta} \cdot \mathbf{M})[(a + 2\cdot \boldsymbol{e}) \cdot \mathbf{x} + 3\boldsymbol{b} \cdot \mathbf{y}] \tag{10}$$

$$
\mu\_{\boldsymbol{\theta}}(\mathbf{x}, \boldsymbol{y}) = (\sqrt{3} \cdot V\_{\mathrm{dc}} / 6 \cdot \boldsymbol{M}) [\boldsymbol{\varepsilon} \cdot \mathbf{x} + (\boldsymbol{d} + 2 \cdot \boldsymbol{f}) \cdot \boldsymbol{y}].\tag{11}
$$

In Equations (10) and (11), *x* and *y* are the coordinates of the different sectors, and the coefficients (*a*, *b*, ... *f*) are obtained from Table 1 [20]. Figure 4 schematically shows the voltage vectors for sectors *S*4, *S*5, and *S*6 for *M* = 3.


**Table 1.** Coefficients for Each Sector.

**Figure 4.** Space vector diagram of conventional DSVM-MPC.

To determine the candidate voltage vectors, the deadbeat method uses the reference inverter voltage vector phase (θ∗) and magnitude (|*u*<sup>∗</sup>|). Assuming that the control works correctly, it is possible to assume:

$$i(k+2) = i^\*(k+2).\tag{12}$$

Under the assumption of Equation (12), it is possible to calculate the reference voltage vector as:

$$
\mu\_{dq}^\*(k+1) = \mathbf{R} \cdot \mathbf{i}\_{dq}^\*(k+1) + (T\_s/L) \Big(\mathbf{i}\_{dq}^\*(k+2) - i\_{dq}(k+1)\Big) + \varepsilon\_{dq}(k+1). \tag{13}
$$

Hence, θ∗ and *u*<sup>∗</sup> can be expressed as:

$$\theta^\* = \tan^{-1} \left( u\_d^\*(k+1) / u\_q^\*(k+1) \right) \tag{14}$$

$$\left|u^\*(k+1)\right| = \sqrt{\left(u\_d^\*(k+1)\right)^2 + \left(u\_q^\*(k+1)\right)^2}.\tag{15}$$

Among the twelve sectors on the space vector diagram, a single sector is selected by θ<sup>∗</sup>. Since *uop*<sup>t</sup> exists in the vicinity of the circle, this method determines two concentric hexagonal diagrams (SVD1 and SVD2), as given below:

$$SVD\_1 = |\mathfrak{u}^\*| \cdot (M/V\_{dc}) \cdot (3/2) \tag{16}$$

$$\text{SVD} \mathfrak{z} = \left[ |\mathfrak{u}^\*| \cdot (M/V\_{dc}) \cdot (3/2) \right] + 1. \tag{17}$$

Hence, only the voltage vectors within *SVD*1 and *SVD*2 are taken into account during the calculation and prediction processes. In this way, the candidate voltage vectors are restricted, which significantly reduces the computational burden on the DSP. Finally, the optimal voltage vector *uop*<sup>t</sup> is selected at *k* + 2, using the cost function in Equation (8), before it is sent in the next sampling instant to the space vector modulator. To simplify our discussion in the next section, deadbeat DSVM-MPC was used to identify the FS-MPC with DSVM and deadbeat control.

### **4. Deadbeat DSVM-MPC with Proposed Neural Point Balancing Method**

In this paper, the deadbeat DSVM-MPC used virtual voltage vectors obtained using the DSVM strategy, and their values were calculated instantly for the current prediction [20]. Although good performance can be obtained with deadbeat DSVM-MPC, the 3L T-type VSI topology can lead to an unbalanced neutral-point voltage, which increases the voltage stress on the switching device. It also

increases the total harmonic distortion (THD) of the output current, because a low-order harmonic will appear in the output voltage. A large deviation of the DC link capacitance voltage is caused by the inconsistency in switching or imbalance of DC capacitors, owing to the manufacturing tolerance [22].

It is worth mentioning that there are various modulation strategies to synthesize output voltages, which can be categorized into two common types: continuous-based modulation (CPWM), such as sine pulse-width modulation (SPWM), and discontinuous-based modulation, namely discontinuous pulse-width modulation (DPWM). To optimize the performance of the 3L T-type VSI system, the voltages of the in-series connected DC link capacitors should be balanced. Unlike our previous work [20], wherein the problem of balancing the capacitor voltages was treated using a separate cost function to modify the o ffset voltage in SPWM (increasing the computational burden), the proposed deadbeat DSVM-MPC implements a modification in DPWM using a hysteresis capacitance voltage control. The main advantage of this proposed method is that it is straightforward and easily implemented, without additional hardware or extensive computation. Furthermore, it is known that by using DPWM, the switching losses are reduced, and better harmonic characteristics can be obtained for high modulation indices, compared with inverters that use continuous pulse-width modulation [23–26]. Although there are several di fferent DPWM methods, conventional 60◦ DPWM is most commonly used for systems with the unity power factor. The idea behind the 60◦ DPWM method is schematically shown in Figure 5. Therefore, the pole reference voltages to be applied to the VSI are described by:

**Figure 5.** Reference voltage, o ffset voltage, and pole reference voltages of the conventional 60◦ discontinuous pulse-width modulation (DPWM).

$$\begin{array}{l} \mu\_{\rm an}^\* = \mu\_{\rm as}^\* + \mu\_{offset, DPWM} \\ \mu\_{\rm bn}^\* = \mu\_{\rm bs}^\* + \mu\_{offset, DPWM} \\ \mu\_{\rm cn}^\* = \mu\_{\rm cs}^\* + \mu\_{offset, DPWM} \end{array} \tag{18}$$

where *<sup>u</sup>\*an*, *<sup>u</sup>\*bn*, and *u\*cn* are the pole reference voltages to be applied to the VSI, whereas *<sup>u</sup>\*as*, *<sup>u</sup>\*bs*, and *u\*cs* are the optimal reference voltages by deadbeat DSVM-MPC of each phase, respectively. The voltage *uo*ff*set,DPWM* is the o ffset voltage used in the DPWM, which is calculated as follows:

$$\begin{cases} u\_{offset, DPVM} = \frac{V\_{dc}}{2} - u\_{\text{max}}, \quad (u\_{\text{max}} + u\_{\text{min}} > 0) \\ u\_{offset, DPVM} = -\frac{V\_{dc}}{2} - u\_{\text{min}}, \quad (u\_{\text{max}} + u\_{\text{min}} < 0) \end{cases} \tag{19}$$

where *umax* and *umin* are, respectively, the maximum and the minimum values among the phase reference voltages.

Figure 6a depicts the imbalance of the DC link capacitor voltage for the 3L T-type VSI. Note that when the switch of the either phase is locked in the P state, the top DC link capacitor voltage *Vtop* is decreased and the bottom DC link capacitor voltage *Vbottom* is increased. Conversely, if the switch of the same switch is locked in the N state, the top and the bottom DC link capacitor voltages are increased and decreased, respectively. Thus, clamping plays a major role in decreasing or increasing the top and bottom capacitance voltages. Figure 6b shows the proposed DPWM method using the hysteresis capacitance voltage band ( Δ*HBcv*). The proposed neutral-point voltage balancing method uses a compensated voltage o ffset (*uo*ff*set,cv*) depending on the top and bottom capacitor voltages in the linear modulation range. The *uo*ff*set,cv* has an opposite influence from *uo*ff*set,DPWM* on changing the direction of the top and bottom voltages, which is given as:

**Figure 6.** Behavior of top and bottom capacitance voltages with respect to: (**a**) conventional DPWM; (**b**) proposed DPWM.

$$\begin{cases} \boldsymbol{u}\_{offst,\mathbf{c}\mathbf{v}} = \frac{V\_{dc}}{2} - \boldsymbol{u}\_{\text{max}} & (V^{top} > V^{bottom})\\ \boldsymbol{u}\_{offst,\mathbf{c}\mathbf{v}} = -\frac{V\_{dc}}{2} - \boldsymbol{u}\_{\text{min}} & (V^{top} < V^{bottom}) \end{cases} \tag{20}$$

The proposed method seeks to maintain the advantage of diminishing the stress on transistors and minimizing the power loss, while simultaneously achieving a balanced DC link capacitance voltage with a stable and acceptable capacitance voltage error |*Ecv*|, which is defined as

$$|E\_{\rm UV}| = \left| V^{top} - V^{bottom} \right|. \tag{21}$$

The capacitance voltage error |*Ecv*| is inevitable; thus, it should be limited to an acceptable error band Δ*HBcv*, to avoid large deviations of the DC link capacitance voltage and high switching. The limited error band is defined as |*Elimit*|. The resultant voltage offset (*uo*ff*set,res*) can then be designed depending on the following condition:

$$\begin{cases} \boldsymbol{u}\_{offset, \text{res}} = \boldsymbol{u}\_{offset, \text{DPWM}} + \boldsymbol{u}\_{offset, \text{cv}} & (|\boldsymbol{E}\_{\text{cv}}| > |\boldsymbol{E}\_{\text{limit}}|) \\ \boldsymbol{u}\_{offset, \text{res}} = \boldsymbol{u}\_{offset, \text{DPWM}} & (|\boldsymbol{E}\_{\text{cv}}| \le |\boldsymbol{E}\_{\text{limit}}|) \end{cases} \tag{22}$$

According to Equation (22), if the capacitance voltage error |*Ecv*| exceeds the limited error band, the *uo*ff*set,cv* will be injected into the *uo*ff*set,DPWM* to have an opposite effect on the clamped voltage, otherwise, the *uo*ff*set,DPWM* will continue with its normal operation.

The effect of the resultant voltage offset *uo*ff*set,res* on one of the pole reference voltages to be applied to the VSI is seen in Figure 6b. Note that the clamping areas are almost similar to the conventional DPWM; at the same time, the error of the DC link capacitance voltage is stable. In addition, there is a short clamping area injected by the *uo*ff*set,cv* to maintain the capacitance error range. It is noteworthy that the switching frequency of *uo*ff*set,res* and the non-switching area depend mainly on the setting of |*E*limit|; increasing the limited error band will result in a lower switching of *uo*ff*set,res* and will deteriorate the quality of the current, whereas reducing the limited error band will cause undesirable switching frequency of *uo*ff*set,res* and a small clamping area. Thus, it is recommended that the tradeoff error band limit for achieving desirable current control performance be determined.
