**1. Introduction**

In modern power systems, more and more renewable energies such as solar and wind energy are integrated with the power grid through grid-connected power converters. To use this energy in more efficient ways, several advanced techniques, such as high voltage direct current transmission (HVDC) [1], flexible AC transmission systems (FACTS) [2] and energy storage systems (ESSs) [3], are developed. Some power electronic converter-based applications on the customer side, such as constant power load (CPL) and micro-grids with ESSs, are also widely used for some purposes, like peak load shaving. All the above yields a more complicated power system with a large amount of power converters. A typical power system integrating high penetrated renewable energy sources is depicted in Figure 1. The irregular phenomenon and uncertainty of wind and solar energy may cause undesired grid conditions [4]. Sub- and super-synchronous oscillations may emerge in wind farms if the controller is not well-designed [5]. In recent years, these issues happened several times in Oklahoma, USA [6] and Hebei and Xinjiang, China [7,8], and caused many wind turbines to be tripped <sup>o</sup>ff. This highly impacted the operation of power distribution and renewable energy utilization. The grid frequency is prone to deviate from its nominal value since the inertia of the grid decreases. Grid voltages contain an amount of undesired components, such as fundamental frequency negative sequences (FFNSs) and harmonic components, which results in unbalanced and distorted grid conditions. It is an essential requirement for a renewable energy power converter to maintain stable operation with high performance under such conditions. To achieve this goal, a proper grid synchronization method is needed for all grid-connected applications. It is a big challenge for a grid synchronization method to extract grid frequency and phase information under such adverse conditions.

**Figure 1.** Block schematic of a typical power system with high penetration of renewable energy.

Among various grid synchronization techniques, phase-locked loop (PLL) is the most widely used method in grid phase and frequency detection area for its robust performance and simple implementation [9–12]. Figure 2 shows the most common employment of PLLs in practical applications. After extracting grid voltage information at the common coupling point (PCC), PLL sends estimated grid phases to the controller of the grid power converter (GPC). For a three phase power system, synchronous reference frame PLL (SRF-PLL) is an effective and typical method under ideal conditions [13,14]. However, with more utilization of renewable energy sources, a power system turns "weak" [15–18]. The grid voltages usually contain fundamental frequency negative sequence components (FFNSs) and other harmonic components. Furthermore, grid frequency does not always stay at its nominal value. To maintain the phase tracking accuracy under distorted grid voltages conditions, various filtering technique were used to remove disturbances at the cost of slowing down the transient response, which may violate the requirement on settling time in common grid codes [19–23].

**Figure 2.** Block schematic of a typical grid-connected power converter system.

The block diagram of SRF-PLL is depicted in Figure 3. Park transformation is utilized as a phase detector (PD). An integrator is employed as a voltage controller oscillator (VCO). A proportional-integral controller (PI) is used to mitigate the phase-tracking error. To enhance the disturbance rejection capability and keep the phase tracking accuracy of SRF-PLL, a low pass filter (LPF) or moving average filter (MAF) is employed in the inner loop. However, LPF-based PLL can only attenuate but not eliminate

the disturbance component. To achieve good disturbance rejection, the bandwidth of LPF-based PLL must be significantly reduced, which results in a large settling time [23]. Compared with LPF, MAF can totally remove a specific set of disturbances, which depends on its window length (*T*ω). However, *T*ω deteriorates the dynamic response since *T*ω has to be 0.01 s (half grid period) to eliminate all disturbance [24].

**Figure 3.** Block diagram of SRF-phase-locked loop (PLL).

To tackle the problem mentioned above, many advanced methods were proposed in recent years. According to their various filtering methods, these advanced PLLs can be classified into two categories: LPF-based PLLs and MAF-based PLLs. To improve the performance of LPF-based PLLs, dual second-order generalized integrators (DSOGIs) [25], multiple complex-coefficient filters (MCCFs) [26], multiple reference frame-based filter structures (MRFs) [27] and decoupled double synchronous reference frame-based filter structures (DDSRFs) [28] were arranged before applying Park transformation. The basic idea of these PLLs is to make the filtering stage act as a hybrid filter that consists of notch filters and LPFs. Notch filters are responsible for eliminating FFNS components and other important harmonics. LPFs are used to attenuate other disturbances. These methods are not suitable when grid voltages contain several significant components. Only the disturbance components coincident with the specific frequency in a notch filter can be totally removed. Compared with LPF-based PLLs, MAF-based PLLs can provide ideal filtering capabilities at the cost of increasing time delay. With a *T*ω time delay, MAF can eliminate all *<sup>n</sup>*/*T*ω (*n* = 1, 2, 3, ... ) frequency components. The delay signal cancellation (DSC) operator is another effective filter, the behavior of which is similar to MAFs. However, single DSCs cannot eliminate all desired disturbances. To overcome this weakness, several DSCs with different *T*ω are usually employed to build an entire filtering stage in cascaded [29–31]. Consequently, the time delay of the filtering stage is the sum of delay introduced by all DSCs. Too many DSCs also increases the computational burden and implementation complexity.

Besides using an advanced filter, another way to improve PLLs' performance is to change the control structure. In [32,33], a secondary control path is built to accelerate the transient behavior. However, an inappropriate design of a secondary control path may give rise to the stability problem. It also increases the order of open loop transfer functions and the implementation complexity of a system [34]. Recently, a PLL with a new structure named quasi-type-1 PLL (QT1-PLL) was proposed in [35]. Compared with the traditional type-2 SRF-PLL, QT1-PLL provides a feed-forward control path to the output. This makes QT1-PLL able to track phase precisely without using integral operations in the controller. One more open-loop pole is provided at the origin point, which accelerate the dynamic response. Since the filtering stage of QT1-PLL is built by MAFs, QT1-PLL can also offer a satisfied filtering capability. It is a good idea to do some further performance improvement of PLL based on the QT1-PLL structure.

To improve the dynamic performance without degrading PLLs' filtering capability, this paper propose a new PLL based on the QT1-PLL structure. In order to provide a fast transient response, a hybrid filtering stage is designed and arranged at the inner loop of the proposed PLL. The proposed hybrid filtering stage consists of a modified DSC (MDSC) and MAFs with narrowed *T*<sup>ω</sup>. Our basic idea is to eliminate two sets of disturbance components by using MDSCs and MAFs, separately. Different from the conventional DSC-based PLL, there is only one MDSC unit in our method, which is easy for digital implementation. To demonstrate the effectiveness, an experimental case study is carried out when grid voltage conditions are under phase jump, frequency jump, frequency ramp change and harmonic polluted voltage conditions, which usually happens to high renewable energy-penetrated power system.

This paper is organized as follows. In Section 2, the modified DSC is presented based on the analysis of DSCs. The hybrid filtering stage and new PLLs are proposed in Section 3. In Section 4, the mathematics model is established. Based on this model, the parameters are designed based on analysis of the system. In Section 5, the performance of the proposed method is validated by a comprehensive case study.

### **2. Modified Delay Signal Cancellation Operator**

The DSC operator has been widely studied in much literature [36]. In the Laplace domain, most of the existing DSC operators can be written as:

$$\text{DSC}\_{\text{ll}}(s) = \frac{1 + e^{\frac{j2\pi}{n}}e^{-\frac{T}{n}s}}{2} \tag{1}$$

To achieve a desired performance, several DSCs have to be connected in cascaded. For instance, five DSCs with different value of *n* (*n* = 2, 4, 8, 16, 32) were arranged at the pre-filtering stage in [37]. The typical block diagram of the control strategy is shown in Figure 4. Too many DSCs used in PLLs results in complicated implementation. It is a normal idea to simplify the system by reducing the number of DSCs.

**Figure 4.** The common block diagram of using delay signal cancellation (DSC)s in PLL.

Observing Equation (1), it can be found that there is only one parameter *n* which can decide the characteristics of DSC*<sup>n</sup>*. To make its property more flexible, DSC*n* is modified to the following form with two parameters.

$$\text{MDSC}\_{m,n}(s) = \frac{1 + e^{\frac{f^{2m}}{m}} e^{-\frac{T}{n}s}}{2} \tag{2}$$

In Equation (2), *T* is the grid period (0.02 s for 50 Hz power system). *m* is used to shift the original DSC*n* frequency characteristics along the frequency axis. *n* is a parameter that can decide the time delay inside the DSC*<sup>n</sup>*. After using Euler transformation, the implementation of MDSC*m,n* is shown in Figure 5. It should be noted that the input of MDSC*m,n* is a vector with two dimensions. The output of MDSC*m,n* is also a 2D vector. The effect of *m* can be considered as a rotating operation to the input vector.

**Figure 5.** Time-domain implementation of a modified delay signal cancellation (MDSC) operator.

To examine the effect of two parameters (*<sup>m</sup>*, *n*), two bode diagrams are depicted in Figures 6 and 7. In Figure 6, *n* is set to 4. The solid lines, dashed lines and dotted lines correspond to different MDSC*m,n*=<sup>4</sup> with *m* = 4, 2, 4/3, respectively. The frequency characteristic of MDSC*<sup>m</sup>*=4,*<sup>n</sup>*=<sup>4</sup> can be considered as that of MDSC*<sup>m</sup>*=1,*<sup>n</sup>*=<sup>4</sup> shifted *nTm* = 50 Hz along the positive frequency direction. MDSC*<sup>m</sup>*=2,*<sup>n</sup>*=4, MDSC*<sup>m</sup>*=4/3,*<sup>n</sup>*=<sup>4</sup> corresponds to *nTm* = 100 Hz and *nTm* = 150 Hz, respectively. This nice property can be used to arrange the notch frequency of MDSCs by setting an appropriate *m*.

**Figure 6.** The frequency characteristic of MDSCs with different *m* (*n* = 4).

In Figure 7, *m* is 2. The solid lines, dashed lines and dotted lines are the bode diagrams of MDSC*<sup>m</sup>*=2,*<sup>n</sup>* with *n* = 2, 4, 8, respectively. With different value of *n*, the interval of the notch frequency of an MDSC can be changed. This property can be used to eliminate a set of specific harmonic frequency components. In the next section, the design procedure of the proposed hybrid filtering stage is presented based on the analysis of MDSCs above.

**Figure 7.** The frequency characteristic of MDSCs with different *n* (*m* = 2).
