**Contents**


### **About the Editor**

**Manuel Arias** received an M.Sc. in electrical engineering from the University of Oviedo, Spain, in 2005, and a Ph.D. from the same university in 2010. In 2007, he joined the University of Oviedo as an Assistant Professor and, since 2016, he has been an Associate Professor at the same university. His research interests include AC–DC and DC–DC converters, battery-cell equalizers, LED lighting, and aerospace applications.

## **Preface to "Design and Control of Power Converters 2020"**

In terms of research, power electronics is one of the most prolific fields in the world of electronics. One of the main reasons for this is its relevance in present-day society, which is increasingly concerned with energy savings and greener energy production. This scenario constitutes a powerful catalyst for research, not only increasing the amount of interesting ideas, solutions, and studies, but also the number of topics that have emerged under the umbrella of power electronics. This can be observed in well-established research topics as varied as renewable energies, battery management, and electric traction coexisting, or even merging, with more recent topics, such as LED lighting or micro- and nano-grids. These topics can be considered as established compared to others like wide band-gap devices and electric vehicles, where research is still incipient. In all of the aforementioned topics, in addition to others, the design and control of power converters plays a key role. In this book, representative papers that focus on well-established topics, as well as more recent ones, can be found. This mixture will foster new ideas for readers and help researchers detect solutions that can be migrated from one topic to another, making this book a relevant milestone for any power electronics engineer.

> **Manuel Arias** *Editor*

### *Article* **Distortion Due to the Zero Current Detection Circuit in High Power Factor Quasi-Resonant Flybacks**

**Claudio Adragna 1, Giovanni Gritti 1, Santi Agatino Rizzo 2,\* and Giovanni Susinni <sup>2</sup>**


**Abstract:** In a high-power factor quasi-resonant Flyback, an ideal zero current detection (ZCD) circuit and control circuitry enable the power switch turn-on in the exact instant a zero ringing current is reached after demagnetization. A nonzero current at the turn-on instant affects the input current shape and; consequently, affects its Total Harmonic Distortion (THD). This paper firstly deeply analyzes the effect on the distortion due to a nonideal ZCD circuit. After, some typical implementations of the ZCD circuit and their effect on the THD are analyzed, identifying their pros and cons. Finally, some experimental results are obtained to validate the analytical investigation.

**Keywords:** converter control; power factor correction; total harmonic distortion; flyback; solid-state lighting

### **1. Introduction**

The Flyback topology circuit represents one of the most attractive dc-dc converters used for low and medium power applications. To date, the Flyback converters have been widely employed as USB chargers for cell phones, notebooks, LCD TVs, and LED drivers [1–6]. The key factors that make this solution very popular are related to the simple design of the conversion stage, high efficiency, inexpensive cost of the components, possible multiple isolated output stages, and high output voltage.

It is worth remembering that the Flyback topology has been widely studied in the literature, where several advantageous results with respect to other converter topologies have been pointed out. In this perspective, the authors in [7] have compared the performance between a flyback, a buck-boost, and a hybrid solution [8–14] in terms of some key factors (e.g., cost, efficiency, step-down ability, etc.). The comparison has highlighted the superior performance of the flyback converter, which makes it the preferred choice for countless dc-dc power applications.

The flyback converter can be summarized into two different operating modes. When the current in the secondary windings goes to zero before the OFF time of the power switch, the Flyback operates in discontinuous conduction mode (DCM). On the other hand, when the current in the primary windings is greater than zero before the OFF time is complete, the converter operates in the continuous conduction mode (CCM) [15].

In many applications, the flyback converter can be used with a feedback control loop, with the aim to sense the voltage and current variations of the output. Generally, an optocoupler is used to sense the output voltage and in addition, it provides electrical isolation (SSR—secondary side regulation). Nevertheless, the use of an optocoupler presents a few disadvantages [16]. Indeed, the current transfer ratio may be subjected to variation due to the temperature, and furthermore, the optocoupler introduces an undesired pole in the feedback loop, which may lead to an instability of the converter.

**Citation:** Adragna, C.; Gritti, G.; Rizzo, S.A.; Susinni, G. Distortion Due to the Zero Current Detection Circuit in High Power Factor Quasi-Resonant Flybacks. *Energies* **2021**, *14*, 395. https://doi.org/ 10.3390/en14020395


Received: 2 December 2020 Accepted: 7 January 2021 Published: 12 January 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

On the other hand, the adoption of the constant-current primary sensing regulation (CC-PSR) technique [3,4], the feedback loop at the output(secondary) side is not used and consequentially, the output voltage can be adjusted by using only the control method of the electrical quantities in the primary side. This leads to a save cost and the power losses are strongly reduced. More specifically, in this configuration, only the auxiliary winding is used to sense the output voltage. It is worth underlining that this approach brings greater safety and reliability. As a disadvantage, the primary-side control may result in less accuracy in comparison to the feedback conventional method.

The high-power-factor (Hi-PF) flyback converter is one of the most popular topologies used in low-medium power applications (e.g., LED drivers that feed from the ac power line [17–20]). It has been widely used due to its low input current distortion (low THD) and it guarantees high safety isolation. Furthermore, it is easily suitable for CC-PSR operation [21–23]. The Hi-PF flyback converters can be used with a fixed switching frequency and in the DCM mode (FF-DCM) [24,25]. This mode operation is theoretically able to obtain unity power factor and zero THD.

Furthermore, the Hi-PF flyback converters can also be used in the Quasi-Resonant (QR) mode, where the switching period depends on transformer demagnetization. It presents several advantages compared to FF-DCM such as valley-switching, (almost zero-voltage switching, ZVS) and low EMI emissions. However, its standard implementation guarantees a sinusoidal envelope of the peaks of the primary current. This cannot achieve a very low THD of the input current, as widely discussed in [22–27]. However, more recently, an enhanced QR control method [28] able to provide Hi-PF QR flyback converters with the ability to ideally get a sinusoidal input current has been disclosed.

In this paper, the contribution to the distortion of the input current in a Hi-PF Flyback converter due to a nonzero current at the turn-on instant of the power switch in a switching cycle has been discussed in depth.

Firstly, the general trend of the impact of a nonzero current at the turn-on instant on the input current shape and, ultimately, on its THD is analyzed with both the traditional (QR) method and the enhanced QR (EQR) method. Secondly, this impact is analyzed more in detail with reference to some typical implementations of the zero current detectors (ZCD) circuit responsible for determining the turn-on instant of the power switch.

It is worth underlining that both the quantitative and the qualitative effects of a nonzero initial current due to the implementation of the zero-current detection circuit have not been yet documented in the literature.

Finally, several experimental results showing the aforementioned contributions in a couple of prototypes of Hi-PF Flyback converter controlled with both the traditional QR method and the enhanced QR method are presented.

### **2. Review of the Hi-PF QR Flyback Converter and Its Control Methods**

A flyback converter (whether Hi-PF or not) is said to be QR-operated when the turn-on of the power switch (usually a MOSFET) is synchronized to the instant when the transformer demagnetizes (i.e., as the secondary current becomes zero), normally after an appropriate delay. In this way, the turn-on can be commanded on the valley of the drain voltage ringing that follows the demagnetization, thus with minimum turn-on losses. For this reason, this operation is often termed "valley-switching".

A Hi-PF QR flyback converter, whose principle schematic and relevant key waveforms are shown in Figures 1 and 2 respectively, is powered from the ac power line with no energy reservoir capacitor after the input bridge rectifier (*Cin* serves as a high-frequency smoothing filter). Thus, its input voltage is essentially a rectified sinusoid (*VIN*(θ) = *VPK*|*sin*(θ)|) and the current *IAC*(θ) drawn from the power line is sinusoidal-like (the rectified input current *IIN*(θ) downstream the bridge is |*IAC*(θ)|. In these expressions and in the following discussion, *VPK* is the peak line voltage, θ = 2p *fL t* is the instantaneous phase angle of the line voltage, *fL* is the line frequency. Note also that uppercase subscripts will refer to quantities considered on a line cycle time scale, lowercase subscripts to quantities

considered on a switching cycle time scale. Circuit parameters have a lowercase subscript, dc quantities do not have subscripts.

**Figure 1.** Principle schematic of a Hi-PF QR flyback converter.

**Figure 2.** Key waveforms of the circuit in Figure 1; switching cycle time scale (**a**), line cycle time scale (**b**). In the second diagram from top on the right-hand side, black and blue shapes are the envelopes of primary and secondary current with EQR control; light grey and dark grey shapes are the same with QR control.

With no loss of generality, whichever type of feedback -SSR or PSR- is used, it is possible to assume that the error signal is processed producing a control voltage *Vc* that controls the input-to-output power flow. Being a Hi-PF system, the open-loop bandwidth of the overall control loop is very narrow—typically below 20 Hz—and under steady-state operation, *Vc* can be regarded as a dc level, at least to a first approximation.

Considering peak current mode control, the turn-off of the power switch is determined by the current sense signal reaching the value programmed by the control loop that regulates *Vout* or *Iout* via *Vc*. This value is set by the reference *VcsREF*(θ) output by the "Current reference generator" block that receives at its inputs the control voltage *Vc*, the voltage *VMULT*(θ)—a scaled-down image of the input voltage *VIN*(θ) that serves as a sinusoidal template—and, in case, the output Q of the PWM latch.

In fact, *VcsREF*(θ) is fed into the inverting input of the PWM comparator that receives the voltage *Vcs*(*t*,θ) on the other input. *Vcs*(*t*,θ) is sensed across the sense resistor *Rs*, which is proportional to the instantaneous current *Ip*(*t,*θ) flowing through the primary winding *Lp* and the power switch M when this is in the on state. Assuming that the PWM latch is set (and M turned on) at *t* = 0, the current *Ip*(*t*,θ) will be ramping up linearly and so will do *Vcs*(*t*,θ); at the instant *t* = *TON*, when *Vcs*(*TON*, θ) = *VcsREF*(θ), i.e., *Ip*(*TON*, θ) = *VcsREF*(θ)/*Rs*, the PWM comparator resets the PWM latch, thus switching off M.

As M is switched off, most of the energy stored in *Lp* is transferred to the secondary winding *Ls* so that current starts flowing through *Ls* and *D*, dumping this energy into the output capacitor *Cout* and the load. As *Ls* is completely demagnetized (i.e., the current through *Ls* zeroes) the diode *D* opens. The drain voltage *Vds*, which was fixed at *VIN*(θ)+*VR* (*VR* = *nVout*) while *D* was conducting, starts oscillating around the instantaneous line voltage *VIN*(θ) due to the resonance of the parasitic capacitance of the drain node (*Cds*) with *Lp*. The quick drain voltage fall that marks the onset of this ringing is coupled to the ZCD block in the controller through the auxiliary winding *Laux* and the resistor *Rzcd*. The ZCD block releases a pulse as it detects the negative-going edge and this pulse sets the PWM latch and turns on the power switch M, starting a new switching cycle.

Therefore, the shape of *VcsREF*(θ) determines the shape of the envelope of the peak primary current *IpPK*(θ) = *Ip*(*TON*, θ) = *VcsREF*(θ)/*Rs* and, in turn, that of the average inductor current, i.e., the rectified input current *IIN*(θ) and ultimately the current *IAC*(θ) drawn from the power line. The way the "Current reference generator" block combines the input signals *Vc* and *VMULT*(θ) (and, in case, Q) to produce the reference *VcsREF*(θ)defines the control method.

With the traditional control method [27], which in the following discussion will be referred to as the "QR method", the reference *VcsREF*(θ)is defined by the relationship:

$$V c s\_{REF}(\theta) = K\_M V c V\_{MILT}(\theta) \tag{1}$$

where *KM* is a constant (multiplier gain, dimensionally 1/V). Being *Vc* a dc level and *VMULT*(θ) a rectified sinusoid, the peaks of the primary current will be enveloped by a sinusoid:

$$I\_{pPK}(\theta) = \frac{Vcs\_{REF}(\theta)}{Rs} = I\_{PPK} \sin \theta\_{\prime} \tag{2}$$

where *IPPK* is the peak value of the envelope *IpPK*(θ). With this method there is an inherent distortion in the input current because the input current flows only during the on-time *TON* of the power switch M. Assuming that the turn-on of the power switch is commanded in the instant when the transformer demagnetizes (i.e., assuming *TV* = 0, see Figure 2 right-hand side), *TON* is constant along a line cycle whereas the switching period *T* is not [27]. The rectified input current is, therefore:

$$I\_{IN}(\boldsymbol{\Theta}) = I\_{PPK} \frac{T\_{ON}}{T(\boldsymbol{\Theta})} \sin \boldsymbol{\Theta} \tag{3}$$

In [28] an enhanced control method was proposed that produces a reference *VcsREF*(θ) related to the input signals by the relationship:

$$Vcs\_{REF}(\boldsymbol{\Theta}) = K\_M V\_\mathcal{C} V\_{MULT}(\boldsymbol{\Theta}) \frac{T(\boldsymbol{\Theta})}{T\_{ON}(\boldsymbol{\Theta})} \tag{4}$$

In this way, the peak primary current envelope will not be sinusoidal:

$$I\_{pPK}(\theta) = \frac{V c s\_{REF}(\theta)}{R s} = I\_{PPK} \frac{T(\theta)}{T\_{ON}(\theta)} \sin \theta \tag{5}$$

but, considering again the approximation *TV* = 0, the rectified input current will be:

$$I\_{IN}(\theta) = I\_{PPK} \sin \theta\_{\prime} \tag{6}$$

so that, in this case, *IPPK* coincides with the peak value *IPK* of both *IIN*(θ) and *IAC*(θ). As previously mentioned, we will refer to this enhanced method as the "EQR method".

### **3. Input Current Distortion Due to Power Processing: A Closer Look**

The simplification *TV* = 0 used to determine the shape of the rectified input current *Iin*(θ) described by (3) for the QR method and (6) for the EQR method leads to neglecting the contribution to *IIN*(θ) provided by the negative inductor current that flows during this time interval.

The distortion caused by this negative current is discussed in [7], where the analysis has been carried out based on the equivalent circuit depicted in Figure 3. This has been done under the simplifying assumption that the primary current in the instant when M is turned on to start a new switching cycle is zero (Zero-current switching at turn-on, ZCS), as shown in the timing diagrams of Figure 4. Notice that this is equivalent to saying that M is turned on with ZVS (Zero-voltage switching) if *VIN* ≤ *VR* and with valley-switching if *VIN* > *VR*.

**Figure 3.** Simplified equivalent circuit of primary side after transformer's demagnetization.

**Figure 4.** Key waveforms of the circuit in Figure 2 with *VIN* ≤ *VR* and zero-current switching (left); with *VIN* > *VR* and valley switching (right). DCM waveforms (dotted lines) are shown for reference.

Assuming that *t* = 0 is the instant when the transformer demagnetizes (i.e., when secondary current zeroes and ringing starts) and *tON* the instant when the power switch is turned on, this condition can be labeled as *tON* = *Tneg*. The results of the analysis, as well as the definition of the relevant timing and electrical quantities, are summarized in Table 1.

**Table 1.** Timings and primary current characteristics of Hi-PF QR flyback converters assuming that current in the turn-on instant of power switch M is zero (*tON* = *Tneg*).


The ZCS assumption is not always true in practice, because the control circuit that initiates a new switching cycle upon detecting the transformer's demagnetization (ZCD circuit) is not always realized in such a way that the power switch M can be always turned on in the exact instant when the ringing current after demagnetization zeroes.

### *3.1. Effects of a Nonzero Current at the Turn-on Instant of the Power Switch M*

A nonzero current at the turn-on instant will alter the *Qpos* and/or the *Qneg* contribution in a switching cycle and this, in turn, will have an impact on the input current shape and, ultimately, on its THD. Both the quantitative and the qualitative effects of this impact have not been analyzed in the existing literature and will be addressed in this section.

The impact is different depending on whether one analyzes the open-loop operation (i.e., with assigned input and output voltages and a profile of the peak primary current *IpPK*(θ) having a fixed amplitude) or the closed-loop operation. In this second case, the input voltage is assigned but the amplitude of the profile of the peak primary current *IpPK*(θ) is determined by the control loop to deliver the average power demanded by the load in a line cycle with a regulated output voltage or current.

The analysis carried out in this section refers to the open-loop operation.

In the following analysis, the definitions of the quantities considered in Table 1 do not change. To distinguish the quantities related to the *tON* = *Tneg* case from those related to the *tON* = *Tneg* case, the former ones will have an "\*" superscript.

It is worth reminding that instantaneous values of all time-varying quantities are considered a function of the phase angle θ = 2π*fL t* when considering their evolution on a line cycle time scale. Instantaneous values of those quantities that vary within a switching cycle as well are a function of both phase angle and time, being intended that time extends over a single switching cycle, during which the phase angle can be considered constant. To simplify the notation, these dependances will not be explicitly indicated.

We will consider two fundamental cases.

• Case I: 0 < *tON* < *Tneg* (refer to Figure 5)

In this hypothesis, the initial current *Ip*(*tON*) is negative and *TON* > *Tpos*. *Qneg* may be affected by the *tON* value; considering an open-loop operation, *Qpos* and *Tpos* will not be affected, in closed-loop operation they will be: a different *Qneg* value due to a different *tON* value needs to be compensated by an opposite change in *Qpos* so that the input current to the converter is such that the average power delivered to the load in a line cycle does not change. *Tpos* will need to change accordingly.

**Figure 5.** Close-up of primary current with *tON* < *Tneg*. Dashed lines, which refer to the case *tON* = *Tneg*, are shown for reference. The diagonally striped area marks the interval where *T\*neg* and *Q\*neg* are not affected by *tON* position (subsubcase I a2).

We need to distinguish two subcases.


We need to distinguish two further subdivisions.


In this case, the sinusoidal portion of the negative current will be truncated by the turn-on of the power switch before the drain voltage touches zero. Turn-on will not be exactly ZVS (Zero-voltage switching). The duration of the negative portion of the primary current will be reduced (*T\*neg* < *Tneg*) and so will be *Q\*neg*.


In this case, the turn-on of the power switch occurs while the primary current, though negative, is already ramping up linearly as if the power switch were turned on at *t* = *Tz*. Turn-on will still be exactly ZVS. Both *T\*neg* and *Q\*neg* will be unaffected (*T\*neg* = *Tneg*, *Q\*neg* = *Qneg*).


The situation becomes similar to that when *VIN* ≤ *VR*: current is sinusoidal until *t* = *tON*, after that it is a linear ramp. Turn-on will occur before the drain voltage reaches the valley, so valley switching will be lost. Both *T\*neg* and *Q\*neg* will be reduced.

The results of this analysis are summarized in Table 2, where *Tz* is that defined in Table 1 (it is unaffected by *tON* and is not shown).

The diagrams in Figure 6 show how *T\*neg* and *Q\*neg* vary as a function of the ratio *VIN*/*VR* for different values of *tON*. Values are normalized to those for *VIN* > *VR* (*Tr*/2 and 2 *VR Cds* respectively). The diagrams in Figure 7 show how *T\*neg* and *Q\*neg* vary with *tON* for different values of the ratio *VIN*/*VR*. Values are normalized in the same manner.

• Case II: *Tneg < tON* < *Tneg* + *Tr*/2 (refer to Figure 8)

In this case, the initial current *Ip*(*tON*) is positive and *TON* < *Tpos*. *Qpos* and *Tpos* will be affected, whereas *Qneg* and *Tneg* will not: *Qneg* depends on voltages only and not on the power circulating in the converter. Regardless of whether *VIN* is greater or less than *VR*, turn-on occurs on the positive wave of the drain voltage ringing and with the positive current if *tON* < *Tr*. However, we need to distinguish two subcases.


In this case, due to the charge not transferred from *Lp* to *Cds* while the drain voltage is clamped in the interval *Tz* ≤ *t* ≤ *Tneg*, the ringing occurring after *Tneg* has a peak amplitude reduced from *VR* to *VIN* in voltage and from *VR YL* to *VIN YL* in current:

$$\begin{aligned} V\_{ds}(t) &= V\_{IN} \left[ 1 - \cos \left( 2\pi \frac{t - T\_{\text{avg}}}{T\_r} \right) \right] \\ I\_p(t) &= Y\_L V\_{IN} \sin \left( 2\pi \frac{t - T\_{\text{avg}}}{T\_r} \right) \end{aligned} \tag{7}$$

**Table 2.** Timings and input current characteristics of Hi-PF QR flyback converters assuming current in the turn-on instant of power switch M is negative (*tON* < *Tneg*).


**Figure 6.** Normalized values of *T\*neg* and *Q\*neg* as a function of the *VIN*/*VR* ratio for different turn-on instants *tON*, with *tON* ≤ *Tneg*.

**Figure 7.** Normalized values of *T\*neg* and *Q\*neg* as a function of the turn-on instant *tON*, with *tON* ≤ *Tneg*, for different *VIN*/*VR* ratios.

**Figure 8.** Close-up of primary current with *tON* > *Tneg*. Dashed lines, which refer to the case *tON* = *Tneg*, are shown for reference. Dotted lines show primary current ringing continuation.

#### -Subcase II(b): *VIN* ≤ *VR*.

In this case, the exchange of electric charge between *Lp* and *Cds* is unaffected, and there is no change in the ringing occurring after *Tr*/2.

The results of this analysis are summarized in Table 3, where *Tz* and *Tzz* (which are those defined in Table 1) are not shown because not relevant and unaffected by *tON*.

The diagrams in Figure 9 show how *T\*pos* and *Q\*pos* vary as a function of the ratio *VIN*/*VR* for different values of *tON*. Values are normalized to those of *Tpos* and *Qpos* when *tON* = *Tneg*. The diagrams in Figure 10 show how *T\*neg* and *Q\*neg* vary with *tON* for different values of the ratio *VIN*/*VR*. Values are normalized in the same manner.

**Figure 9.** Normalized values of *T\*pos* and *Q\*pos* as a function of the *VIN*/*VR* ratio for different turn-on instants *tON*, with *tON* ≥ *Tneg*.

**Figure 10.** Normalized values of *T\*pos* and *Q\*pos* as a function of the turn-on instant *tON*, with *tON* ≥ *Tneg*, for different *VIN/VR* ratios.

**Table 3.** Timings and input current characteristics of Hi-PF QR flyback converters assuming current in the turn-on instant of power switch M is positive (*tON* > *Tneg*).


### *3.2. Comments on Previous Analysis*

It is worth reminding that this analysis contains simplifications that impact the quantitative aspect. Especially noteworthy is the one concerning the *Coss* of the power switch M, a strongly nonlinear capacitance that in the latest MOSFET generations increases dramatically (a hundred times or more) when the drain-source voltage falls below few ten volts. This capacitance has been considered constant or, at least, not significantly impacting the overall *Cds*.

Another simplification is that the ringing has been assumed to be undamped. Actually, the ringing current flowing through the primary winding of the transformer encounters the ac resistance of that winding at the ringing frequency (typically, some hundred kHz). Because of skin and proximity effects, and depending on the construction of the transformer, its value may be even significantly high and provide significant damping of the ringing. In the context of the present analysis, the most significant consequence of the damping is that the amplitude of the ringing, even considering the first valley, will be lower than *VR*. Therefore, the valley of the drain voltage will touch zero at an input voltage lower than *VR*.

Another simplification concerns what happens when the ac line voltage *VAC*(θ) approaches zero.

The present analysis points out the existence of a time interval around zero crossings of *VAC*(θ) (often termed dead zone) where the input current to the converter *IAC*(θ) = 0, although *VAC*(θ) = 0, originating the so-called crossover distortion. This happens when the peak current in a switching cycle becomes so small that *Qpos* < |*Qneg*| and the rectified input current *IIN*(θ) becomes negative. The physical interpretation of being *IIN*(θ) < 0 and

*IAC*(θ) = 0 around the zero-crossings is: when *IIN*(θ) < 0 it actually charges back the input capacitor (*Cin* in Figure 1) so that *VIN*(θ) becomes larger than *VAC*(θ), the input bridge is reverse-biased and, consequently, *IAC*(θ) is zero.

The situation is even more complicated because of the residual voltage across the input capacitance *Cin* and the possible interactions with the input EMI filter due to the drastic reduction of the switching frequency that occurs near the zero-crossings. Additionally, there is another dead zone around the line voltage zero-crossings where no primary-tosecondary energy transfer takes place that interacts with that determined by the average inductor current *IIN*(θ) being negative. All these aspects are expanded in [7].

For the completeness of the analysis, it is worth mentioning another minor effect that makes the task of an accurate description of the behavior near the zero crossings even tougher.

As reported in [7], the previously mentioned region around the line voltage zero crossings where there is no input-to-output energy transfer occurs when the inductor peak current is so low that the energy stored in *Lp* during the on-time *TON* of the power switch M is not enough to charge *Cds* up to *VIN*(θ) + *VR* when the power switch turns off.

As illustrated in Figure 11, the drain waveform is a sinusoidal arc going from zero to a peak value *VY* < *VR* and then back to zero. The situation is significantly different as compared to that considered during the previous analysis and shown in Figure 4: *VY* is not large enough for the voltage on the secondary side of the transformer to forward bias the rectifier and have current circulating, thus the *TFW* interval disappears and no energy is delivered to the output.

**Figure 11.** Simplified equivalent circuit after power switch turn-off in the no input-to-output energy transfer region around the line voltage zero-crossings and relevant key waveforms.

Assuming as *t* = 0 the instant when the drain voltage peaks, the interval *Tz* needed for it to fall to zero is essentially the same as that needed to reach the peak after turn-off. Both the rise and fall times are then in the range of *Tr*/4. The rise time of the drain voltage, which has always been assumed to be negligible, in this case, is not so short but the duration of the switching period is largely dominated by the interval *Tzz* + *Tpos* because of the very low input voltage, then its effect on the switching frequency can still be neglected.

The equations shown in Figure 2 and that have been used to derive those in Tables 1–3 are no longer valid and should be modified by substituting *VR* with *VY*.

### *3.3. Quantitative Aspects of a Nonzero Current at the Turn-on Instant of the Power Switch M*

To provide a quantitative idea of the impact of a nonzero current at the turn-on instant in the closed-loop operation, the analysis done so far will be applied to a pair of exemplary cases.

The first exemplary case is a Hi-PF QR flyback converter whose main electrical specification is detailed in Table 4 and that is controlled with the traditional QR method, where the peak primary current is enveloped by a rectified sinusoid as expressed by (2).

**Table 4.** Main characteristics of Hi-PF QR flyback converter with the QR control method used as a first reference.


This control method provides a rectified input current to the converter, *IIN*(θ), which is given by the sequence of *Ip* along each line half-cycle, that is expressed by:

$$I\_{IN}(\theta) = \begin{cases} \frac{1}{2} I\_{PPK} \frac{T\_{\rm pw}(\theta)}{T(\theta)} \sin \theta - \frac{2}{T(\theta)} V\_R \mathbb{C}\_{ds} & V\_{IN}(\theta) > V\_R\\ \frac{1}{2} I\_{PPK} \frac{T\_{\rm pw}(\theta)}{T(\theta)} \sin \theta - \frac{1}{2T(\theta)} \frac{[V\_{IN}(\theta) + V\_R]^2}{V\_{IN}(\theta)} \mathbb{C}\_{ds} & V\_{IN}(\theta) \le V\_R \end{cases} \tag{8}$$

In this converter the turn-on instant *tON* has been swept in the interval 0 ≤ *tON* ≤ *Tr*, considering operation at low line voltage (115 Vac) and high line voltage (230 Vac) at full load. The results are shown in the diagram in Figure 12.

**Figure 12.** Total harmonic distortion (THD) of the input current *IAC*(θ) of the converter specified in Table 4, controlled with the QR control method, upon varying the turn-on instant *tON* of the power switch in the interval 0 ≤ *tON* ≤ *Tr*.

Notice that in a large region around *tON* = *Tr*/2, the one of greater practical interest, the distortion is nearly independent of *tON*, especially at the low line. Based on this observation, it is possible to conclude that with the QR control method the distortion of the input current is essentially insensitive to the way the ZCD circuit is realized and to the statistical spread of its parameters.

The second exemplary case is a Hi-PF QR flyback converter whose main electrical specification is detailed in Table 5 and that is controlled with the EQR method, where the envelope of the peak primary current is given by (5).

**Table 5.** Main characteristics of Hi-PF QR flyback converter with the EQR control method used as a second reference.


This control method provides a rectified input current to the converter, *IIN*(θ), expressed by:

$$I\_{IN}(\theta) = \begin{cases} \frac{1}{2} I\_{PPK} \frac{T\_{\rm pro}(\theta)}{T\_{\rm ON}(\theta)} \sin \theta - \frac{2}{T(\theta)} V\_R \mathbb{C}\_{ds} & V\_{IN}(\theta) > V\_R\\ \frac{1}{2} I\_{PPK} \frac{T\_{\rm prov}(\theta)}{T\_{\rm ON}(\theta)} \sin \theta - \frac{1}{2T(\theta)} \frac{\left[V\_{IN}(\theta) + V\_R\right]^2}{V\_{IN}(\theta)} \mathbb{C}\_{ds} & V\_{IN}(\theta) \le V\_R \end{cases} \tag{9}$$

In this converter too the turn-on instant *tON* has been swept in the interval 0 ≤ *tON* ≤ *Tr* considering operation at 115 Vac and 230 Vac at full load. The results are shown in the diagram in Figure 13.

**Figure 13.** Total harmonic distortion (THD) of the input current *IAC*(θ) of the converter specified in Table 5, controlled with the EQR control method, upon varying the turn-on instant *tON* of the power switch in the interval 0 ≤ *tON* ≤ *Tr*.

Notice that in this case in the region around *tON* = *Tr*/2, at the low line the distortion is a little dependent on *tON*, whereas at the high line the dependence is significantly higher. In both cases, the distortion becomes smaller as *tON* is delayed. Based on this observation, it is possible to conclude that with the EQR control method the distortion of the input current, though lower as compared to the QR method, is more sensitive to *tON* and, then, to the way the ZCD circuit is realized and to the statistical spread of its parameters.

Notice that in the positive terms in (5), the ratio *Tpos*(θ)/*TON*(θ) expresses the effect that the current in the turn-on instant of the power switch M has on the shape of the input current. In fact, in the case *Tpos* (θ) = *TON* (θ), since in general, they are not proportional to one another, the positive term contains a distortion term that adds up to the distortion caused by the negative one. This explains why the EQR method is more sensitive to *tON* and to the implementation of the ZCD circuit.

### *3.4. Notes on the THD Calculation Method*

The THD of *IAC*(θ) vs. *tON* plots of Figures 12 and 13 have been derived determining the expressions of *IIN*(θ), Equation (8) for the QR method and Equation (9) for the EQR method, and then extending them over the interval (0, 2π). In these equations *IPPK*, which is related to the power delivered by the converter, is the unknown parameter, *tON* is the independent variable, the others are those in Tables 2 and 3.

Notice that the quantity *IPPK* in these tables is given by Equation (2) for the QR method and Equation (5) for the EQR method. To prevent the singularity when *VIN* = 0 in the expressions related to *VIN* ≤ *VR* where *VIN* appears at the denominator, a voltage drop *VF* = 0.7 V across the body diode of the power switch has been assumed. Hence, in all formulas in Table 2 where *VIN* ≤ *VR* it is actually *VIN* = *VPK* sin θ + *VF*.

In closed-loop operation, for a given *VAC*, the average value of the product *VIN* (θ)·*IIN* (θ) over a line half-cycle (i.e., the integral of the product in (0, π) divided by π) must be equal to the dc input power to the converter *Pin* = *Vout Iout*/h. This equation is solved by iteration for the unknown parameter *IPPK* with a given value of *tON*, thus completely defining Equations (8) and (9).

As previously said, the Fourier coefficients (i.e., the peak amplitudes of each harmonic) of *IAC*(θ) are computed by extending Equations (8) and (9) over the interval (0, 2π). Being *IAC*(θ) an odd function, there are only sine terms. Because of its rotational symmetry (*IAC*(θ + p) = - *IAC*(θ)) there are only odd harmonics.

The THD is computed as the ratio between the square root of the sum of squares of the peak amplitudes of the higher order harmonics (from 3rd up to 39th) and the peak amplitude of the fundamental one.

Finally, all these calculations are repeated sweeping *tON* from 0 to *Tr*. This has been done with the help of Mathcad®, engineering math software.

### **4. Impact of ZCD Circuit Operation on Input Current Shaping**

The impact of a nonzero current as the power switch M turns on, causing *Tpos*(θ) = *TON*(θ), will be now analyzed more in detail with reference to some typical implementations of the ZCD circuit that determines the turn-on instant *tON* of the power switch M. Some results, referred to the exemplary converter specified in Table 5 and controlled with the EQR method will be presented to provide the reader with some quantitative information. No investigation will be done on the converter specified in Table 4 and controlled with the QR method, since the previous analysis has shown its substantial insensitivity to the position of *tON* and, then, to the operation of the ZCD circuit.

The calculation method used to obtain the results that are shown in the following sections is the same as that described in Section 3.4.

### *4.1. Optimal ZCD Circuit*

An optimal ZCD circuit ensures that the turn-on of the power switch always occurs with zero initial current (*tON* = *Tneg*), so that it is always *Tpos* = *TON* and, as stated by Equation (9), no distortion is introduced in the positive terms all over the *VIN* range:

$$I\_{IN}(\theta) = \begin{cases} \frac{1}{2} I\_{PPK} \sin \theta - \frac{2}{T(\theta)} V\_R \mathbb{C}\_{ds} & V\_{IN}(\theta) > V\_R \\\ \frac{1}{2} I\_{PPK} \sin \theta - \frac{1}{2T(\theta)} \frac{\left[V\_{IN}(\theta) + V\_R\right]^2}{V\_{IN}(\theta)} \mathbb{C}\_{ds} & V\_{IN}(\theta) \le V\_R \end{cases} \tag{10}$$

The principle circuit shown in Figure 14 along with its key waveforms may fulfill this task. The auxiliary winding *Laux* is coupled to the primary winding of the transformer in such a way that its voltage *Vaux* and the drain voltage *Vds* are in-phase. More specifically, *Vaux* is a replica of the drain voltage *Vds* scaled down by the turn ratio and centered on zero.

**Figure 14.** Principle schematic of an optimal ZCD circuit and relevant key waveforms.

*Vaux*, which is negative during the on-time of the power switch M, is positive during the off-time, as long as the current circulates on the secondary winding; when this current zeroes (demagnetization), *Vds* starts ringing with a negative-going sinusoidal arc and the same falling arc appears on *Vaux*.

*Laux* is coupled to the ZCD pin of the control IC via the resistor *Rzcd*: since the voltage *Vzcd* on the ZCD pin is top and bottom clamped, *Rzcd* limits the current sunk/sourced by the clamps.

A comparator (ZCD comparator) with the noninverting input referred to a slightly positive threshold *Vth* (e.g., 100 mV) senses *Vzcd* on its inverting input. Another comparator (CS comparator), whose inverting input is referred to as a negative threshold -*Vth*<sup>1</sup> very close to zero (e.g., −20 mV) senses the voltage on the current sense input *VCS* on its noninverting input. The PWM latch is edge-sensitive and its set input S is driven by the AND gate that receives the outputs of the two comparators. With this circuit arrangement, the output Q of the PWM latch goes high causing the power switch M to turn on both conditions, *Vzcd* < *Vth* and *VCS* > -*Vth*1, are met.

When the secondary current zeroes, *Vaux* collapses and, as it goes below the upper clamp value, also *Vzcd* starts collapsing. As *Vzcd* falls below *Vth* the output of the ZCD comparator goes high. Being *Vth* close to zero, this occurs about *Tr*/4 after the secondary current zeroes. The primary current *Ip* is ringing too (in quadrature to *Vaux*), so in that instant, *Ip* is close to its negative peak, it is *VCS* < -*Vth*<sup>1</sup> and the output of the CS comparator is low. As long as *Ip* is negative and it is *VCS* < -*Vth*1, the output of the CS comparator stays low. Only when *VCS* exceeds -*Vth*<sup>1</sup> (either because of ringing when *VIN* > *VR*, or because *Ip* is ramping up linearly when *VIN* ≤ *VR*), the output of the CS comparator and the output of the AND gate go high too. The PWM latch is then set, its output Q goes high and turns on the gate driver and the power switch M, starting a new switching cycle.

The diagrams of Figure 15 provide some exemplary quantitative results for the converter specified in Table 5. The diagrams on the left-hand side show the shape of the input current to the converter *IAC*(θ) (in red) along with a black sinusoid for reference and, below, its harmonic contents at full load and *Vac* = 115 V. The diagrams on the right-hand side show the same at *Vac* = 230 V.

**Figure 15.** Optimal ZCD circuit: input current shape (**a**,**b**) and its harmonic content (**c**,**d**) for converter specified in Table 5 at 115 *Vac* (**a**,**c**) and 230 *Vac* (**b**,**d**).

The horizontal red dotted lines in the upper diagrams mark the points where |*VIN*| = *VR*, i.e., the transition from the region (|*VIN*| > *VR*), where the negative charge *Qneg* depends on *VR* only, to the region (|*VIN*| < *VR*) of *IIN*(θ) and then, of *IAC*(θ) where *Qneg* depends on *VIN* too.

Note that the shape of *IAC*(θ) shows the crossover distortion, highlighted by the blue circle, i.e., the dead zone corresponding to a negative *IIN*(θ) around the zero crossings of the instantaneous line voltage *VAC*(θ), which makes *IAC*(θ) = 0, although *VAC*(θ) = 0 as previously explained.

The dead zone in *IAC*(θ) predicted by (10) lies in the interval −3.2◦ < θ < 3.2◦ at 115 Vac and in the interval −5.8◦ < θ < 5.8◦ at 230 Vac. As discussed in Section 3.2, the accuracy of the model Equation (10) around line voltage zero-crossings is impaired by the existence of other distortion causes (above all else the input capacitor *Cin*). Therefore, these data on the dead zone amplitude are ballpark figures that can be used only for comparison with other ZCD circuits by isolating their contribution alone.

### *4.2. Differentiator-Based ZCD Circuit*

The principle schematic of this circuit and its key waveforms are shown in Figure 16. Both the external circuit connected to the ZCD pin and its operation are exactly the same as with the optimal ZCD circuit, except that in this case the pin is directly connected to *Laux*.

Internally, the voltage on the ZCD pin is unclamped; as to the differentiator, it is assumed that it is *Rd Cd* << *Tr*/2. The current *Id* (and, then, the voltage *Vd* = *Id Rd*) is zero as long as *Vaux* is on either level and is nonzero when *Vaux* transitions from one level to the other. The voltage *Vd* is sensed by a comparator whose inverting input is referred to a negative threshold -*Vth* close to zero, e.g., −100 mV.

When the secondary current zeroes and the negative-going edge of *Vaux* starts, the voltage *Vd* applied to the noninverting input of the comparator becomes much negative, thus its output goes low. When the negative-going edge ends *Id* zeroes and so does *Vd* too: as it exceeds -*Vth* the output of the comparator has a low-to-high transition. The PWM

latch, edge-sensitive, is then set, its output *Q* goes high turning on the gate driver and the power switch M and starting a new switching cycle.

**Figure 16.** Principle schematic of a differentiator-based ZCD circuit and relevant key waveforms.

With this circuit, if *VIN* > *VR* the turn-on of the power switch M occurs on the valley of the *Vds* ringing (*tON* = *Tr*/2, when its derivative is zero): zero derivative means zero ringing currents and, then, zero initial current and *Tpos* = *TON*. No distortion is associated with the corresponding positive term in Equation (9). When *VIN* ≤ *VR* the turn-on is commanded as the drain voltage touches zero, i.e., *tON* = *Tz* given in Table 1 when the ringing current is still negative. In this case, based on Table 2, *TON* is expressed as:

$$T\_{ON} = T\_{pos} + T\_{zz} \tag{11}$$

and (5), neglecting the contribution of the ringing current as previously stated, becomes:

$$I\_{IN}(\theta) = \begin{cases} \frac{1}{2} I\_{PPK} \sin \theta - \frac{2}{T(\theta)} V\_R \mathbb{C}\_{ds} & V\_{IN}(\theta) > V\_R \\\ \frac{1}{2} I\_{PPK} \sin \theta - \frac{1}{2} I\_{PPK} \frac{T\_{\text{ff}}(\theta)}{T\_{\text{ON}}(\theta)} \sin \theta - \frac{1}{2T(\theta)} \frac{[V\_{IN}(\theta) + V\_R]^2}{V\_{IN}(\theta)} \mathbb{C}\_{ds} & V\_{IN}(\theta) \le V\_R \end{cases} \tag{12}$$

As a conclusion, the differentiator-based ZCD circuit does not introduce any distortion as long as *VIN* > *VR* (condition fulfilled along most of the rectified sinusoid at the high line, e.g., with the European mains); conversely, it introduces a distortion term when *VIN* ≤ *VR*, a condition that is fulfilled along most of the rectified sinusoid at the low line, i.e., with US or Japan mains). The amplitude of this distortion is related to the ratio *Tzz*/*TON* and a Fourier analysis of Equation (12) shows that the distortion term creates a component at the fundamental frequency and odd harmonics, all in phase opposition to the fundamental component.

With reference again to the converter specified in Table 5, the diagrams of Figure 17 provide the same exemplary quantitative results as those shown in Figure 15 with the optimal ZCD circuit. Note that the harmonic contents have a distribution not too different from that provided by the optimal ZCD circuit, but with a slightly larger amplitude. This results in a slightly higher THD: +1% at 115 Vac and +1.3% at 230 Vac.

In this case the crossover distortion due to the positive term in Equation (12) becoming smaller than the negative term is slightly wider: the dead zone in *IAC*(θ) occurs in the interval −3.4◦ < θ < 3.4◦ at 115 Vac and in −6.7◦ < θ < 6.7◦ at 230 Vac. The external circuit connected to the ZCD pin and its operation are the same as the optimal ZCD circuit. Internally, the voltage *Vzcd* on the ZCD pin is top and bottom clamped and there is the same ZCD comparator with the noninverting input referred to as a slightly positive threshold *Vth* (e.g., 100 mV) that senses *Vzcd* on its inverting input as seen in the optimal ZCD circuit. The output X of the ZCD comparator goes through a delay block *Td*, ideally tuned to slightly less than *Tr*/4, after that it reaches the set input of the edge-sensitive PWM latch.

**Figure 17.** Differentiator-based ZCD circuit: input current shape (upper) and its harmonic content (lower) for converter specified in Table 1 at 115 Vac (left) and 230 Vac (right).

### *4.3. Comparator-plus-Delay ZCD Circuit*

The principle schematic of this circuit and its key waveforms are shown in Figure 18.

**Figure 18.** Principle schematic of a comparator-plus-delay ZCD circuit and relevant key waveforms.

When the secondary current zeroes, *Vaux* collapses and, as it goes below the upper clamp value, *Vzcd* also starts collapsing. As *Vzcd* falls below *Vth* the output X of the comparator has a low-to-high transition. After a delay *Td* the PWM latch is set, its output *Q* goes high and turns on the gate driver and the power switch M, starting a new switching cycle.

Note that, being *Vth* close to zero, the negative edge is detected about *Tr*/4 after the secondary current zeroes. Note also that the resistor *Rzcd*, along with the parasitic capacitance of the internal clamp plus some external stray contributors (which are anyhow well defined once the layout of the external circuit is defined), form an RC low-pass filter that delays *Vzcd* with respect to *Vaux*. This delay adds up to *Td* and can be fine-tuned by adjusting *Rzcd* (or even adding a small external capacitor between the ZCD pin and ground) so that the overall delay equals *Tr*/2 and it is *tON* = *Tr*/2 both with *VIN* > *VR* and *VIN* ≤ *VR*.

With this circuit, therefore, when *VIN* > *VR* turn-on occurs on the valley of the *Vds* ringing, the initial current is zero, *Tpos* = *TON,* and no distortion is introduced. When *VIN* ≤ *VR* the ringing current at *t* = *Tr*/2 is ramping up linearly but is still negative. In this case, based on Table 2, *TON* is given by:

$$T\_{\rm ON} = T\_{\rm pos} + T\_{\rm nc\lg} - \frac{T\_r}{2} \tag{13}$$

and (9) becomes:

$$I\_{IN}(\theta) = \begin{cases} \frac{1}{2} I\_{PPK} \sin \theta - \frac{2}{T(\theta)} V\_R \mathbb{C}\_{ds} & V\_{IN}(\theta) > V\_R \\\\ \frac{1}{2} I\_{PPK} \sin \theta - \frac{1}{2} I\_{PPK} \frac{T\_{\text{ref}}(\theta) - \frac{T\_\theta}{T}}{T\_{\text{ON}}(\theta)} \sin \theta - \frac{1}{2T(\theta)} \frac{[V\_{IN}(\theta) + V\_R]^2}{V\_{IN}(\theta)} \mathbb{C}\_{ds} & V\_{IN}(\theta) \le V\_R \end{cases} \tag{14}$$

Once more with reference to the converter specified in Table 5, the diagrams of Figure 19 provide the same results as those shown in Figures 15 and 17, with the comparatorplus-delay ZCD circuit. Note that the harmonic contents is lower in amplitude as compared to that of the differentiator-based ZCD circuit and quite close to that of the optimal ZCD circuit: the THD values are only 0.4% at 115 Vac and 0.3% at 230 Vac larger.

**Figure 19.** Comparator-plus-delay ZCD circuit: input current shape (**a**,**b**) and its harmonic content (**c**,**d**) for converter in Table 1 at 115 Vac (**a**,**c**) and 230 Vac (**b**,**d**).

Compared to the previous case, the dead zone in *IAC*(θ) is slightly narrower at high line: it occurs in the interval −3.4◦ < θ < 3.4◦ at 115 Vac and in −6.2◦ < θ < 6.2◦ at 230 Vac. To summarize:


It is worth noticing that all the three ZCD circuit implementation do not alter the shape of the input current in the region *VIN* > *VR*; their difference in THD performance comes from the different behavior in the *VIN* ≤ *VR* region. A significant portion of this difference is in the amplitude of the dead-zone in *IAC*(θ) that is generated. The diagram of Figure 20 shows how the total amplitude of the dead-zone changes as a function of the parameter *Kv* = *VPK*/*VR* for various implementations of the ZCD circuit.

**Figure 20.** Dead-zone amplitude with various types of ZCD circuit as a function of the *VPK/VR* ratio.

It has been shown that the detrimental effect of the ZCD circuit on the input current shape is caused by a negative current in the turn-on instant of the power switch M that makes *Tpos*(θ) < *TON*(θ). If we artificially delay the turn-on instant beyond *Tr*/2 after demagnetization, the initial current will be positive, thus making *Tpos*(θ) > *TON*(θ). This will create a positive term (increasing with the extra delay) that will partly compensate for the negative term due to the ringing current and is expected to result in a lower THD of the input current. Actually, this is shown in the diagram of Figure 13 and is consistent with the reduction of the dead-zone amplitude and the resulting crossover distortion shown in Figure 20 with an increasing delay.

In conclusion, the comparator-plus-delay ZCD circuit seems to be the best practical choice, due to its fine-tuning capability, good performance, and simplicity. The comparator-plus-delay ZCD circuit might even outperform the optimal ZCD circuit when *Tpos*(θ) > *TON*(θ). Anyway, any improvement in the THD attempted in this way should be traded off against the consequences of a long delay in restarting a new switching cycle: losing exact valley switching (higher turn-on losses and electromagnetic noise) and pushing the operation more deeply into DCM (worsening of current form factor, higher conduction losses).

### **5. Experimental Verifications**

A pair of test benches have been set up to experimentally assess the impact of a nonzero current at turn-on on the THD of the input current to verify the theoretical predictions outlined in Section 4.

The first test bench was based on the reference Hi-PF QR flyback converter specified in Table 4 and whose picture is shown in Figure 21 on the left-hand side. The converter is an old design based on the L6562A, a PFC IC from STMicroelectronics primarily intended for boost-based PFC converters, that implements the QR control method.

The second test bench was based on the reference Hi-PF QR flyback converter specified in Table 5 and whose picture is shown in Figure 21 on the right-hand side. The converter is a newly developed design based on the HVLED007, a PFC IC from STMicroelectronics specific for flyback topology that implements the EQR control method.

The instrumentation used to set up the test benches included an ac source Chroma 61501 and an e-load Chroma 6314A + 63108A set in constant current mode (both converters provide a regulated output voltage); voltage waveforms acquisitions and time measurements were done with the oscilloscope Tektronix DPO 7054C; the THD was measured with a power meter Yokogawa WT210.

**Figure 21.** 35 W Hi-PF QR flyback controlled with QR method by the L6562A IC (**a**); 35 W Hi-PF QR flyback controlled with EQR method by the HVLED007 IC (**b**).

Both controllers have a comparator-plus-delay ZCD circuit onboard and in both cases, the delay from the transformer's demagnetization instant to the turn-on instant of the power switch M has been adjusted by acting on the external interface circuit between the auxiliary winding and the ZCD input pin, as shown in Figure 22.

**Figure 22.** External circuits are used to adjust the delay between the transformer's demagnetization instant to turn-on instant of the power switch M. Upper circuit delays turn-on, lower circuit brings it forward.

It is worth reminding that the experimental data will provide the total result of all the concurrent causes of distortion and it is not generally possible to isolate each of them. Additionally, they are interacting with each other, thus a change in one of them may affect the amount of distortion caused by another one in a way that may be either detrimental or ameliorative. The objective is, therefore, to possibly capture a trend.

Experiments have been carried out at full load, where the contribution of other distortion causes (primarily, *Cin*) is expected to be at a minimum, at 115 Vac and 230 Vac.

Figure 23 shows a few key waveforms (drain-source voltage *Vds*, auxiliary winding voltage *Vaux* and the gate-drive output *Vgs*) at the lower and upper ends of the adjustment

range in the converter specified in Table 4 and controlled by the L6562A control IC with the QR method.

**Figure 23.** Key waveforms at the ends of the adjustment range of the turn-on instant *tON* for the converter specified in Table 4 and controlled by the L6562A control IC with the QR method.

The period of the ringing after demagnetization is 1.72 μs, then *Tr*/2 = 860 ns and the explored range (730 ns to 1.16 μs) includes both conditions *tON* < *Tneg* and *tON* > *Tneg* for *VIN* > *VR*.

Figure 24 shows (round markers connected by solid lines) the measured THD values of the input current *IAC*(θ) as a function of different *tON* instants, obtained by varying *Cadj*, at both 115 Vac and 230 Vac and 100% load. For comparison, the plot shows also the corresponding values obtained by calculation (rhomboid markers connected by dotted lines) shown in the plot of Figure 12.

**Figure 24.** Plot of THD of the input current *IAC* for different values of the delay between transformer's demagnetization instant to the turn-on instant *tON* of the power switch M for the converter specified in Table 4 and controlled by the L6562A control IC with the QR method. Theoretical values are shown for reference.

The experimental data confirm the "flat" trend of THD vs. *tON* predicted by the theoretical analysis, even though there is some discrepancy, a sort of offset, in the predicted values. The reasons for this difference have not been investigated but they might be explained by the presence of other distortion causes (e.g., *Cin*, or a negative input offset of the PWM comparator).

Figure 25 shows the same key waveforms (*Vds*, *Vaux*, and *Vgs*) as in Figure 23 at the lower and upper ends of the adjustment range in the converter specified in Table 5 and controlled by the HVLED007 control IC with the EQR method.

**Figure 25.** Key waveforms at the ends of the adjustment range of the turn-on instant *tON* for the converter specified in Table 5 and controlled by the HVLED007 control IC with the EQR method.

The period of the ringing after demagnetization is 2.07 μs, then *Tr*/2 = 1.035 μs and the explored range (550 ns to 1.22 μs) includes both conditions *tON* < *Tneg* and *tON* > *Tneg* for *VIN* > *VR*.

Figure 26 shows (round markers connected by solid lines) the measured THD values of the input current *IAC*(θ) as a function of different *tON* instants, obtained by varying *Cadj*, at both 115 Vac and 230 Vac and 100% load. For comparison, the plot shows also the corresponding values obtained by calculation (rhomboid markers connected by dotted lines) reported in the plot of Figure 13.

**Figure 26.** Plot of THD of the input current *IAC* for different values of the delay between transformer's demagnetization instant to the turn-on instant *tON* of the power switch M for the converter specified in Table 5 and controlled by the HVLED007 control IC with the EQR method. Theoretical values are shown for reference.

The experimental data at low line are very well aligned to those calculated, except for the longest delay where the actual THD trend and the predicted one seem to diverge. At the high line, surprisingly, the measured values are lower than the calculated ones. However, the trend is the same except for the shortest delay, where the two values are much closer to one another. This difference is compatible with a positive offset of the PWM comparator, which increases the positive contribution of the per-cycle charge *Qpos* and then, tends to reduce the THD.

To complete the experimental analysis, it is worth measuring the impact of *tON* on converter's efficiency (h = *Pout*/*Pin*). With valley switching (*tON* = *Tr*/2 when *VIN* > *VR*) the per-cycle energy lost at turn-on is at a minimum and increases as *tON* moves in either direction. However, with a shorter *tON* the switching frequency increases slightly (so do capacitive and switching losses) but operation gets closer to transition and the current form factor improves slightly (so conduction losses are a bit lower). With a longer *tON* there are

the opposite changes in power losses. Additionally, a positive initial current causes a small amount of switching losses at turn-on, as if the converter worked in slight CCM.

Figure 27 shows the measured efficiency values of the converter specified in Table 4 and controlled by the L6562A control IC with the QR method as a function of different *tON* instants, the same as those considered in the plot of Figure 24, at 115 Vac and 230 Vac, 100% and 50% load.

**Figure 27.** Plot of the measured efficiency for different values of the delay between transformer's demagnetization instant to the turn-on instant *tON* of the power switch M for the converter specified in Table 4 and controlled by the L6562A control IC with the QR method.

Figure 28 shows the measured efficiency values of the converter specified in Table 5 and controlled by the HVLED007 control IC with the EQR method as a function of different *tON* instants, the same as those considered in the plot of Figure 26, at 115 Vac and 230 Vac, 100% and 50% load.

**Figure 28.** Plot of the measured efficiency for different values of the delay between transformer's demagnetization instant to the turn-on instant *tON* of the power switch M for the converter specified in Table 5 and controlled by the HVLED007 control IC with the EQR method.

In both cases it is possible to observe that the efficiency at low line is essentially insensitive to *tON*, which is a benign characteristic: since at low line the full load efficiency is at a minimum, i.e., power losses are at a maximum, the thermal design of the converter will be unaffected by the ZCD circuit, its setting, and its tolerances. This makes sense since under these conditions, conduction losses dominate.

At high line, where capacitive and switching losses dominate, the efficiency has a peak in the neighborhood of *tON* = *Tr*/2, meaning that capacitive losses are actually dominant. At 50% load this trend becomes more visible at low line as well.

These observations suggest a few system-level design guidelines. In converters controlled with the QR method, since *tON* has essentially no impact on the THD of the input current, it makes sense to set the ZCD circuit to target *tON* = *Tr*/2 to optimize their efficiency. In converters controlled with the EQR method one can aim to minimize the THD of the input current by setting the ZCD circuit to target *tON* > *Tr*/2 with no impact on the thermal design. However, by doing so the drop in efficiency at high line and/or lighter load will be more pronounced. This fact should be kept in mind in designs where the electrical specification sets efficiency targets at high line and/or light load as well.

### **6. Conclusions**

Hi-PF QR Flyback is the preferred converter different application thanks to the related high benefit/cost ratio. Although, one can implement an optimal control there are some inherent causes of distortion due to the nonideality of the components. In this work, the distortion due to the actual ZCD circuit has been qualitatively and quantitatively investigated. Moreover, a comparison among three ZCD has been performed. An optimal ZCD circuit does not negatively affect the input current but requires much silicon for implementing the control IC. A differentiator-based ZCD is the worst in terms of THD and, similarly to the previous case, it is silicon consuming. The comparator-plus-delay ZCD circuit enables the best trade-off between performance (only slightly worse than the optimal ZCD circuit) and silicon consumption (the lowest one). Two test benches have been used to experimentally assess the impact of a nonzero current at turn-on on the THD of the input current and verify the aforesaid theoretical predictions, finding a good agreement especially as far as the trend is concerned. The impact of a nonzero current at turn-on on efficiency has been assessed too.

As a conclusion, it is possible to state that the impact of the ZCD circuit on the THD of the input current in Hi-PF QR flyback converters is essentially negligible with the traditional QR method and low with the enhanced QR method. In other words, the detection method, as well as the quality and the performance of the semiconductor components utilized for the ZCD circuit, only slightly affect the THD of the input current or the efficiency of the converter. Therefore, utilizing more sophisticated and/or costly detection circuits does not necessarily provide significant improvement. Rather, it appears that the low-cost comparator-plus-delay ZCD circuit in use in the control ICs considered for the experiments is all in all the best choice.

The experiments have shown also that with the traditional QR method it is possible to set the comparator-plus-delay ZCD circuit to target the maximum conversion efficiency with no impact on the THD of the input current by setting *tON* = *Tr*/2. With the enhanced QR method it is possible to have a slight improvement of the THD by setting the ZCD circuit so as to have *tON* > *Tr*/2, with no penalty on the thermal design but with a higher deterioration rate of the efficiency at high line and/or light load.

**Author Contributions:** Writing-review and editing, C.A., G.G., S.A.R., G.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** The authors appreciate the help of Gianluca De Grandis from STMicroelectronics' Industrial and Power Conversion Division Application Laboratory for setting up the bench experiments.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


### *Article* **Analysis of the Usefulness Range of the Averaged Electrothermal Model of a Diode–Transistor Switch to Compute the Characteristics of the Boost Converter**

**Paweł Górecki \* and Krzysztof Górecki**

Department of Marine Electronics, Gdynia Maritime University, Morska 83, 81-225 Gdynia, Poland; k.gorecki@we.umg.edu.pl

**\*** Correspondence: p.gorecki@we.umg.edu.pl

**Abstract:** In the design of modern power electronics converters, especially DC-DC converters, circuitlevel computer simulations play an important role. This article analyses the accuracy of computations of the boost converter characteristics in the steady state using an electrothermal averaged model of a diode–transistor switch containing an Insulated Gate Bipolar Transistor (IGBT) and a rapid switching diode. This model has a form of a subcircuit for SPICE (Simulation Program with Integrated Circuit Emphasis). The influence of such factors as the switching frequency of the transistor, the duty cycle of the signal controlling the transistor, the input voltage, and the output current of the boost converter on the accuracy of computing the converter output voltage and junction temperature of the IGBT and the diode were analysed. The correctness of the computation results was verified experimentally. Based on the performed computations and measurements, the usefulness range of the model under consideration was determined, and a method of solving selected problems limiting the accuracy of computations of the characteristics of this converter was proposed.

**Keywords:** DC-DC converter; IGBT; averaged model; electrothermal model; SPICE; power electronics

### **1. Introduction**

DC-DC converters [1–3] are commonly used to supply power electronics devices. One of the most popular types of these converters is a boost converter. This converter allows obtaining the output voltage higher than the input voltage while maintaining high conversion efficiency [1–3]. The diagram of the considered converter is shown in Figure 1.

**Figure 1.** Diagram of a boost converter.

At the designing stage of all electronic systems, including DC-DC converters, computer simulations are necessary [1,4,5]. One of the most popular simulation programs used in electronics is SPICE (Simulation Program with Integrated Circuit Emphasis) [4,6]. One of its greatest advantages, compared to other popular simulation environments [7], is the ability to easily implement any compact model of an electronic component. Unfortunately, the models included in the SPICE program are isothermal, i.e., they do not

**Citation:** Górecki, P.; Górecki, K. Analysis of the Usefulness Range of the Averaged Electrothermal Model of a Diode–Transistor Switch to Compute the Characteristics of the Boost Converter. *Energies* **2021**, *14*, 154. https://doi.org/10.3390/en 14010154


Received: 21 November 2020 Accepted: 25 December 2020 Published: 30 December 2020

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**Copyright:** © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

take into account thermal phenomena. In these models, the junction temperature of the component is constant and does not depend on the power dissipated in it. In order to take into account thermal phenomena in computations, the SPICE program formulates models called electrothermal in the form of subcircuits for this program. The second significant disadvantage of the models built into the SPICE program is their limited accuracy, resulting from the simplified modelling of some important physical phenomena occurring in the component, which for the Insulated Gate Bipolar Transistor (IGBT) was presented, among others, in the paper [8].

The methods of estimating the internal temperatures of semiconductor devices using the model-order reduction techniques are described in the paper [9]. In turn, the methods of behavioural electrothermal modelling of power devices are described in the paper [10], whereas the methods of electrothermal simulations of switch-mode power converters are considered in the paper [11].

Performing the transient analysis of DC-DC converters in SPICE using the built-in models of electronic components is time-consuming. As it results from the paper [9], the time required to perform the computations to an electrically steady state is equal to even 24 h. From the engineering point of view, this is an unacceptably long time. Therefore, for many years, scientists have been conducting research on new methods of analysis that will allow reducing this time to an acceptable value [10–16]. These methods consist of modifying the classic method of transient analyses of electronic networks [10,11,13]. They use special algorithms to predict values of voltages and currents at the steady state.

Yet, another way is to use the method of a DC analysis with the averaged models of semiconductor devices or the whole electronic systems [12–14,16,17]. Using this method, it is possible to achieve a significant reduction in the computation time while maintaining the accuracy of computations of static characteristics.

One of such methods is a method using the averaged model of the diode–transistor switch [12,16,17], which is included in each single-inductor DC-DC converter, e.g., a boost converter, the diagram of which is shown in Figure 1. In such a model, the observation is used that at operation of the converter, the diode and the transistor contained in it conduct the current alternately, and for each of these devices associated with subcircuits, the equations describing the average values of voltages and currents of the converter in the steady state are formulated [3,17]. The following assumptions are made when formulating the equations constituting the average models used in the analysis of DC-DC converters:


The equations of the model are obtained by equating to zero the dependences describing the average values of voltage on inductors and the average values of the capacitor currents occurring in the modelled network.

Averaged models of the diode–transistor switch have been described in the literature for many years, and the results of computations performed using such models are described for different DC-DC converters [3,12,17–26]. However, until recently, such models were formulated only for converters containing ideal switches [3,17–22] or Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) [12,23–26], although IGBTs are not less popular in this application [27–30]. It is worth noting that when using models of ideal switches, it is impossible to compute the junction temperature of the diode and the transistor operating in the DC-DC converter. Meanwhile, the information about the values of these temperatures is important for the designer of the system and it allows verifying the correctness of the design. A diode–transistor switch with an IGBT requires a different approach than for MOSFET, e.g., for modelling the output characteristics, which results from their different shapes.

The main advantage of the averaged electrothermal model of a diode–transistor switch is short time of computations, which typically does not exceed 0.1 s. Nonetheless, this kind of model has some drawbacks. These drawbacks include neglecting dynamic effects in the thermal behaviour, impossibility of monitoring voltage on the transistor gate to observe a possible dielectric breakdown, and omitting the parasitic capacitances of semiconductor devices. Therefore, the averaged models may be useful to designers who need a fast and accurate estimation of the converter characteristics and verification that the semiconductor devices operate within their safe operating area.

The papers [31,32] propose a model of a diode–transistor switch for the analysis of DC-DC converters containing an IGBT. The model presented in [31] is a simplified model. In this model, a simplified method of describing the output characteristics of the transistor was used, and the influence of thermal phenomena is not taken into account. The main disadvantages of the model from [31] were removed in its next version, which are presented in [32]. However, this model does not take into account some important physical phenomena that may significantly affect the accuracy of computations using this model. The correctness of the cited model was verified only in a limited range of load current changes and at one value of the control signal frequency equal to 10 kHz.

This article analyses the influence of the accuracy of selected factors on the accuracy of the computations of the boost converter characteristics made with the use of the model from [32] under various operating conditions. Section 2 presents the model under consideration, Section 3 describes the measurement system used to verify the correctness of this model. Furthermore, in Section 4, the computed and measured characteristics of the boost converter in a wide range of changes in the load current and frequency of the control signal are presented. We also comment on the reasons for the discrepancies between the results of computations and measurements. A method of reducing these discrepancies is proposed, and their effectiveness is demonstrated in practice.

### **2. Considered Model**

As it was mentioned above, in order to compute the DC characteristics of DC-DC converters, the averaged electrothermal models of a diode–transistor switch can be effectively used. The considered electrothermal model of the diode–transistor switch proposed in [32] is based on the known concept, which was previously presented for the MOSFET and the ideal lossless switch described, among others, in the papers [16,24]. This model allows determining the DC characteristics of any DC-DC converter containing a diode–transistor switch and junction temperature of the semiconductor devices contained therein. The diagram of this switch is shown in Figure 2.

**Figure 2.** Diagram of a diode–transistor switch with the IGBT and the diode.

The network representation of the considered electrothermal averaged model of a diode–transistor switch (AVG model) is shown in Figure 3. This switch contains an IGBT and a diode.

Terminals 1, 2, 3, and 4 of the AVG model correspond to the terminals of the IGBT and the diode visible in the diagram of the diode–transistor switch shown in Figure 2. The considered model is connected to other components of the analysed DC-DC converters, using these terminals according to the respective diagrams. The frequency f and the duty cycle d of the signal controlling a DC-DC converter are parameters of the AVG model. These parameters that are used occur in the formulas describing some controlled voltage and current sources in this model. Internal temperatures of the IGBT and the diode correspond to voltages on terminals TjT and TjD, respectively.

**Figure 3.** Network representation of the AVG model including the IGBT and the diode [32].

The described model contains four blocks: main circuit, aided block, thermal model, and CCM/DCM.

The main circuit contains two controlled voltage sources ER and ET and the controlled current source GD. These voltage sources model the average voltage between the collector and the emitter of the IGBT, whereas the current source models the average value of the diode current. V1 is the voltage source of zero value that monitors this current. I1av and I2av, as well as V1av and V2av in the main circuit, denote the average values of voltages and currents of the semiconductor devices. The output values of the controlled voltage and current sources are described with the equations formulated using the idea presented in the papers [12,24]. According to this idea, at the steady state in each period T of the control signal, the current flows through one semiconductor device only. The transistor current flows for the time equal to d·T, and the diode current—for the time (1 − d)·T (in CCM (Continuous Conduction Mode) or less in DCM (Discontinuous Conduction Mode)). In the considered model, the current–voltage characteristics of both the semiconductor devices are described by piecewise linear functions. These functions use parameters depending on the internal temperatures of these semiconductor devices. Values of these parameters are computed in the aided block. In turn, internal temperatures of the diode and the IGBT are computed in the thermal model. The value of the equivalent duty cycle Veu is computed in the controlled voltage source Eu included in the CCM/DCM block. The output value of this source depends on the parameters control signal—the duty cycle d and frequency f of the control signal, as well as inductance L of the inductor contained in the analysed DC-DC converter and load resistance of this converter.

The internal temperature of the IGBT (TjT) and the diode (TjD) are computed in the thermal model with self-heating phenomena taken into account. This model uses the electrical analogue of a DC compact thermal model [1,33]. In this analogue, voltages TjT and TjD correspond to internal temperatures of the IGBT and the diode, respectively. In turn, the average values of power dissipated in these semiconductor devices are represented by the controlled current sources GTT and GTD. The output currents of these sources are described as follows [32].

$$\mathbf{G\_{TD}} = \left(\mathbf{V\_D} + \frac{\mathbf{R\_D} \cdot \mathbf{I\_{2av}}}{1 - \mathbf{V\_{eu}}}\right) \cdot \frac{\mathbf{I\_{2av}}}{1 - \mathbf{V\_{eu}}} \tag{1}$$

$$\mathbf{G\_{TT}} = \left(\mathbf{V\_{IGBT}} + \frac{\mathbf{R\_{IGBT}} \cdot \mathbf{I\_{1av}}}{\mathbf{V\_{eu}}}\right) \cdot \frac{\mathbf{I\_{1av}}}{\mathbf{V\_{eu}}} \tag{2}$$

where VIGBT, VD, RD, and RIGBT describe the parameters of piecewise linear models of the transistor and the diode characteristics.

The efficiency of the removal of heat generated in these devices is characterised by thermal resistance represented by resistors RthT and RthD. The voltage source VTa represents ambient temperature.

The other equations describing the controlled sources presented in Figure 3 are in [32].

### **3. Measurement Setup**

In order to evaluate the usefulness of the considered model, the characteristics of the boost converter containing the considered semiconductor devices are measured and computed. The diagram of the investigated converter is presented in Figure 4.

**Figure 4.** Diagram of the tested boost converter.

In the considered converter, the input voltage VCC is supplied from the GWInstek PSB-2800L power supply. Appa 208 multimeters are used as ammeters and voltmeters. The inductance of coil L1 is equal to 560 μH, and the capacitance of C1 is 1 mF. The voltage controlling the IGBT Vctrl is produced by the NDN C5603P function generator and connected to the gate of the IGBT via the driver IR2125. The prototype is mounted on the Printed Circuit Board (PCB). The diode of the type IDP08E65 is characterised by the maximum repetitive peak reverse voltage equal to 650 V and the maximum forward current equal to 16 A, and the IGBT of the type IGP06N60T is characterised by the maximum collector–emitter voltage equal to 600 V and the maximum DC collector current equal to 12 A. Based on the data given in the datasheet, the maximum switching frequency of this IGBT is estimated as equal to 500 kHz. Some waveforms of voltages and currents of the investigated DC-DC converter were measured using an oscilloscope Rigol MS05104 and a current probe Tektronix PCPA 300 for different values of load resistance and parameters of the control signal.

In order to determine the internal temperature Tj of the IGBT (TjT) or the diode (TjD), the case temperature TC of these semiconductor devices is measured using a pyrometer

PT-3S by Optex. Next, using the values of thermal resistances junction-ambient Rthj−<sup>a</sup> and junction-case Rthj−c, the values of temperature Tj are calculated using the following formula [7]

$$\mathbf{T\_{j}} = \mathbf{T\_{c}} + (\mathbf{T\_{c}} - \mathbf{T\_{a}}) \cdot \frac{\mathbf{R\_{thj-c}}}{\mathbf{R\_{thj-a}} - \mathbf{R\_{thj-c}}} \tag{3}$$

where Ta denotes ambient temperature. Values of thermal resistance Rthj−<sup>c</sup> are given in the data provided by the manufacturer, whereas thermal resistance Rthj−<sup>a</sup> is measured with the use of indirect electrical methods described e.g., in the paper [34].

The investigated DC-DC converter operates without any feedback loop, which is typically used in switch-mode power supplies including such converters. Therefore, at the selected operating conditions, the influence of changes in the load resistance and parameters of the control signal are not compensated for by the feedback loop. For this reason, any disadvantages of the considered model can be clearly illustrated for the investigated circuit.

### **4. Investigation Results**

In order to analyse the usefulness range of the model from [32], hereinafter referred to as the AVG model, computations and measurements of the characteristics of the boost converter in various operating conditions are performed. In particular, the change of the following operating parameters of the considered converter is taken into account: input voltage Vin, load resistance RL, frequency f, and the duty cycle d of the IGBT control signal. The measurements are carried out for a transistor and a diode operating at different cooling conditions. The operation of the investigated converter in both the CCM (Continuous Conduction Mode) and the DCM (Discontinuous Conduction Mode) [2] is considered.

The computations were performed for parameters with values identical to those given in [32], with the stipulation that the values of the model parameters RthD and RthT correspond to thermal resistances of the transistor and the diode. For the considered elements placed on heat sinks of the dimensions of 7.5 cm × 5 cm × 3.5 cm, the values of these parameters were 6.2 K/W, and for the devices operating without a heat sink, it was 43.85 K/W.

Selected results of measurements and computations of the investigated DC-DC converter are illustrated in the successive figures. In all these figures, points denote the results of measurements, whereas solid lines denote the results of computations performed with the AVG model.

Figure 5 shows the output characteristics of a boost converter operating with low input voltage Vin = 12 V under various cooling conditions, and Figure 6 shows the corresponding dependences of junction temperature of the transistor (a) and the diode (b) on the output current.

As it results from the data presented in Figures 5 and 6, the AVG model correctly reproduces the output characteristics of a boost converter operating in the CCM and the DCM, but only for the output current higher than 10 mA. For lower values of this current, there are significant discrepancies between the results of computations and measurements. The source of these discrepancies is losses resulting from switching off the IGBT omitted when formulating the considered model. The effect of these losses is an increase in the temperature of the transistor despite a decrease in the current value of the IGBT, as shown in Figure 6a. In order to improve the accuracy of modelling this characteristic, the heat generation model should take into account not only power losses related to the conduction of the IGBT but also power losses resulting from its switching. The method of modelling losses associated with the transistor switching for the needs of the averaged diode-transistor switch model is presented in [27] for the MOSFET transistor. In the range of very low values of the Iout current, the cause of the discrepancy may also be the omission of leakage currents of the transistor and the diode at the stage of formulating the considered model.

**Figure 5.** Measured and computed output characteristics of the boost converter for semiconductor devices operating at different cooling conditions.

**Figure 6.** Measured and computed dependences of the IGBT junction temperature (**a**) and the diode junction temperature (**b**) on the output current of the investigated converter.

As shown in Figure 5, the cooling conditions do not significantly affect the shape of the Vout(Iout) dependence for Iout > 1 mA. However, they significantly affect the efficiency of heat removal from the semiconductor devices contained in the considered converter. As shown in the range of very low values of Iout current, an increase in temperature TjT is visible, which proves that an average value of the dissipated power is as much as 0.5 W.

Figure 7 shows the output characteristics of the considered converter for four values of the IGBT switching frequency. Computations and measurements are performed for the transistor and the diode placed on heat sinks.

The results of computations and measurements presented in Figure 7 prove that for the collector currents below 10 mA and for switching frequencies higher than 10 kHz, the measurement results differ significantly from the results of computations made with the use of the AVG model. For the constant value of the output current, the discrepancy between the computations and measurements results increases with the switching frequency of the IGBT. An increase in the discrepancy also results from the fact that with an increase of switching frequency, the value of the current switched off by the transistor decreases [2]. A measure of this discrepancy is the relative error in determining voltage δVout calculated from the formula

$$
\delta \mathbf{V}\_{\text{out}} = \frac{\left| \mathbf{V}\_{\text{outmeasured}} - \mathbf{V}\_{\text{outcomputed}} \right|}{\mathbf{V}\_{\text{outmeasured}}} \tag{4}
$$

where Voutmeasured denotes the measured value of the output voltage, whereas Voutcomputed is the value of this voltage computed with the use of the AVG model.

**Figure 7.** Measured and computed output characteristics of the boost converter for the transistor and the diode placed on heat sinks for selected values of switching frequency.

The computation error of the output voltage as a function of the output current is shown in Figure 8.

As it can be seen from the data presented in Figure 8, the relative error of determining the output voltage using the AVG model decreases with an increase of the output current of the boost converter and a decrease of frequency in the CCM. The error δVout does not exceed a few percent. The graph has clear minima and maxima resulting from the modelling of the output characteristics of the turned-on IGBT using the piece-wise linear function. The smallest error values occur for a switching frequency equal to 10 kHz, and the highest error values occur for the highest among the considered frequencies, which is related to the AVG model not taking into account the influence of parasitic capacitances in the IGBT on the characteristics of the considered DC-DC converter.

**Figure 8.** Computed values of the relative error in determining the output voltage as the function of the converter output current.

Figure 9 shows the dependence of the output voltage of the boost converter on the duty cycle of the signal controlling the transistor contained in it. During the measurements, the considered converter operated with the input voltage of 48 V. The IGBT and the diode were placed on the heat sinks, and the measurements were made for two values of load resistance. Additionally, in Figure 10a, the dashed line marks the results of computations made in the SPICE program using the AVG model, to which are added the values of the junction temperature increase ΔTj resulting from dynamic losses in the IGBT computed on the basis of the Equations (5) and (6).

$$
\Delta T\_{\text{j}} = T\_{\text{jcond}} + R\_{\text{thj}-\text{a}} \cdot P\_{\text{swt}} \tag{5}
$$

$$P\_{\rm swt} = \left(\mathbf{E}\_{\rm con}(\mathbf{I}\_{\rm con}, \mathbf{T}\_{\rm j}, \mathbf{V}\_{\rm CE}, \mathbf{R}\_{\rm G}) + \mathbf{E}\_{\rm off}(\mathbf{I}\_{\rm off}, \mathbf{T}\_{\rm j}, \mathbf{V}\_{\rm CE}, \mathbf{R}\_{\rm G})\right) \cdot \mathbf{f} \tag{6}$$

where Tjcond is the value of the IGBT junction temperature computed using the AVG model, Rthj−<sup>a</sup> is the IGBT thermal resistance junction—ambient, and Pswt is the mean value of the power dissipated in the IGBT resulting from switching losses.

**Figure 9.** Measured and computed dependences of the output voltage on the duty cycle of the boost converter for selected values of load resistances.

The values of Eon and Eoff necessary for the computations were obtained by approximating with linear functions the dependencies presented in the datasheet of the considered IGBT [35]. Due to the sawtooth shape of the collector current of the IGBT operating in the boost converter, it was necessary to separately determine the value of the switched currents Ion and Ioff. The following formulas were used for this purpose [2].

$$\mathbf{I}\_{\rm on} = \mathbf{I}\_{\rm invg} - \frac{\Delta \mathbf{I}\_{\rm L}}{2} \tag{7}$$

$$\mathbf{I}\_{\rm eff} = \mathbf{I}\_{\rm invg} + \frac{\Delta \mathbf{I}\_{\rm L}}{2} \tag{8}$$

$$
\Delta \mathbf{I}\_{\rm L} = \frac{(\mathbf{V}\_{\rm out} - \mathbf{V}\_{\rm in}) \cdot \mathbf{d}}{\rm L \cdot \rm f}. \tag{9}
$$

The results presented in Figure 10a prove that even with the correctly determined values of the converter output voltage, which are shown in Figure 9, the computations of the corresponding values of the IGBT junction temperature may be characterised by a big error. The reason for this error is the omission of switching losses in the heat generation AVG model. In the case of the IGBT operation with high switching frequency, switching power losses that are proportional to e.g., to frequency and the switched current, can be much higher than the conduction losses of the IGBT [36,37]. This is demonstrated by the computation results presented in Figure 11, which show the conduction losses (red line) computed using the AVG model and the switching losses averaged for one period that

are computed using the Formula (3)—blue line. The effect of frequency and the collector current on the average power dissipated in a transistor operating with resistive load is illustrated in Figure 11a,b, respectively.

**Figure 10.** Measured and computed dependences of the IGBT junction temperature (**a**) and the diode junction temperature (**b**) on the duty cycle of the control signal of the IGBT in the investigated converter.

The curves shown in Figure 11 show that both switching and conduction losses are an important component of the power dissipated in this device during its operation. It is particularly noteworthy that in Figure 11 in the considered operating conditions, switching losses of the transistor are equal in the value to conduction losses for the frequency of 35 kHz, and for the frequency of 100 kHz, switching losses are already four times higher. It is also worth noting that in Figure 11b, for the considered operating conditions, switching losses depend more strongly on the collector current than on conduction losses.

The discrepancy between the computation results taking into account the impact of the IGBT switching losses on its junction temperature and the measurement results shown in Figure 11a probably results from not taking into account the influence of overvoltages and overcurrents on the value of turn-on and turn-off energies. Examples of overvoltages and overcurrents are shown in the waveforms shown in Figure 12.

**Figure 11.** Computed dependences of the IGBT power losses caused by its switching (blue line) and conducting (red line) on frequency (**a**) and the collector current (**b**).

**Figure 12.** Measured waveforms of the collector–emitter voltage (blue solid line) and the collector current (red solid line) of the IGBT in the investigated boost converter.

In the case of a diode, in the considered frequency range, switching losses are much lower than conduction losses [38]. This is visible in Figure 10b, on the basis of which it can be stated that when using the diode model that does not take into account the effect of losses associated with its switching, the value of its junction temperature is computed with good accuracy.

Minor discrepancies between the results of computations and measurements, which are presented in Figure 9, result from inaccurate determination of the value of the duty cycle for the converter operating in the CCM. The problem of determining the value of the duty cycle is due to the fact that the operation of the IGBT with high switching frequency differs significantly from the operation of an ideal switch. In the case of an ideal switch, the value of the duty cycle voltage between the output terminals is equal to the value of the transistor control signal coefficient subtracted from one.

The computation method presented above was used in the formulas in the considered model. However, in the case of an IGBT operating with high switching frequency, due to non-zero values of parasitic capacitances, the value of the duty cycle of the signal between the output terminals of the transistor may significantly differ from the value for an ideal switch. In Figure 13, the dependences of the relative error in determining the duty cycle on the frequency of the control signal and the duty cycle of the control signal for the considered IGBT resulting from omitting the non-ideality of this device in determining this factor are presented. The value of this error was determined according to the formula

$$\delta \mathbf{d} = \frac{|\mathbf{d}\_{\rm CG} - (1 - \mathbf{d}\_{\rm VCE})|}{1 - \mathbf{d}\_{\rm VCE}} \tag{10}$$

where dGG is the value of the duty cycle of the signal at the output of the driver controlling the transistor, and dVCE is the value of the duty cycle between the output terminals of the IGBT.

**Figure 13.** Measured values of the relative error in determining the duty cycle of the signal between the IGBT output terminals as a function of the duty cycle of the control signal (**a**) and the frequency of the signal controlling this transistor (**b**).

As it is presented in Figure 10, for low control signal duty cycle values, the user has poor control over the actual voltage duty cycle value between the transistor output terminals. A similar effect can be observed with increasing frequency. This can lead to significant discrepancies between the computed value of the converter output voltage from the mathematical model and the one obtained during the measurements of the real converter.

Figure 14 shows the dependence of the output voltage of the DC-DC converter on the switching frequency of the IGBT contained therein. In the figure, the computation results for the duty cycle value consistent with the signal at the driver output are marked using the solid line, and the dashed line is used for the Vout voltage values computed for the converter operating in the CCM taking into account the error in determining the duty cycle described above. In these computations, the dependence of the form is used:

$$\mathbf{V}\_{\rm out} = \mathbf{V}\_{\rm out} + \mathbf{V}\_{\rm in} \cdot \left( \frac{1}{1 - \mathbf{d}\_{\rm CG} - \Delta \mathbf{d}} - \frac{1}{1 - \mathbf{d}\_{\rm CG}} \right) \tag{11}$$

where Voutc is the computed value of the output voltage using the model [33], and Δd is the absolute error in determining the duty cycle.

The converter output voltage dependencies presented in Figure 14 prove that neglecting the influence of electrical inertia related to the switching of the IGBT leads to a value of the duty cycle of the collector–emitter voltage different than for the ideal switch. This is the reason why the error in determining the output voltage increases with increasing frequency. At the same time, as the computations show, taking this into account in computations allows for a significant improvement of its accuracy.

As indicated in the papers [39,40], the omission of the nonlinear dependence of thermal resistance of the IGBT junction temperature significantly influences the accuracy of determining the transistor junction temperature. In order to check whether this problem also occurs for the transistor operating in the boost converter, the measurements and computations of its output characteristics and the correlation between the interior temperature of the IGBT operating without a heat sink were carried out. In order to emphasise the considered issue, Figure 15 presents only the measurement results for the converter operating in the CCM.

**Figure 14.** Measured and computed dependences of the output voltage on frequency.

The results presented in Figure 15 prove that even with the correct representation of electrical properties of the converter, i.e., losses related to switching the IGBT, the computed junction temperature value for high values of the output current is significantly overestimated due to the use of a linear thermal model in the AVG model. This problem could be solved relatively easily by averaging the nonlinear thermal model described in the paper [39]. In the modified model, the thermal capacitances will be omitted, and one nonlinear resistor describing the dependence Rthj−a(Tj) will be used.

**Figure 15.** Measured and computed dependences of the output voltage (**a**) and the IGBT junction temperatures (**b**) on the output current of the investigated converter.

### **5. Conclusions**

The paper presents the results of simulation and experimental studies illustrating the limitations of an electrothermal averaged model of a diode–transistor switch containing an IGBT and a rapid switching diode. The investigations were carried out for the boost converter in a wide range of changes of load current, frequency, and the duty cycle of the control signal. Various cooling conditions for the transistor and the diode contained in the tested converter were considered.

It was proved that for both the considered types of cooling conditions of semiconductor devices in the whole considered range of changes in the duty cycle and frequency of the control signal, good agreement was obtained between the computed and measured values of the output voltage of the boost converter operating in the CCM. On the other hand, in the DCM, the results of computations and measurements are convergent for the frequency f < 20 kHz and the load current Iout > 10 mA.

The problem of determining the value of the control signal duty cycle in the highfrequency range is pointed out. In this regard, the transistor switching times are not negligible in relation to the pulse duration. It was shown that at high frequency values f > 70 kHz, the error in determining the output voltage resulting from inaccuracy in determining the value of the duty cycle can reach even 10%. It is shown that this error could be reduced if the value of duty cycle is estimated, taking into account values of switch-on and switch-off times of the used transistor.

It is indicated that switching losses in the IGBT are significant for characteristics of the boost converter. It was shown that omitting these losses in the considered model causes significant, even twofold lowering of the value of the IGBT junction temperature increase above the ambient temperature. A modification of the description of the thermal model of the transistor using Formulas (5) and (6) was proposed to allow taking into account the influence of switching losses in the transistor on its junction temperature. It was shown that this modification allows improving the computation accuracy.

The problem of nonlinearity of thermal phenomena in semiconductor devices, which causes the junction temperature value to be overestimated in the range of high output currents of a converter, is also highlighted. The manner of taking into account the nonlinearity of the thermal model of the used semiconductor devices is proposed.

The problem of the junction temperature in the range of very low Iout values is also indicated. Improvement of the model under consideration that enables obtaining high accuracy of computations in a wide range of frequency changes will be the subject of further research by the authors.

The presented research results may be useful for designers of DC-DC converters. The presented results of computations and measurements also allow assessing the influence of the control signal frequency and load current as well as the cooling conditions of semiconductor devices on the properties of the tested boost converter.

**Author Contributions:** Conceptualisation, P.G. and K.G.; computations, P.G.; methodology, P.G. and K.G.; experimental verification, P.G.; writing—original draft preparation, P.G. and K.G.; writing review and editing, K.G. and P.G.; visualisation, P.G.; supervision, K.G. All authors have read and agreed to the published version of the manuscript.

**Funding:** The scientific work is a result of the project No. 2018/31/N/ST7/01818 financed by the Polish National Science Centre.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


### *Article* **A Universal Mathematical Model of Modular Multilevel Converter with Half-Bridge**

**Ming Liu 1,2, Zetao Li 1,3,\* and Xiaoliu Yang <sup>1</sup>**


Received: 30 June 2020; Accepted: 27 August 2020; Published: 29 August 2020

**Abstract:** Modular multilevel converters (MMCs) play an important role in the power electronics industry due to their many advantages, such as modularity and reliability. In the current research, the simulation method is used to study the system. However, with the increasing number of sub-modules (SMs), it is difficult to model and simulate the system. In order to overcome these difficulties, this paper presents a universal mathematical model (UMM) of MMC using half-bridge cells as SMs. The UMM is a full-scale model with switching state, capacitance, inductance, and resistance characteristics. This method can calculate any number of SMs, and it does not need to build a simulation model (SIM) of physical MMC—in particular, parametric design can be realized. Compared with the SIM, the accuracy of the proposed UMM is verified, and the computational efficiency of the UMM is 8.7 times higher than the simulation method. Finally, by utilizing the proposed UMM method, the influence of the parameters of MMCs is studied, including the arm induction, SM capacitance, SM number, and output current/voltage total harmonic distortion (THD) based on the UMM in the paper. The results offer an engineering insight to optimize the design of MMCs.

**Keywords:** modular multilevel converter (MMC); total harmonic distortion (THD); universal mathematical model (UMM); switching state; nearest level modulation (NLM)

### **1. Introduction**

With the rapid development of offshore wind farms, the demand for a high power, high-quality transmission system becomes more urgent. Modular multilevel converter (MMC)-based high voltage direct voltage (HVDC) technology provides a promising solution, due to its advantages of modularization, scalability, high efficiency, excellent harmonic performance, fault blocking ability, small filter size, high efficiency, and low redundancy cost [1–3]. MMC has been applied to many industries, such as energy storage systems, medium-voltage and high-power motor drive systems, distribution systems, etc. [4–8].

However, it is difficult to formulate an explicit expression of MMC, because it is a hybrid system of discrete and continuous models. The main feature of MMCs is the cascaded connection of a large number of sub-modules (SMs). These SMs are arranged in groups called arms or branches. The low-frequency voltage or current at the AC side is controlled by high-frequency switching values to manage SMs on/off. Therefore, the interaction between the arm and line quantities (variables) generates low- and high-frequency components on the AC and DC side of the SMs in an MMC [9]. In other words, MMC has strong coupling nonlinear multi-input and multi-output dynamic features [10]. The simulation studies were utilized to analyze the behavior of an MMC. However, the simulation process consumes time and computer resources to create a large number of SMs (up to 400 per arm) [11]. For example, a traditional detailed model (TDM) of MMC requires hundreds and thousands of Insulated Gate Bipolar Transistors(IGBTs) with antiparallel diodes and capacitors to be built and electrically connected in the simulation package's graphical user interface, resulting in a large admittance matrix.

To simplify the simulation model, the conventional switching models/detailed models with full capabilities of replicating the conduction of power electronic devices such as IGBTs and their anti-parallel diodes are inefficient for the modeling of MMC-HVDC, as the simulation time is prohibitively long [1]. To simplify the calculation, it was assumed that the SM capacitor voltages are well balanced at their reference values [12,13]. The SM terminal voltage in each arm was modeled as a single equivalent voltage source [14]. In [15], the equivalent model was used and a small-signal analysis was carried out. Alternatively, each arm of MMC was modeled as a nonlinear capacitor with a time-variant sinusoidal capacitance [16]. Moreover, to simplify the analysis, the average value models (AVMs) are presented in [17–20]. However, the methods above do not reflect the switching state and the transient process of the SM capacitor voltage.

To address this problem, an efficient model was proposed by Udana and Gole in [21], which is referred to as the detailed equivalent model (DEM) in this paper; yet, a drawback of the DEM is that the individual converter components are invisible to the user. A new model, referred to as the accelerated model (AM), was proposed by Xu et al. in [22], but a full and objective comparison could not be completed because different researchers built the models on different computers. In [23], an enhanced accelerated model (EAM) with improved simulation speed was proposed by Antony et al., which further improved the computational efficiency of one method. A new dynamic phasor (DP) model of an MMC with an extended frequency range for direct interfacing with an electromagnetic transient (EMT) simulator was presented in [24]. In reference [25], a method of MMC modeling and design based on parametric and model-form uncertainty quantification is proposed, which can establish confidence in modeling and simulation in the presence of manufacturing variability and modeling errors, and may eliminate the need for heuristic safety factors. However, the high-efficiency calculation of large-scale SMs is not involved. The internal dynamics of the MMC are modeled considering the dominant harmonic components of each variable. However, the improved simulation models introduced above are based on Power Systems Computer Aided Design/Electromagnetic Transients including DC(PSCAD/EMTDC) for electromagnetic transient simulation. It is inconvenient to set variable parameters or change the topology of the whole circuit. It cannot be satisfied by loop calculation to compare the changes of parameters.

In this paper, a universal mathematical model for MMC is proposed which can reflect the steady-state and dynamic process of MMC. The model is a detailed numerical model, including the capacitor voltage and switch function of SMs. It can be implemented by a computer for any number of SMs. The whole model is parametric programmed; by setting one or several parameters, the desired results can be quickly obtained. Compared with the simulation model, this algorithm can easily modify the circuit parameters by setting cycle statements, and automatically carry out repeated simulation and multi-state simulation, so it is convenient to observe the operation characteristics of the system under different parameter values. Using the proposed MMC, the output voltage and the current THDs of MMC have been analyzed under different parameters (such as module number, capacitor voltage, arm inductance). In addition, the change in the capacitance voltage has been studied as one capacitance value decayed.

Without losing generality, in this paper the research is based on MATLAB/Simulink because of its powerful numerical calculation ability and rich processing module (such as Pulse Width Modulation (PWM) generator, and various transformation and comparison modules), especially the demonstration of control strategy. Compared with Simulink, PLECS is more professional, but does not have as many toolboxes as Simulink. The LTSpice installation package is small, easy to operate, and fast, but most of the support is for the ADI company's own chip model. PSIM has the advantages of simple operation and fast simulation speed, and supports mainstream simulation mode analysis. However, due to the use of ideal switches, the simulation accuracy is limited.

This paper is organized as follows. Section 2 introduces the MMC topology, operation, and mathematical model. The algorithm of the universal mathematical model (UMM) is explained in Section 3. The correctness of the UMM is demonstrated in Section 4. A performance analysis under different conditions is shown in Section 5. The conclusions of the study are presented in Section 4.

### **2. Topology and Mathematical Model of the MMC**

### *Topology and Principles of Operation*

The circuit structure of a three-phase MMC is shown in Figure 1. The single-phase consists of an upper and a lower arm. Each arm is composed of *N* sub-modules (SM), and an inductor and equivalent resistance are connected in series. Each individual SM contains a capacitor and two complementary insulated gate bipolar transistor modules (i.e., *Sjm*,*<sup>n</sup>* and *S*- *jm*,*n*). In this paper, the subscript *j* = *a*, *b*, *c* means three-phase; *m* = *u*, *l*, where *u* represents the upper arm and *l* represents a lower arm; *n* = 1, 2, 3, ... , *N* represents the number of sub-modules. The rest of the symbols are as follows: *L* (the arm inductance), *R* (the arm equivalent resistance), *ujm* (the arm voltage), *ijm* (the arm current), *uj* (the AC side voltage), *ioj* (the output current), *icj* (the circulating current), *Loj* (the load inductance), *Roj* (the load resistance), U*dc* (the DC source voltage), *ujm*,*<sup>n</sup>* (the capacitor voltage).

$$\frac{du\_{jm,n}}{dt} = \frac{S\_{jm,n}i\_{jm}}{C} \tag{1}$$

where *Sjm*,*<sup>n</sup>* is the switch function of the *n*th SM in the *m* arm of phase-*j*, and its value is 1 or 0; *C* is the SM capacitance.

The relationship between the arm voltage and the capacitor voltage in phase-*j* and the switching function is:

$$\mu\_{\rm jin} = \sum\_{n=-1}^{N} S\_{jm,n} \mu\_{jm,n} \tag{2}$$

Considering a fictitious midpoint in the DC side of Figure 1 and using Kirchhoff's circuit laws, the following mathematical equations that govern the dynamic behavior of the MMC in phase-*j* can be obtained:

$$\dot{u}\_{ju} + R\dot{u}\_{ju} + L\frac{d\dot{i}\_{ju}}{dt} + R\_{oj}\dot{i}\_{oj} + L\_{oj}\frac{d\dot{i}\_{oj}}{dt} + u\_j - \frac{\mathbf{U}\_{dc}}{2} = 0\tag{3}$$

$$\dot{\mu}\_{jl} + R\dot{\imath}\_{jl} + L\frac{d\dot{\imath}\_{jl}}{dt} - R\_{o\jmath}\dot{\imath}\_{o\jmath} - L\_{o\jmath}\frac{d\dot{\imath}\_{o\jmath}}{dt} - \mu\_{\jmath} - \frac{\mathbf{U}\_{dc}}{2} = 0\tag{4}$$

$$
\dot{\mathbf{r}}\_{oj} = \dot{\mathbf{r}}\_{ju} - \dot{\mathbf{r}}\_{jl} \tag{5}
$$

The arm currents can be expressed as:

$$i\_{\rm ju} = \frac{i\_{oj}}{2} + i\_{cj\prime} i\_{j\rm l} = -\frac{i\_{oj}}{2} + i\_{cj} \tag{6}$$

where *icj* is the circulating currents flowing through phase-*j* of the MMC and can be calculated by Equation (7):

$$i\_{cj} = \frac{i\_{ju} + i\_{jl}}{2} \tag{7}$$

Substitute (3) and (5) into (4), and the dynamics of phase-*j* AC-side currents can be obtained as:

$$\frac{di\_{oj}}{dt} = -\frac{R+2R\_{oj}}{L+2L\_{oj}}i\_{oj} - \frac{1}{L+2L\_{oj}}u\_{ju} + \frac{1}{L+2L\_{oj}}u\_{jl} - \frac{2}{L+2L\_{oj}}u\_{j} \tag{8}$$

**Figure 1.** Structure of a three-phase MMC-based inverter and its SM.

Similarly, the dynamic behavior of the circulating current in phase-*j* can be obtained by substituting (3) and (7) into (4):

$$\frac{d\dot{\imath}\_{c\dot{\jmath}}}{dt} = -\frac{R}{L}\dot{\imath}\_{c\dot{\jmath}} - \frac{1}{2L}\mu\_{\dot{\jmath}u} - \frac{1}{2L}\mu\_{\dot{\jmath}\dot{l}} + \frac{1}{2L}lI\_{dc} \tag{9}$$

Based on (1), (2), (8), and (9), the state-space equation of the MMC in phase-*j* can be described as:

$$
\dot{\mathbf{x}}(t) = A(t)\mathbf{x}(t) + \mathbf{D}d(t) \tag{10}
$$

where *x* = [*ioj*, *icj*, *uju*,1, ... , *uju*,*N*, *ujl*,1, ... , *ujl*,*N*] *<sup>T</sup>* <sup>∈</sup> <sup>R</sup>2*N*+<sup>2</sup> is the state vector; *<sup>d</sup>* = [*uj*, U*dc*] *<sup>T</sup>* is a perturbation vector; the desired value (*u*∗ *j* ) of *uj* is presented in Equation (11); *<sup>A</sup>* <sup>∈</sup> <sup>R</sup>(2*N*+2)×(2*N*+2) is a time-varying structure state matrix, presented in (12); and *<sup>D</sup>* <sup>∈</sup> <sup>R</sup>(2*N*+2)×<sup>2</sup> is the perturbation coefficient matrix, presented in (20).

$$u\_j^\* = \sqrt{2}ll\sin\{2\pi ft + \varphi\_j\}\tag{11}$$

where *U* is the voltage effective value (RMS) on the AC side, *f* is the AC system frequency, and ϕ*<sup>j</sup>* is the initial phase angle in phase-*j*.

$$A(t) = \begin{bmatrix} A\_1 & A\_2(t) \\ A\_3(t) & 0 \end{bmatrix} \in \mathbb{R}^{(2N+2)\times(2N+2)} \tag{12}$$

where *<sup>A</sup>*<sup>1</sup> <sup>∈</sup> <sup>R</sup>2×<sup>2</sup> is a constant matrix in (13), and *<sup>A</sup>*<sup>2</sup> <sup>∈</sup> <sup>R</sup>2×2*<sup>N</sup>* and *<sup>A</sup>*<sup>3</sup> <sup>∈</sup> <sup>R</sup>2*N*×<sup>2</sup> are time-varying matrixes in (14) and (18), respectively.

$$\mathcal{A}\_1 = \begin{bmatrix} -\frac{\mathcal{R} + 2\mathcal{R}\_{vj}}{L + 2L\_{vj}} & 0\\ 0 & -\frac{\mathcal{R}}{L} \end{bmatrix} \tag{13}$$

$$A\_2(t) = A\_2' 
diag(\mathfrak{u}(t))\tag{14}$$

where *A*- <sup>2</sup> <sup>=</sup> *A*- <sup>21</sup> *<sup>A</sup>*- 22 <sup>∈</sup> <sup>R</sup>2×2*N*; *<sup>A</sup>*- <sup>21</sup> <sup>∈</sup> <sup>R</sup>2×*<sup>N</sup>* is presented in (15); *<sup>A</sup>*- <sup>22</sup> <sup>∈</sup> <sup>R</sup>2×*<sup>N</sup>* is presented in (16); and *u*(*t*) is the input control vector, presented in (17).

$$\mathbf{A}'\_{21} = \begin{bmatrix} \frac{-1}{L + 2L\_{\upsilon j}} & \frac{-1}{L + 2L\_{\upsilon j}} \cdots & \frac{-1}{L + 2L\_{\upsilon j}}\\ -\frac{1}{2L} & -\frac{1}{2L} \cdot \cdots & -\frac{1}{2L} \end{bmatrix} \tag{15}$$

$$A'\_{22} = \begin{bmatrix} \frac{1}{L + 2L\_{\nu j}} & \frac{1}{L + 2L\_{\nu j}} \cdots & \frac{1}{L + 2L\_{\nu j}}\\ -\frac{1}{2L} & -\frac{1}{2L} \cdots & -\frac{1}{2L} \end{bmatrix} \tag{16}$$

$$\mathfrak{u}(t) := \begin{bmatrix} \mathbb{S}\_{\text{ju},1\prime} \mathbb{S}\_{\text{ju},2\prime} \cdots \mathbb{S}\_{\text{ju},N\prime} \mathbb{S}\_{\text{jl},1\prime} \mathbb{S}\_{\text{jl},2\prime} \cdots \mathbb{S}\_{\text{jl},N} \end{bmatrix} \tag{17}$$

$$A\_3(t) = \operatorname{diag}(\mathfrak{u}(t)) A\_3' \tag{18}$$

where *A*- <sup>3</sup> <sup>∈</sup> <sup>R</sup>2*N*×<sup>2</sup> is as follows:

$$A'\_3 = \begin{bmatrix} \frac{1}{2\overline{C}\_{\text{j},1}} & \cdots & \frac{1}{2\overline{C}\_{\text{j},N}} & \frac{-1}{2\overline{C}\_{\text{j},1}} & \cdots & \frac{-1}{2\overline{C}\_{\text{j},N}}\\ \frac{1}{\overline{C}\_{\text{j},1}} & \cdots & \frac{1}{\overline{C}\_{\text{j},N}} & \frac{1}{\overline{C}\_{\text{j},1}} & \cdots & \frac{1}{\overline{C}\_{\text{j},N}} \end{bmatrix}^T \tag{19}$$

$$\mathbf{D} = \begin{bmatrix} \mathbf{D}\_1 \\ \mathbf{0} \end{bmatrix} \in \mathbb{R}^{(2N+2)\times 2} \tag{20}$$

where *D*<sup>1</sup> is as follows:

$$\mathcal{D}\_1 = \begin{bmatrix} \frac{-2}{L + 2L\_{vj}} & 0\\ 0 & \frac{1}{2L} \end{bmatrix} \tag{21}$$

The output voltage of the MMC, such as phase-*j*, is defined as the voltage difference from point *j* to *N*.

$$\boldsymbol{v}\_{jN} = \,^{\mathcal{R}}\!\_{oj}\dot{\boldsymbol{i}}\_{oj} + \,^{\mathcal{L}}\!\_{oj}\frac{d\dot{\boldsymbol{i}}\_{oj}}{dt} + \boldsymbol{u}\_{j} \tag{22}$$

In (10), the control of the system is to adjust the structure of matrix *A* so that *uj* → *u*<sup>∗</sup> *j* , U*dc* → U<sup>∗</sup> *dc* (or the active power and reactive power are close to their desired values). As the focus of the paper is the universal mathematical model of the controlled object, the control method is shown in reference [26], and will not be detailed here.

From Equation (8), we can get the formula of *uj* as follows (in active inverter, *uj* - 0, *Roj* = 0; in passive inverter, *uj* = 0, *Roj* -0):

$$u\_{j} = -\frac{1}{2}(L + 2L\_{oj})\frac{d\dot{i}\_{oj}}{dt} - \frac{R}{2}\dot{i}\_{oj} - \frac{1}{2}u\_{j\mu} + \frac{1}{2}u\_{jl} \tag{23}$$

### **3. Algorithm of the Universal Mathematical Model**

Equation (10) shows that the MMC is a nonlinear multi input system where the nonlinearity consists of the products between the states and inputs. The direct solution is difficult to find; as a result, the discrete sampling method will be used. The algorithm of the universal model is shown in Figure 2.

**Figure 2.** Block diagram of the universal mathematical model algorithm for MMC. (**a**) Open-loop control system, (**b**) closed-loop control system.

### *3.1. Discrete-Time Model of the MMC*

It is assumed that the switching of equations occurs at the sampling points. Based on (10) and assuming a sampling time of *Ts*, the discrete-time model of the MMC, based on a forward Euler approximation, is obtained as:

$$\mathbf{x}(k+1) = (I + T\_s \mathbf{A}(k))\mathbf{x}(k) + T\_s \mathbf{D}d(k) \tag{24}$$

The output current, *ioj*(*k*), can be calculated as:

$$i\_{oj}(k) = \ x\_1(k) \tag{25}$$

The circulating current, *icj*(*k*), is obtained by Equation (26):

$$\dot{a}\_{cj}(k) = \ x\_2(k) \tag{26}$$

The capacitance voltage, *ujm*,*n*(*k*), is obtained by the following Equation:

$$
\mu\_{jm,n}(k) \; : \; \mathbf{x}\_{\\$}(k) \; \sim \mathbf{x}\_{2N+2}(k) \tag{27}
$$

Based on Equations (6), (25), and (26), the arm currents can be calculated as:

$$i\_{\!\!\!\!/}(k) \;=\ \frac{\mathbf{x}\_1(k)}{2} + \mathbf{x}\_2(k), \; i\_{\!\!\!/\!}(k) \;=\ -\frac{\mathbf{x}\_1(k)}{2} + \mathbf{x}\_2(k) \tag{28}$$

Based on Equation (22), the output voltage of the MMC can be expressed as:

$$w\_{j\mathbf{N}}(k) = R\_{oj}\mathbf{x}\_1(k) + L\_{oj}\frac{\mathbf{x}\_1(k+1) - \mathbf{x}\_1(k)}{T\_s} + u\_j(k) \tag{29}$$

Based on Equation (23), the AC voltage of the MMC can be expressed as:

$$
\mu\_j(k) = -\frac{1}{2}(L + 2L\_{\rm ori})\frac{\mathbf{x}\_1(k+1) - \mathbf{x}\_1(k)}{T\_s} - \frac{R}{2}\mathbf{x}\_1(k) - \frac{1}{2}\mu\_{ju}(k) + \frac{1}{2}\mu\_{jl}(k)\tag{30}
$$

### *3.2. Nearest Level Modulation*

The nearest level modulation (NLM), also known as the round method, is an approach that uses the nearest voltage level to estimate the desired output voltage. The three phases are controlled independently. Given a normalized voltage reference *vj*,*res*, the nearest output voltage level *njm* can be determined by:

$$\begin{cases} n\_{\rm ju} &= \frac{N}{2} - \text{round}\left(\frac{mNv\_{j,res}}{2}\right) \\ n\_{\rm jf} &= \frac{N}{2} + \text{round}\left(\frac{mNv\_{j,res}}{2}\right) \end{cases} \tag{31}$$

where *m* is the modulation coefficient, and *vj*,*res* is defined as:

$$\left(v\_{\text{j.res}} = \sin(2\pi ft + \theta\_{\text{j}})\right) \tag{32}$$

where θ*<sup>j</sup>* is the initial phase angle in phase-*j*. Normalized voltage references for the three phases can be presented as:

$$\begin{cases} v\_{a, \text{res}} = \sin(2\pi ft) \\ v\_{b, \text{res}} = \sin(2\pi ft - \frac{2\pi}{3}) \\ v\_{c, \text{res}} = \sin(2\pi ft + \frac{2\pi}{3}) \end{cases} \tag{33}$$

### *3.3. Control Systems*

In this paper, the control strategy applied in [26] is utilized to obtain the optimal value *u*∗ *ju* and *u*<sup>∗</sup> *jl* through the tracking control of the AC voltage or DC voltage. Of course, not limited to this control strategy, other controls (such as the traditional PI control) are also applicable.

$$\begin{cases} n\_{j\mu} = \text{round}\left(\frac{u\_{j\mu}^\*}{u\_C}\right) \\ n\_{jl} = \text{round}\left(\frac{u\_{jl}^\*}{u\_C}\right) \end{cases} \tag{34}$$

where *uC* is the capacitor-rated voltage, *uC* = U<sup>∗</sup> *dc*/*N*.

The MMC control diagram is shown in Figure 3, and a more detailed closed-loop control is shown in Figure 2b. Since this study focuses on the universality of the model controlled (UMM), only the system is considered as an open-loop system (in Figure 2a) in the early stage of the design, and the control system is designed after the system-controlled parameters are fixed.

**Figure 3.** MMC control diagram.

### *3.4. Voltage Sorting Algorithm*

In this paper, the voltage sorting algorithm applied in [27] is utilized to equalize all the capacitor voltages of the MMC *ujm*,*n*. The algorithm reads the insertion indices *nju* and *njl* and determines which SMs are connected or bypassed in each arm of the MMC according to the plus-minus of the arm current *ijm*. For example, if *ijm*(*k*) > 0, the algorithm connects *njm* SMs with the lowest voltages in the corresponding arm and bypasses all the others. Conversely, if *ijm*(*k*) < 0, the algorithm connects *njm* SMs with the highest voltages and bypasses the others. Therefore, the switching signals *Sjm*,*<sup>n</sup>* to be applied in the sampling time *k* can be obtained. Finally, *u*(*k*) is obtained based on (17).

### **4. Verification of Universal Mathematical Model**

To evaluate the performance of the proposed UMM, a comparison between the results from the UMM and the nonlinear time-domain simulation model has been conducted. The nonlinear time-domain simulation model (SIM) is implemented in MATLAB/Simulink, and the UMM is performed using an m-file in MATLAB. The initial value is set as *x*(0) = [0, 0, *uC*, *uC*, ... , *uC*] *<sup>T</sup>* <sup>∈</sup> <sup>R</sup>2*N*<sup>+</sup>2. The comparison was conducted for a single-phase converter with 20 submodules. The main parameters of the MMC in the simulation are listed in Table 1. All the simulations were conducted using a Microsoft Windows 10 operating system with a 2.7 GHz Intel® core ™ i7-7500U processor and 16 GB of RAM. The test results are given in the following sub-sections.


**Table 1.** Main parameters of the MMC (phase-a).

### *4.1. Accuracy Analysis*

The waveforms calculated by the UMM were compared with those generated from the SIM to evaluate the accuracy of the proposed approach. The results are shown in Figures 4 and 5. In these figures, the solid line "I" represents the result of UMM, the dashed line "II" represents the result of SIM.

### 4.1.1. Dynamic Simulation under Normal Operation

Figure 4 displays the out current, *ioa*, and output voltage, *vaN*, versus time. It shows that within a 0.2 s time range, the results calculated via UMM are favorable compared with the result obtained from SIM. According to Table 2, the root mean square errors are within a reasonable range. These results demonstrate the accuracy of the UMM method at steady state.

**Figure 4.** Output current/voltage diagram of the MMC. "I" represents the result of UMM, "II" represents the result of SIM. (**a**) current *ioa*, (**b**) voltage *vaN*.

For example, Figure 5a shows the transient behaviors of the circulating current. Figure 5b shows a trend of capacitor voltages for the upper and lower arm from transient to steady state. The upper arm current waveform is shown in Figure 5c. Before 0.06 s, the system was at a transient state, and the UMM and SIM results had shown similar behavior with a slight amplitude difference. After the transient state, the system tended to be stable and the two results were completely coincident.

The root mean square errors are shown in Table 2. From the numerical point of view, except for *vaN* the errors of other variables are small. In the meantime, the value of *vaN* is only less than 3/10,000 relative to its RMS (21,216 V).

In short, the perfect coincidence of the above-mentioned various dynamic waveforms (output current *ioa*/voltage *vaN*, circulating current *ica*, capacitive voltage *uam*,*n*, and upper arm current *iau* ) has proved the accuracy and correctness of the proposed algorithm UMM.

**Figure 5.** Circulating current/capacitor voltage diagram of the MMC. "I" represents the result of UMM, "II" represents the result of SIM. (**a**) circulating current *ica*, (**b**) voltage *vaN*. "1" represents the upper arm, "2" represents the lower arm, (**c**) upper arm current *iau*.


**Table 2.** Root mean square error of UMM and SIM.

### 4.1.2. Dynamic Simulation of SM Open Circuit Fault

The open circuit fault of SM was assumed to study the effect of the internal fault of sub module on the MMC system. The time interval of failure is given as [3, 3.04]—i.e., two cycles.

In Figure 6, it can be seen that in the transient process of fault, the waveforms of UMM and that of SIM also match well.

**Figure 6.** The waveform in case of open circuit fault. "I" represents the result of UMM, "II" represents the result of SIM. (**a**) output voltage, (**b**) circulating current, (**c**) capacitor voltage waveform in the case of open circuit fault.

### *4.2. Computational E*ffi*ciency*

A 5 s period was tested with a 50 μs simulation time step. In this paper, we considered three groups of data (number of submodules, *N* = 8, 12, 20) for calculation, and the calculation results are shown in Figure 7. For example, when *N* = 20, the UMM took 7.1 s to get the result, while SIM consumed 62.2 s. The computational efficiency of UMM is significantly improved, which is about 8.7 times faster than that of SIM. However, the computational efficiency of the average value model (AVM) lies in the middle of the three.

Another advantage of UMM over SIM is that the SIM system took a large amount of time to build a system with many SMs.

**Figure 7.** CPU times for UMM and SIM.

Under different sampling times (10, 30, 50 μs), the Central Processing Unit (CPU) times for UMM have been shown in Figure 8 as a 0.1 s period. It can be seen in Figure 8 that at *N* < 150, the three sampling times have little difference. However, with the increase in *N*, the time gap among them becomes larger. Especially when *N* is 404, the CPU times of the three were 162.8, 44.0, and 25.5 s, respectively. However, in fact, only the sampling time 50 μs for the UMM system met the accuracy requirements.

**Figure 8.** CPU times for UMM under different sampling times.

### **5. Application Based on UMM**

Section 4 had proved the accuracy and efficiency of UMM. However, in this section, UMM will be used to study the MMC system, which is also the biggest difference from most existing models. The quality of the output voltage and current is a criterion to judge the performance of an inverter. For a long time, it was believed that the output current and voltage quality would be improved with an increase in the SM quantity, but there is no definite conclusion and mathematical evidence for this.

It is time-consuming to build simulation models, so it is impossible to simulate and analyze a large number of SMs. The utilization of UMM can facilitate this analysis. In this section, the influence of the number *N* of SMs on the output voltage and current THD under different conditions will be investigated. The dynamic performance of the MMC system was analyzed on the effects of different *N*s.

### *5.1. Output Voltage*/*Current Harmonic Performance under Di*ff*erent N Values*

The calculation parameters are given with Table 1, except for the parameter *N*, where *N* is an independent variable from 0 to 400. The simulation results are shown in Figure 9.

**Figure 9.** The oscillogram varying with the number of SM. (**a**) Output voltage THD, (**b**) output voltage fundamental amplitude, (**c**) output current THD, (**d**) output current fundamental amplitude.

In Figure 9, during the period when *N* was increased from 4 to 50, both the THD and fundamental amplitude decreased rapidly. After that, as *N* increased, the change rate tends to reduce. The optimal value was at (308, 0.352%) in Figure 9a, and (92, 0.1335%) in Figure 9c. The fundamental amplitude reached the minimum value at *N* = 28, then increased slightly in Figure 9b,d. After *N* > 50, it reached a stable state with small fluctuations.

In summary, the results show that the relationship between the quality of output voltage (or current) and the number *N* of SMs is not proportional. It has an optimal solution; using UMM, it is possible to find the optimal solution. In practice, in the design of N should be also considered the cost of hardware, the voltage grade, and the complexity of control.

### *5.2. Output Voltage*/*Current Harmonic Performance under Di*ff*erent SM Capacitance C and N Values*

The influence of different SM capacitances, *C*, is studied in this section. The results are shown in Figure 10.

**Figure 10.** The THD diagram of the output current varying with *C* and *N*. The *C* value is shown in the legend.

Figure 10 displays the THD value of the output current and voltage changing with a different number *N* of SMs and SM capacitance *C*, respectively. As illustrated, when the N is small, less than 50, the THD basically coincides with different *C* values. After *N* > 100, the THD of the curve of *C* = 0.5 mF rises rapidly and become unstable. This phenomenon indicates that, along with the increase in the SMs, the capacity should be increased accordingly to keep the system stable.

According to [28], the voltage fluctuation rate of the SM capacitor can be calculated in the following equation:

$$\varepsilon = \frac{1}{3} \frac{S\_{\rm vN}}{\rm NaOH\_{\odot}^2} \tag{35}$$

where *S*vN is the MMC nominal power, and ω = 2π*f*.

Substitute *uC* = *Udc*/*N* into (32), then:

$$\kappa = \frac{N \text{S}\_{\text{vN}}}{3a \text{C} \text{U}\_{\text{dc}}^2} \tag{36}$$

Generally, *S*vN, ω, and *Udc* are constants. As a result, ε is directly proportional to *N* and inversely proportional to *C*. When *N* increases and *C* is a fixed value, the system will diverge and become unstable after ε exceeds the allowable value.

### *5.3. Output Voltage*/*Current Harmonic Performance under Di*ff*erent Arm Inductance L and N Values*

The influence of different SM inductances, *L*, is studied in this section. The simulation results are shown in Figure 11.

In Figure 11, when *N* is less than 110, the THD of the output voltage is basically the same for all the inductance values; after that, the THD decreases slowly as *N* increases, but the larger the arm inductance value, the higher the THD. It shows a small mutation near *N* = 140.

**Figure 11.** The THD diagram of the output voltage varying with *L* and *N*. The *L* value is shown in the legend.

Figure 12 shows the THD value of the output voltage changing with *N* and *L*. When N is less than 40, the output current THD is around the same value. The inductance value has different effects on THD in different areas of *N*. For example, the areas with the smallest THD are as follows: *L* = 1 mF, *N* ∈ [44, 56]; *L* = 1.5 mF, *N* ∈ [56, 68] ∩ [100, 116]; *L* = 3 mF in the interval [68, 80], *L* = 0.5 mF, *N* ∈ [68, 100] ∩ [116, 144] in the interval [68, 100]. After *N* increased to greater than 96, the THD increases significantly with the increase in *L*.

From the general trend, as *N* becomes larger, the inductance value should become smaller. However, if the inductance value is too small, it will lose the effect of suppressing the arm current and fault tolerance. Therefore, the design should be selected based on the actual situation.

### *5.4. Dynamic Performance under SM Capacitance Decay Fault*

In this test, the capacitance of the SM*au*<sup>1</sup> was attenuated by 0.6 times. Shown as Figure 13, the failure occurred at 3 s and continued until the end. From the SM voltage waveform, the difference between the waveforms before and after 3 s is obvious. This means that, in addition to the IGBT open circuit fault mentioned above, the proposed model can also study the parameter fault.

**Figure 12.** The THD diagram of the output current varying with *L* and *N*.

**Figure 13.** The SM1 capacitor voltage diagram under capacitance decay fault.

### *5.5. Object-Oriented Parametric Design*

Through object-oriented programming in Figure 14, the program can realize human-computer interaction and reduce the workload of designers, so as to realize the universality, versatility, ease of use, and operation of MMC. Of course, this is only an example. See reference [28] for the calculation of relevant parameters, which will not be discussed here.

**Figure 14.** Design and verification interface for MMC.

### **6. Conclusions**

A general mathematical model has been derived in detail from the circuit structure of MMC in this paper. The mathematical model includes the non-linear or linear characteristics of switching state, capacitance voltage, inductance, and resistance. Compared with the traditional MATLAB/Simulink (21-level MMC), the output voltage/current, circulating current, and capacitor voltage coincide, and the accuracy of the proposed model is fully proved. Additionally, this model is 8.7 (*N* = 20) times faster than the traditional simulation method. By changing the arm induction, SM capacitance, and the number of SMs to study the impact of each parameter on the output current/voltage THD, the optimal number of SMs has been found. In addition, the proposed model can also analyze the structure and parameter faults of MMC. The UMM proposed lays a solid foundation for further research into the dynamic performances of MMC with a large number of SMs.

The UMM mainly analyzes the static/dynamic system by discretizing the state equation of MMC. In essence, it belongs to the analytical analysis mathematical model. Its iterative calculation speed is much faster than that of the simulation model. At the same time, it also reduces the modeling time of the large-scale component modules and improves the universality. This is the reason that although the simulation model compared is only based on MATLAB/Simulink, it is not lost generality.

**Author Contributions:** Conceptualization, M.L. and Z.L.; methodology, M.L.; software, M.L.; validation, M.L.; resources, X.Y.; data curation, X.Y.; writing—original draft preparation, M.L.; writing—review and editing, M.L.; project administration, X.Y.; funding acquisition, Z.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the National Natural Science Foundation of China (No. 61963009) and (No. 61861007); Science and Technology Planning Project of Guizhou Province (No.2154 (2019)) and (No. 2302 (2016)); Collaborative Foundation of Guizhou Province (No. 7228 (2017)); Platform Talent Project of Guizhou Province (No. 5788 (2017)); and the special fund project of provincial governor for outstanding science and technology education talents in Guizhou Province (No. 4 (2010)).

**Conflicts of Interest:** The authors declare no conflict of interest.

### **Abbreviations**


### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **Inrush Current Control of High Power Density DC–DC Converter**

### **Ahmed H. Okilly 1, Namhun Kim <sup>2</sup> and Jeihoon Baek 1,\***


Received: 29 June 2020; Accepted: 18 August 2020; Published: 19 August 2020

**Abstract:** This paper presents a complete mathematical design of the main components of 2 kW, 54 direct current (DC)–DC converter stage, which can be used as the second stage of the two stages of alternating current (AC)–DC telecom power supply. In this paper, a simple inrush current controlling circuit to eliminate the high inrush current, which is generated due to high input capacitor at the input side of the DC–DC converter, is proposed, designed, and briefly discussed. The proposed circuit is very easy to implement in the lab using a single metal–oxide–semiconductor field-effect transistor (MOSFET) switch and some small passive elements. PSIM simulation has been used to test the power supply performance using the value of the designed components. Furthermore, the experimental setup of the designed power supply with inrush current control is built in the lab to show the practical performance of the designed power supply and to test the reliability of the proposed inrush current mitigation circuit to eliminate the high inrush current at initial power application to the power supply circuit. DC–DC power supply with phase shift zero voltage switching (ZVS) technique is chosen and designed due to its availability to achieve ZVS over the full load range at the primary side of the power supply, which reduces switching losses and offers high conversion efficiency. High power density DC–DC converter stage with smooth current startup operation, full load efficiency over 95%, and better voltage regulation is achieved in this work.

**Keywords:** DC–DC converter; phase shift PWM; ZVS; inrush current; MOSFET; telecom server

### **1. Introduction**

The spread of 5G technology in communications and telecom systems making universal electronic devices makes 5G technology one of the largest sources of electrical energy consumption, including such electronic devices usually operated with DC power, so that the supply AC voltage needs to be rectified. Conventional AC–DC rectifiers can be used to supply these devices, but circuit performance and power efficiency at high power density applications limit the use of such rectifiers; therefore, their energy efficiency must be increased. Recently, highly efficient AC–DC power supply with a high power factor has been modified for this purpose. Figure 1 illustrates the general construction of the AC–DC telecom power supply, where the two stages power supply consists of the power factor correction (PFC) stage and where the DC–DC output converter stage is the best option to get high power performance and good energy quality [1–3].

The design of power supply with a high input power factor requires the modifying of the input AC current waveform to follow the input voltage waveform to reduce the phase shaft between them, and then the reduction of the harmonic contents of the input current [3]. The power supply first stage usually includes an electromagnetic interference (EMI) filter, bridge rectifying circuit, boost converter, and output bulk capacitor; by controlling the boost converter operation, the input power factor can approach to, or near to, unity [4]. Single switch, two switches or full bridge switching topology can

be used to implement PFC boost converter, but switching topology proper switches must be used to withstand the output voltage stress of this stage normally (320–400 V) DC [1]. Different techniques and topologies of the analog control PFC stage of the telecom power supply with power factor more than 99% are previously discussed in [5].

**Figure 1.** Block diagram of the complete AC–DC power supply for a telecom server.

The power supply second stage is the target of this paper and it is designed to regulate the PFC output voltage to the required load voltage (usually 45–63 V) for the telecom applications. In this stage we must choose an appropriate technique to provide high power density conversion with high efficiency [6], DC–DC converter based on phase shifted ZVS technique is one of the most widely used techniques, because it has features to minimize the switching losses and offer better regulation over a wide load range [7]. Moreover, by using the ZVS technique, it is available to have high power density conversion with low voltage stress and small switching losses [8–10].

Switches on both sides of the high power density DC–DC converter must be designed to withstand the high voltage stress in the primary side and the high current stress in the secondary side [10]. So, one of the most important issue in designing DC–DC converter circuits is to choose the appropriate switching schematics for the converter to reduce the stress in the switches during the converter operation. Based on the phase shifted converter applications, phase shift pulse width modulation (PWM) converter can be implemented using different switching schematics (full bridge, half bridge, dual half bridge) in primary and secondary sides, and analysis of phase shifts isolated DC–DC converter different topologies previously given in [11]. Analysis and design of phase shift controller for a dual half bridge DC–DC converter is provided in [12]. Based on the application of DC–DC converter, it can be designed as an isolated or non-isolated converter; for the isolated DC–DC converter, transformer design and choice are a big challenge to have ZVS for the wide range of the load, which can reduce the switching and conduction losses [13]. Analysis of the phase shifted converter by using series connected transformers for low conduction losses are given in [14,15]. Design and implementation of the non-isolated phase shift ZVS converter is presented in [16].

DC–DC converter control circuits can be implemented using analog or digital control circuits, but analog control chip as compared with digital micro controller unit (MCU) has some demerits such as the temperature drift, fixed control parameters, and slow response speed; on the other hand the price of the MCU and the required analog digital interfacing sensors are expensive as compared with the analog control technique requirement. Optimization analysis and the design of different control techniques for the DC–DC converter have been previously presented in [17–21]. Design of 1 kW efficient phase shift telecom DC–DC converter based on the maximum duty cycle and optimal hold-up time is given in [22]. Controlling techniques to reduce the switching and conduction loss are presented in [23,24].

The bulk capacitor, which is introduced between the two stages of power supply as shown in Figure 1 for adjustment of the input voltage hold-up time and harmonic values of the input waveform, causes high inrush current for a few cycles where a very high "dv/dt" occurred at the initial power application to the power supply; this high dv/dt cause spikes of short-duration and a high peak current, which value may be higher than the circuit component rating current and can seriously damage or destroy these components [25–27]. So appropriate inrush current controlling circuit must be designed to limit such this current. Usually, limiting and reducing of the high inrush current is done by using a large size inductor or resistors in series with the input capacitors [28], but by using these techniques, converter compact design, and weight and power losses cannot be optimally utilized.

In order to reduce the power dissipation on the series resistor, a parallel semiconductor switch or relay can be connected through the resistance. However, based on the converter operating current, size of the relay can be also excessive large. Moreover, by using of a semiconductor switch an appropriate controlling circuit must be designed to control the switch operation. Another technique used to control the inrush current is by handling a soft starter time at the beginning of the DC–DC converter operation; soft starter technique works to limit inrush current based on controlling the duty cycle of the converter switches in order to slowly charge the capacitors, and hence reduce the high dv/dt for limiting the inrush current [29–31]; this technique is usually implemented to limit the inrush current inside the analog controller chips such as PWM controller integrated circuits (IC's) UCC256403 and UCC28950 from Texas Instruments, Dallas, Texas, United States, 2016 [32].

Recently, NTC thermistor is the most famous device used in reducing the inrush current generated in the telecom power supplies. An NTC thermistor has a compact size and a negative temperature coefficient, is connected in series with the input power supply, and when the current flows, its temperature will increase and the device resistance will decrease [33,34]. The shortcoming of this device is that it requires a cool off time after the stopping of the current flowing in order to return back the device high resistance.

Another more applicable and simple technique to limit the converter inrush current can be done using a single MOSFET switch connected with the input side of the DC–DC converter [35–37]. MOSFETs switches are usually considered as ideal devices because they are characterized by fast switching time due to majority carrier, lower switching losses due to fast rise and fall times, as well as very small on-state DC resistance, which helps to reduce the voltage drop through the switch at steady state operation [38]. Control of the inrush current to the required limit can be done by controlling the gate charge transfer characteristics of the MOSFET switch in order to control the slew rate of the input capacitance charging time [39]. This technique offers inrush current control with economic price, compact design, and simple implementation, without using any sophisticated control circuit for the MOSFET operation [38–40]. High reliability using this technique can be obtained with the appropriate choice of the MOSFET switch, as well as design of the biasing circuit schematic and the connection strategy to the input side of the DC–DC converter [41].

In this paper, complete design, analysis, and mathematical calculations of the circuit main components and control systems of 2 kW, 54 V telecom DC–DC converter stage with phase shift ZVS technique, using full bridge at primary and synchronous rectification at secondary side are presented. A sample inrush current controlling circuit based on using MOSFET switch is proposed and is inserted in the input side of the DC–DC converter, proposed controlling circuit schematics as well as design and choice of the circuit components are briefly discussed. The main advantages of the proposed circuit are that the controlling of the gate charge transfer characteristics of the MOSFET occurs without any contribution or connection with the DC–DC converter control circuit, which make the proposed circuit usable with analog and digital control converters, and has fast response and high reliability to control the inrush current to the required value as well as simple implementation for any converter with different input–output operation conditions. The designed main components and control system of the power supply circuit make the power supply output voltage performance follows the standard specifications IEC61000-3-3, which is required by telecom applications.

The result sections of this paper are organized as follow: first, simulation of the complete designed converter is performed using PSIM software to be sure that the reliability of the designed components enhances the required power supply performance. Then, an experimental setup of the designed converter with the proposed inrush current mitigation circuit is inserted between the power supply two stages is performed in the lab, which shows that the designed DC–DC converter with proposed inrush control circuit can achieve smooth startup operation at the input side, where efficiency is more than 95.5%, and with better voltage regulation at the output side of the converter.

### **2. Design Procedure of the DC–DC Stage of the Telecom Power Supply**

Figure 2 shows the schematic circuit of the telecom DC–DC converter stage with the proposed inrush current control circuit connected at the input side of the DC–DC phase shift converter. In designing the high-power density power supply with high conversion efficiency, losses in this stage must be maintained at their lowest value; one of the highest efficiency conversion techniques at high power density is the full bridge phase shift converter, which can offer very small switching losses by means of the ZVS technique at the converter primary side, which leads to increase the conversion efficiency [7,42].

**Figure 2.** Schematic diagram of DC–DC phase shift ZVS converter with the proposed inrush current control.

The most important components in the DC–DC converter stage to be designed in the next subsections are the input filter capacitor (*Cin*), inrush current control circuit, resonant inductor (*Lr*), transformer (*TR*1) turns ratio (a) and magnetizing reactance (*Lm*), and load inductance and capacitance (*Lload* and *Cload*). Other important factors are the choice of appropriate switches for the full bridge rectifier at the primary side and synchronous rectifier at the secondary side, which can withstand the high voltage stress at transformer primary and high current rated at secondary side [42].

### *2.1. Input Capacitor Design*

Input capacitor of the DC–DC converter is designed to meet the hold-up time (*thold*) for the minimum input voltage (*Vin min*) applied to the converter circuit [15,40], and can be calculated as

$$C\_{in} \geq \frac{2P\_o \ t\_{hold}}{\eta \left(V\_{in}^2 - V\_{in \,\,min}^2\right)}\tag{1}$$

where *Po* refers to the rated converter power, *Vin* refers to the Converter input voltage, and η is the designed efficiency of the DC–DC converter.

### *2.2. Proposed Inrush Current Control Circuit*

In this subsection the proposed inrush current control circuit based on the controlling of the gate charge characteristic of the MOSFET switch was designed to be used with any DC–DC converter topology (analog or digital); the proposed circuit was tested in PSIM software and also was implemented in the lab to show the power supply two stages (PFC and DC–DC converter) practical current characteristic with, and without, using this circuit.

The input of DC–DC converter stage usually contains filter to adjust the total harmonics distortion (THD) of the input voltage to the DC–DC converter. Input filters usually consist of passive elements such as capacitor and inductor; when power is initially applied to the DC–DC converter circuit, high inrush current will flow due to high dv/dt of the filter capacitor as illustrated in Figure 3, which shows the converter input current curves at initial power application to the converter circuit.

**Figure 3.** Inrush current at the startup operation of DC–DC converter.

Mathematical analysis, which briefly describes the startup response of the power supply operation and the phenomena of the inrush currents in DC–DC converters, are previously discussed in [26,27]. At the moment of applying the voltage to the DC–DC converter circuit, the current flowing through the input capacitor (*Cin*) can be expressed as

$$I\_{\rm Cin} = C\_{\rm in} \frac{dV\_{\rm in}}{dt} \tag{2}$$

This current has a high amplitude with very small duration and can damage or destroy circuit components if it exceeding the rating of the designed components. Therefore, this current must be effectively managed to ensure system safety operation and stability.

MOSFET switches are charge controlled devices, so if a MOSFET device is connected between two stages of the power supply, as shown in Figure 4, inrush current due to high *dVin*/*dt*, which is caused by the input capacitor (*Cin*) at the initial power application, can be controlled by controlling the initially high *dVin*/*dt* of the input capacitor by using the ability to control the constant linear slope of the drain voltage transition, which allows accurate control of the inrush current to the capacitive load. This is possible because the current flowing through the capacitor is dependent upon the transition of the voltage as shown in Equation (2). Reliability of this technique depends on the ability to control the MOSFET gate charge transfer curve illustrated in Figure 5 [29].

**Figure 4.** Proposed inrush current controlling circuit.

**Figure 5.** Gate charge transfer characteristics of MOSFET.

Figure 6 shows the equivalent representation of the MOSFET switch, where the gate charge curve is influenced by the MOSFET equivalent input capacitance [29].

**Figure 6.** Circuit of N-MOSFET.

Cgd and Cgs represents the gate-drain and gate-source capacitances, respectively; these two capacitance values represent the input capacitance of the MOSFET device. Usually for MOSFET, Cgd is greater than Cgs. So Cgd strongly influences the input capacitance of the MOSFET, this means that MOSFET input capacitance can control the inrush current value, if the value of Cgd is controlled. By inserting the appropriate design capacitance, *Cadd*, between the drain and gate terminals of MOSFET, as shown in the proposed circuit in Figure 4, Cgd can be controlled, which then can control the slew

rate of the gate-source voltage, *VGS*, which controls the slew rate of the input capacitance charging (*dVin*/*dt*), and consequently controls the inrush current of the circuit.

As shown in the characteristics in Figure 5, when MOSFET is turned on, the charging of the equivalent capacitance occurs at Region 1, and the charging time is determined by the equivalent input capacitance of MOSFET. The voltage (*VGS*) increases until the starting point of Region 2, where it reaches the threshold value (*Vth*). At this time drain current starts to flow and the rate of increase of drain current given by

$$\frac{dI\_{d\text{min}}}{dt} = \mathcal{g}\_f \frac{dV\_{GS}}{dt} \tag{3}$$

where *gf* is the switch forward trans-conductance and can be easily know from the switch datasheet.

At the end of Region 2, charging and discharging of Cgs simultaneously occurs, which causes *VGS* to be maintained constant at Miller plat voltage (*Vplt*) as shown in Region 3. With *Vplt*, the drain current is saturated at peak constant value dependent of *VGS* voltage value, and *Vplt* can be calculated as

$$V\_{plt} = V\_{tl} + \frac{I\_{drain}}{\mathcal{S}f} \tag{4}$$

The constant voltage of *VGS* causes the input gate current to flow through the additional capacitance *Cadd*, and can be calculated as

$$I\_S = \frac{V\_{GG} - V\_{\rm plt}}{R\_G} = \mathcal{C}\_{\rm add} \frac{dV\_{DS}}{dt} \tag{5}$$

$$V\_{GG} = V\_{in} \times \frac{R\_2}{R\_1 + R\_2} \tag{6}$$

where *RG* is designed and connected in a series with the gate for controlling the gate current *Ig*. Finally, by controlling the value of *VGS* and *Ig*, it is possible to control the maximum drain current of the MOSFET and control the inrush current at the initial power application to the power supply circuit, when the drain terminal of the MOSFET is connected to the return path of the DC–DC converter, as shown in Figure 4. *RGD*, a small value resistor, as compared with *RG*, connected with the *Cadd* and prevents unwanted high frequency oscillation [29]. Using Equations (5) and (6) inrush peak current value is approximately given by

$$I\_{\rm irreush} = -I\_{\rm drain} = g\_f \left( \mathbf{C}\_{\rm add} \times \mathbf{R}\_{\rm G} \times \frac{dV\_{\rm DS}}{dt} + V\_{\rm th} - V\_{\rm GG} \right) \tag{7}$$

The value of this current must be less than the maximum permissible DC current (inrush peak) of the primary side of the DC–DC converter stage.

Figure 7 shows the flow chart for the complete design procedure for the proposed inrush current control circuit by using the method of the controlling in the gate charge transfer characteristics of the MOSFET.

In Region 4, *VGS* still increases to higher values. If this voltage reaches a value higher than the gate source breakdown voltage (B*VGS*), MOSFET may be damaged; therefore, MOSFET must be protected at this region from the higher applied voltage; therefore, PFC output stage voltage (input voltage to the DC–DC converter) is divided using resistors R1 and R2 and only a small voltage is required to be applied to the MOSFET. Additionally, we can use one switch from the family of Zener-protected MOSFETs, such as switches from STMicroelectronics company [43]; in this protected switch, when the voltage applied to the switch is more than the breakdown voltage of the Zener (less than B*VGS*), the Zener diode breaks down and the voltage is saturated at the safe limit. The design result of the active inrush current control circuit, which used in simulation and experimental modeling is shown in Table 1.

**Figure 7.** Flow chart of design process of the proposed inrush current control circuit.


**Table 1.** Design Results for Active Inrush Current Control Circuit.

### *2.3. Transformer (TR1) Turns Ratio (a) and Magentizing Reactance (Lm) Calculation*

Transformer turns ratio (a) is calculated based on maximum operating duty cycle (*Dmax*) at the minimum input voltage rating of the converter (*Vin min*) as follows:

$$a = \frac{N\_P}{N\_S} = \frac{V\_P}{V\_S} \tag{8}$$

Let *Dmax* be about 70% and *Vin min* about 320 V, and the transformer turns ratio is calculated as

$$a = \frac{V\_P}{V\_S} = \frac{(V\_{in\ min} - 2VD\_Q)D\_{\max}}{V\_{load} + VD\_Q} = 4.1\tag{9}$$

where *VDQ* is the switch voltage drop and it is assumed to be 0.5 V in calculations.

Let *a* = 5, the typical operating duty cycle (*D*), is calculated as

$$D = \frac{\left(V\_{\text{load}} + V D\_Q\right)a}{\left(V\_{\text{in}} - 2VD\_Q\right)} = 0.68\tag{10}$$

Transformer magnetizing inductance (*Lm*) designed based on the maximum magnetizing inductance to realize ZVS as expressed in [13,18], and can be expressed as

$$L\_{m} = \frac{T\_{dead} \text{ a } V\_{load\\_min}}{C\_{HB} \text{ } V\_{in\\_min}} \times \left(\frac{T\_{s\\_min}}{4} - \frac{T\_{dead}}{2}\right) \tag{11}$$

where *CHB* refers to the total equivalent capacitance of the primary H bridge, which can be known from the primary switch data sheet. *Ts min* is the minimum switching time depends on the designed minimum switching frequency, also *Tdead* is the PWM dead time which can be calculated according to the previously calculated duty ratio.

One more important issue is the choosing of a transformer with appropriate magnetizing inductance to minimize the output current ripple and to make sure that the converter works in the required control mode, where the smallest value of magnetizing inductance makes the converter work in voltage control mode instead of current control mode [10].

### *2.4. Resonant Inductor (Lr) Design*

Resonant inductor tank is calculated based on the amount of energy required to achieve ZVS condition. The energy absorbed by the inductor values of the resonant inductance (*Lr*) and the transformer leakage inductance (*Llk*) must be able to exhaust the energy supplied by the average parasitic capacitance of the primary switches (*Cossavg*), and also the energy from the transformer winding capacitance (*Cw*) [42,44].

$$\frac{1}{2}I\_P^2(L\_r + L\_{\text{lk}}) \ge \frac{4}{3}\mathbb{C}\_{\text{cosaw\%}}V\_{\text{in}}^2 + \frac{1}{2}\mathbb{C}\_{\text{uv}}V\_{\text{in}}^2\tag{12}$$

where *IP* refers to the converter primary current (A).

### *2.5. Output Inductance and Capacitance (Lload and Cload)*

Output load inductor (*Lload*) is designed based on 10% ripple value in the load DC current (*Iload*), as follows:

$$
\Delta I\_{load} = \frac{P\_{load} \times 0.10}{V\_{load}} \tag{13}
$$

$$L\_{load} = \frac{V\_{load} \times (1 - D)}{\Delta I\_{load} \times F\_s} \tag{14}$$

Output load capacitor (*Cload*) is selected based on hold-up time (*thu*) and 20% (200 mV) of the allowable load transient voltage (*Vtran*) as follow:

$$C\_{load} \ge \frac{0.9 I\_{load} \times t\_{hu}}{0.2 V\_{trau}} \tag{15}$$

where hold-up time (*thu*) is calculated as the time required for the inductor current to reach to 90% of the full load current [41].

$$t\_{\rm llu} = \frac{L\_{\rm load} \times 0.91\_{\rm load}}{V\_{\rm load}} \tag{16}$$

### *2.6. DC–DC Converter Controller Design and Implmentation*

Phase shift PWM technique is used to control the full-bridge in the primary side of the DC–DC converter by phase shifting the switching pulses of one half-bridge with respect to the other. High power density efficient conversion is available using ZVS technique at high switching frequency in this part. Voltage-mode or current-mode control techniques can be used in this part. Current-mode controlled DC–DC switching is popular and provides a more highly efficient power conversion than voltage mode control. However, the current-mode design can suffer from instability when the duty cycle of the PWM rises above 50% [45]. To overcome this instability, converter primary current slope compensation technique is used to restore reliability over the wide range of duty-cycle [19,46].

Figure 8 shows the schematic of control technique of DC–DC converter, implemented in PSIM software where the primary current and the output voltage are the feedback signals used in this control system. First, primary current is sensed using current transformer with turns ratio (100:1) and then sampled by a resistor to get a primary current signal (VIp); load voltage (*Vload*) signal is also sensed. To overcome the instability in current waveforms at high duty cycles, value slope compensation technique with the ramp signal of 200 kHz is added to the VIp signal to generate the primary current (Iprim); output DC voltage signal is compared with the appropriate reference value and passed to the voltage PI controller to generate the primary current reference value (Iprim-ref), then the primary current (Iprim) is compared with reference value (Iprim-ref) to generate the duty cycle of the PWM generator for the primary and secondary switches QA, QB, QC, QD, QA1, and QB1.

**Figure 8.** Technique of the phase shift PWM DC–DC converter controller.

Table 2 shows the input/output specifications and the results of the design converter main components of the DC–DC converter.



### **3. Simulation Results and Discussions**

Phase shift DC–DC converter with power density about 2 kW has been implemented in PSIM software using the designed components in the previous sections to show the system performance under different loading conditions and to test the reliability of inrush controlling circuit to limit the high inrush current at initial power application to the primary side of the power supply circuit.

With full load condition and DC input voltage about 400 V, Figure 9 shows the steady state simulation result of the DC output power curve of the DC–DC converter.

**Figure 9.** Converter output power curve at full load condition.

The designed power supply efficiency curve at loading condition from 10% to 100% of the rated output power (2 kW) with input voltage 400 V and switching frequency about 100 kHz is illustrated in Figure 10, which shows that the designed power supply offers full-load efficiency at about 95.1%, half-load efficiency at about 95.3%, and the maximum being three-quarter-load efficiency at about 95.6%.

**Figure 10.** Converter efficiency curve with different loading condition at *Vin* = 400 V.

As mentioned before in Section 2.2, the gate charge transfer characteristics of the MOSFET switch can be used to control the slew rate of the input capacitance charging in order to control and limit the inrush current to the required value. Figure 11 shows the bulk input capacitance charging voltage curves with, and without, using the proposed inrush current control circuit, where the black curve refers to the supply DC input voltage, the red curve is the voltage curve of the input capacitance without using the proposed control circuit, and the blue curve is the voltage curve of the input capacitance using the proposed control circuit. From these curves, it is clearly observed that controlling the slew rate of VGS voltage by controlling the input capacitance of the MOSFET, leads to the reduction of the high dv/dt of the input capacitance, which subsequently reduces the inrush current at initial power application.

**Figure 11.** Bulk input capacitance charging voltage with and without using the proposed control.

Waveforms of the average value of the converter input current at switching frequency of 100 kHz with, and without, using the inrush current control circuit are shown in Figures 12 and 13, respectively. From both cases, and as the result of controlling the voltage slew rate at the initial power application to the converter circuit based on the transition time, which is required to meet the required inrush current, we can notice that the proposed controlling circuit reduced the peak inrush current from 16.10 A to about 6.40 A, which is in the allowable range (given in Table 1) of the input DC current to the primary side of DC–DC converter; moreover, it is clear to observe that the peak value of the input current at steady state with full load condition is about 8.20 A in both cases.

**Figure 12.** Converter input current without inrush current mitigation circuit at full load and *Vin* = 400 V.

**Figure 13.** Converter input current with inrush current control circuit at full load and *Vin* = 400 V.

Figure 14 shows the VGS and Idrain characteristics of the MOSFET in the inrush current control circuit. When the VGS voltage reached to Vth (about 3.75 V) of the used MOSFET switch, the drain current starts to increase, at the point when VGS reaches *Vplt*, and circuit inrush current tries to increase but based on the gate charge transfer characteristic depicted in Figure 5, drain current saturated at constant value about 6.40 A as shown in the simulation result. Additionally, from this figure it is clearly observed that the protection of the MOSFET switch, which occurred at Region 4 when the Zener diode circuit broke down before the voltage reached 30 V (B*VGS* of the used MOSFET) and the voltage was saturated at about 28.5 V.

**Figure 14.** Gate charge waveform of the MOSFET in inrush current mitigation circuit.

Phase shift PWM controlling circuit and the resonant inductor are designed to offer ZVS at the two legs of the bridge at the primary side of the DC–DC converter switches, as shown in current and voltage waveforms of the switches (QA and QC) in Figures 15 and 16.

**Figure 15.** Voltage and current waveforms of switch QA converter primary side at *Po* = 2 kW.

**Figure 16.** Voltage and current waveforms of switch QC in converter primary side at *Po* = 2 kW.

### **4. Experimental Setup**

The complete designed converter circuit and the proposed inrush current mitigation circuit are experimentally setup and tested with the available maximum DC electronic load in the lab (1000 W), UCC28950 phase shift PWM controller IC from Texas Instruments, Dallas, Texas, United States, 2016 is used to control the DC–DC converter switches, UCC28950 IC provide 4-PWM signals with constant frequency (100 kHz) for the primary side switches, and 2-PWM for the synchronous rectification at the secondary side switches with the availability of the primary current compensation to restore the current stability and the voltage loop control to adjust the output voltage at the specified value.

The proposed inrush current mitigation circuit was tested with the practical case of the telecom two stages AC–DC power supply, where the DC–DC converter was supplied by the PFC converter stage with output voltage of 400 V DC. In order to show the reliability of the proposed inrush current control circuit in mitigation of the high current overshot in the input current to the converter, soft starter of the analog UCC28950 IC is disabled through the (SS/EN) pin and only the proposed inrush current control circuit is connected to the input side of the DC–DC converter circuit.

Figure 17 shows the appearance of the experimental setup of the complete power supply consisting of PFC and DC–DC converter stages and with using the proposed inrush current control circuit connecting in between. 1000W KIKUSI PLZ1004WH, Japan, 2019 DC electronic load was connected at load side, and 2.5 kW PFC converter stage from Infineon with average efficiency more

than 95% [47], inrush current control circuit was connected between the two stages and the input AC voltage was applied to the input of the PFC stage so that the output voltage will be 400 V DC, input current to the both stages has been measured using high scale current probe FLUKE i1000s, USA, FLUKE company with scale choice of (10:1) A with, and without, connecting of the proposed inrush current mitigation circuit.

**Figure 17.** Experimental setup of DC–DC converter circuit with inrush current mitigation circuit.

Figures 18 and 19 show the DC–DC converter stage input current, from which we can investigated that with using inrush current control circuit, the inrush current at the startup of the converter is reduced from 20.32 A to about 4.06 A. Additionally, in both figures, differences in current shape and starting time of each waveform can be observed, this occurred due to changing in the slew rate of the input capacitance voltage, which leads to limit the inrush current at the safe limit using the inrush current controlling circuit, in Figure 19, with the current still increasing gradually until it reached to 4.06 A, at this moment, and as explained before in the controlling circuit characteristics in Figure 14, the drain current is saturated at the safe limit to prevent the inrush current from increasing to higher limits.

Figures 20 and 21 show the PFC converter stage AC input current, from which we can investigate that by connecting the proposed inrush current control circuit between the two stages of the power supply, the peak overshoot of the input current to the PFC stage will reduced from 33.55 A to 15.33 A. Additionally, the difference is noticed between starting time and waveform shapes, due to the controlling of the slew rate of the input voltage by using the proposed inrush current control circuit.

**Figure 18.** DC–DC converter stage input current without using of the proposed inrush current mitigation circuit.

**Figure 19.** DC–DC converter stage input current with using of the proposed inrush current mitigation circuit.

**Figure 20.** Power factor correction (PFC) converter stage AC input current without using of the proposed inrush current mitigation circuit.

**Figure 21.** PFC converter stage AC input current with using of the proposed inrush current mitigation circuit.

Figure 22 shows the converter output voltage and current waveforms at steady state operation using the inrush current control circuit, in which the converter DC output power was about 1085.25 W, where the output voltage was constant at about 54.02 V and current value was about 20.090 A.

**Figure 22.** DC–DC converter stage output voltage and current waveforms at *Vin* = 400 V.

DC–DC converter output filter capacitor was designed to maintain the output voltage ripple to the specified value as explained previously in Section 3; in order to clearly observe the ripple component in the output voltage waveform, the vertical axis scale of the voltage was changed and the measurement set in scope was adjusted to measure the ripple peak to peak value and the mean value of the voltage waveform, as shown in Figure 23, which clearly shows that the peak to peak ripple voltage is about 34.4 mV (less than the designed value 200 mV) and the mean output voltage value is about 54.094 V.

**Figure 23.** DC–DC converter stage output voltage ripple peak to peak measurement at *Vin* = 400 V.

In case of designing the DC–DC converter stage for the telecom applications, voltage controller must be implemented in order to achieve different loading condition with good voltage regulation. Figure 24 depicts the output voltage versus output power, which shows that the designed DC–DC converter with the proposed inrush current controlling circuit also provides different loading conditions with good voltage regulation, where the voltage drop is less than 1 V (1.85%) for changing loading conditions from 200 W to 1000 W, which is less than the IEC61000-3-3 standard limit for the limitation of the voltage changes (3.3%) [48].

**Figure 24.** DC–DC converter load voltage-power characteristics at *Vin* = 400 V.

The inrush current control circuit, designed and connected between the two stages of the power supply, to control the inrush current at the initial power application to the power supply, must not effect the performance of the PFC stage at steady state operation. To study the effect of the proposed inrush current control circuit on the PFC converter performance, power analysis of the input side of the PFC converter have been performed with, and without, using the inrush current control circuit with the same loading and input voltage conditions as shown in Figures 25 and 26, which clearly shows that the reduction in the inrush current of the input supply at initial power application leads to a reduction in the supply total reactive power from 103 VA to about 90 VA, and it can also clearly be observed that the power factor value of the power supply was not affected by the connection of the proposed circuit.

**Figure 25.** PFC converter stage power analysis with using of the proposed inrush current mitigation circuit.

**Figure 26.** PFC converter stage power analysis without using of the proposed inrush current mitigation circuit.

As shown in Figure 22 the total input power to the two stages with inrush current control circuit is about 1171 W, and as shown in Figure 25, the load power is about 1085.25 W, so the power supply includes about 85.75 W power losses, distributed as 39.5 W in the PFC stage with efficiency of about 96.62% and 46.25 W in DC–DC converter and inrush current control circuit, with efficiency of about 95.73%, which is very close to the simulation results (95.40%) at the same loading. Total losses distribution in the system different parts are performed and the result is depicted in Figure 27.

**Figure 27.** Losses distribution in different parts of the two stages power supply with inrush current control.

From the loss distribution of the power supply, it is noticed that the highest budget of the DC–DC converter losses was accounted by the primary side bridge and the resonant inductor with about 20 W; this loss amount is due to primary side switches internal resistance and forward voltage drop, and also due to the internal DC resistance of the resonant inductor. The second highest budget of the power losses accounted in the secondary side synchronous switches with about 10.5 W. Power loss of about 6 W was dissipated in the converter transformer primary and secondary DC resistances. Internal DC resistance of the output filter inductor and the equivalent series resistance (ESR) of the output electrolytic capacitor introduce power loss about 3 W. The remaining converter power losses budget was accounted by the proposed inrush current control circuit and the ESR of the bulk input

electrolytic capacitor. One disadvantage of the proposed inrush current, is that it has an amount of about 5 W of the total supply power losses, but on the other hand, it has many advantages, which can be summarized in the following:


### **5. Conclusions**

Complete design of a high power density efficient DC–DC converter stage of the telecom power supply has been discussed in this paper; a high inrush current, which is generated between two stages of power supply where the bulk input capacitor is controlled using the proposed simple inrush current control circuit designed by using single MOSFET switch and some passive elements. Simulation analysis as well as experimental setup of the practical two stages telecom power supply and inrush current control circuit is performed. Phase shifted PWM with ZVS technique is applied in DC–DC converter stage, which provided system experimentally overall efficiency about 95.73% at 50% loading condition. Furthermore, reliability of the converter designed components to achieve the performance of the telecom power supply was established; ability of the proposed inrush current control circuit to control the slew rate of the input capacitance voltage in order to reduce the high dv/dt and to mitigate the inrush current of the input current of the two stages of power supply was also achieved, which ensures a safe and smooth startup operation of the power supply.

**Author Contributions:** The literature review and manuscript preparation, as well as the simulations, were carried out by A.H.O. Experimental results and implementation of the prototype were carried by A.H.O. and J.B. Final review of manuscript corrections was done by N.K. and J.B. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by grant (2018R1D1A3B0704376413) from National Research Foundation of Korea (NRF) and grant (18RTRP-B146050-01) from Railroad Technology Research Program (RTRP) funded by Ministry of Land, Infrastructure and Transport of Korean government.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **Methods of Modulation for Current-Source Single-Phase Isolated Matrix Converter in a Grid-Connected Battery Application**

### **Goh Teck Chiang \* and Takahide Sugiyama**

Toyota Central R&D Labs Inc., Nagakute City 480-1192, Japan; t-sugiyama@mosk.tytlabs.co.jp **\*** Correspondence: tcgoh@mosk.tytlabs.co.jp

Received: 29 May 2020; Accepted: 21 July 2020; Published: 27 July 2020

**Abstract:** This paper discusses three methods of modulation for a single-phase isolated matrix converter. The matrix converter is combined with a transformer integration to perform power decoupling control in order to reduce the number of component and capacitor volumes. Due to the reason of (i) Alternating current (AC/AC) direct conversion and (ii) transformer integration, obtaining a clean sinusoidal grid current waveform in the modulation of matrix converter (MC) is important. Three methods of modulation are compared in terms of control complexity, quality waveform, and inductive-capacitive-inductive (LCL) filter sizing. The principal control of each method is described. Finally, a prototype was tested to verify the validity and the effectiveness of grid current control and power decoupling in the spoken circuit structure.

**Keywords:** AC/AC conversion; decoupling control; modulation

### **1. Introduction**

The rapidly expanding growth of battery storage system (BSS) has urged high demands for a single-phase power converter. Figure 1a shows the applications such as home energy management system (HEMS), uninterruptible power supply (UPS), and small-scale datacenter, which uses a single-phase power converter as an interface between BSS and grid (AC 80–240 V 50/60 Hz). These applications require isolation and typically rate from 1–3 kW with a high voltage battery (100–300 V). As the price of battery is expected to reach a new low in the near future, a low cost and small size single-phase power converter is highly demanded.

**Figure 1.** (**a**) Single-phase power converter for a grid-connected battery application. (**b**) Conventional circuit structure consists of a dual-active bridge (DAB) and a single-phase inverter (SPI).

Figure 1b shows the conventional circuit for a single-phase power converter. The circuit is composed of a dual-active bridge (DAB), a single-phase inverter (SPI), and an LCL filter [1,2]. The size reduction of a single-phase power converter is challenging because of using many passive components. Several studies have focused on reducing the size of inductive component such as inductor and transformer by using a high frequency technique [3–5]. However, the major size of the converter is occupied by the capacitors *Cdc* that are used to absorb the single-phase power fluctuation. Due to the reason of current limitation in the electrolytic capacitor, capacitors are connected in parallel to form a big capacitor bank in order to absorb the single-phase power fluctuation.

The matrix converter (MC) shows a promising solution for size reduction because the capacitor can be removed [6,7]. Hence, MC can convert high frequency transformer voltage (i.e., 50 kHz) to low frequency voltage (i.e., 50 Hz), at the same time controlling the current flow bidirectional. However, for a single-phase application, a low frequency current that contains twice of the grid frequency occurrs in the battery side due to the direct AC/AC conversion. Depending on the type of battery, such as lithium battery, the single-phase fluctuation in the battery needs to be eliminated in order to protect the battery from overvoltage.

Single-phase active power decoupling techniques have been discussed and reported for compensating the single-phase power fluctuation [8,9]. A power decoupling circuit can be considered to add between the battery and full-bridge inverter (FBI) in order to compensate the single-phase low frequency current. Figure 2 shows a conventional circuit structure that consists of a power decoupling circuit, a FBI, and a MC. The power decoupling circuit consists of an inductor *Lb*, a capacitor *Cb*, a diode, and two switching devices. The single-phase power fluctuation is compensated by charging and discharging the capacitor *Cb* according to the grid phase angle. As a result, the single-phase power fluctuation can be eliminated with a smaller capacitor than the conventional capacitor bank.

**Figure 2.** Circuit structure consists of a power decoupling circuit, a full-bridge inverter (FBI), and a matrix converter (MC).

The required capacitance in a single-phase converter can be defined by Equation (1).

$$\Delta v\_b \ge \frac{p\_{\text{cap}}}{2 \times \pi \times 2 \times f\_{\%} \times \Delta v\_{cb} \times v\_{cb}} ; \Delta v\_{cb} = v\_{cb \text{max}} - v\_{cb \text{min}} \tag{1}$$

where *vcb* is the average battery voltage, Δ*vcb* is the capacitor voltage difference, and *fg* is grid frequency. Figure 2 shows that a 1 kW calculation (capacitor power (*pcap*) is half of the rated power), by using the power decoupling control to increase the capacitor voltage difference Δ*vcb* to 50 V, the required capacitance can be reduced by 80% comparing that to the conventional circuit at the same rated power.

However, the major drawback is that this circuit requires extra switching devices and passive component. Here, an integration technique that utilized the center-tapped of a transformer has been discussed, as shown in Figure 3 [10,11]. The center-tapped of the transformer is utilized by connecting the passive components (*Lb* and *Cb*) in order to perform the power decoupling control. Then, the FBI controls the high frequency transformer voltage and the capacitor voltage at the same time, therefore the switching devices in the power decoupling circuit can be reduced.

Without the transformer integration, the power decoupling circuit can be individually controlled and the method of modulation for the matrix converter is rather simple. Literature reviews [12–14] have demonstrated several valid modulations for the MC, where a good quality waveform can be obtained without the need for concern for the power decoupling. However, when the transformer integration is applied with MC, the modulation for MC has to be changed in order to synchronize with the FBI to obtain a proper voltage period. The failure of obtaining a clean sinusoidal waveform can distort the battery current inherently, because this capacitor cannot absorb the current fluctuation.

**Figure 3.** Circuit structure consists of a full-bridge inverter (FBI) with a transformer integration decoupling control and a matrix converter (MC).

This paper discusses three methods of modulation for the MC that is applied with the transformer integration. The first conventional method is a carrier comparison with a D-FF and the second conventional method is a delta-sigma conversion based on pulse density modulation (PDM) which have been addressed in [15–17]. This paper introduces a third method which is a carrier comparison with a zero-vector commutation, and further discusses the difference of each method. The details of each method is described individually. Then, the comparisons among these methods in term of (i) control complexity, (ii) waveform quality, and (iii) LCL sizing are discussed. Then, the validity of the modulation along with comparison results is shown. Finally, a 1 kW prototype was tested to show the validity of the power decoupling with a MC.

### **2. Control Scheme**

### *2.1. System Control*

The system control block diagram is shown in Figure 4. The control is divided into two parts: (i) Voltage and current closed-loop controls in FBI and (ii) grid voltage and current with a phase locked loop (PLL) in MC. The FBI is performed as a voltage source to control the high frequency transformer voltage *vts* and capacitor voltage *vcb* at the same time. Then, the high frequency transformer voltage is fed into the MC, and therefore MC is performed as a current source converter to control the grid current.

**Figure 4.** System control block diagram, full-bridge inverter (FBI) controls the voltage level and matrix converter (MC) controls the current for the single-phase power converter.

In FBI, a low time response of automatic voltage regulator (AVR) is applied to control the capacitor voltage proportionally to half of the battery voltage. Then, the grid phase angle which is calculated from the PLL in the grid control is added to control the phase angle of the inductor current. Then, a high time response current control (automatic current regulator ACR) is applied into the inductor current control. Note that the input of phase angle in the FBI control is also used to enable or disable the power decoupling control (where 0 is disabled).

Since the MC is a current source controller, a normalized grid voltage command is feed-forwarded into the controller. Then, a high time response current control is applied into the grid inductor current, where a sinusoidal duty command (*Dmc*) is used to generate the corresponding gate signals.

Figure 5 shows the principal control of the power decoupling. The relationship among the grid power *pg*, battery power *pbat*, and capacitor power *pcb* is defined in Equation (2), where *pavg* is the average power and μ*<sup>o</sup>* is the grid phase angle. When subjected to the frequency of the grid power, the battery current contains twice the grid frequency.

$$p\_{\%} = p\_{\text{bat}} - p\_{\text{cb}}; \; p\_{\text{cb}} = p\_{\text{avg}} \cos(2\omega\_0 t) \tag{2}$$

**Figure 5.** Principle control of power decoupling, charging and discharging states in the capacitor are used to compensate the single-phase current that occurs in the battery current.

In the power decoupling, the capacitor power is divided into a charging and discharging state. When the grid power is lower than the average power, this period is known as a charging state. During the charging state, the battery power is loaded into the capacitor by controlling the center-tapped inductor current. Then, the capacitor voltage difference Δ*vcb* increases from *vcbmin* to *vcbmax* during this period.

When the grid power is higher than the average power, this period is known as a discharging state. During the discharging state, the previously charged power in the capacitor is discharged by the center-tapped inductor current. Then, the capacitor voltage difference Δ*vcb* decreases from *vcbmax* to *vcbmin* during this period. Since no power delivery is needed from the battery, the battery current remains at its average value. By repeating these two cycles according to the grid phase angle, the capacitor voltage difference is controlled to compensate the single-phase current in the battery.

### *2.2. Switching Behaviors in FBI*

The switching behavior and current relationships in FBI are described. Figure 6 shows the relationships between the two current components (DC and AC) in the FBI. The DC current component occurs when the DC/DC conversion is performed between the battery voltage and capacitor voltage. In this case, the FBI is equivalent to a buck converter with a 180 degree phase shift. Two DC currents, *iLb1* and *iLb2*, are manipulated with the duty to control the center-tap connected inductor current and capacitor voltage, which can be defined in Equations (3) and (4).

$$
\omega\_{cb} = D\_{fbi} \times v\_{bat}.\tag{3}
$$

$$
\dot{a}\_{Lb} = \dot{a}\_{Lb1} + \dot{a}\_{Lb2};\tag{4}
$$

where *vcb* is the capacitor voltage, *vbat* is the battery voltage, *D* is the duty of FBI, and *iLb* is the inductor current.

**Figure 6.** Relationship between the two current components in FBI.

On the other hand, the AC current component occurs when the battery power delivers the grid via the transformer, which is the transformer current. The AC current component is controlled with corresponding to the modulation of MC, which is equivalent to the grid inductor current. Therefore, the relationship between the transformer current and grid inductor current can be expressed as Equation (5).

$$i\_{tp} \times N = i\_{ts} = i\_{\mathbb{g}^l} \text{:} \tag{5}$$

where *itp* is the primary side current (FBI), *its* is the secondary side current (MC), *N* is the transformer ratio, and *igl* is the grid inductor current.

According to the state of the capacitor (charging or discharging) and the amplitude of the battery current, the total of four switching behaviors can be summarized as shown in Figure 7. The zero-voltage periods of FBI (S1S3 or S2S4 are turned on) are utilized to discharge and charge the inductor current.

During the discharging state, the battery current needs to be reduced and therefore the charged energy in the capacitor *Cb* discharges to the battery side. When S2S4 are turned on, the current circulates via S2 and S4 to keep the charged energy. When S1S3 are turned on, the charged energy in the inductor is released to the battery via S1 and S3. The current cancellation between the battery current and inductor current reduces the high peak of the battery current.

During the charging state, the battery current needs to be increased and therefore the low peak of the battery current charges into the capacitor *Cb*. Here, when S1S3 are turned on, the battery current flows via S1 and S3 to charge inductor *Lb*. Then, when S2S4 are turned on, the charged energy in the inductor circulates via switching devices.

**Figure 7.** Switching behavior of full-bridge inverter (FBI) according to the state of capacitor and amplitude of the battery current.

### *2.3. Modulation in MC*

In MC, a low frequency voltage pulse width is formed to control the grid inductor by accumulating from the high frequency transformer voltage *vts*. The high frequency transformer is controlled by FBI which is magnetized from the battery voltage. As shown in Figure 8, the switching sequence is divided into positive and negative voltage periods according to the polarity of the grid voltage. Then, each of these voltage periods is implemented with zero-vector periods in order to discharge the grid inductor current. As a result, the method of modulation is used to control the length of these voltage periods in order to control the 50 Hz grid inductor current sinusoidal.

**Figure 8.** Modulation in matrix converter (MC), zero-vector periods are implemented in both positive and negative voltage periods.

Figure 9a shows the switching behavior in MC, which can differ to normal switching states and zero-vector periods. When the gate signals S5S8 are turned on, the grid inductor is induced by the positive transformer voltage to charge the grid inductor. Otherwise, when the gate signals S6S7 are turned on, the grid inductor is then induced by the negative transformer voltage. On the other hand, when the gate signals S5S7 (or S6S8) are turned on, known as the zero-vector periods, a circulating loop is created inside the switching devices to allow the grid inductor current to circulate and discharge the energy in the grid inductor.

**Figure 9.** Switching behaviors in matrix converter (MC). (**a**) Normal switching states and zero-vector periods. (**b**) Zero-voltage switching (ZVS) relationship between full-bridge inverter (FBI) and matrix converter (MC).

Furthermore, Figure 9b illustrates the zero-voltage switching (ZVS) relationships between FBI and MC. Since the transformer voltage is magnetized from the battery voltage, a three-level high frequency transformer voltage can be produced. That is, when gate signals S1 S3 or S2 S4 in FBI are turned on, no voltage-product occurrs in the MC. These zero-voltage periods are utilized in the switching intervals of MC to reduce the switching loss. During the gate-off transition, the drain-source voltage of switching devices drops to zero before the gate signal is turned off. Then, during the gate-on transition, the gate signal is turned on before the voltage is applied to the switching devices. Therefore, both of the transitions can achieve ZVS.

However, the leakage inductance of the transformer needs to be taken into consideration during the switching intervals. The energy in the leakage inductance needs to be discharged while the transformer current changes the direction. Here, the approach is to use the grid inductor current to cancel out with the leakage inductance current during the switching intervals. Figure 10 explains and illustrates the phenomenon, where the positive transformer voltage is changed to the negative transformer voltage while the grid side produces a positive voltage.

As shown in Figure 10, the transformer voltage becomes zero before the switching intervals start. Then, following that the S6AB and S7AB are turned on in the next switching interval. During this state, the leakage inductance current is used to discharge the capacitance S5A and also charge the capacitance S6B. At the same time, the grid inductor current is flowing via S6AB in a reverse direction, as a result the leakage inductance current and grid inductor current cancel out each other. The same phenomenon applies to S7AB and S8AB, capacitance S7B is charged and capacitance S8A is discharged by the leakage inductance current. Then, the grid inductor current is flowing via S7BA in an opposite direction to achieve the current canceling.

As a result, forming an accurate voltage period, achieving ZVS, and current cancelling at the same time is important in the method of modulation.

**Figure 10.** Current cancelling in matrix converter (MC) to discharge the leakage inductance current during switching intervals.

### **3. Methods of Modulation**

### *3.1. Carrier Comparison with D-FF (D-FlipFlop)*

The first method is to use a D-flipflop (D-FF) function, the control block diagram is shown in Figure 11. A carrier comparison with *Dmc* is used to generate two sets of switching signals SPQ and SNQ. When SPQ and SNQ are both turned on zero-vector periods are formed. These two switching signals are inputted to a D-FF, where the D-FF is synchronized with the CLK, and a XNOR logic is applied to produce gate signals for S5–S8. The CLK is used to synchronize the switching intervals of MC with the zero-voltage periods of FBI in order to achieve ZVS.

**Figure 11.** Carrier comparison with the D-flip flop block diagram.

However, D-FF creates a voltage error due to the occurrence of improper time length. Figure 12 shows the relationships among switching signals SPQ SNQ, gate signals S5–S8, and voltage pulse width. First, SPQ and SNQ form the required voltage pulse width accordingly based on the carrier comparison. After the SPQ and SNQ are aligned with D-FF, the voltage pulse width applied to the grid inductor either becomes longer or shorter than the original voltage pulse width. These improper pulse widths create voltage errors and the average grid inductor current is misadjusted. As a result the grid current fluctuates irregularly.

### *3.2. Delta-Sigma Conversion with Pulse Density Modulation (PDM)*

In order to eliminate the voltage error, a delta-sigma conversion which is based on pulse density was discussed. Figure 12 shows the control block diagram and Figure 13 shows the relationship between duty *Dmc* and quantization error *Qr*. The carrier comparison is not applied because the integral changes corresponding to the quantization error. One cycle of the quantization level is equivalent to one cycle of the CLK. The *Qr* is obtained based on the differential value between the *Dmc* and *Dmc*. Note that the amplitude of *Dmc* does not change according to the grid current command (*ig*\*) but the

level of quantization error changes depending on the pulse density. As shown in Figure 14, the original middle point is *Dmc* = 0.5. Then, the level of *Qr* changes depending on the pulse density that is used to form the grid current command, which is *Qr* > *Dmc* or *Qr* < *Dmc*. The comparison between the *Dmc* and *Qr* produces the corresponding voltage signals Sa and Sb in order to produce the desired voltage pulse width. EXOR logic is applied to Sa and Sb to synchronize with CLK in order to produce gate signals.

That is, when *ig* needs to increase, a longer voltage pulse width is required and therefore *Qr* gets higher than *Dmc*. On the other hand, when *ig* needs to decrease, a shorter voltage pulse is required and *Qr* gets lower than *Dmc*.

These phenomenon are illustrated in Figure 15, where (a) *Qr* < 0.5 and (b) *Qr* > 0.5. In Figure 15a, in order to decrease the grid current, most of the *Qr* periods are lower than *Dmc*, then Sa produces a short voltage signal only when *Qr* is higher than *Dmc*. On the other hand, in Figure 15b, in order to increase the grid current, a longer voltage pulse is required. Notice that the level of *Qr* increases, and most of the *Qr* periods are higher than *Dmc* to produce the desired voltage pulse width. As a result, the grid current can be controlled sinusoidal without the voltage error, and ZVS can be achieved by synchronizing to CLK.

**Figure 12.** Relationship among CLK, SPQ, SNQ, MC voltage, and the grid inductor current are shown to demonstrate the voltage error in D-flip flop.

**Figure 13.** Delta-sigma conversion block diagram.

**Figure 14.** Principle control of delta-sigma, where quantization error changes according to the power level in order to obtain the desired pulse width (*Qr* > *Dmc* or *Qr* < *Dmc*).

**Figure 15.** Relationship among CLK, *Dmc*, *Qr*, MC voltage, and the grid inductor to demonstrate the control of delta-sigma. (**a**) *Qr* < 0.5. (**b**) *Qr* > 0.5.

However, without the carrier comparison the integral resets the value depending on the quantization level at a random frequency, as shown in Figure 16. As a result, the grid current ripple has an inconsistent frequency which causes a resonance problem during thelow output power [18]. Furthermore, the resonance also occurs in the battery current due to the AC/AC direct conversion. Note that this resonance cannot be compensated in the single-phase power decoupling, therefore one approach is to decrease the cut-off frequency of the LCL; however, the size of LCL needs to increase as a drawback.

### *3.3. Carrier Comparison with Zero-Vector Commutation*

The method of carrier comparison with zero-vector commutation is shown in Figure 17. This control is implemented with a constant frequency and a commutation to eliminate voltage error. A carrier comparison which is based on the pulse width modulation (PWM) is used and compared with *Dmc* to generate a constant frequency voltage pulse width, similar to D-FF. Then, a zero-vector determination (FS-SYN) is used to distinguish between the normal switching states and zero-vector periods. During the normal switching states, the CLK synchronizes the switching timing so that each of the switching intervals of MC can achieve ZVS.

**Figure 16.** Inconsistent frequency in the grid inductor current due to the quantization error.

**Figure 17.** Carrier comparison with zero-vector commutation is introduced to overcome the voltage error and the inconsistent frequency problem.

During the zero-vector periods, since the transformer voltage is applied on the switching devices, hard-switching will cause the voltage at the switching device. In order to prevent the short-circuit state, the transformer current first needs to be blocked before switching. Furthermore, a current circulating path must first be created in order to achieve current cancelling.

The zero-vector commutation is applied only to the first and last switching intervals of the zero-vector periods. A total of six categories are divided in the zero-vector commutation which depends on the polarity of the transformer voltage, as shown in Figure 18. That is, if the zero-vector period occurs from a positive transformer voltage and ends on a positive voltage or ends on a negative voltage, it is known as PV-to-Z, PVZ-to-PV or PVZ-to-NV, respectively. On the other hand, if the zero-vector period occurs from a negative transformer voltage and ends on a positive voltage or ends on a negative voltage, it is known as NV-to-Z, NVZ-to-PV or NVZ-to-NV, respectively. Then, a two-step commutation is performed to circulate and cancel out the leakage inductance current. The switching algorithms of normal switching states are summarized in Table 1, and the switching algorithms of zero-vector commutation are summarized in Table 2.

**Figure 18.** Categories of zero-vector commutation depending on the polarity of transformer voltage.


**Table 1.** Switching algorithms of normal switching states (ZVS).



Figure 19 shows the switching sequence of the zero-vector commutation for the case PV-to-Z. First, S7B is turned on and S8B is turned off, the transformer current continues to flow in the same direction via the S8A and S8B diode. Then, as S8A is turned off, the capacitance in S8A is charged by the leakage inductance current in order to build up the blocking voltage. Thus, the capacitance in S7A is discharged to reduce the blocking voltage. At the same time, the grid inductor current flows in the opposite direction via S7AB and therefore both currents are cancelled out with each other in S7AB. After S8 is completely turned off the grid inductor current starts circulating via S5AB and S7AB, the zero-vector period is created in the grid side.

Figure 20 shows the switching sequence of the zero-vector commutation for the case PVZ-to-NV. First, S6A is turned on and S5B is turned off, the circulating current continues to flow in the same direction via S5AB and S7AB. Then, as S6B is turned on, the capacitance in S5B is charged by the transformer current to build up the blocking voltage and capacitance in S6B is discharged. At the same time, the grid inductor current is cancelled out with the transformer current in S5AB. Since S5B is completely turned on, S5A is turned off at no loss and the transformer current starts to flow to the grid via S6AB and S7AB.

**Figure 19.** Switching sequence for PV-to-Z, current cancelling in S7AB.

**Figure 20.** Switching sequence for PVZ-to-NZ, current cancelling in S5AB.

On one hand, for the case of PVZ-to-PV, current cancelling cannot be performed due to the polarity of transformer voltage. The differential current is creating a voltage surge but a short-circuit state is not created and therefore a breakdown of the device does not happen. Figure 21 explains the phenomenon of the switching sequence. First, S7A is turned off and S8B is turned on. Next, the capacitance in S8A needs to discharge in order to allow the current flows. Therefore, as S7B is turned off, the transformer current is charging the capacitance in S7A at the same time discharging the capacitance in S8A. Note that the only circulating path for the grid inductor current is via S5AB and S8AB and therefore the grid inductor current flows with the transformer current via S8AB in the same direction. As a result, the voltage surge occurs while turning on S8AB.

**Figure 21.** Switching sequence for PVZ-to-PV, current cancelling is not achieved.

Figures 22–24 illustrate the switching sequence for the case of negative transformer voltage. The principle control of current cancelling is similar, Figure 22 shows the switching sequence for NV-to-Z. While the transformer current is flowing via S6AB and S7AB, S8A is first turned on. Then, as S7B is turned off, the capacitance in S7B is charged and the capacitance S8B is discharged by the transformer current. At the same time, the grid inductor current flows via S8AB and current cancelling can be achieved in S8AB during this state.

**Figure 22.** Switching sequence of NV-to-Z, current cancelling in S8AB.

**Figure 23.** Switching sequence of NVZ-to-PV, current cancelling in S6AB.

**Figure 24.** Switching sequence of NVZ-to-NZ, current cancelling is not achieved.

Figure 23 shows the switching sequence for NVZ-to-PV. While the grid inductor current is circulating via S6AB and S8AB, S5B is turned on and S6A is turned off. Then, as S5A is turned on, the capacitance in S5A is discharged and the capacitance in S6A is discharged by the transformer current. The grid inductor current flows in an opposite direction in S6AB to achieve current cancelling. Since the S6A is completely turned on, the transformer current starts to flow via S5AB and S8AB. On the other hand, similar to PVZ-to-PV, current cancelling cannot be achieved in NVZ-to-NV. As shown in Figure 24, as S8B is turned on, the capacitance in S8B is charged and the capacitance in S7B is discharged by the transformer current. Due to this reason, the grid inductor current flows in the same direction with the transformer current in S7AB, and the voltage surge occurs during this interval.

Note that this zero-vector commutation differs from the traditional commutation in MC [19,20]. The traditional commutation is applied to form the voltage pulse width, however the zero-vector commutation is applied during the zero-vector periods only (no voltage-product). Therefore, the voltage error that occurred in the traditional commutation is not a concern. The purpose of the zero-vector commutation is to cancel the current while charging and discharging the capacitance in the switching devices, which is simpler than the traditional commutation.

### **4. Simulation Results**

The comparisons among the methods of modulation are demonstrated in the simulation results. The simulation parameters of each method are summarized in Table 3, which is similar to the experimental parameters. Moreover, the proportional-integral (PI) gain control for each method has been tuned to provide the best result. Figure 25 shows the relationships between transformer voltage, MC voltage, and grid inductor current based on the threemodulations: (a) Carrier comparison with D-FF, (b) delta-sigma conversion with PDM, and (c) carrier comparison with zero-vector commutation, respectively.


**Table 3.** Simulation/experimental parameters.

**Figure 25.** Simulation results that demonstrate the relationship between the matrix converter (MC) voltage pulse width and grid inductor current with different modulation methods. (**a**) D-flip flop, (**b**) delta-sigma conversion, (**c**) zero-vector commutation.

In the D-FF, it can be noticed that due to the misalignment of pulse width, the average of the grid current cannot be constantly controlled. As a result, the fluctuation of grid inductor current is the largest among the three methods. In the delta-sigma conversion, the voltage error can be resolved and therefore the fluctuation of grid inductor current is smaller than D-FF. However, it can be confirmed from the voltage pulse width that it has an inconsistent frequency due to the level of quantization error. With the zero-vector commutation, the voltage error can be eliminated and the fluctuation of grid inductor current is removed due to containing a consistent frequency in the current ripple. Therefore, the waveform quality can be improved as compared to the other two methods.

Figure 26 shows the simulation results at a low output power (300 W) that demonstrates the waveform of the battery current with all the three methods. Due to the direct AC/AC conversion, the distortion of grid current directly affects the waveform of the battery current. Notice that in Figure 26a, the battery current is heavily distorted in the D-FF because of the voltage error. In the case of delta-sigma conversion as shown in Figure 26b, the distortion in the battery current can be

greatly reduced because the voltage error has resolved. However, a resonant frequency of the LCL filter occurrs at the battery current because of inconsistent frequency in the grid inductor current. As shown in Figure 26c, the zero-vector commutation can solve the two above problems. The distortion and resonance frequency in the battery current can both be removed due to a clean sinusoidal waveform that can be achieved in the grid inductor current.

**Figure 26.** Low power (300 W) simulation result to demonstrate the differences of each method of modulation. (**a**) D-flip flop, (**b**) delta-sigma conversion, (**c**) zero-vector commutation.

Figure 27 shows another operating waveform at larger power (3.3 kW) to demonstrate the waveform of battery current with all the three modulation methods. D-FF is shown to have the worst distortion in battery current among the three methods. On the other hand, delta-sigma can achieve a clean sinusoidal waveform in the grid current nearly to the zero-vector commutation. This is because the peak-peak current is limited by the cut-off frequency of LCL filter, as the amplitude of the grid current becomes larger, the ripple current that is caused by the resonant frequency has lesser effect compared to the low power.

**Figure 27.** High power (3.3 kW) simulation result to demonstrate the difference of each method of modulation. (**a**) D-flip flop, (**b**) delta-sigma conversion, (**c**) zero-vector commutation.

Figure 28 shows the comparison of grid current THD among these modulations at low and high output power, respectively. The LCL cut-off frequency is regulated from 3 to 7.5 kHz by adjusting inductor *Lf* and the *Cf* capacitor while keeping the same impedance percentage. The results in Figure 28a (low power) shows that D-FF has the highest THD, and only the zero-vector commutation can reach the THD below 5% at a cut-off frequency of 5 kHz. In Figure 28b (high power), both the delta-sigma conversion and zero-vector commutation can reach the THD below 5% within the cut-off frequency from 3 to 7.5 kHz.

**Figure 28.** Comparison of grid current total harmonic distortion (THD) with the different inductivecapacitive-inductive (LCL) cut-off frequency betweenlow power and high power. Zero-vector commutation achieves the lowest total harmonic distortion (THD) regardless of power level. (**a**) Low power (300 W). (**b**) High power (3k W).

As a result, in order for the delta-sigma control to achieve 5% THD at low output power, the cut-off frequency needs to be reduced with the penalty of a larger size in the LCL filter. Therefore, the zero-vector commutation can achieve the smallest size in the LCL filter and also achieve THD below 5% for both low and high output power, among the three methods.

### **5. Experimental Results**

Figure 29 shows the layout of the 1 kW prototype (203 × 113 × 10 mm). Switching devices are placed on both sides (left: MC; right: FBI), then a planer transformer is placed in the middle and the capacitor *Cb* (400 μF) and an inductor *Lb* (10 μH) that is connected to the center point of transformer is placed on the top side of the prototype.

**Figure 29.** Layout of a 1 kW prototype.

Figure 30 shows the effectiveness of ZVS and zero-vector commutation. Figure 30a shows the result before applying zero-vector commutation. During the first (PV-to-Z) and last (PVZ-to-PV) switching intervals of zero-vector periods because hard-switching happens at a short-circuit state, therefore over-voltage occurrs at the transformer voltage. On the other hand, during the ZVS periods it can be confirmed that voltage spikes did not occur at the transformer voltage because switching devices are aligned to the zero-voltage of the transformer to achieve ZVS.

Figure 30b shows the result after applying the zero-vector commutation. As shown in the result, the voltage spike at the transformer voltage can be greatly reduced in PV-to-Z, comparing that to Figure 30a. The zero-vector commutation enables the switching state to go into the zero-vector periods to allow the current to circulate inside a loop and achieve current cancelling. As a result, the voltage

spike of the switching device during the zero-vector periods can be resolved. On one hand, current cancelling cannot be achieved in PVZ-to-PV and therefore the voltage surge occurs on the transformer voltage. Since the short-circuit state can be prevented, the voltage surge is smaller than that compared to Figure 30a.

**Figure 30.** Experimental result to demonstrate the effectiveness of the zero-voltage switching (ZVS) and zero-commutation. (**a**) Without the zero-vector commutation. (**b**) With the zero-vector commutation.

The comparison of experimental results at low output power (300 W) between the delta-sigma and zero-commutation is shown in Figure 31a,b. In this result, the power decoupling was disabled in order to validate the effectiveness of the method of modulation. The capacitor voltage *vcb* is controlled at 90 V constantly with a battery voltage of 180 V. In Figure 31a, we noticed that the grid inductor current *igl* has a huge current ripple due to the inconsistent frequency. As a result, the battery current fluctuates at a resonance frequency of 1.25 kHz. Figure 30b shows the results obtained by the zero-vector commutation, the distortion in the battery current can be nearly eliminated because a clean sinusoidal grid inductor current can be obtained.

**Figure 31.** Comparison of experimental results between delta-sigma and zero-vector commutation. (**a**) Delta-sigma shows fluctuation in the battery current at 1.25 kHz. (**b**) Zero-vector commutation shows a clean sinusoidal waveform that can be obtained in the grid inductor current and battery current.

Figure 32a,b shows the fast Fourier transform (FFT) analysis of the grid current between the delta-sigma and the zero-vector commutation, respectively. Even the number of harmonic components contains the battery current. Then, it can be noticed that the 4th, 6th, and 8th harmonic components in the delta-sigma conversion is higher than that of the zero-vector commutation. The result can confirm that the zero-vector commutation could achieve better THD than the conventional ones.

Figure 33 shows the effectiveness of power decoupling with the zero-vector commutation. In Figure 33a, the power decoupling control was disabled and therefore the battery current contains a low frequency component. Then, after being applied to the power decoupling control as shown in

Figure 33b, the single-phase power fluctuation occurs in the capacitor voltage. The average capacitor voltage is constantly kept at half of the battery voltage, then Δ*vcb* of approximately 30 V is controlled at 100 Hz sinusoidal waveform to compensate the single-phase power fluctuation. This is also identical to the theoretical calculation which is explained in Figure 3, where a 400 μF capacitor with 30 V voltage difference is designed for the power decoupling. As a result, the single-phase power fluctuation can be reduced in the battery current. Note that the low frequency fluctuation occurrs in the battery current because of the DC bias effect in the ceramic capacitor.

**Figure 32.** Comparison of the fast Fourier transform (FFT) analysis on grid current between delta-sigma and zero-vector commutation, the even harmonic component is lower in the zero-vector commutation. (**a**) Delta-sigma. (**b**) Zero-vector commutation.

**Figure 33.** Experimental results to demonstrate the effectiveness of power decoupling control with the zero-vector commutation. (**a**) Without the decoupling control; capacitor voltage is constantly controlled at the average of battery voltage. (**b**) With the decoupling control; the capacitor voltage difference is 30 V with the decoupling control to compensate the single-phase power fluctuation.

Figure 34 shows the experimental measurement efficiency of the prototype. The prototype achieves the highest efficiency 91.5% at 1 kW. Optimization of the losses will be considered in the future work to improve the efficiency.

**Figure 34.** Measurement of efficiency, the prototype achieves the highest efficiency of 91.5%.

### **6. Conclusions**

The comparisons among the three methods and along with other literature reviews are summarized in Table 4. Power decoupling is obviously not considered in the past studies due to the difference of circuit structure. The control also shows a difficult level due to complex commutation rules. This paper describes and compares three methods of modulation of MC for the power decoupling with the transformer integration. Zero-vector communication is introduced in this paper. The effectiveness of these modulations have been demonstrated in simulation and experimental.


**Table 4.** Comparison results among the three methods of modulation.

Modulations that consider the power decoupling are summarized as follows. The D-FF is simple in terms of control but the quality waveform is poor due to the voltage error. Delta-sigma achieves average among the three, in order to improve the THD during low-power, a bigger size of LCL filter is required. The zero-vector commutation can produce a better quality waveform but the control complexity requires a high-bandwidth controller. If the design level is only concerned for high-power, delta-sigma with a lower bandwidth controller is another option of choice.

**Author Contributions:** Conceptualization, G.T.C. and T.S.; methodology, G.T.C.; software, G.T.C.; validation, G.T.C. and T.S.; formal analysis, G.T.C.; investigation, G.T.C.; resources, G.T.C.; data curation, G.T.C.; writing—original draft preparation, G.T.C.; writing—review and editing, G.T.C. and T.S.; visualization, G.T.C.; supervision, T.S.; project administration, T.S.; funding acquisition, T.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


<sup>ʕ</sup> <sup>=</sup> good, = average, × = poor.


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **Modeling of Magnetic Elements Including Losses—Application to Variable Inductor †**

### **Sarah Saeed \*, Ramy Georgious and Jorge Garcia**

LEMUR Research Group, Department of Electrical, Electronics, Computers and Systems Engineering, University of Oviedo, 33204 Gijon, Spain; georgiousramy@uniovi.es (R.G.); garciajorge@uniovi.es (J.G.)


Received: 4 March 2020; Accepted: 6 April 2020; Published: 11 April 2020

**Abstract:** This paper proposes and develops a circuit-based model aiming to simulate variable magnetic power elements in power electronic converters. The derived model represents the magnetic element by a reluctance-based equivalent circuit. The model takes into consideration device core losses, with the main emphasis given to hysteresis losses, which are modeled using the Jiles-Atherton model. The core loss model is further validated on different ferromagnetic materials to prove its range of applicability. The winding losses of the magnetic device are also taken into consideration, which are obtained using Dowell empirical formulas. In addition, the frequency dependence of the device losses is also considered. The proposed modeling procedure has been applied to study and characterize a double E-core variable power inductor structure in a 1 kW SiC full bridge DC-DC converter. The procedure has been verified by comparing the simulation results to the experimental measurements, confirming the validity and accuracy of the full circuit-based model.

**Keywords:** magnetics modeling; variable inductor; hysteresis; eddy currents; saturable core

### **1. Introduction**

Understanding the behavior of a magnetic device in a Power Electronic Converter (PEC) is essential to optimize the design and to foster the performance of the whole system. Variable magnetic elements allow for additional degrees of freedom in the design and control of PECs. This is particularly useful in resonant converters where the usual frequency control has some drawbacks due to Electro-Magnetic Interference (EMI) issues, synchronization, variable sampling time, etc., especially for a large range of variation. If variable magnetics are used, the same control margins can be obtained at a constant switching frequency, therefore allowing for an optimization of the EMI filters and sampling procedures. In other applications, such as the Dual-Active-Bridge (DAB) converter, in addition to adding a new degree of freedom to the control, the inclusion of variable magnetics can increase operation parameters, such as the soft switching margins [1–3].

The recent growing applications of variable magnetic elements have implied the need for developing accurate models to define the magnetic device behavior. The magnetic core as well as the device windings must be characterized to achieve an accurate device model.

Some models define the magnetic core material in terms of a relationship between magnetic flux density and field intensity referred to as a hysteresis curve. In [4], an initial survey has been conducted classifying the existing magnetic material models, according to different frequencies, bias conditions, and temperatures of interest. It aims to provide comparable information for models and their availability in some circuit simulators. More recently, a literature review on the fundamentals, modeling, and design of magnetic regulators has been comprehensively presented in [5]. After a careful review of these and other references, the modeling methods are confined to analytical and numerical methods. Specific

to variable magnetic devices, modeling strategies are confined to three directions: Finite Elements Analysis (FEA), gyrator-capacitor model [6], and reluctance equivalent circuit [7]. The FEA model is based on the numerical method, while the gyrator-capacitor model and the reluctance model are based on the analytical method.

As the complexity of magnetic devices increases, the analytical method becomes too complicated to predict the behavior of the device in a simple and practical manner. Therefore, incorporating those concepts in a computer-based simulation provides a good compromise between convenience, accuracy, and numerical efficiency. On the other hand, developing such simulations enables real-time applications on the modeling at the converter controller level, which can provide an on-line calculation of model parameters for real-time control [8]. Consequently, many efforts have been directed towards computer-based simulations, especially time-domain models [9,10]. Although the analytical methods of calculation are generally known and can be implemented in simulation models in a straight-forward manner, the selection of the suitable methods is critical from the circuit simulation perspective. The computation methods are expected to achieve good convergence with an acceptable compromise of accuracy to the time of processing the simulation results.

Henceforth, the aim of this work is to develop a circuit-based time-domain model of the variable magnetic element. The proposed model includes the device losses, mainly core and winding losses. Also, this circuital model is able to work in different platforms, for e.g., LTSpice (Linear Technology Corporation, Milpitas, CA, USA) [11], MATLAB-Simulink (MathWorks, Natick, MA, USA) [12], and PSIM (Powersim Inc., Rockville, MD, USA) [13], with equally valid accuracy. Thereby, the whole electromagnetic system design and simulation can be carried out using only one simulator environment. This provides an acceptable accuracy in compromise with the complication and time required for FEA models. Consequently, it allows the investigation of the overall PEC performance incorporating the variable magnetic device. Section 2 presents an overview of the variable magnetic device structure that will be used, together with the models of interest in the literature. In Section 3, the magnetic core losses are studied and the method used to model those losses is presented. This section also provides an idea on the implementation of the model equations, the validation of the model against experimental measurement, and the approach to estimate the model parameters as a function of the operation frequency. Later, in Section 4, the model of the winding losses is presented, and validated against experimental results. After that, Section 5 explains the use of the loss models to implement the full device model. In Section 6, the proposed simulation model is validated in comparison to the previous models that does not include losses, and experimental results are provided. Finally, Section 7 summarizes the conclusions of the work.

### **2. Modeling of Variable Magnetic Elements**

From the study of the state of the art, the double E-core structure, depicted in Figure 1, is selected to be the most appropriate for the implementation of the variable inductor in this study and the most comprehended in literature [14]. The basic principle of operation of a double E-core variable inductor is described in this section.

**Figure 1.** Variable inductor based on a double E-core structure.

Due to the current (*Ic*) flowing through the main winding (*Nc*) of the inductor, as clarified in Figure 1, an AC flux (*φC*) circulates through the center arm of the typical E-core structure of the magnetic core and splits to the outer arms. Applying a relatively small DC current (*Ib*) to the bias control windings (*Nb*), a DC flux (*φ<sup>R</sup>* or *φL*) is produced, which circulates mainly through the outer (ungapped) closed path of the core [14]. This DC flux can bias the operation of the magnetic material towards the nonlinear region on the *B*(*H*) curve, thus causing the inductance seen from the main winding terminals to vary as a function of the DC bias current, Equation (1).

$$L = f(I\_b),\tag{1}$$

In order to model the variable magnetic device, the operation regions of the magnetic material on the *B*(*H*) curve must be considered. These are divided into three areas: the linear region, the saturation knee, and the non-linear region [9].

In addition, to attain accurate results in the modeling procedure, the different involved device losses are included. There are two main types of losses associated to the magnetic device; core losses and winding losses. For MnZn-ferrite materials, the core losses are composed of three fractions. A fraction of the losses is related to the crystal composition, which is called hysteresis losses. Another fraction is related with the structural form of the core, which is called eddy current losses. As the frequency increases, the eddy currents dominate, and for a frequency range of approximately 1 MHz, those losses can contribute with more than 50% of the total power losses. There is also a third fraction known as resonance losses [15]. This fraction is related to the ferrimagnetic resonance of the material and is pertinent to both the crystal and microstructure.

On the other hand, the winding losses depend on the frequency of operation of the magnetic device. At DC operation, the winding losses are due to the resistance of the copper wire. However, as the frequency of operation increases, two effects take place, which are the skin and the proximity effects. Those effects cause the wire resistance to vary, and this modified resistance is referred to as the AC (or high-frequency) winding resistance.

Although ready-made modules are available in many circuit simulation environments [12,13], it is not considered comprehensive to study the magnetic device. The SPICE-based reluctance equivalent circuit provided by authors in [9] is, thus, found to be of more interest. Figure 2 shows the reluctance equivalent circuit for the double E-core variable inductor.

**Figure 2.** Reluctance equivalent circuit of the double E-core variable inductor shown in Figure 1.

The voltage sources in the circuit represent the magnetomotive forces due to the bias control windings (*Nb* · *Ib*), as well as the main winding (*Nc* · *Ic*). *gap* is a constant reluctance that represents the air gap, while *sep* is a constant reluctance that represents the air separation between the two E-cores due to non-idealities in the manufacturing process. The components *<sup>L</sup>*, *<sup>C</sup>*, and *<sup>R</sup>* are the reluctances of the magnetic paths of the left, center, and right arms, respectively. These reluctance values are represented as a function of the permeability of the magnetic material (*μ*), and it must be noticed that, unlike the usual case, in variable magnetic elements, these permeability values can vary depending on the operation point of the magnetic core material on the characteristic *B*(*H*) curve. Thus, for calculating

these reluctances, the referred model uses Brauer's equation [16], which defines the *B*(*H*) characteristic curve of the magnetic material neglecting the hysteresis effect, as stated by Equation (2).

$$H(B) = (k\_1 \varepsilon^{k\_2 B^2} + k\_3) B \,, \tag{2}$$

where *k*1, *k*2, and *k*<sup>3</sup> are constants that depend on the considered magnetic material. For the present work, the afore-mentioned SPICE-based model has been replicated, specifically, in the MATLAB-Simulink platform. This has been carried out in order to take advantage of the feature of this environment to integrate MATLAB script with existing Simulink library tools, aiming to combine complex, accurate simulations with digital processing of information. This allows including the device design calculations into the overall model of the system in one integrated environment.

Two key limitations are found in this model, which restrict its applicability range and accuracy. Firstly, the hysteresis effect is not taken into consideration. Secondly, the model input quantities are dependent on the output ones, which introduces difficulty in the implementation of the computations. In particular, the latter issue implies the necessity for implementing system calculation delays, with an adequate initialization of parameters, especially when including the device in a switching converter simulation. This, furthermore, complicates the simulation in different test platforms. In Simulink, for instance, the solver applies a numerical method to solve the set of ordinary differential equations that represent the model; therefore, the model causality must be decided [17].

In this paper, the model of the variable inductor has been extended to include device losses. The main loss components that have been taken into consideration are the hysteresis losses of the magnetic core and the winding losses. The following sections will justify the studied loss components and discuss the implementation and validation of the full model [18].

It is worth noting that, throughout the discussion hereafter, the vectorial nature of the magnetic quantities are disregarded to reduce the analysis to a simple unidimensional statement of equations by assuming: (1) specific symmetrical magnetic core geometries, of which geometrical references and paths are well-defined, and (2) the homogeneous nature of typical magnetic core materials together with the uniform distribution of the magnetic core properties. Such assumptions are often used in the analysis and design of magnetic devices for power electronics converters.

### **3. Model of Core Losses**

The core losses in a magnetic core are due to two phenomena: the hysteresis loss, and the eddy currents loss. The hysteresis loss is due to energy required to rotate the magnetic domains when aligning with the applied magnetic field. On the other hand, the eddy current losses are due to currents induced in the magnetic core, which opposes the changing flux in the core. Previous studies in literature [19] have shown that for a ferrite magnetic material operating in a range of frequency up to 100 kHz, the eddy current losses are a very small part of the total core losses. Therefore, for the range of frequencies under study herein, the hysteresis losses will always be dominant. For this reason, the eddy current losses in the magnetic core will be neglected in this study for the sake of simplicity.

There are several methods to calculate the hysteresis losses in a ferro-magnetic material, which were grouped by the authors in [20] to be three main approaches: hysteresis models, empirical equations, and loss separation. This paper undertakes the first approach, specifically the Jiles-Atherton (JA) hysteresis model [21]. The main strengths of the JA model compared to its counterpart approaches are: being the most suitable for development from a circuital simulation perspective, besides having good convergence and acceptable accuracy among a variety of materials and operation conditions [22].

This section is dedicated to explaining in detail the model of core losses. First, the JA equations are defined and implemented using block diagram modeling in Simulink. Second, a test setup is built for measuring the magnetic flux density and field intensity to validate the model in comparison to experimental measurements. Finally, to include the effect of the switching frequency on the core loss model, expressions are obtained for the JA parameters as a function of the switching frequency based on an empirical approach.

### *3.1. Model Implementation*

The JA model separates the magnetization, *M*, into reversible, *Mrev*, and irreversible magnetizations, *Mirr*, which correspond to the reversible or irreversible phenomena, which take place within the magnetic material during the magnetization [22]. By computing the latter components, the total magnetization, *M*, is defined as the summation of both components as explained by Equation (3).

$$M = M\_{irr} + M\_{r\text{rev}} \,. \tag{3}$$

The reversible component of magnetization is defined as a fraction, *c*, of the difference of the anhysteretic magnetization and the irreversible one, as explained by Equation (4).

$$\frac{dM\_{rcv}}{dH} = \mathcal{c} \left( \frac{dM\_{an}}{dH} - \frac{dM\_{irr}}{dH} \right) \,, \tag{4}$$

where *c* is referred to as the reversibility coefficient. The irreversible component of magnetization is defined by the differential Equation (5).

$$\frac{dM\_{irr}}{dH} = \frac{M\_{an} - M\_{irr}}{\frac{\delta k}{\mu\_o} - \kappa \left(M\_{an} - M\_{irr}\right)} \,'\,\tag{5}$$

where *k* is the loss coefficient, and *α* is the interdomain coupling. *δ* indicates the direction of the magnetizing field *H*, such that *δ* = 1 for increasing field, and *δ* = −1 for decreasing field, as defined by Equation (6).

$$
\delta = \begin{cases} 1, & \frac{dH}{dt} > 0. \\ -1, & \frac{dH}{dt} < 0. \end{cases} \tag{6}
$$

*Man* is the anhysteretic magnetization. The anhysteretic magnetization describes the magnetization of an ideal ferromagnet that does not have a loss effect, and thus, its magnetization curve does not present hysteresis. Langevin's function [23] is used within the JA model for defining the anhysteretic magnetization, in which case, an effective field, *He*, replaces the magnetic field, *H*, as explained by Equation (7) [24].

$$M\_{an} = M\_s \left( \coth \frac{H\_\varepsilon}{a} - \frac{a}{H\_\varepsilon} \right) \,, \tag{7}$$

where *Ms* is the saturation magnetization, *a* is the shape parameter for anhysteretic magnetization, and *He* is defined by Equation (8).

$$H\_{\ell} = H + aM.\tag{8}$$

Consequently, the magnetic flux density can be calculated using Equation (9).

$$B = \mu\_0 H\_\mathfrak{e} \,. \tag{9}$$

Table 1 summarizes the definition of the model parameters, *Ms*, *a*, *c*, *α* and *k*. The parameters are initially estimated by an iterative procedure to fit the model to the magnetic material *B*(*H*) curve data provided by the manufacturer.

**Table 1.** Jiles-Atherton model parameters.


Figure 3 shows a block diagram of the detailed implementation of the JA equations [22]. Following this block diagram, the model equations have been implemented in Simulink. Therefore, for a given core size and magnetic material, the instantaneous magnetic flux density (*B*) can be estimated for a certain instantaneous magnetic field intensity (*H*) applied to the magnetic core.

**Figure 3.** Schematic of the implementation of the Jiles-Atherton (JA) model.

### *3.2. Test Setup for Measuring Core Losses*

In order to validate the implemented JA model and study the effect of frequency on the model parameters, a test setup is developed. The purpose of the experiments is to measure the hysteresis losses of the magnetic core and compare it to the one obtained by the implemented JA model. In literature, mainly two approaches for measuring core losses can be found [25]: electrical methods, and calorimeter-based methods. One of the former approaches has been selected, which is the *B*(*H*) curve electrical measurement technique. Specific to the selected technique, the two-winding measurement method [26] is used since it is reported to be accurate for the frequency range under test in this study (<100 kHz) [27].

Figure 4 illustrates a schematic to clarify the test setup used for measuring the core losses, while Figure 5 shows the experimental platform developed.

The power stage used in the tests is a simple half-bridge converter suitable for low power levels. A square-waveform excitation voltage is sought to verify the loss study under non-sinusoidal conditions. The core used for the identification tests is a toroidal core with the design parameters listed in Table 2. This toroidal geometry is used in order to ensure that the model results are not only valid for the selected double E-core structure but also for other geometrical schemes.

**Figure 4.** Schematic diagram of the test setup used to measure the *B*(*H*) curve.

**Figure 5.** Experimental setup used to measure the *B*(*H*) curve.

**Table 2.** Specifications of the test setup developed to measure the *B*(*H*) curves.


In addition to the main excitation winding (*Np*), a secondary sensing winding (*Ns*) is added to sense the induced voltage due to the flux in the main one. The advantage of a separate winding is to exclude the voltage drop due to the resistance of the main winding. Therefore, the magnetic flux density can be computed using Equation (10).

$$B = \frac{1}{N\_{\rm s}A} \int\_0^T V\_{\rm s} dt \,\,, \tag{10}$$

where *A* is the cross-section area of the toroid, and *Vs* is the open-circuit secondary winding voltage. The integration is performed over one switching period, *T*. The field intensity can, thus, be computed using Equation (11).

$$H = \frac{\mathcal{N}\_p I\_p}{l},\tag{11}$$

where *Ip* is the current flowing through the main winding, and *l* is the effective length of the core. The measured voltage (*Vs*) and current (*Ip*) are illustrated in Figure 6a,b, respectively. By applying these measurements to Equations (10) and (11), the *B* and *H* quantities can be calculated. In this manner, the measured *B*(*H*) curve of the N87 magnetic material is compared to the *B*(*H*) curve obtained from the implemented JA model simulation under the same operation conditions. To apply the JA model, the model parameters are estimated by iterative fitting as mentioned previously, the obtained parameters for N87 magnetic material at 50 kHz are stated in Table 3. The resulting comparison is shown in Figure 7. It can be observed that the JA simulation model predicts the *B*(*H*) curve of the N87 magnetic material with an error of less than 5%. It can, thus, be concluded that the model is valid and provides acceptable accuracy. Furthermore, the model has been tested under different magnetic materials. The previous measurements were repeated at the exact same operation conditions while using a similar toroidal core from 3C90 magnetic material, the JA parameters of which are stated in Table 3. The *B* and *H* quantities were again measured, and the *B*(*H*) curves were compared together with the modeled ones, as illustrated in Figure 7. Similar to the previous results, the model shows a clear coincidence with the experimental measurements.

**Figure 6.** Experimental measurements. (**a**) Voltage applied to the toroid, and (**b**) current flowing through the main winding.

**Table 3.** Estimated Jiles-Atherton parameters for N87 and 3C90 magnetic materials at 50 kHz.


**Figure 7.** Model (dotted line) versus experimental (solid line) *B*(*H*) curves for two different magnetic materials: N87 (blue) and 3C90 (green).

The hysteresis losses are estimated in terms of the area enclosed by the *B*(*H*) loop and, therefore, can be expressed as shown by Equation (12).

$$P\_{core} = V\_{\text{eff}} \oint B(H) dH,\tag{12}$$

where *Ve* is the core volume, and *f* is the switching frequency. The integral is performed over a complete cycle of the magnetic field intensity.

### *3.3. Frequency Dependence of JA Parameters*

Since the behavior of the magnetic core material depends on the excitation frequency, different voltage waveforms in the magnetic element imply notable variations in the associated trajectories on the *B*(*H*) characteristic of the material. Specifically, it changes the area enclosed in the hysteresis loop, which is directly related to the core losses. This variation of the trajectory in itself implies a variation of the parameters of the JA model parameters. It is, thus, of interest to develop a model that can be used for any frequency without having to readjust the parameters each time different operating conditions are considered.

A practical approach has been taken by conducting a few experiments to characterize the variation of the JA model parameters as a function of the frequency. For the same core size and material, a number of independent tests were carried out, each test for a given frequency of operation. Then, a simple procedure is followed to obtain the parameters, as listed below:


The obtained expressions for the JA parameters are stated by Equations (13)–(15).

$$M\_s(f) = 5.189e^{-8}f^{2.334} + 4e^5,\tag{13}$$

$$a(f) = 6.004e^{-15}f^{3.002} + 16.935,\tag{14}$$

$$k(f) = -3.398e^{-7}f^{1.458} + 15.4$$

The expressions are intrinsic to a certain magnetic material. In this case, the procedure has been implemented for the N87 material; however, the same procedure can be followed for extracting a set of expressions for the JA parameters of any other ferrite material.

To test the validity of the obtained expressions for the JA parameters as a function of frequency, several experiments were carried out using the N87 toroidal core described in Table 2. The switching frequency of the converter was changed and the *B*(*H*) curves corresponding to different frequency values were measured and compared to the modeled ones, as illustrated in Figure 8. The results of the comparison show that the modeled *B*(*H*) curves match the obtained experimental measured curves at a wide range of the operation frequency with acceptable accuracy.

**Figure 8.** *B*(*H*) curves for the prototype under different operation frequencies. Model (dotted line) versus experimental results (solid line).

### **4. Model of Winding Losses**

### *4.1. Winding Eddy Current Losses*

The winding losses are due to the resistance of the copper wire. At DC operation currents or relatively low operation frequencies, this resistance component is constant and calculated using Equation (16).

$$R\_{dc} = \rho\_{cu} \frac{l\_{wire}}{A\_{wire}}\,\mathrm{\,\,\,\,\,}\tag{16}$$

where *<sup>ρ</sup>cu* is the resistivity of copper material at 20◦C, which is equal to 1.68 × <sup>10</sup>−<sup>8</sup> <sup>Ω</sup>m, *lwire* is the total length of the winding wire, and *Awire* is the cross-section area of the wire.

However, as the switching frequency increases, two effects start to appear, which are the skin effect and proximity effect. These effects induce eddy currents in the winding conductors, altering the resistance of the winding, and significantly contributing to the overall winding losses. It is necessary in this case to calculate the AC resistance of the winding. Dowell provided a method that computes the equivalent winding resistance using a one-dimensional analytical approach [28]. Initially, this method was intended to describe high-frequency loss in foil windings; however, it has been extended to multilayer windings with round conductors by introducing the porosity factor [28,29]. Dowell's method uses a sinusoidal approach, and the calculations are limited to non-gapped cores [30]. On the other hand, the method presents a great advantage of simplicity and a fast computation of the AC winding resistance; thus, it can be easily integrated into the magnetic device model without extra complexity. Dowell estimates the AC resistance (*Rac*) by scaling the DC winding resistance by a factor, as shown in Equation (17).

$$R\_{\rm ac} = R\_{\rm dc} \left( \mathcal{M} + \frac{\left( m^2 - 1 \right) D}{3} \right),\tag{17}$$

where *M* and *D* are coefficients defined based on the geometrical dimensions of the winding, material characteristics, and frequency of operation, and *m* is the number of layers. The accuracy of the full winding model will be provided in the following sections to assess the validity of using Dowell's method for the application herein.

### *4.2. Winding Stray Capacitance*

As the operation frequency increases, the parasitic capacitance of the inductor winding becomes more significant, causing the impedance of the inductor to change and introduce the resonant frequencies. In order to attain a full comprehensive model of the device, the stray capacitance of the windings is added to the model. The calculation of the stray capacitance is based on an analytical approach previously presented in literature [31]. This method is valid for multi-layer inductors with ferromagnetic cores, as well as being simple and reliable for simulation purposes. Briefly, the inductor winding is divided into partitions, and the turn-to-turn and turn-to-core capacitances of the winding are predicted as a function of a few geometrical parameters of the device. Accordingly, the overall stray capacitance of the coil (*Cs*) converges to the expression stated in Equation (18).

$$\mathbf{C}\_{\text{g}} \cong 1.366 \mathbf{C}\_{\text{tl}},\tag{18}$$

where *Ctt* is the turn-to-turn capacitance of the coil and is defined by Equation (19).

$$\mathbf{C}\_{tt} = \varepsilon\_0 l\_t \left( \frac{\varepsilon\_r \theta^\*}{\ln \frac{D\_o}{D\_c}} + \cot \left( \frac{\theta^\*}{2} \right) - \cot \left( \frac{\pi}{12} \right) \right), \tag{19}$$

where *lt* is the turn length, *θ*∗ is the angular coordinate, *ε*<sup>0</sup> and *ε<sup>r</sup>* are the permittivity of air and relative permittivity of the insulation medium, respectively, and *Do* and *Dc* are the diameters of the wire with and without the insulation coating, respectively, as clarified by Figure 9.

**Figure 9.** Two adjacent turns of the winding.

### *4.3. Full Winding Model*

The full model of the inductor winding is expressed by the circuit diagram in Figure 10. Therefore, the total impedance of the winding is calculated by Equation (20).

$$Z\_T = \frac{(sL + R\_{\rm ac} + R\_{\rm dc})\frac{1}{s\mathcal{C}\_s}}{sL + R\_{\rm ac} + R\_{\rm dc} + \frac{1}{s\mathcal{C}\_s}} \,. \tag{20}$$

An inductor prototype was implemented based on the specifications summarized in Table 4. The inductance value is not of specific importance in the design; however, it is interesting to distribute the winding on several layers to emphasize the proximity effect. Figure 11 illustrates the total winding impedance as a function of frequency to compare the developed winding model against the experimental measurements. As it can be observed, the error between the measured and modeled impedances is less than 1%, which represents a quite high accuracy for the study in context.

**Figure 10.** Full winding model.

**Table 4.** Specifications of the inductor prototype developed to validate the winding model.


**Figure 11.** Total winding impedance as a function of frequency. (**a**) Magnitude, and (**b**) argument of modeled impedance compared to experimental measurements.

### **5. Applications of Loss Models to Simulate the Variable Inductor**

After the verification of the loss models, the study is applied to model the double E-core variable inductor shown in Figure 1. The full model is implemented based on the reluctance circuit concept previously stated. However, the two issues associated with the previous reluctance model have been tackled. To avoid algebraic loops due to model causality, the magnetic core has been partitioned according to its operation, as mentioned previously, in Section 2, thus defining each partition in terms of electrical inputs and outputs as explained below.

The middle arm has the main winding, and to model this arm, the input will be the excitation voltage, and the output should be the main inductor current. On the other hand, the lateral arms have the control windings, so for these coils, the input will be the control current, and the output should be the induced voltages in the control windings.

Figure 12a illustrates the magnetic system, which is represented by the reluctance equivalent circuit of the device. The reluctance equivalent circuit is composed of three branches. The left and right branches represent the magnetic circuits of the control arms of the device. The voltage source (*Nb* · *Ib*) models the magnetomotive force created by each control winding. The voltage sources (*φ<sup>R</sup>* · *<sup>R</sup>*) and (*φ<sup>L</sup>* · *<sup>L</sup>*) model the variable reluctance of the magnetic path of the right and left arms, respectively. Using the control current as the input quantity, the values of the variable voltage sources are calculated

based on the JA hysteresis model. The middle branch represents the magnetic circuit of the main arm, the variable reluctance of the magnetic path is similarly represented by the voltage source (*φ<sup>C</sup>* · *<sup>C</sup>*), while in this case, the magnetomotive force is the output quantity and is represented by a current source. The current in the main winding (*Ic*) can, thus, be calculated by measuring the voltage across this current source and dividing by the number of turns of the winding (*Nc*).

**Figure 12.** Schematic of the variable inductor model based on the reluctance circuit. (**a**) Magnetic circuit, and (**b**) electric circuit.

On the other hand, Figure 12b illustrates the electrical system, which includes the electrical model of the winding, as well as the input voltage and the output current source. The electrical part of the three windings is represented by Equation (21).

$$N\_w = N\_w \frac{d\phi\_w}{dt} \, , \qquad w \in L \, R \, \text{C} \tag{21}$$

where *Vw* is the voltage at winding *w*, *φ<sup>w</sup>* is the magnetic flux created by the winding *w*, and *Nw* is the number of turns of the winding *w*. The winding *w* refers to the left (*L*), right (*R*), or center (*C*) windings. In order to account for the main winding DC losses, a constant resistor, *Rdc*, is added to the electrical circuit of the main winding in series with the current-controlled current source, which represents the main winding current. Also, to represent the AC winding losses, a variable frequency-dependent resistor, *Rac*(*f*), is added in series to *Rdc*.

### **6. Model Validation Using Simulations and Experimental Results**

In order to compare the initial lossless equivalent circuit with the proposed model, which includes core and winding losses, detailed simulations have been carried out. Furthermore, those two simulation models have been compared against experimental measurements obtained from the variable inductor prototype shown in Figure 13. The device has been developed based on the double E-core structure with the design specifications indicated in Table 5, and the models have been adjusted correspondingly.

**Figure 13.** Variable inductor prototype based on double the E-core structure.


**Table 5.** Specifications of the test setup developed to validate the full VI model.

Figure 14a shows a circuit diagram of the developed test platform. It consists of a SiC full-bridge DC-AC converter to apply a square waveform excitation voltage on the inductor main winding. As mentioned previously, the square waveform voltage allows testing the device model under non-sinusoidal conditions, thus assure the validation of the loss study under a general condition of excitation voltage. The converter is controlled using a TMS320F28335 Texas Instruments peripheral board. Additionally, a variable DC voltage source is connected in series with a resistor to provide a DC control current of maximum 1 A to the control winding of the variable inductor. The constructed test platform is illustrated in Figure 14b.

**Figure 14.** Experimental setup used to test the variable inductor under small and large-signal analyses. (**a**) Circuit diagram, and (**b**) test platform.

### *6.1. Small-Signal Analysis*

To validate the proposed model under small-signal analysis, the control current was increased from 0 to 1 A in steps of 0.05 A, while keeping zero excitation voltage on the main winding. The equivalent inductance seen from the main winding was measured using the impedance analyzer. Figure 15a illustrates the measurement of the equivalent inductance as a function of the bias control

current. Also, the figure illustrates the simulated inductance obtained from the developed models, the initial lossless equivalent circuit, as well as the proposed model, which includes losses. Figure 15b shows the error of each model compared to the experimental results, as calculated by Equation (22). It can be observed that the proposed model that includes losses predicts the inductance within an acceptable error (<6%). On the other hand, the inductance predicted by the initial lossless model shows a clear deviation from the experimental one as the control current increases. It reaches an error of 30% at maximum control current.

$$Error(\%) = \frac{\left(L\_{Expriment} - L\_{Model}\right)}{L\_{Expriment}} \times 100 \,\text{.}\tag{22}$$

**Figure 15.** Small-signal characterization of the variable inductor prototype comparing simulation models with experimental results. (**a**) Inductance value, and (**b**) percentage error as a function of control current.

### *6.2. Large-Signal Analysis*

The prototype has also been characterized under large-signal analysis. Similar to the small-signal analysis, a DC control current is applied to the control windings and varied from 0 to 1 A. However, in this case, a square waveform voltage of 30 V is applied to the main winding of the inductor. The inductance is calculated by two different methods using the experimental measurements of the voltage and current through the main winding. The first method calculates the inductance using the RMS values of the waveforms over each cycle at a steady state. On the other hand, the second method uses the instantaneous values of the waveforms. The two methods were then compared to verify the accuracy of the measured inductance value, as explained hereafter.

### 6.2.1. Impedance Calculation

A simplification applied by considering the RMS value of the first harmonic component of the voltage and current measurements, so the resulting inductance is calculated by Equation (23).

$$L = \frac{X\_L}{\omega} = \frac{V\_{\mathbb{C}}}{I\_{\mathbb{C}}} \cdot \frac{\pi/4}{2\pi f} \,\mathrm{}\,\mathrm{}\,\tag{23}$$

where *VC* is the voltage applied to the main winding of the variable inductor, and *IC* is the current flowing through it.

### 6.2.2. System Identification Tools

The System Identification Toolbox from Matlab is used, which requires a set of data that represent the input and output variables of a system; in this case, *VC* is the input to the system, and *IC* is the output. Using these variables, the tool defines the transfer function of the system based on the user selection of the number of poles and zeros of the system. In the case of an inductor, the system is defined as a 1st order system (1 pole, no zeros), and the transfer function is stated by Equation (24).

$$\frac{I\_{\mathbb{C}}(s)}{V\_{\mathbb{C}}(s)} = \frac{1}{sL + R\_{dc}} \,. \tag{24}$$

Figure 16 compares both methods of inductance calculation to verify the accuracy of the measured inductance and then uses it to assess the proposed model. It shows that the inductance calculated based on RMS values is in very close agreement with the inductance obtained by the Matlab identification tool. This conclusion justifies the use of RMS measurements for calculating the inductance in the large-signal analysis in order to simplify the computations.

**Figure 16.** Inductance calculation from experimental measurement.

Similar to the previous small-signal analysis, Figure 17a illustrates the equivalent inductance as a function of the bias control current for the large-signal analysis case. Figure 17b clarifies the trend of deviation or convergence of the models as a function of the control current, compared to the measured results. The results are quite consistent with the previous small-signal analysis; the inductance calculated by the proposed model still approaches the experimental measurements, while the one calculated by the lossless model shows a clear dispersion.

**Figure 17.** Large-signal characterization of the variable inductor prototype comparing simulation models with experimental results. (**a**) Inductance value, and (**b**) percentage error as a function of control current.

### **7. Conclusions and Future Developments**

In this paper, a full accurate circuit-based time-domain model for a variable magnetic device has been developed, demonstrated, and experimentally validated. The model can predict the inductance variation as a function of the control current in a variable magnetic element. The main contribution of this work is the development of a model that can be used in several simulation platforms, and, moreover, the inclusion of core losses as well as winding eddy current losses in the magnetic device. Additionally, it solves the causality issues, which are present in previous approaches.

A double E-core variable inductor prototype has been characterized under small-signal as well as large-signal analyses in order to assess the accuracy of the model. The proposed approach is considered an autonomous tool that can analyze any given set of data (simulated or experimental) for a magnetic core, detect the operation frequency, and correspondingly, adjust the magnetic core model with the core and winding loss parameters, and finally predict the inductance as a function of the control current, along with other electric and magnetic quantities that characterize the magnetic core operation. Consequently, only one simulator environment is used for the design and simulation of the electromagnetic system.

The test results validate the model under operation frequencies of hundreds of kHz (<200 kHz). Accordingly, the future developments of this work include the extension of the model's validity to frequency ranges of 1–1.5 MHz. Also, the employment of the developed electromagnetic model to study the behavior of the variable inductor in a power electronic converter, specifically a DAB converter. The proposed model will allow for several studies using time-domain simulations, such as the control of the converter power transfer using the variable inductor, the possibility of the linearization of the system transfer function, and finally, the boost of the efficiency over critical operation ranges, for example, light load and heavy load operation ranges.

**Author Contributions:** S.S. and J.G. conceived the research and designed and performed the experiments; R.G. contributed to the reviewing and editing; all the authors analyzed the data and contributed in the discussion and conclusions. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work has been partially supported by the Spanish Government, Innovation Development, and Research Office (MEC), under research grant ENE2016-77919, Project "Conciliator", and by the European Union through ERFD Structural Funds (FEDER). Also, this work has been partially supported by the government of Principality of Asturias, Foundation for the Promotion in Asturias of Applied Scientific Research and Technology (FICYT), under Grant FC-GRUPIN-IDI/2018/000241 and under Severo Ochoa research grants, PA-13-PF-BP13-138 and PF-BP16-133.

**Conflicts of Interest:** The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the decision to publish the results.

### **Abbreviations**

The following abbreviations are used in this manuscript:


### **References**


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