**SiC-Based High E**ffi**ciency High Isolation Dual Active Bridge Converter for a Power Electronic Transformer**

### **Mariam Saeed \*, María R. Rogina, Alberto Rodríguez, Manuel Arias and Fernando Briz**

Department of Electrical Engineering, University of Oviedo, 33204 Asturias, Spain; rodriguezrmaria@uniovi.es (M.R.R.); rodriguezalberto@uniovi.es (A.R.); ariasmanuel@uniovi.es (M.A.); fernando@isa.uniovi.es (F.B.)

**\*** Correspondence: saeedmariam@uniovi.es

Received: 30 January 2020; Accepted: 1 March 2020; Published: 5 March 2020

**Abstract:** This paper discusses the benefits of using silicon carbide (SiC) devices in a three-stage modular power electronic transformer. According to the requirements to be fulfilled by each stage, the second one (the DC/DC isolation converter) presents the most estimable improvements to be gained from the use of SiC devices. Therefore, this paper is focused on this second stage, implemented with a SiC-based dual active bridge. Selection of the SiC devices is detailed tackling the efficiency improvement which can be obtained when they are co-packed with SiC antiparallel Schottky diodes in addition to their intrinsic body diode. This efficiency improvement is dependent on the dual active bridge operation point. Hence, a simple device loss model is presented to assess the efficiency improvement and understand the reasons for this dependence. Experimental results from a 5-kW Dual Active Bridge prototype have been obtained to validate the model. The dual active bridge converter is also tested as part of the full PET module operating at rated power.

**Keywords:** SiC devices; antiparallel diode; dual active bridge; power electronic transformer; high-frequency transformer

### **1. Introduction**

A line-frequency transformer (LFT) is a key element in transmission and distribution for traditional centralized generation-based systems. Their main functionality is to interface different voltage levels in the grid [1]. LFTs are a well-established, relatively cheap, and reliable technology. However, they fail to cope with modern grid demands, such as the integration of distributed resources and energy storage systems, as well as power flow control.

The power electronic transformer (PET), also called a solid-state transformer (SST), was introduced in 1970 [2]. It is considered an alternative to LFT, as it connects two AC voltage ports while providing galvanic isolation [1]. PET is a semiconductor-based energy conversion system based on fast-switching devices, which potentially enables a significant reduction in volume and weight [3]. Moreover, thanks to the controllability of the power devices, the PET provides additional functionalities, such as reactive power, harmonics and imbalances compensation, ride-through capabilities, and smart protections.

The power semiconductor technology used in PETs has been traditionally based on Silicon (Si). However, the fast advances in wide-band-gap (WBG), specially the Silicon Carbide (SiC), power semiconductors has attracted the attention to their use in the medium voltage (MV) modular three-stage PETs [4], mainly due to their high blocking voltage along with their superior switching behavior [5,6].

Several examples of using SiC devices in different PET topologies exist in literature [7–13]. In the majority of applications, 1.2/1.7 kV commercial SiC MOSFETs are used for LV side devices, while for HV side, 10 kV non-commercial MOSFETs are used [6,8]. In some works, SiC was used in all the PET stages, such as in the TIPS (transformer-less intelligent power substation), which is an all-SiC three-stage PET topology [12]. In [14], a detailed comparison was carried out between two cases: (1) using 10 kV and 3.3 kV SiC MOSFETs and, (2) using 10 kV and 3.3 kV Si IGBTs, for different PET topologies. Authors concluded the importance of further research into the combined use of Si IGBT with SiC MOSFETs for three-stage PETs. Moreover, authors hinted at the importance of analyzing the relevance of including a SiC antiparallel diode to justify its additional cost implication.

Accordingly, the contribution of this paper is thought in two aspects:


The paper is organized as follows: Section 2 describes the selected PET topology. Section 3 studies the integration of SiC devices in the different stages of the PET and identifies the practical limitations to the enhancements introduced by the use of these devices. Section 4 discusses the DAB converter development where the selection of the devices is detailed and the improvements introduced by using a SiC antiparallel diode is studied. Experimental results are provided in Section 5.

### **2. PET Topology**

The selected PET topology is shown in Figure 1, and was previously discussed in [15–20]. It is a three-stage modular PET, with a Cascaded H-Bridge (CHB) converter acting as the front end AC/DC converter providing a HVAC link (VacHV). Each CHB cell integrates a DAB converter to provide the isolation between the HV and LV sides. Moreover, the integration of the DAB to the CHB cell provides the capability of bidirectional power transfer at the cell level [18,19]. The LV outputs of all DABs are connected in parallel to provide a high-current LVDC link (VdcLV), which is connected to a three-phase four-leg (3P4L) converter providing the LVAC link (VacLV).

**Figure 1.** Selected Power Electronic Transformer (PET) structure: (**a**) Three-stage modular PET topology based on a Cascaded H-Bridge (CHB) converter [17]. (**b**) One PET module composed of a Dual Active Bridge (DAB) and the full bridge of the CHB.

As is clear in Figure 1, the structure is fully modular as it is formed by several identically-stacked cells. Thanks to this modular structure, the number of cells of the CHB is chosen in such a way that the cell voltage (Vcell) is equal to the required VdcLV. In this way the design of this DAB is, to some extent, simplified using a unity transformation ratio (i.e., no step-up/down).

This PET topology requires high galvanic isolation between HV and LV sides. The isolation is provided by the DAB high frequency transformer (HFT). Table 1 shows the characteristics of the developed PET.


**Table 1.** Main Power Electronic Transformer (PET) characteristics.

### **3. Use of WBG for PET**

The superior material properties of WBG semiconductors allow power devices to operate at higher temperatures, voltages and switching frequency in comparison to Si counterparts [4,21]. Among WBG materials, SiC presents the most mature technology for high voltage devices [4]. Both 1.2 kV and 1.7 kV SiC MOSFETs are already available on the market with a wide range of current ratings [5,22,23]. The use of SiC MOSFETs not only introduces a relevant improvement to the efficiency of fast switching power converters, but also enables going to higher switching frequencies at high blocking voltage which cannot be achieved using available Si IGBTs. However, at limited switching frequency requirements (<10 kHz), especially for high power (>100 A), Si IGBTs are still the preferred choice due to cost-effectivity and reliability in addition to SiC MOSFET higher dv/dt, di/dt, and EMI issues [24].

Accordingly, to analyze the merits of integrating SiC devices in the PET, the device requirements for each of the three stages of the PET are identified below.

### *3.1. Device Requirements per PET Stage*

In the addressed PET topology, since no step-up/down is needed, the power devices employed on both transformer sides (i.e., HV and LV sides) have the same voltage rating. These include devices of the CHB full bridge (FB), the two DAB full bridges (FB1, FB2), and the DC/AC converter devices (see Figure 1). While this is true, the specifications in terms of current ratings and commutation requirements differ significantly.

*CHB:* its power devices do not need to commutate fast due to the multilevel nature of the topology [25,26]. Moreover, Ccell size is not determined by the cell switching frequency. Therefore, SiC switching devices are not of special merit here, even when going to higher Vcell (i.e., to reduce the number of stacked modules), still Si IGBT would be the selected option [14]. On the other hand, SiC free-wheeling antiparallel diodes are quite interesting in this case since the CHB full bridge is required to handle positive and negative currents (i.e., not only during the dead time). Therefore, SiC diodes can effectively improve the CHB efficiency due to their reduced conduction forward voltage drop as well as lower reverse recovery time compared to Si diodes [27].

*DAB:* high switching frequencies can provide significant reduction of the size and weight of the converter magnetics and the input and output capacitors. Additionally, going to higher PET module voltage is not achievable using Si devices, unless the switching frequency is reduced to few kHz. Regarding the antiparallel diode, the advantages of using SiC are still a controversial issue [14,28] and, therefore, will be analyzed in this work.

*3P4L DC*/*AC:* commutation requirements are not high (in the range of few kHz [29]), and since it interfaces the LVAC grid, high blocking voltages are not required. Therefore, Si devices are a good candidate for this stage.

Considering the above discussion, for this PET, 1.7 kV Si IGBT devices with SiC freewheeling diodes are used for the CHB FB. As for the DAB, 1.2 kV SiC MOSFETs are used and possible enhancements introduced by a SiC antiparallel diode will be discussed in detail in Section 4. Finally, 1.7 kV Si IGBTs are used for the 3P4L converter.

In the next section, the possible achievable enhancements gained by employing SiC in the DAB are discussed highlighting the practical limitations intrinsic to this PET topology.

*3.2. Benefits and Practical Limitations of Using SiC MOSFETs for the DAB Converter*

The use of SiC MOSFETs for the DAB converter in this PET structure has two main benefits:


**Figure 2.** Theoretically calculated High Frequency Transformer (HFT) power density for three designs varying the Power Electronic Transformer (PET) module voltage (Vcell) and the handled power [17].

However, these SiC potential benefits may be compromised by certain practical implementation constraints.

On one hand, increasing Vcell has several adverse effects. High DC link voltages create practical problems for feeding the control circuitry in each cell. As commercial auxiliary power supplies (APS) do not provide the required isolation [29], each module circuitry has to be supplied from its DC link, where the HV and LV sides have separate APSs [32]. Commercial APSs can be used for voltages under 1 kV, otherwise, custom solutions must be implemented, such as the modular ISOP topology proposed in [29]. Consequently, various aspects must be considered for the selection of Vcell.

On the other hand, the size reduction of the HFT, in this particular case, is constrained by the high isolation required by the PET. This isolation imposes minimum clearance distances between windings, which compromises the window utilization factor resulting in a physical limit on further size reduction.

### **4. SiC-Based DAB Converter**

The DAB (see Figure 3) is selected for the intermediate stage of the PET, as it provides galvanic isolation as well as bidirectional power flow [33,34]. The DAB is based on two active bridges interfaced through an HFT, which provides the required galvanic isolation. This converter provides bidirectional operation by controlling the phase shift between the AC voltages generated by both bridges (V1 and V2). Also, this converter can have relatively high efficiency due to the soft-switching operation of all the devices at nominal conditions (zero-voltage switching, ZVS) [35,36].

**Figure 3.** Dual active bridge (DAB) converter schematic.

### *4.1. SiC Device Selection*

Regarding the selection of the SiC devices for the DAB, 6.5, 10, and 15 kV SiC MOSFETs have been reported for laboratory prototypes [37–42], but are far from being a viable commercial alternative yet. Current ratings offered in commercially available 1.7 kV SiC MOSFETs are still limited [23], and their commutation characteristic must be improved. The 1.2 kV SiC devices remain as the most mature technology available in the SiC device market. Consequently, these devices have been selected for the DAB. The DC link voltage is, therefore, set to 800 V.

Seven 1.2 kV SiC commercial MOSFETs were selected; two power modules and five discrete N-channel SiC MOSFETs. A comparative analysis of these devices was carried out in a boost converter operating in continuous conduction mode (CCM) (see Figure 4).

**Figure 4.** Boost converter test bench schematic.

The boost converter was chosen as a preliminary test bench due to its simplicity and rapid prototyping, but foremost, due to its similar operation to a DAB converter as it has two switching devices in a leg with an inductance connected to the middle point. However, the differences in operation between a CCM boost and a DAB are well understood and, therefore, perspective devices resulting from the first selection stage are then tested in a DAB converter prototype.

The test bench used commercial driver boards from CREE and a commercial FPGA-based controller platform (BASYS2). Tests in the boost converter were done at 2 kW 400/800 V for switching frequencies of 30, 50, and 100 kHz and a dead time of 500 ns. Table 2 summarizes the results. The efficiency is calculated using the input and output DC voltages and currents of the converter measured using digital multimeters. It is observed that all the devices show a high efficiency barely affected by the increase in switching frequency which was increased by a factor of more than three.


**Table 2.** SiC MOSFET comparative analysis in a boost converter.

Since the performance of all seven MOSFETs is comparable, the selection of the adequate option was mainly based on the size and the price. The specifications for the DAB converter are shown in Table 1. Accordingly, the peak current handled by the devices can be calculated from Equation (1) [35], where T is half the switching period, d is the phase shift, Llk is the leakage inductance, vo is the output voltage, vi is the input voltage and n is the HFT turns ratio:

$$I\_{p\text{\\_}k} = \frac{T}{2L\_{\text{lk}}} \left( 2\frac{\upsilon\_o}{n}d + \upsilon\_i - \frac{\upsilon\_o}{n} \right) \tag{1}$$

The current peak is calculated for the maximum phase-shift, this is selected to be 0.35 according to [35]. Based on Equation (1), this current is approximately equal to 11 A. The device current rating is selected to be twice the magnitude of the peak current handled by the devices to keep a safety margin. Therefore, the minimum required current rating is 22 A. This eliminates the two modules, and the CREE 60 A discrete, as the size and price are not justified in this case. The remaining four discrete devices are almost equally favored except for the ROHM SCH2080KE, as it includes a SiC Schottky barrier diode (SBD) co-packaged with the MOSFET.

### *4.2. Antiparallel SBD for a DAB Converter*

Observing the efficiency of the boost converter using ROHM SCH2080KE versus for example ROHM SCT2080KE (without an additional SBD), it is consistently higher without SiC SBD. For the boost converter, this is logical as an additional antiparallel diode increases the output capacitance (see Table 2) and since hard-switching occurs, this increases the switching losses. Although, this makes sense and is simple to understand for the boost, for the DAB, it is more complicated as ZVS is implemented. That being the case, it is not valid to make a selection between both devices unless the additional diode behavior is studied for the DAB operation to identify if it improves or worsens its efficiency. This issue is addressed as follows, including: (1) understanding the potential effects introduced by a SiC antiparallel diode in a DAB converter, (2) developing a simple analytical loss model to estimate the possible efficiency improvement introduced by the SiC diode at a certain DAB operating point, and (3) validation of the proposed model using experimental results in a DAB prototype.

The two devices used in the analysis are the ROHM devices (i.e., SCH2080KE and SCT2080KE) as it is the same die but one packed with a SiC antiparallel SBD [22]. Characteristics of both devices are provided in Table 3. The diode forward voltage, VF-diode, is obtained from the datasheet at the value of Ip\_lk (see Equation (1)) where the employed phase shift is that corresponding to 5 kW.


**Table 3.** Specifications of the compared devices.

### 4.2.1. Advantages and Disadvantages of an Additional SBD

In order to provide a qualitative preliminary understanding of the possible effects of the SiC SBD on the DAB efficiency, the waveforms of the DAB are shown in Figure 5.

**Figure 5.** Dual Active Bridge (DAB) converter waveforms.

The potential advantages of using SCH2080KE +SBD in comparison to SCT2080KE are analyzed as follows:


VF-MOSFET, is applied to the diode. If VF-MOSFET is higher than the diode knee voltage (Vknee), then the diode conducts. If this case is true, current is shared between the MOSFET and the diode and, therefore, conduction losses are reduced.

• Unlike boost converter operation, soft switching is adopted in DAB devices at turn ON and, therefore, the additional output capacitance introduced by the additional SiC diode, illustrated in Figure 4, does not significantly penalize the switching losses (see Table 2).

However, these advantages can be compromised by several situations resulting in almost no advantages of having a SiC SBD, these cases are summarized as follows:


**Figure 6.** Waveforms of the gates and drain to source voltages of two MOSFETs in one leg during the dead time period.

As a conclusion to the previous discussion, it is important to develop a simple model to determine, for a certain DAB operation point, if an extra antiparallel SiC diode co-packed with the SiC MOSFET is worthy or avoiding it is better. This is introduced in the next section.

### 4.2.2. Model to Assess the Efficiency Improvement Using a SiC Diode

### Diode Conduction Intervals

Regarding diode conduction interval during the dead time, in order to estimate the time duration (B) (see Figure 6), the capacitor charging time during (A) is estimated using Equation (2), where Co(er) is the MOSFET effective output capacitance given by the data sheet and V1 = Vi = Vo. Accordingly, ilk is considered flat (I1 = I2 in Figure 5) and, therefore, as an approximation, the peak current (Ip\_lk) is considered to be equal during all the switching transitions.

$$t\_{(A)} = 2\frac{V\_1 \, \mathcal{C}\_{\mathbf{v}(cr)}}{I\_{p\\_lk}} \tag{2}$$

Since t(B) = dead time − t(A), therefore diode operates for 570 ns for the case of the SiC SBD and 588 ns for the body diode. This time represents around 95% of the total dead time (600 ns) and, therefore, the reduction in conduction losses during diode operation is relevant to consider.

Regarding the diode conduction interval during MOSFET ON time, first, the diode characteristics are identified from the MOSFET datasheet (see Table 3). Figure 7 shows the forward voltage drop for both diodes (VF-Diode) as a function of the current through the diode. Additionally, the voltage drop on the MOSFET due to its ON resistance (VF-MOSFET) as a function of the current it is conducting is illustrated.

**Figure 7.** MOSFET voltage drop and diode characteristic curve for the SiC Schottky Barrier Diode (SBD) and the body diode.

It is possible to see that each diode conducts when the current through the MOSFET is above a certain minimum value. It is clearly lower in the case of the SiC SBD. This can be estimated from Equation (3), where RON-MOSFET stands for ON-state drain-to-source MOSFET resistance:

$$I\_{\rm min} = \frac{V\_{\rm kunc}}{R\_{\rm ON-MOSSET}}\tag{3}$$

Based on the data in Table 3, Imin SiC is 6.8 A while Imin body is 11.2 A. Since the theoretical calculated Ip\_lk = 9 A, therefore it is not possible that the body diode enters into conduction while the MOSFET is ON. On the other hand, the SiC diode would conduct when the current exceeds 6.8 A.

Estimation of the Power Losses

Power losses are estimated for both cases of the DAB using MOSFETs with a SiC antiparallel diode (SCH2080KE) and with only the body diode (SCT2080KE). Theoretical power loss estimation will be compared to the experimental efficiency results presented in the next section.

First, the periods where the diode can conduct (when it is forward biased) are identified as shown in Figure 8. It can be seen that, the diodes of all the ON MOSFETs can conduct during (1) and (4) as the current through all the devices is negative (see Figure 5), while during (3) and (6) only the diodes of the secondary bridge can conduct.

Accordingly, to simplify the power loss estimation the following assumptions are made:


**Figure 8.** Current through the power transfer inductance of the Dual Active Bridge (DAB) showing periods where the antiparallel diode can enter into conduction mode during MOSFETs conduction.

During intervals (3) and (6), the conduction and switching losses of all the devices are estimated, while during the dead times, only the diodes conduction losses are estimated.

### *(a) Losses during dead time:*

During one switching period (Tsw), four intervals of dead time take place. During each interval two diodes conduct. Accordingly, the diodes total conduction losses are estimated using Equation (4), where VF-Diode is the diode forward voltage at Ip\_lk obtained from the diode characteristic curve given by the datasheet (linearized in Figure 7).

$$P\_{\text{dandtime}} = 8 \cdot V\_{F-\text{Divide}} \cdot I\_{p\_{-\text{d}k}} \cdot \frac{t\_{(B)}}{T\_{sw}} \tag{4}$$

### *(b) Losses during interval (3) and (6) (Figure 8):*

Losses during these two intervals are divided into: (1) turn OFF switching losses (Psw) and (2) MOSFET and diode conduction losses (PMOSFET and PDiode). The switching losses are straightforward, estimated from MOSFET EOFF using Equation (5).

$$P\_{sw} = 8 \cdot E\_{OFF} \cdot f\_{sw} \tag{5}$$

On the other hand, conduction losses are not straight forward. As noticed from Figure 8, in both (3) and (6) intervals, the primary bridge devices are different from the secondary ones. For example, during (3), for the primary, only the MOSFETs conduct (i.e., all the current flows through the MOSFETs, S1 & S4). In this case, four MOSFETs of the primary bridge conduct during (3) and (6) (two in each interval). Therefore, the total primary conduction losses can be easily estimated using Equation (6).

$$P\_{\text{MOSFET}\to\text{prinn}} = 4 \cdot I\_{p\\_lk} \cdot R\_{\text{ON}-\text{MOSFET}} \cdot \frac{T - dT}{T\_{sw}} \tag{6}$$

However, for the secondary, the current is shared between the diode and the MOSFET (S5, D5 and S8, D8). Accordingly, the current conducted by each element has to be estimated. Since the voltage drop on the MOSFET is equal to the diode VF-Diode, then:

$$I\_{M} \cdot R\_{ON-MOSFET} = V\_{\text{knee}} + I\_{D} \cdot R\_{D} \tag{7}$$

where IM and ID are the currents through the MOSFET and the diode respectively and RD is the diode dynamic resistance.

Since the current is shared by both elements, then, IM and ID can be obtained from Equations (7) and (8):

$$I\_M + I\_D = I\_{p\\_lk} \tag{8}$$

Finally, the total conduction losses of the secondary bridge during Tsw can be calculated from Equations (9) and (10):

$$P\_{\rm MOSFET-suc} = 4 \cdot I\_M ^2 \cdot R\_{\rm ON-MOSFET} \cdot \frac{T - dT}{T\_{\rm sur}} \tag{9}$$

$$P\_{\text{Diode-scc}} = 4 \cdot I\_{D} \cdot V\_{F-\text{Diode}}|\_{I\_{D}} \cdot \frac{T - dT}{T\_{\text{sur}}} \tag{10}$$

The values of the power loss components estimated in this section are summarized in Table 4 where the enhancement to the DAB efficiency is estimated to be approximately 0.22% given the rated power is 5 kW.


**Table 4.** Theoretically-estimated power losses.

4.2.3. Experimental Validation of the Proposed Loss Model

A DAB test bench was constructed and tests were performed at the nominal operation defined in Table 1 and the results are summarized in Table 5.

**Table 5.** Experimental results of the Dual Active Bridge (DAB) with and without SiC Schottky Barrier Diode (SBD).


It was observed that the measured efficiency of the DAB converter composed of MOSFETs with an additional SiC antiparallel SBD is higher than that with only the body diode. The enhancement observed from the experimental results is around 0.3%, which validates the calculation introduced previously resulting in 0.22%. These results validate the proposed hypothesis and approach.

### **5. Experimental Results of the PET Module**

The developed full-scale PET module is shown in Figure 9. Its structure is that schematically shown in Figure 1b. Table 6 summarize the main components of the PET module.

**Figure 9.** The developed Power Electronic Transformer (PET) module.


Controller Xilinx FPGA (Spartan 3E) custom board XC3S250E-4TQG144I

**Table 6.** Main Power Electronic Transformer (PET) module components.

### *5.1. Developed HFT*

One of the key aspects in the design of this HFT is the high galvanic isolation required between its primary and secondary sides, being 24 kV in this PET. This presents significant challenges compared to the ones considered in literature [43,44]. Moreover, the DAB power transfer inductance (Llk) is magnetically integrated in the HFT by making use of its series leakage inductance [43]. This reduces size and cost but, on the other hand, imposes additional constrains on the HFT design due to the required accuracy of Llk.

The HFT design is, therefore, a tradeoff between four variables: transferred power capability, temperature rise (i.e., losses), size and cost. Several design iterations are performed to achieve the required isolation with an acceptable tradeoff between these variables. The HFT design was previously presented in [45]. The main experimental validation tests are provided in this work for completeness.

Figure 10a shows laboratory developed HFT for test purposes and Figure 10b shows the final factory encapsulated HFT. A UU core structure is used typically selected in literature for separate winding [46,47]. The core ferrite material is selected to be Ferroxcube® 3C90 based on the DAB switching frequency [43]. An epoxy resin providing 15 kV/mm and exhibiting acceptable thermal conductance of 3 W/mK was used for encapsulation.

Figure 11 shows a schematic representation of the HFT design from ANSYS PEmag® software (Canonsburg, PA, USA).

**Figure 10.** High Frequency Transformer (HFT) prototype. (**a**) Non-encapsulated laboratory developed using 3D printed bobbins. (**b**) Encapsulated final HFT.

**Figure 11.** High Frequency Transformer (HFT) design taken from ANSYS PEmag®.

To verify the achieved isolation, a high potential test is done for both porotypes and results are compared. A Hipot tester is used to apply a voltage potential of up to 24 kV between both windings. The leakage current flowing from the winding with the higher potential, through air/resin, is recorded and shown in Figure 12. A significant diversion between both prototypes is clear at higher voltage potentials. Having lower leakage currents means that successive partial discharge due to high dv/dt is avoided which would lead to eventual insulation breakdown [48].

**Figure 12.** Experimental results. Leakage current measured between High Frequency Transformer (HFT) windings, as a function of the voltage difference between them.

To locate the hottest spot and verify its temperature rise, five NTC sensors were mounted inside the HFT (see Figure 11). The location of this spot differs in encapsulated (NTC 1) and non-encapsulated prototypes (NTC 4). The temperature profile of the encapsulated HFT hottest spot during a four-hour DAB test at rated operation is shown in Figure 13. The steady state temperature, under natural convection, was recorded to be 60 ◦C.

**Figure 13.** Experimental results. Hottest spot temperature profile for the encapsulated High Frequency Transformer (HFT) using 3C90 ferrite core measured using a Negative Temperature Coefficient (NTC) sensor.

A summary of the final HFT design is shown in Table 7.


**Table 7.** High Frequency Transformer (HFT) design summary.

### *5.2. Experimental Validation*

Figure 14 shows the performed test connection diagram. A DC power supply is connected to the LVDC side to provide VdcLV and the power is transferred from FB2 to FB1. The DAB current control regulates the transferred power using single phase shift (SPS) modulation while the CHB full bridge regulates the cell capacitor voltage (Vcell).

**Figure 14.** Schematic of the Power Electronic Transformer (PET) module during the performed experimental test.

Figure 15 shows the experimental results for the PET module nominal operation (described in Table 1). Figure 15a shows the DAB waveforms, where FB2 gates are leading FB1 gates and the phase shift between both controls the magnitude of the transferred power [35].

**Figure 15.** Experimental results. (**a**) Dual Active Bridge (DAB) waveforms. Two gate signals of DAB FB1 and FB2 and leakage inductance current (ilK). (**b**) Cascaded H-Bridge (CHB) full bridge waveforms. CHB full bridge output voltage (VCHB), CHB full bridge output current (iCHB), and the cell capacitor voltage (Vcell).

Figure 15b shows the CHB waveforms, where VCHB and iCHB are the CHB full-bridge output voltage and current respectively. Vcell is regulated at 800 V by the CHB voltage control.

### **6. Conclusions**

This paper analyzes the use of SiC devices in three-stage modular PETs. It has been shown that SiC MOSFETs can be especially advantageous in the isolation stage, as they combine high blocking voltage and high switching frequencies, leading to higher efficiency, size reduction of the isolation transformer, and higher power density. On the other hand, limited merit is achieved using SiC in the front end AC/DC and the LV side DC/AC converters. However, this partially depends on the application of the PET and the selected topology.

The paper details the selection of SiC MOSFETs for the DAB DC/DC isolation stage experimentally comparing different commercial devices. The benefits of a SiC antiparallel SBD is investigated. It is concluded that the SiC diode improves the efficiency of the DAB as it reduces the total conduction losses of the device. However, this improvement strongly depends on two critical design aspects: the employed dead time interval and the time interval during which the current is driven by both the MOSFET and the diode at the same time (due to the voltage drop in the MOSFET on resistance directly biasing the diode). Generally, the efficiency improvement can be more relevant for a flatter inductor current shape and when the DAB is working around its nominal operation point. A loss model was presented to assess the introduced efficiency improvement and was experimentally validated.

Experimental results showing the operation of the full-scale DAB converter at rated conditions as part of the PET module are provided.

**Author Contributions:** Conceptualization, A.R., M.A. and F.B.; methodology, A.R., M.A. and F.B.; software, M.S.; validation, M.S. and M.R.R.; formal analysis, M.S. and M.R.R.; investigation, M.S. and M.R.R.; writing—review and editing, M.S., M.R.R., A.R., M.A. and F.B.; supervision, A.R., M.A. and F.B.; funding acquisition, A.R., M.A. and F.B. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the Spanish Government under projects MCIU-19-RTI2018-099682-A-I00, FC-GRUPIN-IDI/2018/000179, and PAPI-18-PF-10 and by the European Commission FP7 Large Project NMP3-LA-2013-604057, under grant UE-14-SPEED-604057.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **Nomenclature**


### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

### *Article* **Analysis of Intrinsic Switching Losses in Superjunction MOSFETs Under Zero Voltage Switching**

### **Maria R. Rogina 1,\*, Alberto Rodriguez 1, Diego G. Lamar 1, Jaume Roig 2, German Gomez <sup>2</sup> and Piet Vanmeerbeek <sup>2</sup>**


Received: 7 February 2020; Accepted: 26 February 2020; Published: 2 March 2020

**Abstract:** Switching losses of power transistors usually are the most relevant energy losses in high-frequency power converters. Soft-switching techniques allow a reduction of these losses, but even under soft-switching conditions, these losses can be significant, especially at light load and very high switching frequency. In this paper, hysteresis and energy losses are shown during the charge and discharge of the output capacitance (COSS) of commercial high voltage Superjunction MOSFETs. Moreover, a simple methodology to include information about these two phenomena in datasheets using a commercial system is suggested to manufacturers. Simulation models including COSS hysteresis and a figure of merit considering these intrinsic energy losses are also proposed. Simulation and experimental measurements using an LLC resonant converter have been performed to validate the proposed mechanism and the usefulness of the proposed simulation models.

**Keywords:** soft-switching; Superjunction MOSFET; LLC resonant converter; zero voltage switching; COSS hysteresis; COSS intrinsic energy losses

### **1. Introduction**

During the last 15 years, the acceptance of resonant converters in the industry application market has been massive, especially regarding adapters, flat panel TVs, electric and hybrid vehicle (EV/HEV), datacenters, and photovoltaic (PV) inverters, among others [1–3] (Figure 1). Besides, new markets and research centers are focusing on moving to higher frequencies to obtain further advantages and gaining power density, taking the present technologies in semiconductors to their physical limit. This is the case of gallium nitride (GaN) and silicon carbide (SiC) technologies, which are thought to be used in the market of resonant converters for low power and high-frequency applications, besides other well-known high-power applications.

A resonant topology operating at a high switching frequency and zero voltage switching (ZVS) provides high power density and is commonly chosen for the previously mentioned applications. The primary side power transistors used in a resonant converter must comply with high-voltage and high-frequency requirements, and need to be properly selected to provide good performance. However, the information given by the manufacturers of these transistors is not usually enough to calculate all the existing energy losses.

**Figure 1.** Markets in which resonant converters are used, for different ranges of frequencies (kHz) and power (kW). EV/HEV, electric and hybrid vehicle; PV, photovoltaic.

The parasitic output capacitance (COSS) of the power transistors has an important role in energy losses, even under ZVS conditions. Traditional switching losses models are not valid for very high switching frequencies. In the work of [4], significant energy dissipation in the process of charging and discharging COSS of Superjunction MOSFET (SJ-MOSFET) while the gate is shorted to the source is observed. In another paper [5], these intrinsic energy losses (Ei) are measured and compared in different power switches, including Silicon SJ-MOSFETs, GaN cascode, SiC cascode, and SiC MOSFETs. These Ei cannot be eliminated by using ZVS and set an upper limit for the switching frequency of the converters. Similar losses are presented in the work of [6], where energy dissipation during the charging and discharging of the junction capacitance of SiC Schottky diodes is evaluated. In the work of [7], the Ei are included for the determination of soft-switching losses of 10 kV SiC MOSFET modules. Calorimetric measurements are used to evaluate these losses (based on the charge and discharge of the COSS, and especially of the antiparallel junction barrier Schottky diode). In the work of [8], the variation of Ei with dV/dt is evaluated at very high switching frequency (1–35 MHz) in silicon (Si) and wide-bandgap active devices.

In the work of [9], these Ei are related to a significant hysteresis exhibited by the COSS of some of the most advanced SJ-MOSFETs. In a further paper [10], the physical mechanism responsible for this COSS hysteresis is briefly shown by means of mixed-mode simulations. Finally, mixed-mode simulations are also proposed to analyze Ei and the cause of the COSS hysteresis in different SJ-MOSFETs in the work of [11].

The authors of this paper have previously analyzed the COSS hysteresis and its related switching losses (including Ei) for different dead-times of three generations of SJ-MOSFETs in an LLC resonant converter in the work of [12]. Moreover, they provide a guideline to select SJ-MOSFETs of different manufacturers to improve the efficiency of this converter in a wide power range in the work of [13].

In this paper, a simple methodology is suggested to manufacturers to include information related to the COSS hysteresis and Ei of power devices in their datasheets. These data will be useful to select the optimum devices in high-frequency and soft-switching applications. Moreover, a spice model including the COSS hysteresis and a figure of merit (FoM) including Ei are proposed in Section 2 and 3, respectively. Both proposals are validated using simulation and experimental results of an LLC resonant converter in Section 4.

### **2. Spice Model Including COSS Hysteresis E**ff**ect**

In order to design a resonant converter with low cost and high efficiency and power density, special attention is crucial during the selection of the high-voltage (~600 V) silicon SJ-MOSFET device needed. However, even if the high-voltage SJ-MOSFETs are selected based on major vendors recommendations for soft-switching applications in resonant converters, they present different values of Ei. Ei might not seem so significant for hard-switching conditions, but it can make the difference under soft-switching operation, especially for low and medium load demands, where conduction power losses are lower and switching losses are relevant because of the high-frequency operation.

Ei is intrinsic to the structure of SJ-MOSFETs, as it is briefly reproduced in Figure 2a–c and explained in detail in the work of [12], where a physical relationship between COSS hysteresis and Ei was demonstrated, elucidating the existence of energy losses during the charge and discharge of COSS. Holes and electrons (h+ and e-, respectively, in Figure 2), flowing in parallel to the capacitance, originate stucked charges between the pillars that need to be removed through highly resistive paths that may vary among devices.

**Figure 2.** (**a**) Cross section of a Superjunction (SJ)-MOSFET basic cell. Description of (**b**) COSS charge and (**c**) COSS discharge. Electron (e-) and hole (h+) currents and charge pockets are indicated (red and blue). (**d**) Illustrative comparison between COSS extracted by small-signal (solid blue line) and large-signal (green dashed and red dotted lines).

Ei used to be neglected [14,15], but some simulations models started to consider non-linear COSS effects, and non-ZVS operation of SJ-MOSFETs [16–18]. However, COSS hysteresis discoveries are not still considered in those simulation models.

The degree of severity of COSS hysteresis varies from device to device depending on technological and geometrical features. Up to now, application notes and datasheets do not provide any information regarding this phenomenon. Besides, manufacturers only give small-signal characterization of the transistors, whereas COSS hysteresis is only detectable during large-signal analysis (Figure 2d). In order to solve this fact, a simple methodology to include in the datasheets enough information to generate simulation models predicting this behavior will be proposed.

In contrast to other reported techniques, a commercial system commonly used by power devices manufactures, an Auriga pulsed I–V system [19], is proposed. This characterization system is able to capture measurements with very high speed and resolution (up to 0.01% of max current), and it is temperature independent. Moreover, voltage/current measurements have emerged as the preferred method of capturing different characteristics of active devices. The simple setup and the voltage and current waveforms obtained using one of the SJ-MOSFETs under test are shown in Figure 3.

**Figure 3.** Auriga pulsed I–V tests: ID and VDS waveforms.

Using these voltage/current measurements, COSS large-signal curves during its charge and discharge can be inferred using

$$\mathcal{C}\_{\rm OSS} = \frac{I\_D}{\frac{dV\_{DS}}{dt}}.\tag{1}$$

Following the presented procedure, COSS large-signal curves during its charge and discharge of the SJ-MOSFETs under test (Table 1) were estimated (as an example, results of device under test 1 (DUT1) are included in Figure 4).

**Figure 4.** COSS large-signal curves of device under test 1 (DUT1) (Table 1) during its charge and discharge obtained using (1) and the Auriga pulsed I–V curves.

A detailed simulation model should include this behavior to obtain accurate simulation waveforms of the switching process. The calculated COSS could be described using a polynomial expression, but in this paper, the use of look-up-tables with pairs of values voltage-capacitance is proposed. Two different look-up-tables, one for the charge and one for the discharge, can be easily included in the spice model of the SJ-MOSFETs. This option is preferred (compared with polynomial expressions) from the point of view of saving computational time and the ease to use, follow, and change data if a different power device is chosen for simulation. The simulations results using the proposed model will be shown and compared with the experimental results in Section 4.



COSSstored energy at VDS= 400V. 2 Output characteristic charge, result of charging COSS (time-related effective output capacitance is considered) rising from 0 to 400

 V.

1 ### **3. Simple Methodology to Include Ei in the Datasheets**

The cumulative energy (ECUM) of COSS can be calculated with the previously shown voltage and current waveforms obtained using the Auriga pulsed I–V system.

$$E\_{\rm CLIM} = \int I\_D \cdot V\_{DS} \, dt. \tag{2}$$

Using (2), the energy stored during the charge and extracted during the discharge of COSS can be easily estimated. In Figure 5, an example of the value of ECUM using one of the SJ-MOSFETs under test is shown as an example. As can be seen, the stored energy is higher than the extracted energy, and this difference is the value of Ei. Concretely, Ei is considered as the energy losses after applying a complete cycle of charge–discharge to the device, and consequently is directly related to COSS hysteresis.

**Figure 5.** Auriga pulsed I–V tests: ID and VDS waveforms. Procedure to obtain the cumulative energy and the value of Ei to propose the new figure of merit (FoM).

The proposed FoM, defined as the conduction resistance (RON) multiplied by Ei, considers both RON (important for heavy loads) and Ei (crucial for low and medium loads), allowing a proper selection of SJ-MOSFETs in soft-switching applications operating at high frequencies. The lower the FoM value of an SJ-MOSFET, the higher its performance. In Section 4, the prediction of the performance of different SJ-MOSFETs using this FoM is validated with experimental efficiency results.

Besides, it is worth mentioning that, as occurring in other common FoMs, the direct and indirect proportionalities of RON and Ei with the die area result in an area-independent FoM. This is a preferred FoM approach to facilitate the benchmarking between technologies. In addition, common to other FoMs are the limitations for devices with a small die area, where the termination area could be as relevant as the active area of the transistor (RON does not perfectly scale with the die area).

### **4. Validation of the Proposed Simulation Model and FoM**

The power supplies used in the applications mentioned in the introduction of this paper must comply with challenging standards, such as 80PLUS Titanium® [20]. An LLC resonant converter is the topology generally selected to develop this kind of power supply, mainly owing to their high efficiency and power density. More information and new models are needed to properly design these power converters operating at a very high switching frequency.

Silicon SJ-MOSFETs are the preferred devices during the design of the primary side of the LLC resonant converter as they meet the requirements regarding voltage, current, and frequency, and an accurate procedure for their proper selection for each specification is important, especially operating at a high switching frequency. The devices under test (DUT) in this work are detailed in Table 1. SJ-MOSFETs with similar voltage blocking capability, RON, and QOSS are selected in order to obtain a fair comparison under the same working conditions. In all the tests, ZVS is assured and, consequently, differences in the value of RG are not relevant because the switching losses were forced to be independent of RG. Exhaustive experimental tests are carried out using an LLC resonant converter with the DUTs. Waveforms, breakdown losses, and efficiency results are analyzed and compared.

### *4.1. LLC Resonant Converter Description*

The previously described SJ-MOSFETs were tested in a commercial evaluation board of an LLC resonant converter [21] featuring the specifications of Table 2.


**Table 2.** LLC resonant converter evaluation board specifications.

The fundamental requirements related to a fixed resonant tank (CR, LR, and LM) and deadtimes (tD) are fulfilled, guaranteeing the ZVS inductive mode for the whole power range and for all the transistors under examination [13]. As the devices selected share very close values of RON and QOSS, there is no need to redesign different LM values for each transistor, reassuring ZVS the whole load range. A simplified scheme of the LLC resonant converter with the main components and the sensing methods is shown in Figure 6.

**Figure 6.** Simplified circuit scheme of the LLC resonant converter and sensing method.

Mixed-mode (MM) simulations were also carried out to analyze the evolution of certain signals that cannot be experimentally measured (as the current through the channel of the MOSFETs). The developed MM simulations consist of spice circuits, where the half-bridge (HB) structure of the primary side of the LLC resonant converter is replaced by TCAD (Technology Computer Aided Design) structures (finite-element structures) simulating the power transistors (DUTHIGH and DUTLOW in Figure 6).

Calibration of TCAD structures was done by means of process simulations in the case of own SJ-MOSFETs technologies, and by means of reverse engineering and reverse calibration technique in the case of other commercial SJ-MOSFETs technologies. Information about the doping profiles is included in the TCAD structures and data regarding voltages, power, magnetics, frequencies, and so on are extracted from the evaluation board datasheet [21].

The accuracy of the MM simulations and its good match with experimental waveforms can be seen in Figure 7. Moreover, the current through the channel of the DUTLOW (ICH) obtained using MM simulation (it cannot be experimentally measured) was included to verify the ZVS operation (ICH falls to zero before VSW is increased). As ICH is zero before VSW rises, the area below PINS waveform represents the energy stored in the output capacitance of the SJ-MOSFET during the turn-off (Eoff). This energy cannot be considered as losses, because it can be retrieved in the turn-on.

**Figure 7.** Simulated and measured waveforms for DUTLOW during the turn-off. ISHUNT, VGS, and VSW are referenced in Figure 6. PINS is the instantaneous power (product of VSW and ISHUNT) and ICH is the simulated current through the channel of the SJ-MOSFET.

### *4.2. Experimental Results, E*ffi*ciency, and Power Losses Break-Down*

Several experimental measurements and waveforms are analyzed to validate the proper operation of the converter at different loads and with different DUTs. Examples of experimental waveforms measured in the converter are shown in Figure 8.

**Figure 8.** Experimental IRES and VSW measured at different loads for DUT1 as an example of how the resonant current varies with the load. As can be seen, different switching frequencies are also used for different loads.

In Figure 8, the current through the resonant tank (IRES in Figure 6) is shown for different power levels, as well as its corresponding VSW waveform. As can be seen, the IRES value during the transition of both DUTs remains almost the same regardless of the load level, which will be helpful to estimate switching losses (they are calculated by means of the energy dissipated during the turn-on and turn-off) and to understand the behavior of the transistors during these transitions.

An efficiency comparison of the LLC resonant converter using all the DUTs as the primary side transistors is carried out in the whole power range, going from 10% to 100% of full load (600 W), always following the same test protocol and operating conditions. In order to minimize error measurements and its influence on the efficiency comparison, a repetitive protocol was performed using an automatic program based on Java. First, the converter is turned-on at 10% of maximum load, and it remains under this working condition for 15 minutes to achieve a constant working temperature. Then, the efficiency at 10% of maximum load is measured (this measurement is the result of averaging 10 consecutives measurements of VIN, VOUT, IIN, and IOUT). Finally, the load is increased, and new measurements are done after one minute. This procedure is repeated to 20%, 30%, 50%, 70%, and 100% of full load. In Figure 9, the differential efficiencies obtained are shown, taken as reference DUT1, as it is the device that shows best performance for the whole range.

**Figure 9.** Differential efficiencies of the LLC resonant converter with respect to the best SJ-MOSFET (DUT1).

Using experimental waveforms of VGS, VSW, and ISHUNT, switching (PSW), driving (PDR), and conduction (PON) power losses contributions from each DUT are calculated for three power loads demands of 60 W (10%), 300 W (50%), and 600 W (100%), and are shown in Figure 10a–c, respectively.

**Figure 10.** Measured power losses owing to driving (PDR), switching (PSW), and conduction (PON) at (**a**) 10%, (**b**) 50%, and (**c**) 100% load for each primary-side SJ-MOSFET.

In Figure 10a, at a low load, whereas low PON losses remain almost equal for all the DUTs, differences in PDR losses have a small impact and PSW losses are dominant. For heavy loads (Figure 10c), PON is by far the main factor of losses in the SJ-MOSFETs, yet disparity among the PSW losses is discernible. At a medium load (Figure 10b), divergence in PSW among transistors makes the difference (PON losses are the highest, but fairly the same value, but differences at PSW have a great impact in the losses contribution). Even performing ZVS, PSW losses are relevant and differences in the total power losses between DUTs are the result of PSW + PDR at light loads (Figure 10a) and PSW + PON at heavy loads (Figure 10c). These PSW losses under ZVS conditions are consistent with the existence of the Ei previously reported.

### *4.3. Validation of the Simulation Model Including COSS Hysteresis*

The developed spice model of all the SJ-MOSFETs under test includes the definition of the COSS with two look-up-tables with pairs of values voltage-capacitance, one for the charge and one for the discharge (obtained using the procedure presented in Section 2). On the basis of the circuit proposed in Figure 6 and using the proposed spice models of the SJ-MOSFETs, some simulations of the LLC resonant converter are carried out using LTSpice. In these simulations, emphasis is on the primary side of the converter and the accurate definition of the COSS value. Experimental and simulated VSW waveforms are compared in Figure 11 and good agreement is obtained.

**Figure 11.** VSW waveform extracted by experimental measurement (green) and simulation with the proposed large-signal spice model (red) during (**a**) the increase of VSW and (**b**) the decrease of VSW.

It should be noted that the equivalent capacitance seen from the port defined by VSW is the parallel combination of the output capacitance of DUTLOW and DUTHIGH (two nonlinear capacitors), defined as

$$\mathbf{C\_{eq}} = \frac{\mathbf{C\_{OSS\_{DIT\_{LOW}}}}(V\_{SW}) \cdot \mathbf{C\_{OSS\_{DIT\_{HIGH}}}}(V\_{IN} - V\_{SW})}{\mathbf{C\_{OSS\_{DIT\_{LOW}}}}(V\_{SW}) + \mathbf{C\_{OSS\_{DIT\_{HIGH}}}}(V\_{IN} - V\_{SW})} \tag{3}$$

Taking into account that the value of COSS of each SJ-MOSFET is different during its charge and discharge, Ceq is not symmetric (as presented in previous works not including the COSS hysteresis [15]) and a different value is obtained when VSW goes up and down. As can be seen in Figure 12, the equivalent impedance during the increase of VSW (Ceq1) has the same value at high voltage than the equivalence impedance during the decrease of VSW (Ceq2) at low voltage. Consequently, in Figure 11, similar VSW evolution can be seen in the corners marked as A and B during the increase and the decrease of VSW. The proposed spice model captures the corner asymmetry (see corners A and B have different curvature) when VSW goes up and down during DUTLOW turn-off and turn-on transitions, thus being consistent with the existence of a COSS hysteresis and matching the experimental measurements.

**Figure 12.** Derivation of Ceq1 and Ceq2, which are asymmetric with respect to the charge and discharge of the COSS of DUTHIGH and DUTLOW. (**a**) Increase of VSW and (**b**) decrease of VSW.

### *4.4. Validation of the Proposed FoM including Ei*

In Figure 9, there is not a clear trend regarding the efficiency that DUTs show for different load demands. Some of them might be suitable for low power, but, in contrast, their performance is worse at full load. That is the case of DUT5. FoMs based on the information provided by the datasheet do not always explain these differences in operation. For example, the worse performance at full load of DUT5 can be explained by its high on-resistance, but the performance for a light load of DUT5 is better than the performance of DUT6, while their switching characteristics are almost the same (even a bit better than those of DUT6).

Consequently, new FoMs are needed to know in detail where the power losses come from, as a great percentage of the converter total losses is attributable to the primary-side SJ-MOSFETs [13] for the whole load range. The proposed FoM should allow a proper selection of the SJ-MOSFETs in an LLC resonant converter. In the last column of Table 1, the value of the proposed FoM for all the DUTs is included, while in Figure 13, these values are compared with respect to DUT1.

**Figure 13.** Comparison of the proposed FoM of the DUTs.

The best performance of the LLC is obtained with DUT1, which also has the lowest value of the proposed FoM. DUT2, DUT3, and DUT5 have low values of the proposed FoM and the performance of the LLC with them is also good, especially at medium and light loads. DUT4 has the highest value of the proposed FoM, and the LLC with this DUT has the lowest performance.

As can be clearly seen, the proposed FoM can predict the better performance of the LLC with DUT5 than with DUT6 (especially at light load), which cannot be explained using the characteristics from datasheets.

### **5. Conclusions**

The existence of Ei in power devices, which produces significant switching energy losses in high switching frequency power converters, even under ZVS, has been shown in this paper. Moreover, Ei are related to a COSS hysteresis.

A simple methodology using a commercial system is suggested to manufacturers to provide Ei (which is not included in datasheets) and information about the COSS hysteresis. The relevance of the COSS hysteresis information is validated by developing simulation models that accurately match the experimental charge and discharge waveforms of the COSS. These new models will allow the designer to better predict the behavior of the power devices and their corresponding power losses, in order to to be able to design more efficient applications.

Efficiency experimental results on an LLC resonant converter are used to validate the suitability of the proposed FoM including Ei, to properly select the transistors used in soft-switching power converters operating at high frequencies.

The impact of these kinds of losses is important in high switching frequency power converters and should be properly modelled to be able to predict the performance of different commercial power transistors in case the designer needs to compare several of those for a certain application; consequently, new data and models are needed.

**Author Contributions:** Conceptualization, J.R.; methodology, M.R.R.; software, G.G.; validation, M.R.R.; formal analysis, A.R.; resources, P.V.; writing–original draft preparation, M.R.R. and A.R.; writing–review and editing, A.R., D.G.L., and J.R.; supervision, A.R., J.R., and D.G.L.; All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was supported by the Spanish Government under projects MCIU-19-RTI2018-099682-A-I00 and by the Principado de Asturias under the project FC-GRUPIN-IDI/2018/000179

**Conflicts of Interest:** The authors declare no conflict of interest.

### **Nomenclature**


### **References**


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