*6.2. ISIP-OSOP Generic DC-DC Converter Small-Signal Analysis*

The SSM for the ISIP-OSOP converter shown in Figure 8 is derived using the SSM presented in [37], and expanding the study of the presented multimodule DC-DC converters presented in [38–42].

**Figure 8. n** module Input-Series Input-Parallel Output-Series Output-Parallel (ISIP-OSOP) DC-DC converter SSM.

Since the input current and voltage per module are *Iin* <sup>α</sup> and *Vin* <sup>β</sup> , respectively, and the output current and voltage per module is *Io <sup>a</sup>* and *Vo <sup>b</sup>* , respectively. Therefore, the load resistance per module is *<sup>a</sup> b R*. Accordingly, ˆ *dij* and ˆ *dv*j, which are the effect of changing the filter inductor current and the effect of changing the input voltage on the duty cycle modulation, as well as *Ieq* presented in Figure 8 can be expressed as [39,42]:

$$\text{S\,d}\_{ij} = -\frac{4\text{\\$}\text{L\,d}\_{\text{lk}} f\_{\text{l},j}}{K V\_{\text{in}}} \text{\,^\*\_{\text{l},j} \quad j = 1, 2, \dots, n} \tag{94}$$

Equation (94) can be re-written as:

$$\hat{d}\_{ij} = -\frac{\mathsf{p}\mathsf{K}\mathsf{R}\_d}{V\_{\rm in}}\hat{\mathsf{i}}\_{\rm Lj}, \quad j = 1, 2, \ldots, n \tag{95}$$

where *Rd* <sup>=</sup> <sup>4</sup>*Llk fs <sup>k</sup>*<sup>2</sup> .

$$\hat{d}\_{vj} = \frac{4\mathfrak{gl}L\_{lk}f\_sD\_{eff}}{ak^2RV\_{in}}\mathfrak{d}\_{cdj\prime} \quad j = 1,2,...,n\tag{96}$$

Equation (96) can be re-written as:

$$d\_{vj} = \frac{\Re R\_d D\_{eff}}{a R V\_{in}} \mathfrak{d}\_{c d j \prime} \quad j = 1, 2, \ldots, n \tag{97}$$

$$SI\_{c\eta} = \frac{bV\_{in}}{\beta aKR} \tag{98}$$

The following equations are obtained from Figure 8:

$$\begin{cases} \begin{array}{c} \frac{D\_{eff}}{K} \mathfrak{d}\_{cd1} + \frac{V\_{in}}{\mathfrak{PK}} \Big(\hat{d}\_{i1} + \hat{d}\_{v1} + \hat{d}\_{1}\Big) = sL\hat{I}\_{L1} + \mathfrak{O}\_{out1} \\\\ \frac{D\_{eff}}{K} \mathfrak{d}\_{cd2} + \frac{V\_{in}}{\mathfrak{PK}} \Big(\hat{d}\_{i2} + \hat{d}\_{v2} + \hat{d}\_{2}\Big) = sL\hat{I}\_{L2} + \mathfrak{O}\_{out2} \\\\ \vdots \\\\ \frac{D\_{eff}}{K} \mathfrak{d}\_{cdn} + \frac{V\_{in}}{\mathfrak{PK}} \Big(\hat{d}\_{in} + \hat{d}\_{vn} + \hat{d}\_{n}\Big) = sL\hat{I}\_{Ln} + \mathfrak{O}\_{outn} \end{array} \tag{99}$$

$$\begin{aligned} \hat{\imath}\_{L11} + \hat{\imath}\_{L21} + \dots + \hat{\imath}\_{La1} &= \frac{s\mathcal{C}}{s\mathcal{R}\mathcal{C} + 1}\mathcal{O}\_{out1} + \frac{\triangle\_{out}}{\mathcal{R}}\\ \hat{\imath}\_{L12} + \hat{\imath}\_{L22} + \dots + \hat{\imath}\_{La2} &= \frac{s\mathcal{C}}{s\mathcal{R}\mathcal{C} + 1}\mathcal{O}\_{out2} + \frac{\triangle\_{out}}{\mathcal{R}}\\ \vdots\\ \hat{\imath}\_{L1b} + \hat{\imath}\_{L2b} + \dots + \hat{\imath}\_{Lab} &= \frac{s\mathcal{C}}{s\mathcal{R}\mathcal{C} + 1}\mathcal{O}\_{outb} + \frac{\hat{\imath}\_{out}}{\mathcal{R}} \end{aligned} \tag{100}$$

Based on the feature of modularity, it is assumed that all the employed modules are ideal. Moreover, the Equivalent Series Resistance (ESR) of the output capacitance is considered in this model. Summing Equations in (100):

$$\sum\_{i=1}^{a} \sum\_{j=1}^{b} \hat{\imath}\_{Lij} = \frac{\text{sC}}{\text{sR}\_c \text{C} + 1} \vartheta\_{out} + \frac{b \vartheta\_{out}}{R} \tag{101}$$

Equation (101) can be written as:

⎧ ⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎩

$$\sum\_{i=1}^{a} \sum\_{j=1}^{b} \hat{\imath}\_{Lij} = \vartheta\_{out} \left( \frac{sRC + s\mathbf{b}R\_cC + b}{R(1 + sR\_cC)} \right) \tag{102}$$

Defining the summation terms of the module's input and output voltage appearing after summing up Equations in (99):

$$\sum\_{j=1}^{n} \mathfrak{d}\_{cdj} = \mathbf{y} \mathfrak{d}\_{in} \tag{103}$$

where:


$$\sum\_{j=1}^{n} \hat{v}\_{outj} = c\hat{v}\_{out} \tag{104}$$

where:

