**3. Discrete Fast Terminal Sliding Mode Controller Design for the Buck Converter**

During the charging of the ultra-capacitor, its voltage *Uuc* and current *Iuc* vary in real time due to which *RL* constantly varies and can be derived as follows,

$$R\_L = \frac{\mathcal{U}\_{uc}}{I\_{uc}}\tag{26}$$

The ultra-capacitor can be charged at maximum efficiency if the system output power is equal to the optimal power, i.e., *Pout*=*Pop*. However, if initially, *Uuc* is too low and it is charged with high power, then it will draw an enormous amount of current, which can damage the system. To solve this issue, the charging of the ultra-capacitor is divided into two stages. The charging strategy is shown in Figure 9. In the first stage, constant current *Iref* is provided to the ultra-capacitor till its voltage *Uuc* reaches *U<sup>r</sup> uc*, then in the second stage, it is charged with optimal power *Pop* for maximum efficiency.

**Figure 9.** Charging strategy for the ultra-capacitor.

In order to regulate the output current (*Iout*) and output power (*Pout*) to the desired *Iref* and *Pop*, respectively, a buck converter at the secondary side of the proposed system is used. The required references can be tracked by controlling the duty cycle of the switch *S*5. The circuit diagram of the buck converter is shown in Figure 3. Under the assumption that the buck converter is operating in continuous conduction mode, the following dynamic model is derived.

$$I\_L = u\frac{V\_{ab}}{L} - \frac{\mathcal{U}\_{out}}{L} \tag{27}$$

$$
\dot{\mathcal{U}}\_{\rm out} = \frac{I\_L}{\mathcal{C}} - \frac{\mathcal{U}\_{\rm out}}{R\_L \mathcal{C}} \tag{28}
$$

where *IL* and *Uout* are the values of the inductor current and capacitor voltage. *u* = [0, 1] is the duty ratio, used to generate the driving cycle for the switch. For the control design, we will average the model over one switching period. If *x*<sup>1</sup> is the average value of *IL*, *x*<sup>2</sup> is the average value of *Uout*, and *μ* is the average value of *u*, then Equations (27) and (28) take the form,

$$
\dot{x}\_1 = \mu \frac{V\_{ab}}{L} - \frac{x\_2}{L} \tag{29}
$$

$$
\dot{\mathbf{x}}\_2 = \frac{\mathbf{x}\_1}{\mathbf{C}} - \frac{\mathbf{x}\_2}{\overline{\mathbf{R}}\_L \mathbf{C}} \tag{30}
$$

By controlling the output voltage of the buck converter, the output current *Iout* and output power *Pout* of the proposed structure can be tracked to the desired references, i.e., *Iref* and *Pref* , respectively.

$$V\_{r1} = I\_{ref} R\_L \tag{31}$$

$$V\_{r2} = \sqrt{P\_{op} R\_L} \tag{32}$$

A discrete fast terminal sliding mode controller is designed to generate the required duty ratio for these reference voltages. For this purpose, an error signal is defined.

$$x\_1 = x\_2 - V\_{rj} \tag{33}$$

where (*j* = 1,2). When *j* = 1, the controller will track constant current, and for *j* = 2, the controller will track constant power. By converging the *e*<sup>1</sup> to zero, we can get our desired result. The dynamic model in Equations (29) and (30) can be rewritten as,

$$
\dot{\varepsilon}\_1 = \dot{x}\_2 - \dot{V}\_{r\dot{j}} = \frac{\mathcal{X}\_1}{\mathcal{C}} - \frac{\mathcal{X}\_2}{R\_L \mathcal{C}} - \dot{V}\_{r\dot{j}} \tag{34}
$$

To simplify the expressing, a new variable *e*<sup>2</sup> is defined as,

$$
\epsilon\_2 = \dot{\epsilon}\_1 \tag{35}
$$

Taking the derivative of *e*<sup>2</sup> and using Equations (34), (29), and (30), it yields:

$$\dot{\omega}\_2 = \frac{1}{LC} \left( \mu V\_{ab} - \left( \mathbf{x}\_2 - V\_{r\dot{j}} \right) - V\_{r\dot{j}} \right) - \frac{\dot{\mathbf{x}}\_2}{RC} + \frac{\dot{V}\_{r\dot{j}}}{RC} - \dot{\mathcal{V}}\_{r\dot{j}} \tag{36}$$

The overall dynamic model can be represented as follows,

$$\begin{cases}
\dot{\varepsilon}\_1 = \varepsilon\_2 \\
\dot{\varepsilon}\_2 = \frac{1}{\text{LC}} \left(\mu V\_{ab} - \varepsilon\_1 - V\_{r\bar{j}}\right) + \frac{1}{\text{RC}} \left(\dot{V}\_{r\bar{j}} - \varepsilon\_2\right) - \ddot{V}\_{r\bar{j}}
\end{cases} \tag{37}$$

Using Euler's discretization method, the dynamical model presented in Equation (37) can be discretized as follows,

$$\begin{cases} \varepsilon\_1 \left( k+1 \right) = \quad \varepsilon\_1 \left( k \right) + h \varepsilon\_2 \left( k \right) \\ \varepsilon\_2 \left( k+1 \right) = \quad \varepsilon\_2 \left( k \right) + \frac{h}{\text{LC}} \left( \dot{V}\_{\text{f}} \left( k \right) - \varepsilon\_2 \left( k \right) \right) - h \dot{V}\_{\text{f}} \left( k \right) + \frac{h}{\text{LC}} \left( \mu \left( k \right) V\_{ab} \left( k \right) - \varepsilon\_1 \left( k \right) - V\_{\text{f}} \left( k \right) \right) \end{cases} \tag{38}$$

where *h* is the sampling period. To converge these error signals to zero, a fast terminal sliding surface can be designed as follows,

$$s\left(k\right) = \left.e\_2\left(k\right) + a\_1e\_1\left(k\right) + a\_2\operatorname{sign}\left(e\_1\left(k\right)\right)\left|e\_1\left(k\right)\right|^{\frac{p}{q}}\tag{39}$$

where 0 < *<sup>α</sup>*1*<sup>h</sup>* < 1, 0 < *<sup>α</sup>*2*<sup>h</sup>* < 1, and 0 < *<sup>p</sup> <sup>q</sup>* < 1 with *p* and *q* positive odd integers. As discussed in [32], the sliding mode condition occurs when *s*(*k* + 1) = 0, and Equation (39) becomes,

$$\text{res}\left(k+1\right) = 0 \Rightarrow \mathfrak{e}\_2 \text{sign}\left(\mathfrak{e}\_1\left(k+1\right)\right) \left|\mathfrak{e}\_1\left(k+1\right)\right|^{\frac{p}{q}} + \mathfrak{e}\_2\left(k+1\right) + \mathfrak{e}\_1\mathfrak{e}\_1\left(k+1\right) = 0\tag{40}$$

Substituting Equation (38) into (40), it yields,

$$\begin{split} 0 &= \varepsilon\_2\left(k\right) + \frac{h}{L\mathcal{C}}\left(\mu\left(k\right)V\_{a\flat}\left(k\right) - \varepsilon\_1\left(k\right) - V\_{\overline{\gamma}}\left(k\right)\right) + \frac{h}{RC}\left(\dot{V}\_{\overline{\gamma}}\left(k\right) - \varepsilon\_2\left(k\right)\right) + a\_1\left(\varepsilon\_1\left(k\right) + h\varepsilon\_2\left(k\right)\right) \\ &+ a\_2\text{sign}\left(\varepsilon\_1\left(k\right) + h\varepsilon\_2\left(k\right)\right)\left|\varepsilon\_1\left(k\right) + h\varepsilon\_2\left(k\right)\right|^{\frac{p}{q}} - h\dot{V}\_{\overline{\gamma}}\left(k\right) \end{split} \tag{41}$$

Finally by solving Equation (41), the DFTSMC law can be obtained as,

$$\begin{split} u(k) &= \frac{-\mathcal{L}\mathcal{C}}{hV\_{ab}} \left( e\_2\left(k\right) \left(1 - \frac{h}{RC} + a\_1 h\right) + \frac{h\dot{V}\_{r\bar{\eta}}(k)}{RC} \right) - \frac{\mathcal{L}\mathcal{C}}{hV\_{ab}} \left( e\_1\left(k\right) \left(a\_1 - \frac{h}{LC}\right) - h\ddot{V}\_{r\bar{\eta}}(k) - \frac{hV\_{r\bar{\eta}}}{LC} \right) \\ &- \frac{\mathcal{L}\mathcal{C}}{hV\_{ab}} \left( a\_2 \text{sign}\left(e\_1\left(k\right) + hc\_2\left(k\right)\right) \left|e\_1\left(k\right) + hc\_2\left(k\right)\right|^{\frac{p}{q}} \right) \end{split} \tag{42}$$

### **4. Results and Discussion**

To verify the performance of the proposed controller, simulations were performed in MATLAB/Simulink using the "Sim Power Systems" toolbox under the abrupt and time-varying fluctuation in load *RL*. The uncontrolled rectifier was connected to the load through the buck converter, which was controlled by the DFTSMC. Under variations in "*RL*", DFTSMC could regulate the output current *Iout* and output power *Pout*. The specifications of the wireless charging system are shown in Table 1. Using Equations (9)–(11), the parameters of the compensation network were designed and are listed in Table 2. The parameters of the buck converter and DFTSMC are listed in Table 3.

**Table 1.** Wireless charger parameters.



**Table 2.** Compensation network parameters.

**Table 3.** Buck converter and DFTSMC parameters.


According to the charging strategy shown in Figure 9, the DFTSMC was used to generate duty cycle *u* to regulate the output current to the reference current, i.e., *Iuc* = *Iref* , and the output power to the optimal power *Pout* = *Pop*. The current, voltage, and power of the ultra-capacitor are shown in Figure 10.

**Figure 10.** Current, voltage, and power of the ultra-capacitor.

In the first stage,a5A current was tracked by the DFTSMC, and then, in the second stage, the output power was regulated to the optimal power, i.e., 120 Watts. It can be seen in Figure 11 that when the DFTSMC regulated *Pout* to *Pop*, the *Req* was regulated to *Rop*, i.e., 11 Ω. The duty cycle generated by the DFTSMC, during the charging process, is shown in Figure 12. The efficiency curve is shown in Figure 13, verifying that during the constant power charging stage of the ultra-capacitor, the system operated at a maximum efficiency of about 96%. During the constant power stage, the inverter output voltage and current are shown in Figure 14. According to the voltages and currents in Figure 14, the inverter output power was approximately 129 Watts, which showed that the overall efficiency from the inverter output to the load was approximately 93%.

**Figure 11.** Equivalence resistance of the system.

**Figure 12.** Duty cycle during the charging process.

**Figure 13.** WPT system efficiency during charging process.

**Figure 14.** Inverter output voltage and current.

### *Comparison with Other Control Schemes*

To check the robustness of the DFTSMC and compare it with other control schemes such as PID and SMC, load resistance *RL* was changed abruptly after every 0.1 s, i.e., with a perturbation frequency of 10 Hz. The value of *RL* was initially set at 5 Ω, and then with a fluctuation of 40%, i.e., 2 Ω, it was decremented to 3 Ω and then incremented back to 5 Ω at 0.1 s and 0.2 s, respectively. The perturbation scheme is as follows,

$$R\_L = \begin{cases} 5 \,\Omega, & t\epsilon \,\left[0, 0.1\right)s, \\ 3 \,\Omega, & t\epsilon \,\left[0.1, 0.2\right)s, \\ 5 \,\Omega, & t\epsilon \,\left[0.2, 0.3\right]s, \end{cases}$$

Under the mentioned perturbations in *RL*, a constant output current of 5 A and constant output power of 120 Watts was tracked by the DFTSMC, sliding mode controller (SMC), and PID controller. Figure 15 shows the regulation of the output current to the referenced current, and Figure 16 shows the convergence of the output power to the referenced power, under the mentioned perturbations in *RL*. It can be seen that not only initially, DFTSMC tracked the required current faster, but also under the sudden variations at *t* = 0.1 s and 0.2 s, DFTSMC recovered quickly with respect to PID and SMC with less steady-state error. It can be observed that under these perturbations, although the PID and SMC tracked the required power, compared to DFTSMC, they exhibited initial overshoot, and comparatively, the settling time was large.

**Figure 15.** Regulation of output current, *Iout*, during perturbation in *RL*.

**Figure 16.** Regulation of output Power, *Pout*, during perturbation in *RL*.

### **5. Experimental Validation**

### *5.1. Experimental Setup*

To validate the effectiveness of the proposed system, an experimental platform was fabricated. The topology of the fabricated system was similar to Figure 3, but using DC electronic load instead of the ultra-capacitor. The experiment setup is shown in Figures 17 and 18. The parameters of the

experimental setup are consistent with Tables 1–3. The AC/DC rectifier was used to convert the grid AC voltage into DC voltage, and the high-frequency inverter converted the DC voltage into 40 kHz AC voltage. The transmitter and receiver coils were made from tightly wound litz wire with turns of 23 and 10, respectively. The diameter of the transmitter and receiver coils was 29.5 cm and 18.5 cm, respectively, and the gap between the transmitter and receiver coils was 10 cm. The compensation elements such as filter inductance and capacitors were chosen according to the parameters listed in Table 2. The filter inductance was also made from the litz wire, designed in a DD structure to cancel out the cross-coupling effect due to the transmitter coil [33]. The buck converter was connected to the Chroma programmable DC electronic load 63200E, which was configured in constant resistance mode. The DFTSMC controller for the buck converter was implemented using the STM32F334C8 microcontroller, which generated the required PWM signals to track the constant current and power. The output current, output power, and the inverter output current and voltage were observed using the Tektronix MDO3024 Oscilloscope.

**Figure 17.** Experimental setup.

(**c**) (**d**) **Figure 18.** (**a**) AC/DC rectifier and high-frequency inverter. (**b**) Transmitting and receiving coils' gap. (**c**) Transmitting and receiving coils. (**d**) Uncontrolled rectifier and buck converter.
