4


**Table 2.** Main multilevel inverters advantages.

The development of MLI has been marked by the progress of semiconductor materials technology (IGBT, MOSFET, etc.) and the evident evolution of digital processors (microprocessors, DSP and FPGA). In this sense, in [36], an interesting investigation is presented, and the most important conclusion could be that the use of 4H-SiC constitutes one of the most important aspects that enabled the current development of power converters. Hence, the multilevel inverters are rapidly emerging as a promising alternative in photovoltaic systems for high-power/medium-voltage DC/AC conversion. Within multilevel inverters, the Multilevel Voltage-Source Inverter (MVSI) inverter has go<sup>t</sup> attention for a better quality power supply. In MVSI, the amplitude of the output voltage generally is less than the input, in these cases, the inverter behaves as a buck converter. Therefore, an intermediate boost stage is generally required since, in RES applications, the panel voltage is low. Nevertheless, by including this stage, the complexity of the system control increases, and the efficiency decreases.

There is a close compromise between THD, inverter output levels and filter size. When the levels increases, THD and filter size decrease, but a higher number of components is required. Nowadays, an important challenge is to design schemes with a reduced number of components. Authors in [37] introduce a novel topology, which seeks to reduce the number of switches as shown in Figure 4. This scheme has three power supplies and ten semiconductors to deliver fifteen output levels.

**Figure 4.** Multilevel topology proposed in [37].

The authors propose that the maximum output voltage by using this configuration is:

$$V\_{o,max} = V\_{dc} + 2V\_{dc} = 7V\_{dc} \tag{1}$$

where: *Vdc* is the input power supply and *Vo*,*max* is the output voltage in the load.

The document presented in [38] summarizes the main schemes that make it possible to reduce the number of elements. The work concludes that the reduction of components causes the use of more expensive devices, by raising the voltage rating of semiconductor circuit breakers. Other aspects, such as the increase in the number of energy sources and more complex control schemes are also pointed out. The above approach shows the compromise that exists between the number of energy levels that the converter delivers and the complexity of its control, presenting a proportional relationship between both variables [39].

The grid-connected PV systems must comply with certain standards such as VDE 0126-1-1, which regulates the maximum allowed of leakage current in the system. Leakage current flows when the terminals have high-frequency voltage transitions.This systems generally use transformers to ensure the isolation of the PV system. Hence, it is avoided the appearance of leakage current between the stray capacitances of the panel and the grid [40], causing EMI problems, increased harmonic distortion and possible damage to health. The use of an isolation stage transformer increases as the weight, cost and volume of the system. In addition, this element causes losses in efficiency of around 3%. The newer topologies seek to eliminate this element. The main advantages are higher efficiency, adequate power density, and lower cost [41]. Also, the performance of the control would be affected according to the winding settings [42]. For this reason, transformerless PV inverters capture the interest of the scientific community [43].

The European Network Code "Requirements for Generators" or VDE-AR-N 4105 is aimed at low voltage systems. The code establishes the grid connection standards for generation systems in Germany. The main parameters to monitor are the capabilities for frequency stabilization and the provision of reactive power. A comparative summary of the aforementioned standards is presented in Table 3. In [44], the principal regulations that the grid-connected systems must comply with are summarized.


**Table 3.** German code VDE comparison [45].

#### **3. Neutral Point Clamped Based Topologies**

In NPC inverters, multiple DC sources are generated by dividing the input bus voltage using a capacitors bank as shown in Figure 5a. The topology is recognized as one of the most popular schemes among MLI [46]. Table 4 shows the allowed, potentially destructive, and destructive switching patterns that could be implemented in the basic structure of the Three-Level NPC (3L-NPC) inverters. The NPC converters are mainly employed in high and medium-power range [47,48]. This DC/AC converter have low dv/dt, low THD [49] and can remove common-mode current making it attractive for PV applications [50]. There are certain high-power applications in which NPC inverters allow a higher DC-link voltage and also avoid the series connection of semiconductors in the same branch [51]. This devices have a large number of clamping diodes, unbalance problems in the DC-bus capacitors and a non-uniform distribution of losses in the switches. In standard operating conditions the values of the capacitors must have a value similar voltage. In [52], a new PWM modulation strategy is proposed to control the output voltage and balance the DC bus capacitors for converters.

An alternative to the traditional NPC topology is the Active-NPC (ANPC) scheme. This variant arises to eliminate the previously mentioned disadvantages. In ANPC design, instead of using clamping diodes, bidirectional semiconductors are used, as shown in Figure 5b. In both schemes (NPC and ANPC), it is possible to reduce the leakage current by connecting the middle point of the DC-bus to the grid ground. In this way, the value of *DC* + or *DC* − will depend on the sign of the output current. Therefore, the stray capacitance voltage remains constant and no leakage current arises. The conduction losses can be reduced by using different paths in the zero state. Currently, certain modifications of the traditional PWM have been implemented in ANPC topologies to achieve correct operation of the inverter, reducing conduction losses and achieving a correct balance of the capacitors.

**Figure 5.** Comparison of basic configurations: (**a**) 3L-NPC and (**b**) 3L-ANPC.


**Table 4.** Switching states 3L-NPC.

The techniques for eliminating the leakage current in PV inverters are grouped into two categories. The first introduces one switch to isolate the grid from the panels in freewheeling times. The second category maintains a neutral connection from the grid to the midpoint of the input capacitors and

ensures low-voltage variations. Considering an NPC inverter, the common-mode voltage is defined from Equation (2). From the mathematical point of view the reduction of the leakage current is achieved when there is no variation in the terms *Vcm*−*dm* and *Vcm*. Figure 6 shows a simplified electrical diagram, where the influence of the above terms in the emergence of leakage current is observed.

$$V\_{cm} = \frac{V\_{1n} - V\_{2n}}{2} \tag{2}$$

$$V\_{dm} = V\_{1n} - V\_{2n} \tag{3}$$

where: the common voltage and the differential voltage are defined as *Vcm* and *Vdm*, the voltage at the inverter output at (1) and (2) with respect to the neutral point (n) is defined as *V*1*n* and *V*2*n* respectively.

By considering Equations (2) and (3), *V*1*n* and *V*2*n* can be presented as:

$$V\_{1n} = \frac{V\_{cm} + V\_{dm}}{2} \tag{4}$$

$$V\_{2n} = \frac{V\_{cn} - V\_{dm}}{2} \tag{5}$$

$$V\_{cm-dm} = -\frac{V\_{dm}}{2} \tag{6}$$

where: the relationship between the common mode and the differential mode is determined by *Vcm*−*dm*.

**Figure 6.** Common-mode represented based on simplified electrical circuit diagram.

The control strategy in this type of converter is divided into current loop based controllers and Direct Power Control (DPC). A good dynamic inverter response as well as a simple control scheme are two characteristics present in the DPC technique. The main disadvantage of this control strategy is the presence of a variable-switching frequency. Today this technique is combined with others such as Space Vector Modulation (SVM) [53,54] and MPC to achieve a fixed-switching frequency [55–58]. Control schemes should also include an appropriate modulation strategy, with particular emphasis on capacitor balancing. In this way, safe operation of the switches is achieved, avoiding over-voltage conditions. Table 5 summarizes the works on the modulation techniques for NPC inverters. There are three factors that must be considered for the selection of the modulation strategy [59]:



**Table 5.** Summary of recent works on modulation strategies in NPC inverters.

Most of the methods [68] that reduce the common-mode base their principle on selecting the vectors corresponding to Common-Mode Voltage (CMV) lower or zero without considering the oscillation of the neutral point voltage. In [69], a novel virtual SVM where a zero NP current average and a low CMV in one control cycle is achieved. Martinez et al. in [70], present a comparative analysis on different modulation techniques used in PV inverters. The results of the work throw certain conclusions that are interesting:


An analysis of the lifetime of inverters for photovoltaic applications is carried out in [71], where an NPC based topology and a T-type inverter are compared. The authors conclude that inverters based on the NPC topology have a longer lifetime than T-type inverters. This conclusion exposes the durability and the use of this type of inverter in RES applications [72,73]. In this sense, authors in [74] summarize a group of inverter topologies used in RE applications, highlighting the presence of a low leakage current in each of them. Ma et al. in [72] propose a new PWM strategy for ANPC topologies, the scheme is illustrated in Figure 7. The cited work present a modulation strategy based on an adjustable losses distribution that offers excellent performance and an increase the efficiency of the topology of the 97%. The switching pattern is presented in Table 6.

**Figure 7.** ANPC Half Bridge proposed in [72].

**Table 6.** Switches states of adjustable losses distribution of ANPC Half-Bridge inverter proposed in [72].


Wang et al. in [75] propose a grid-connected 6S-5L-ANPC inverter. The topology reduces the number of switches since eight switches are generally used. This advantage reduces conduction and switching losses. An important comparison with traditional ANPC topologies considering the stress of semiconductor devices, the switching frequency, the switching losses, the conduction losses and the system volume is presented. In PV applications, special attention should be paid to THD. Therefore, the authors select the phase disposition PWM scheme as modulation strategy. This method directly affects the balance of flying capacitors. The proposal achieves a correct balance of the capacitors, also using a selection method to limit its voltage ripple. Figure 8 present the aforementioned topology and Table 7 shows the switching states of the inverter. In total, there are eight possible states. One of the most important results is a THD of 1.6%. The authors also present the equations for sizing capacitors in active and reactive power conditions. Equation (7) establishes the capacitor value under the condition of unit power factor and Equation (8) under reactive power condition.

$$C\_{fc} = \frac{I\_{pk}}{2\Delta V\_{fc} f\_s M} \tag{7}$$

$$\mathcal{C}\_{fc} = \frac{\sum\_{n=1}^{N} \Delta Q\_{fc}}{\Delta V\_{fc}} = \frac{2MI\_{pk}}{\Delta V\_{fc} f\_s} \sum\_{n=1}^{\frac{qf\_s}{2\pi f\_{Line}}} \sin^2(n \frac{f\_{Line}}{f\_s}) 2\pi \tag{8}$$

where: *fLine* represents the line, *fs* is the switching frequency frequency, *Ipk* is the peak value of the output, Δ*Vf c* is the voltage drop, Δ*Qf c* is the electric charge, the modulation index is defined as *M* and *N* is the number of switching cycles.

**Figure 8.** Proposed ANPC inverter topology in [75].


**Table 7.** Operation modes of the proposed topology in [75].

#### **4. Flying Capacitor Based Topologies**

The FC concept was first introduced in 1992; this type of inverter uses different capacitors to deliver various levels of power at the converter output [76]. The topology benefits include attractive properties in different power ranges, however they are more suitable for medium-voltage applications. Another advantage of topology is the possibility of using natural self-balancing. Furthermore, it has an equitable distribution of voltage stress between switches [77]. Also, as in the case of NPC, a single source can be used to generate multiple voltage levels.In commercial applications, the use of FC with more than three output levels are more common than the NPC alternative [78]. The presented topology is generally not used in PV applications. The scheme is more suitable for use in electric vehicles. However, it was decided to include it in work, since it is part of the most widely used voltage-source topologies. Figure 9 illustrates a Five-Level FC (5L-FC) inverter and Table 8 the operation modes are shown.

**Figure 9.** Basic configuration of 5-level inverter based on FC.


Despite the advantages mentioned, FC inverters have certain limitations that are addressed in current works. For example, capacitor banks reduce the life of the system, and sometimes the balance of floating capacitors can be complex [79]. The problem of capacitor voltage balance is the main limitation of the use of the FC topology. Consequently, the scheme has not been generally used in PV applications. In the last decade, investigations related have been reported, for example, in [80], using a *DA*-*DB* duty cycle mismatch measurement between two groups of Three-Level Flying Capacitor (3L-FC) topology switches to control the system without any additional detection. Table 9 summarizes several works between the years 2015–2019.



In [86] a novel converter is proposed, which has certain advantages, for example, reduced voltage stress on semiconductors, a wide voltage gain and a common grounded scheme. These characteristics can be commonly found in this type of inverter, however, FC-based converters are not generally used in RES, since they require a large number of input capacitors that increase the complexity of the techniques for balancing them [87].

THD is reduced with more energy levels at the inverter output. In the case of FC, requires a large number of capacitors. A derivation of this configuration has been presented in [88], where cross-connecting capacitors have achieved a higher voltage level at the output through additional switches.Another of the biggest challenges in this topology is to provide the necessary energy to activate the large number of switches that the scheme has. Ye et al. in [89] present the comparison of five methods that reduce space and increase the efficiency of gate drive power supply circuits. Also, the operation of a multilevel FC inverter where an additional circuit is provided to avoid the defective cell, if it exists, is presented in [90]. However, in this topology, the elements have to be oversized to operate at full-power level when the failure of one of the cells is detected.

The FC design must have several considerations. Various design methodologies are found in the bibliography. For example, authors in [91] propose a methodology based on harmonic representation of the switching functions. The advantage of the proposed methodology lies in the possibility of being extrapolated to any FC-based scheme. Currently the uses of the treated scheme are very varied. There are certain applications in which a DC-bus is used due to voltage variations. Large capacitors are connected in parallel to the bus to avoid such voltage variations. Some of this applications are back-to-back converters, Power Factor Compensators (PFC), and uninterruptible power supply. The FC topology is chosen as the infinite virtual capacitor converter, which is a nonlinear capacitor where the voltage dependence of the load has a flat region and the voltage remains constant [92].

## **5. Cascaded Based Topologies**

The CMLI integrates multiple H-bridge schemes to generate a multilevel voltage [93]. The scheme has certain advantages compared to NPC and FC topologies, for example, they do not employ clamping diodes, in addition, a greater number of energy sources making it more suitable for specific applications such as electric vehicle [94] and PV applications [95]. Another advantage of the CMLI scheme is that, if any device fails in the bridge, the converter will continue to operate although it will deliver less energy. Therefore, this configuration is, to some extent, fault-tolerant. Also, its modularity and smaller filter size make it more attractive for high and medium-power PV applications. Figure 10 present a basic configuration of the CMLI topology, and Table 10 shows the switching pattern for the five output levels.

**Figure 10.** 5L-CMLI basic configuration.


**Table 10.** 5L-CMLI switching table.

Despite the aforementioned advantages, the topology has certain limitations. The main disadvantage is the use of isolated DC sources for each H-bridge. This problem was solved in the FC and NPC topology, but the voltage adjustment of the capacitors is complex [96]. Also, during partial shading the energy captured by the system is reduced. In certain investigations have presented various studies about the partial shading of PV modules, but most of the schemes are complex designs that generally cause a decrease in the efficiency of the system and an increase in the cost of the inverter [97,98].

The selection of the controller in CMLI depends on the topology and the application. Each controller has favorable characteristics in certain systems, ranging from less complexity to a desired dynamic response. Various types of controllers are used with the scheme discussed. The most widely used are PR controller and PI. When used LC or LCL filters using traditional controllers such as PI is not appropriate because it does not completely eliminate the steady state error [99]. Control systems that employ proportional-resonant controllers eliminate steady-state error. These controllers provide infinite gain in resonance frequency. Equation (9) defines the ideal PR control. In [100] a new technique to synchronize MLI with the grid using PR controller is shown. In the presented design, the control scheme has a lower error between the real power and the reference compared to the PI controller.

$$G(S) = k\_P + \frac{k\_i S}{S^2 + w\_o^2} \tag{9}$$

where: *wo* is the fundamental frequency (grid frequency), *kp* and *ki* represent proportional and resonant gains respectively.

Grid-connected systems can be classified according to the Maximum Power Point Tracking (MPPT) method used. The two classifications are centralized or distributed. The distributed technique reports better efficiency in the literature, but is more complex and has a larger volume than the centralized MPPT methods [101]. In the case of cascade inverters, the implementation of a distributed method requires a large number of sensors and considerably increases the cost of the system. Figure 11 illustrates the most common architectures in the distributed MPPT method. In micro-inverters of the Figure 11a, the energy generated by the different modules is injected directly into the grid. In front-end DC optimizers presented in Figure 11b, the converters perform the MPPT separately. Its output is connected in series; thus, the power that is injected into the grid is the sum of each module. If a module has low efficiency, it does not affect the rest of the converters, since each module provides its power separately.

Authors in [102] present a low cost and straightforward distributed MPPT method for energy optimizers in CMLI-based photovoltaic systems using front-end DC optimizers. In [103] a simplified feedforward distributed MPPT method for grid-connected CMLI is presented. The authors use the method as a *"... superior solution for PV system grid integration due to its simple implementation, signal stage power conversion, no added complexity with increasing the number of connected modules, and it eliminates the need for individual control loop for each module..."* It is important to mention that most conventional techniques do not achieve a distributed MPPT, which decreases the efficiency of the system. Goetz et al. in [104] propose a modular Double Cascading H-bridge (*CHB*<sup>2</sup>) topology.

The scheme reduces the output of the inverter filter and achieves a fast dynamic response. The MPPT is carried out in each module, which incorporates a battery for energy storage. The use of batteries in PV applications is avoided since these elements are highly polluting, then they break with the concept of clean energy. One of the essential advantages of the topology is the possibility of being extended to *CHB*<sup>2</sup> circuits in general.

**Figure 11.** Distributed MPPT architectures: (**a**) micro-inverters and (**b**) front-end DC optimizers.

A brief bibliographic review shows the use of topology as a fault-tolerance scheme. In photovoltaic applications, faults distort the output voltage, degrading the power supplied. A fault diagnosis scheme must detect the problem in the shortest possible time to avoid serious failures in the system, and each design requires its strategy. A common problem is considering that the system is in open circuit to monitor its status [105]. Shao et al. in [106], present a technique for detecting faults using Sliding Mode Observer (SMO) able to locate the fault element in the system. The authors in [107] present a detailed review of various faults in photovoltaic systems. The work identifies the main faults as line-line, earth, arc, shadow and others, and proposes its protection strategy. Various strategies are employed for fault detection in PV systems, using standard protection devices or offline/real-time testing of PV systems. Table 11 shows a summary of typical failure cases and respective protection/detection devices.


**Table 11.** Typical fault occurrences and respective protection/detection devices present in [107].

Note: Over Current Protection Devices (OCPDs), Ground Fault Detection and Interruption (GFDI) fuses/Ground Fault Protection Devices (GFPDs), Arc Fault Circuit Interrupters (AFCIs), Residual Current Monitoring Device (RCD), Insulation Monitoring Device (IMD), Earth Capacitance Measurement (ECM).

Currently, there is a trend towards the combined use of PV energy and batteries as a storage medium and certain studies analyze its feasibility. For example, authors in [108] conducts extensive research concluded in 2019, in Finland. The work considers the profitability of BESS investments between the years 2018 and 2035. The authors conclude that, these systems would not be profitable for RES applications at present, although a decrease in costs is estimated from 1270 to 1370 euros/kWh in 2018 to 830–930 euros/kWh in 2035. However, sometimes an uninterrupted flow of energy is required and the use of batteries is essential due to PV power intermittent nature. The BESS output is controllable and the system can be treated as a controllable load [109].

The grid-connected schemes in this typology, as in the previous ones, still have certain challenges. Decreasing the leakage current in transformerless systems is one of the main aspects to consider. In this regard, some research has been carried out, such as [110]. In this work an analysis of the behavior of the leakage current of the different modes of operation of the basic structure CMLI is presented. The analysis considers the common-mode inductor in each switching state and can be simpler if pole voltages are used. Also, the authors propose two schemes of suppression of the leakage current. The first solution uses low-capacitance common-mode capacitors and stray capacitors as part of the output filter. It is included that this solution is suitable for inverters operated at high-frequencies. Solution two is appropriate when the converter uses a switching frequency of less than 1.5 kHz.

Sonti et al. in [111] present a PWM technique to eliminate or reduce leakage current in CMLI-based schemes. The work integrates the applied MPPT and PWM algorithm. In this way, it is possible to reduce the high-frequency transitions of voltage and the CMV. Figure 12 shows the proposed architecture and Table 12 present the switching states. The switches *Sw*4, *Sw*5 and *Sw*6, *Sw*7 operate in a complementary way. Hence, there are three pairs of switches [*Sw*1, *Sw*2, *Sw*3], [*Sw*4, *Sw*5] and [*Sw*6, *Sw*7]. Modulation proposal isolates PV array and grid during freewheeling states, operating similarly to an H5 topology. The authors achieve leakage current reduction with the presence of low-frequency transitions in the PV terminal voltage.

**Figure 12.** Five-level CMLI proposed in [111].


**Table 12.** Operation mode of the topology proposed in [111].
