4.2.4. Performance of Look Downstream Control Rule (LKDN)

The LKDN rule loads the wafer lots even with a smaller batch size than MBS level when the downstream bottleneck workload is less than the predefined target workload, 35 wafers in this case. The target workload is obtained from preliminary experiments. For the benchmark scenario, the MBS6 rule is used. Figure 9a,b show the throughput rate and lead time under the LKDN control rule and the MBS6, under the CONWIP job release environment. It is seen that the LKDN rule gives better performance than the MBS6 with more throughput rate and less lead time, especially with lower BP utilization levels. Since most wafer fabs keep the BP utilization less than 80%, the LKDN rule may be a good alternative to the MBS6. The high performance of LKDN can be realized by utilizing the bottleneck station (BOT) with less starvation downtime. Figure 9c compares the performance of LKDN and MBS6 in terms of the BOT utilization over different BP utilizations. The figure shows that the LKDN provides higher BOT capacity utilization than the MBS6, especially when the BP utilization is

not too high. It should be noted that an increase in BOT capacity utilization directly leads to in greater throughput, which means a great deal in the capital-intensive wafer fab.

**Figure 9.** Performance of LKDN (Look-Downstream) and MBS6 (Minimum Batch Size 6) over different BP utilization levels in terms of (**a**) throughput, (**b**) production lead time, and (**c**) BOT (bottleneck) station utilization.

#### **5. Conclusions**

This paper attempts to provide managerial insights about the operational control policies at batch processing stations in wafer fabs. Batch processors have distinct characteristics different from discrete processors: The long batch processing time and non-smooth product flow caused by repetitive batching and splitting increase the flow variability, resulting in long lead times. Most previous studies on batch processors focus on a stand-alone BP station. Not much study has been done for batch processor control from a systems perspective. We have constructed a simulation model for a wafer fab and performed experiments with a variety of operational environments. From simulation studies, we have collected some interesting findings as follows:


especially in the cases of moderate and lower BP utilization. The result is contradictory to the common belief about batch size determination in industries where BP operation with a full load is widely used. It is believed that the result is one of the major contributions of this paper.


The study in this paper may be improved on different levels. Firstly, a variety of testbeds may be modeled to examine the impact of batch processors with more scenarios. The limitation of our study in this paper is that we only consider a specific wafer fab model, and hence, the experimental analysis is done for a limited manufacturing case. Research work is invited to perform simulation experiments with a variety of wafer fab models, especially within the real-life wafer fab settings to examine the system behavior affected by batch processors. Secondly, some manufacturing settings not covered in this paper, such as sequence-dependent BP setup times, waiting time constraints, BP stations with different batch capacity, multiple product types with different product flows, and orders with due dates, are interesting issues to be addressed. When due dates are involved for each job (order), performance measures, such as tardiness and lateness may be more important than the lead time, the performance measure in this paper. In this case, new BP control rules need to be devised to improve upon the presented rules. Finally, it would be interesting to examine how lot release, DP dispatching (for bottleneck and non-bottleneck stations) and BP control policies interact with each other and how the optimal combination of the control policies is selected under different manufacturing settings.

**Author Contributions:** Conceptualization, P.-H.K.; methodology, P.-H.K. and R.R.; software, P.-H.K.; validation, P.-H.K. and R.R.; writing—original draft preparation, P.-H.K.; writing—review and editing, R.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the Pukyong National University Research Abroad Fund (C-D-2016-0843).

**Conflicts of Interest:** The authors declare no conflict of interest.
